e9b7e615a7| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.761m | 17.660ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 49.760s | 3.148ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.780s | 26.114us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.800s | 29.114us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.770s | 712.765us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.910s | 110.380us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.490s | 69.680us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.800s | 29.114us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.910s | 110.380us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 12.230s | 12.111ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 37.869m | 108.531ms | 14 | 50 | 28.00 |
| V2 | host_maxperf | i2c_host_perf | 17.689m | 48.642ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.740s | 41.059us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.417m | 5.358ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.221m | 10.429ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.340s | 1.430ms | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 25.390s | 486.367us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.750s | 1.770ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.139m | 35.357ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 51.650s | 2.482ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 5.230s | 151.800us | 16 | 50 | 32.00 |
| V2 | target_glitch | i2c_target_glitch | 11.170s | 9.130ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 29.560m | 44.220ms | 47 | 50 | 94.00 |
| V2 | target_maxperf | i2c_target_perf | 7.580s | 4.492ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.576m | 4.071ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.620s | 5.191ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.060s | 254.578us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.770s | 796.497us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 52.536m | 63.627ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.576m | 4.071ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 16.189m | 25.411ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.480s | 5.900ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.051m | 4.837ms | 43 | 50 | 86.00 |
| V2 | bad_address | i2c_target_bad_addr | 8.750s | 1.915ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 36.350s | 10.004ms | 22 | 50 | 44.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.890s | 1.478ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.550s | 1.486ms | 47 | 50 | 94.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 17.689m | 48.642ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 3.821m | 5.873ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 51.650s | 2.482ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 26.040s | 2.165ms | 47 | 50 | 94.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.250s | 10.164ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 2.990s | 1.184ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.660s | 451.912us | 32 | 50 | 64.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 25.070s | 2.194ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.630s | 3.879ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.680s | 18.629us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.770s | 134.199us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.590s | 149.740us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.590s | 149.740us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.780s | 26.114us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.800s | 29.114us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.910s | 110.380us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.270s | 244.036us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.780s | 26.114us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.800s | 29.114us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.910s | 110.380us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.270s | 244.036us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1659 | 1792 | 92.58 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.400s | 643.482us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.920s | 127.190us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.400s | 643.482us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 13.938m | 9.801ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.000s | 264.588us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 15.142m | 50.032ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1839 | 2042 | 90.06 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 29 | 59.18 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.14 | 97.15 | 89.50 | 97.22 | 71.43 | 94.11 | 98.44 | 90.11 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 50 failures:
0.i2c_host_mode_toggle.22145687573017229434881185531267014433146015889760345067733551606797454882569
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 325123991 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @14604
2.i2c_host_mode_toggle.78232927032375391867135743009933974288698909641549166574905526714367648266731
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 178687245 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @22926
... and 18 more failures.
1.i2c_host_stress_all.4940630610369701909222273501799962876579970181934349771859629741970375369695
Line 335, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 92998060470 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5975947
2.i2c_host_stress_all.64364026436842054099440482449607483529170643065740232767296615052969572324317
Line 420, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 18632448316 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @23037695
... and 28 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 30 failures:
2.i2c_target_unexp_stop.47748641568367364319358780694456749531746521537308862648306565739923719238379
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 80375586 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 93 [0x5d])
UVM_INFO @ 80375586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.70665843341090586846608652131885948487697829347498576285991719458471277969090
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 120170737 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 207 [0xcf])
UVM_INFO @ 120170737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
6.i2c_target_stress_all_with_rand_reset.113032973444072260119242021395500698888273591106366493211229388693137981362951
Line 273, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 219536197 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 14 [0xe])
UVM_INFO @ 219536197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.50537555563322231701339635084700129891310454683272116837552275825576408576652
Line 410, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 37627805224 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 31 [0x1f])
UVM_INFO @ 37627805224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 28 failures:
2.i2c_target_hrst.55364653682629824402825915247359803873743551313592689145375840521409083722032
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10459852042 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10459852042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_hrst.61726556771014227705931620357963224769378440072072205280871276428844352071563
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10006440955 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10006440955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 19 failures:
0.i2c_target_unexp_stop.19499335673093683267232859257029083299925816191279706435406684478865998673020
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 242615766 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 242615766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.41081814317579975120281963722206286574330796974913530188922854732954849284246
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 88986906 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 88986906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 18 failures:
6.i2c_target_nack_txstretch.19865791104877670609794571631121884388749762723567914551055279450881901465712
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 127391280 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 127391280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_nack_txstretch.70951374362156595068628467149990572912003616901754938689600502948827504069270
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 861617578 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 861617578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
0.i2c_host_stress_all_with_rand_reset.76750827972567402845594876618864600884276313917121688684912180709759602462432
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 114440286 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 114440286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.92768497069161398088151983276303726976385148938014288147632135797554220467663
Line 316, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 88070667447 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 88070667447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.15996549719462140538838545402444379782412207419621548574821257977372585006154
Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2210120407 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2210120407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.47827725462126835569830697781678635070457766613948508448039797140325299403651
Line 572, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 35918101530 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 35918101530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 11 failures:
1.i2c_host_mode_toggle.106393140835095725503974625887029015076173406608602162387414770805467693092999
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 185962357 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
5.i2c_host_mode_toggle.14998444875092923967929277982984958561417612343923704307804992707938038768587
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 169814538 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 9 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 7 failures:
2.i2c_target_stretch.96751698886064537474164576023136575212902053423424537762990047109754794580811
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10004352459 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10004352459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stretch.111759653997250800552462889926415222979828733563940936390120173362698356012395
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10005903496 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10005903496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 6 failures:
7.i2c_target_tx_stretch_ctrl.56042029060584839922889163367262430243154541825350106142310158377229999998357
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
12.i2c_target_tx_stretch_ctrl.24932656763164592750012756531464706848969013923049027041039341116919789504369
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 1 more failures.
24.i2c_target_fifo_watermarks_tx.108504129403774632705029848657981137136003800155639361973111792967155196910316
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
28.i2c_target_fifo_watermarks_tx.112256672112549272819639724880992421400955570607496653988093452938985979338300
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 1 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
Test i2c_host_perf has 1 failures.
2.i2c_host_perf.59539652844855262977033038000804327900358941385359455304727527139105647914654
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_perf/latest/run.log
Job ID: smart:4b51afd4-78d7-4204-9c46-c8c99593f58b
Test i2c_host_stress_all has 2 failures.
15.i2c_host_stress_all.83822030865818630153131758650896878685942438986404532118629006039099099728912
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log
Job ID: smart:96a7d559-90a7-4253-b327-c24d4df6bc30
31.i2c_host_stress_all.78909560663919738148528747169970491323825015329156727140568223421402843464531
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_host_stress_all/latest/run.log
Job ID: smart:4d65713e-c60d-432a-939a-0441b6e1bec3
Test i2c_target_stress_all has 1 failures.
25.i2c_target_stress_all.76858292198870086188477338981075221959509320873632757106657270086054954327739
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all/latest/run.log
Job ID: smart:6c2ae777-0f46-4467-afb4-9a08fcabb038
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 4 failures:
7.i2c_host_stress_all.61779808023335732233177578982300068296602744529044943134080956898993807545727
Line 389, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 59899592845 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @13185007
11.i2c_host_stress_all.73922099299714732679268952647796534648152170400378494122107634038240750438063
Line 424, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 58777382719 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @10554923
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
11.i2c_host_mode_toggle.102884889863071967009075623758366572399334190819854651279163524805817809789233
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 32523348 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xbc0a8894, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 32523348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.i2c_host_mode_toggle.14076119252087322993624562872831371826053239937902556564517920810217227289060
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 150028598 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x9c627a14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 150028598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 3 failures:
20.i2c_target_unexp_stop.62435826994410799584919221673182787231092989860707269167168901468131896682144
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 670243870 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 670243870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.i2c_target_unexp_stop.53731442805155552745109567076205496868679090843990283652304185420025630956928
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 100520689 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 100520689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:755) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
3.i2c_target_stress_all_with_rand_reset.52784421538069648291982706986002020766038431754300683781406539127654779982384
Line 384, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 64460415955 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 64460415955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.52403478417314503808591909144406970601858863985312750622716899349763328859385
Line 617, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 33044208208 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 33044208208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
30.i2c_target_stress_all.105485092049287566846611884569546878030762793358163712620549853201520111937963
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 44372192049 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 44372192049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.i2c_target_stress_all.13889090663292673450604249181757620561907508664155987843589485222874967653607
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 67980017363 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 67980017363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---