625f353e9c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.832m | 2.039ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 53.180s | 23.216ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.820s | 25.891us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.830s | 38.734us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.110s | 734.319us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.010s | 114.965us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.720s | 37.447us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.830s | 38.734us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.010s | 114.965us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 9.620s | 269.848us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 59.584m | 83.960ms | 16 | 50 | 32.00 |
| V2 | host_maxperf | i2c_host_perf | 14.763m | 28.085ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 0.740s | 26.508us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.015m | 20.696ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.457m | 12.984ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.340s | 208.387us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 19.730s | 1.515ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 10.970s | 216.193us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.843m | 3.470ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 38.230s | 875.766us | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 8.910s | 230.033us | 20 | 50 | 40.00 |
| V2 | target_glitch | i2c_target_glitch | 11.350s | 7.955ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 26.097m | 46.282ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 7.740s | 10.405ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.055m | 1.538ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.360s | 1.503ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.870s | 876.853us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.880s | 277.176us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 43.679m | 63.674ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.055m | 1.538ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 6.620m | 17.255ms | 49 | 50 | 98.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.140s | 6.135ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.722m | 5.156ms | 47 | 50 | 94.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.850s | 1.547ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 35.310s | 10.232ms | 27 | 50 | 54.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.460s | 665.193us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.680s | 377.987us | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 14.763m | 28.085ms | 48 | 50 | 96.00 |
| i2c_host_perf_precise | 3.908m | 5.817ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 38.230s | 875.766us | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 18.460s | 1.568ms | 43 | 50 | 86.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.530s | 3.919ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.160s | 2.241ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.660s | 1.195ms | 35 | 50 | 70.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 27.020s | 7.261ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.740s | 565.313us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.700s | 27.112us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.760s | 19.414us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.800s | 140.390us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.800s | 140.390us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.820s | 25.891us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 38.734us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.010s | 114.965us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.190s | 121.872us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.820s | 25.891us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 38.734us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.010s | 114.965us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.190s | 121.872us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1675 | 1792 | 93.47 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.530s | 83.790us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.910s | 150.638us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.530s | 83.790us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 7.578m | 14.165ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.460s | 353.598us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 12.957m | 77.143ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1855 | 2042 | 90.84 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.28 | 97.21 | 89.61 | 97.22 | 72.62 | 94.26 | 98.44 | 89.58 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 46 failures:
0.i2c_host_mode_toggle.86362209255523397550361998566370235875719431357988964947575075699394426760208
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 161239026 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @50742
1.i2c_host_mode_toggle.69255596999357183021200273495888017257994319478270021792563345340817783378652
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 567568295 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @37880
... and 18 more failures.
4.i2c_host_stress_all.22892548381170934532048776970205375123068944347624694166928790395921138778800
Line 405, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 61922232192 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @75816281
7.i2c_host_stress_all.47648737165824736159035041702892660251570151436455569547193340527967853799577
Line 421, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 68173078536 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @11150307
... and 24 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 30 failures:
0.i2c_target_unexp_stop.85818786171483732209788386809470646087274045712866414116748914491746019461699
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 252534664 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 208 [0xd0])
UVM_INFO @ 252534664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.90280572239239690625228528909403030583230493040554472536268016888008515788799
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 85652959 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 240 [0xf0])
UVM_INFO @ 85652959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
9.i2c_target_stress_all_with_rand_reset.50282219968799030461478727295030785140853844814087292693651623882582768177019
Line 658, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 77142960687 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 246 [0xf6])
UVM_INFO @ 77142960687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 23 failures:
0.i2c_target_hrst.44757968533069529925897452540217678561853175261521224890801433445806607154800
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10017720483 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10017720483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.106545121352537130678008062297132240465267716399125168074554998220448497711763
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10070363308 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10070363308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
0.i2c_host_stress_all_with_rand_reset.106520651829867065176756274912423218962698575358952115300500941450245152818833
Line 292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8314360028 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8314360028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.55390645201872481004876563015353259180202710216736292568326098177532520658587
Line 331, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6846635020 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6846635020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
0.i2c_target_stress_all_with_rand_reset.84846748462954743026932842907775676054432125206849535561803911538360215192856
Line 603, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19547912857 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 19547912857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.95720321749162069562509245803788661530909044331110527496562845397049274622975
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 863415228 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 863415228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 15 failures:
0.i2c_target_nack_txstretch.91868450753981753219494811540811019691645077752745249655057681655687088905644
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 516763693 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 516763693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_nack_txstretch.81606833300809595028819982970155282371534315665086588925944693155994784526307
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 193384576 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 193384576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 14 failures:
4.i2c_target_unexp_stop.3730497045694731093691240194403800521202308890966110208234139819290076937568
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 82915519 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 82915519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_unexp_stop.43307692606331925760748908201893574843436888352572188580878229816048598961175
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 953634764 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 953634764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 8 failures:
14.i2c_host_mode_toggle.76292425468626869955969579984789531122458217748447995498203085131079721572044
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 401433797 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
16.i2c_host_mode_toggle.67010526415871625843625139579075678393027440472406713535662994460342318750159
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 31786229 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 5 more failures.
49.i2c_host_perf_precise.90151946324974369514088220113291128719767552926672023561699454581989066033265
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/49.i2c_host_perf_precise/latest/run.log
UVM_ERROR @ 227703588 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
Error-[CNST-CIF] Constraints inconsistency failure has 7 failures:
4.i2c_target_tx_stretch_ctrl.32946086277136926552918755250716554798121669616213604582768845167139454551227
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
7.i2c_target_tx_stretch_ctrl.47998937402126482293862124265682638308893750495113515646683659576689536921551
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 5 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 7 failures:
5.i2c_target_unexp_stop.25833717045495805703550457025701875655725735678543170308361818593789563410834
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 167052273 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 167052273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.i2c_target_unexp_stop.27405583548624789900968902342827056714633594470353210671956907096847904470617
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 82267032 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 82267032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
Test i2c_host_stress_all_with_rand_reset has 1 failures.
6.i2c_host_stress_all_with_rand_reset.86785642520468825267785681390728131985248737656101670397895100843785529668599
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:4755e055-e8c3-4b5e-899c-990d3227bcdb
Test i2c_host_perf has 2 failures.
14.i2c_host_perf.95656340321841644489063221457899655463439404397413314005762696018634670855464
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_perf/latest/run.log
Job ID: smart:b0ad109c-8050-4e59-bdfb-c90e0b17f472
25.i2c_host_perf.109823901011161063467457028769506105779019654436078801167831168756716742131571
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_host_perf/latest/run.log
Job ID: smart:1c8deb2f-d454-4a15-8e4f-aa4a91589b60
Test i2c_host_stress_all has 3 failures.
18.i2c_host_stress_all.83178821590719399277511081382447728408795857464994292851922574621656568695385
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log
Job ID: smart:1b50f1e1-4494-43b9-af8f-38162ec3430d
35.i2c_host_stress_all.87852421258659755149104620053033526949015339480879211350991564684341625810335
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_host_stress_all/latest/run.log
Job ID: smart:cbc85e82-c3b9-48b1-9b99-dfc5c1bce2a2
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 5 failures:
0.i2c_host_stress_all.21818830523427156876695379355309322965969461294601015530562744923369863441771
Line 391, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 36771139690 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5908699
1.i2c_host_stress_all.109187820525993262233692434929760305009642389747658083857906786229482587508604
Line 391, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 28215787237 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @9598477
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
13.i2c_host_mode_toggle.86183705664052946849749063132761710336889621563205992371581598668725322169405
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 59367729 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xe5bdbd94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 59367729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.i2c_host_mode_toggle.102875853667508301418392141921426459681217387571738825918599163687229956404845
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 177158512 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xe4c3b194, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 177158512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 3 failures:
15.i2c_target_stretch.85562505845318366915859811405296241345663375544445906144114708942518562896766
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10012628930 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10012628930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.i2c_target_stretch.8581465302494083512602709650330838804017520737490735843625750737736057170390
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10001385596 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10001385596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:755) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
1.i2c_target_stress_all_with_rand_reset.55663899732717422926791888894825584887069194542474042253800999960464816164125
Line 344, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 93752261846 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 93752261846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.2514453065301865313114581110382849777867867298318351794668733258525258088993
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2986765748 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2986765748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
Test i2c_target_intr_stress_wr has 1 failures.
9.i2c_target_intr_stress_wr.13954341764171257991282148506296493698371324720559997146558746455152660674444
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 52938905159 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 52938905159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 1 failures.
10.i2c_target_stress_all.76834903751141887641829569176696138883703784382266886817296266239867278372446
Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 43456791657 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 43456791657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
3.i2c_target_stress_all_with_rand_reset.18293044244869337032908621621840158896775266189437712884003468029007860126285
Line 421, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 222483887849 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 222483887849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---