c8985d6745| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.435m | 1.820ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 48.420s | 3.211ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.830s | 41.240us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.810s | 72.767us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.150s | 1.473ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.910s | 313.492us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.280s | 29.470us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.810s | 72.767us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.910s | 313.492us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 12.280s | 695.913us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 58.335m | 23.839ms | 17 | 50 | 34.00 |
| V2 | host_maxperf | i2c_host_perf | 16.247m | 28.324ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 0.740s | 27.387us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.952m | 5.281ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.307m | 2.600ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.470s | 325.262us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 29.210s | 524.827us | 49 | 50 | 98.00 | ||
| i2c_host_fifo_reset_rx | 13.490s | 3.301ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.420m | 3.586ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 52.220s | 1.801ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 5.930s | 219.326us | 19 | 50 | 38.00 |
| V2 | target_glitch | i2c_target_glitch | 11.500s | 13.377ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 54.623m | 75.120ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 7.950s | 4.284ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.114m | 1.469ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.090s | 3.481ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.840s | 941.061us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 2.110s | 1.018ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 48.294m | 62.138ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.114m | 1.469ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 21.757m | 36.370ms | 49 | 50 | 98.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.080s | 2.586ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.421m | 5.644ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.950s | 6.291ms | 49 | 50 | 98.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 36.750s | 10.257ms | 17 | 50 | 34.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.580s | 2.516ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.740s | 188.309us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 16.247m | 28.324ms | 48 | 50 | 96.00 |
| i2c_host_perf_precise | 2.875m | 24.733ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 52.220s | 1.801ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 13.630s | 1.135ms | 50 | 50 | 100.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.420s | 682.212us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.090s | 1.192ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.640s | 402.263us | 39 | 50 | 78.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 23.640s | 2.697ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.650s | 570.376us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.720s | 16.822us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.760s | 17.628us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.540s | 809.050us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.540s | 809.050us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.830s | 41.240us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.810s | 72.767us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.910s | 313.492us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.230s | 37.263us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.830s | 41.240us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.810s | 72.767us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.910s | 313.492us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.230s | 37.263us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1673 | 1792 | 93.36 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.370s | 297.992us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.950s | 638.683us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.370s | 297.992us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 11.219m | 9.579ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 3.220s | 852.611us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 8.681m | 20.098ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1853 | 2042 | 90.74 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 27 | 55.10 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.33 | 97.27 | 89.65 | 97.22 | 72.62 | 94.33 | 98.44 | 89.79 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 36 failures:
1.i2c_host_mode_toggle.38464307316104427275121060163364069450864343148655087664923352534087391416589
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 74735310 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @13018
2.i2c_host_mode_toggle.10845652863204445653352717228616624121708803938340515848478954095491671193347
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 123902539 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @33296
... and 15 more failures.
2.i2c_host_stress_all.6035440631885693502115343779721263506353066784817572758666539630023972838420
Line 295, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 26470049042 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3628515
3.i2c_host_stress_all.56151379495797283375672857790800644478813317984182904198382848915344975378405
Line 373, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 23838530895 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @29579669
... and 17 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 33 failures:
0.i2c_target_hrst.27357019757421876286084554576521042120902785342036392193392159526190875620678
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10203926398 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10203926398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_hrst.87496350900806476438384287693320256202990171087205859972113238792602310351052
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10142129567 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10142129567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 29 failures:
0.i2c_target_unexp_stop.4278716121631524416529519156797393361173912242482219524453533891959462437894
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 810174665 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 181 [0xb5])
UVM_INFO @ 810174665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.101849978228851073321412305041152460445799704240672235812391828862212766263263
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 170435556 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 185 [0xb9])
UVM_INFO @ 170435556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
7.i2c_target_stress_all_with_rand_reset.110334724535069475886712921311521879016250040524496490318034687724687561249932
Line 312, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4533144692 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 192 [0xc0])
UVM_INFO @ 4533144692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:836) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
0.i2c_host_stress_all_with_rand_reset.23309525587010208687381390252284327556416500292181459372976002530675151215771
Line 322, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9578716113 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9578716113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.108115543739288166595861529757554698485060009293329917408225156714767694406107
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1138976332 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1138976332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.45217014365384796348208681466831573913013639051471141291127787337508038883414
Line 457, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13101016953 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 13101016953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.94556143993578252783532874034658174575971864089489520710989150311782775698106
Line 425, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16786744629 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 16786744629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 13 failures:
3.i2c_target_unexp_stop.13951200816975200601215099929342370180421450550374083570798775232649471894208
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 260847783 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 260847783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_unexp_stop.81611016327433237723656624534912692639641987203722079030888657364302052771366
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 134502215 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 134502215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
Test i2c_host_stress_all has 7 failures.
0.i2c_host_stress_all.39361474682771651680488101845385796651388824232038826477846338684738782202106
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
Job ID: smart:dfa2e0bc-23f1-478d-8f3b-9bbde95dc860
1.i2c_host_stress_all.89950376303568229369431282637644518218539707659031533993604757044279306424526
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:e2470b93-f44d-48f7-b3a4-74a999e4e2d8
... and 5 more failures.
Test i2c_target_stress_all_with_rand_reset has 2 failures.
1.i2c_target_stress_all_with_rand_reset.108669571947388205959497079260952267672498261547118309241435240992548553416849
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:a3fe4537-e3fd-4ca6-9aee-103a74f8db6e
6.i2c_target_stress_all_with_rand_reset.43219647979134664612869303078594280317589876961794607557708538338932801214369
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:1f93e726-6c11-4937-8dc8-18c900853887
Test i2c_host_perf has 2 failures.
2.i2c_host_perf.42722813039898813325355124370999450090123171816715951959026157432422296025144
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_perf/latest/run.log
Job ID: smart:a904c909-751f-4bb8-b6f7-09a6b41f9234
34.i2c_host_perf.41271229775970829591928052030023213442810361246565150153270759077422345320611
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_host_perf/latest/run.log
Job ID: smart:32796ec9-a8c6-4c50-84c0-0b542fca694b
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 11 failures:
0.i2c_host_mode_toggle.103551328586542193399164319385738584575595369670191166839640083775434819605454
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 64178927 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
5.i2c_host_mode_toggle.79152229058872571450899906572665889550650212919968688742193087687527770858982
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 49531082 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 9 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 11 failures:
2.i2c_target_nack_txstretch.54223071761008052691395932485097239683345462124435142811534996073049695435250
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 876654010 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 876654010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_nack_txstretch.73557094427194454370343071990123623936234838401275760211460307298123854444233
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 822004746 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 822004746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 9 failures:
5.i2c_target_unexp_stop.98490828339599642678703920584332560282378978408125045363365278740406447791641
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 973653113 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 973653113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_unexp_stop.95009008362273040740734452333016920945168795481308874345427698229974421569589
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 187013630 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 187013630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 7 failures:
7.i2c_host_stress_all.13202539093164641601820879785696803068391911436873385288125808493107215371560
Line 378, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 38051058114 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @6942713
10.i2c_host_stress_all.63802199241104844700041043997179332308240408898450818371465661054813994380779
Line 479, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 136062127665 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2620579
... and 5 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
10.i2c_target_stretch.65598830540525554962887809381948806206615574649537010636201094172232817573
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10001506800 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10001506800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_target_stretch.42498206916014255389805927708799504041965439212071782917058009198224513527249
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10044978181 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10044978181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
Test i2c_target_intr_stress_wr has 1 failures.
3.i2c_target_intr_stress_wr.47904214670595975574973098135612432794694515435119959084869726527904179224096
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 24477951179 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 24477951179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 1 failures.
36.i2c_target_stress_all.115085403613429262942574802596791782613686463475486159394781150960833765138555
Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 27100765669 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 27100765669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:755) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
3.i2c_target_stress_all_with_rand_reset.110675564653274115798586127970661105751470507290961728070433627080613536719264
Line 435, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 20097822246 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 20097822246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.83176767204881335448655072679564329218584144493243222774273108101470772760463
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5515798273 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5515798273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test i2c_target_bad_addr has 1 failures.
4.i2c_target_bad_addr.103365723270453545514120555339959077904970115514224741357736013128022307483112
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_fifo_fmt_empty has 1 failures.
37.i2c_host_fifo_fmt_empty.20832180923892536825524249463405429695220388145895081652080621595173682905058
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_host_fifo_fmt_empty/latest/run.log
UVM_FATAL @ 10000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
31.i2c_host_mode_toggle.61024335252394736144251988008375300870812950375279322217424765858481740400442
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 90759716 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xdcb23394, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 90759716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.i2c_host_mode_toggle.31509274620484361346924548242720166029323467312419783306171894736246691545614
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 41964822 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x688f3814, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 41964822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_timeout_vseq.sv:48) [drv_pause] wait timeout occurred! has 1 failures:
9.i2c_target_stress_all_with_rand_reset.13773360746907908596801184101489045206797931475469514907807398641837325357890
Line 377, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 42284615315 ps: (i2c_target_timeout_vseq.sv:48) [drv_pause] wait timeout occurred!
UVM_INFO @ 42284615315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
26.i2c_target_fifo_watermarks_tx.37251040707791524064576559265378694015084250940692023289174882118275482321621
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Exit reason: Error: User command failed Error-[NOA] Null object access has 1 failures:
35.i2c_host_mode_toggle.2910748359749486046639728115385347880359074435140843421655464335251772764244
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.