I2C Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 host_smoke i2c_host_smoke 0 50 0.00
V1 target_smoke i2c_target_smoke 0 50 0.00
V1 csr_hw_reset i2c_csr_hw_reset 0.790s 19.567us 5 5 100.00
V1 csr_rw i2c_csr_rw 0.790s 190.208us 20 20 100.00
V1 csr_bit_bash i2c_csr_bit_bash 5.160s 2.139ms 5 5 100.00
V1 csr_aliasing i2c_csr_aliasing 1.920s 191.838us 5 5 100.00
V1 csr_mem_rw_with_rand_reset i2c_csr_mem_rw_with_rand_reset 1.260s 27.584us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr i2c_csr_rw 0.790s 190.208us 20 20 100.00
i2c_csr_aliasing 1.920s 191.838us 5 5 100.00
V1 TOTAL 55 155 35.48
V2 host_error_intr i2c_host_error_intr 0 50 0.00
V2 host_stress_all i2c_host_stress_all 0 50 0.00
V2 host_maxperf i2c_host_perf 0 50 0.00
V2 host_override i2c_host_override 0 50 0.00
V2 host_fifo_watermark i2c_host_fifo_watermark 0 50 0.00
V2 host_fifo_overflow i2c_host_fifo_overflow 0 50 0.00
V2 host_fifo_reset i2c_host_fifo_reset_fmt 0 50 0.00
i2c_host_fifo_fmt_empty 0 50 0.00
i2c_host_fifo_reset_rx 0 50 0.00
V2 host_fifo_full i2c_host_fifo_full 0 50 0.00
V2 host_timeout i2c_host_stretch_timeout 0 50 0.00
V2 host_rx_oversample i2c_host_rx_oversample 0 0 --
V2 i2c_host_mode_toggle i2c_host_mode_toggle 0 50 0.00
V2 target_glitch i2c_target_glitch 0 2 0.00
V2 target_stress_all i2c_target_stress_all 0 50 0.00
V2 target_maxperf i2c_target_perf 0 50 0.00
V2 target_fifo_empty i2c_target_stress_rd 0 50 0.00
i2c_target_intr_smoke 0 50 0.00
V2 target_fifo_reset i2c_target_fifo_reset_acq 0 50 0.00
i2c_target_fifo_reset_tx 0 50 0.00
V2 target_fifo_full i2c_target_stress_wr 0 50 0.00
i2c_target_stress_rd 0 50 0.00
i2c_target_intr_stress_wr 0 50 0.00
V2 target_timeout i2c_target_timeout 0 50 0.00
V2 target_clock_stretch i2c_target_stretch 0 50 0.00
V2 bad_address i2c_target_bad_addr 0 50 0.00
V2 target_mode_glitch i2c_target_hrst 0 50 0.00
V2 target_fifo_watermark i2c_target_fifo_watermarks_acq 0 50 0.00
i2c_target_fifo_watermarks_tx 0 50 0.00
V2 host_mode_config_perf i2c_host_perf 0 50 0.00
i2c_host_perf_precise 0 50 0.00
V2 host_mode_clock_stretching i2c_host_stretch_timeout 0 50 0.00
V2 target_mode_tx_stretch_ctrl i2c_target_tx_stretch_ctrl 0 50 0.00
V2 target_mode_nack_generation i2c_target_nack_acqfull 0 50 0.00
i2c_target_nack_acqfull_addr 0 50 0.00
i2c_target_nack_txstretch 0 50 0.00
V2 host_mode_halt_on_nak i2c_host_may_nack 0 50 0.00
V2 target_mode_n_byte_ack_control target_mode_n_byte_ack_control 0 0 --
V2 target_mode_bus_timeout target_mode_bus_timeout 0 0 --
V2 controller_mode_bus_timeout controller_mode_bus_timeout 0 0 --
V2 controller_mode_bus_idle_delay controller_mode_bus_idle_delay 0 0 --
V2 loopback_test loopback_test 0 0 --
V2 multi_controller_clock_synchronization multi_controller_clock_synchronization 0 0 --
V2 multi_controller_arbitration_lost_interference multi_controller_arbitration_lost_interference 0 0 --
V2 multi_controller_arbitration_lost multi_controller_arbitration_lost 0 0 --
V2 target_mode_arbitration_lost_interference target_mode_arbitration_lost_interference 0 0 --
V2 target_mode_arbitration_lost target_mode_arbitration_lost 0 0 --
V2 target_mode_smbus_maxlen i2c_target_smbus_maxlen 0 50 0.00
V2 alert_test i2c_alert_test 0 50 0.00
V2 intr_test i2c_intr_test 0.750s 18.617us 50 50 100.00
V2 tl_d_oob_addr_access i2c_tl_errors 2.880s 538.348us 20 20 100.00
V2 tl_d_illegal_access i2c_tl_errors 2.880s 538.348us 20 20 100.00
V2 tl_d_outstanding_access i2c_csr_hw_reset 0.790s 19.567us 5 5 100.00
i2c_csr_rw 0.790s 190.208us 20 20 100.00
i2c_csr_aliasing 1.920s 191.838us 5 5 100.00
i2c_same_csr_outstanding 1.170s 47.715us 20 20 100.00
V2 tl_d_partial_access i2c_csr_hw_reset 0.790s 19.567us 5 5 100.00
i2c_csr_rw 0.790s 190.208us 20 20 100.00
i2c_csr_aliasing 1.920s 191.838us 5 5 100.00
i2c_same_csr_outstanding 1.170s 47.715us 20 20 100.00
V2 TOTAL 90 1792 5.02
V2S tl_intg_err i2c_tl_intg_err 2.380s 801.518us 20 20 100.00
i2c_sec_cm 0 5 0.00
V2S sec_cm_bus_integrity i2c_tl_intg_err 2.380s 801.518us 20 20 100.00
V2S TOTAL 20 25 80.00
V3 host_stress_all_with_rand_reset i2c_host_stress_all_with_rand_reset 0 10 0.00
V3 target_error_intr i2c_target_unexp_stop 0 50 0.00
V3 target_stress_all_with_rand_reset i2c_target_stress_all_with_rand_reset 0 10 0.00
V3 target_loopback 0 0 --
V3 TOTAL 0 70 0.00
TOTAL 165 2042 8.08

Testplan Progress

Items Total Written Passing Progress
V1 7 7 5 71.43
V2 49 38 3 6.12
V2S 2 2 1 50.00
V3 4 3 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
52.66 40.66 40.68 90.72 0.00 42.98 99.68 53.89

Failure Buckets

Past Results