e4c5daa580| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.013m | 8.785ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 40.810s | 5.291ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.770s | 24.528us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.810s | 21.563us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.180s | 529.613us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.940s | 1.376ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.540s | 215.499us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.810s | 21.563us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.940s | 1.376ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 8.680s | 224.299us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 44.457m | 51.327ms | 22 | 50 | 44.00 |
| V2 | host_maxperf | i2c_host_perf | 58.698m | 47.426ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.740s | 30.568us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.425m | 5.303ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.407m | 2.624ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.490s | 232.157us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 27.270s | 10.000ms | 49 | 50 | 98.00 | ||
| i2c_host_fifo_reset_rx | 12.010s | 219.206us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.229m | 25.495ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 47.250s | 4.391ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 6.650s | 157.624us | 15 | 50 | 30.00 |
| V2 | target_glitch | i2c_target_glitch | 10.430s | 17.365ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 40.226m | 64.862ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 7.150s | 3.971ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.212m | 6.452ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 7.870s | 6.021ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.980s | 302.226us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 2.140s | 326.579us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 42.737m | 60.487ms | 49 | 50 | 98.00 |
| i2c_target_stress_rd | 1.212m | 6.452ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 7.592m | 18.646ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.250s | 3.125ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 4.427m | 5.295ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.180s | 14.811ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 35.590s | 10.149ms | 20 | 50 | 40.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.670s | 1.935ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.720s | 1.008ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 58.698m | 47.426ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 21.726m | 23.391ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 47.250s | 4.391ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 11.030s | 876.207us | 45 | 50 | 90.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.200s | 532.364us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.120s | 1.276ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.660s | 568.435us | 39 | 50 | 78.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 36.970s | 922.164us | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.700s | 596.718us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.700s | 54.870us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.770s | 20.027us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.080s | 276.195us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.080s | 276.195us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.770s | 24.528us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.810s | 21.563us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.940s | 1.376ms | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.180s | 31.306us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.770s | 24.528us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.810s | 21.563us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.940s | 1.376ms | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.180s | 31.306us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1675 | 1792 | 93.47 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.450s | 151.075us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.910s | 246.978us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.450s | 151.075us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 17.181m | 71.216ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 3.800s | 2.508ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 13.586m | 19.573ms | 1 | 10 | 10.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 1 | 70 | 1.43 | |||
| TOTAL | 1856 | 2042 | 90.89 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.30 | 97.27 | 89.57 | 97.22 | 72.02 | 94.33 | 98.44 | 90.21 |
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 34 failures:
0.i2c_target_unexp_stop.3241986581901511462153849939524463264755653159458717142588006898083581391693
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 47678415 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 98 [0x62])
UVM_INFO @ 47678415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.61983512342161546378105809030275190791235435085441006769101506756396359470078
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 271503288 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 107 [0x6b])
UVM_INFO @ 271503288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
0.i2c_target_stress_all_with_rand_reset.94410101146010229676913112244047411404220306016124936592643311538011696353644
Line 546, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 116287711377 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 3 [0x3])
UVM_INFO @ 116287711377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.25372485458980043048880558922677678699163132357321479506330507488432722971578
Line 443, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 24665013557 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 217 [0xd9])
UVM_INFO @ 24665013557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 32 failures:
0.i2c_host_mode_toggle.5722471697115629133691173400554228731332521291817515257162239592007860072865
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 517260426 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @40786
10.i2c_host_mode_toggle.48342607896104818601392154167813987656502884796106017032507821690995149906659
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 140859502 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @125884
... and 15 more failures.
1.i2c_host_stress_all.52241835150627731762361925807757703270465367787821943863554921943015906819741
Line 296, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 3866060557 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @823325
7.i2c_host_stress_all.101205064219165873621600509603440907306626853895344683715434703480724682173656
Line 388, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 77835721007 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5964281
... and 13 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 30 failures:
0.i2c_target_hrst.13069888608961384382524115057367647245558030508224357422069496161882304696781
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10089618668 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10089618668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_hrst.112746812331956934279785518544491344440591115136544027095423143212016150492382
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10012852300 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10012852300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
0.i2c_host_stress_all_with_rand_reset.2625875888255991991138661122184034322381247131389621802548910346645873585946
Line 444, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 71215730074 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 71215730074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.27459023712444293312841024552357179099309870883618621967710325165275575775325
Line 369, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 30826806541 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 30826806541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
1.i2c_target_stress_all_with_rand_reset.13232426294493200146602795399732457162595966847037697544840874200540184291968
Line 429, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 51216403405 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 51216403405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.98478893751311618910332565923480474848605957490671391996305053558293161278087
Line 351, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 52410085194 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 52410085194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 14 failures:
1.i2c_target_unexp_stop.70626212747330194965591212227356037386726379566701966846001125305273565020736
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1410834109 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1410834109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.26085919374640164953812691129298562611680370376820901468573653369906072626648
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 145621800 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 145621800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 11 failures:
12.i2c_target_nack_txstretch.22270860636035980950975022962148811893228339213135697039175558136500390969522
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 122368596 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 122368596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_nack_txstretch.66035076345549295278331170984275717106012033712800175531967345858763011080901
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 362630941 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 362630941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 10 failures:
4.i2c_host_mode_toggle.3785670116360098343440340019763240249492676134667495240046339160272606077140
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 50099517 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
6.i2c_host_mode_toggle.47485568662313631083301747864683805845275501272037172271174097774347903652647
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 105711378 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 7 more failures.
22.i2c_host_perf_precise.105373441195242740635439323892873931055397167954169198663650652799229938221259
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_perf_precise/latest/run.log
UVM_ERROR @ 2957866815 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 9 failures:
2.i2c_host_mode_toggle.56020662216583577487626126578403801967087253130411168282297974450925425843771
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 138582978 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xdb890b14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 138582978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_host_mode_toggle.82769262427216339744864773132640041182274489379906476346756583203771595388551
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 42945894 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x3226aa94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 42945894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
Test i2c_target_stress_all_with_rand_reset has 2 failures.
3.i2c_target_stress_all_with_rand_reset.105488511123312079875870033783334800615606422277975886608886964259625800758364
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:7af11576-d703-41fa-bb51-6fdef23e891d
5.i2c_target_stress_all_with_rand_reset.6267387257720316327960943630149838343315686485404461253242772069356549976189
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:2eb9e248-b2ab-4065-b030-d0177a9be582
Test i2c_host_stress_all has 6 failures.
5.i2c_host_stress_all.60231443659514674414005201793282284356759509680582475117343181364970176124
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
Job ID: smart:8a327241-1737-4b4d-a600-3f28d81dbed5
11.i2c_host_stress_all.111428375932903499629706179264338448907779060293154603085185420654812278904572
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log
Job ID: smart:b5c8868d-c3af-4364-892d-e9df045c6b6b
... and 4 more failures.
Test i2c_target_stress_wr has 1 failures.
8.i2c_target_stress_wr.77153002893055575562915149671794679089154878721723087159947898730925287129146
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_wr/latest/run.log
Job ID: smart:e545ceeb-9657-4ddb-9863-376adb1ccad8
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 6 failures:
4.i2c_host_stress_all.78897631057103889316515602103017603529896935943957314039023370305078849580222
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 14686112641 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @9240655
6.i2c_host_stress_all.8817063710284845584232806782060995867304459763611086791316796472485689252889
Line 311, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 54926193702 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5366929
... and 4 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 6 failures:
11.i2c_target_tx_stretch_ctrl.8407654063896733879137715134343763042397035037511852850266044612886760439580
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
24.i2c_target_tx_stretch_ctrl.107610090114782980378217834301932547009080216669052802915106578250138353888524
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 3 more failures.
45.i2c_target_fifo_watermarks_tx.16571235963935591598443312633087747826911608991246847329883855554275761456944
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
0.i2c_target_stretch.38836955537368741354186249443298217035186636233685325629258515723015440232608
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10012910096 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10012910096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stretch.34915913921913833492035736017736888923510266495967021693687514056421393135229
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10022009498 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10022009498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 4 failures:
26.i2c_target_unexp_stop.63867373249559413105983123307872263359297440907696673876138775944092867494007
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 5560028257 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 5560028257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.i2c_target_unexp_stop.94477341859215673807820982740609961640576670577593944846688892637616292130272
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 504174701 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 504174701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test i2c_host_stress_all has 1 failures.
23.i2c_host_stress_all.8541561142624236021194526691395581573443511336676196789029938282722364097529
Line 414, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_fifo_fmt_empty has 1 failures.
34.i2c_host_fifo_fmt_empty.96862012931303238047986974854160159968716447002589097628003489646589874499889
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_host_fifo_fmt_empty/latest/run.log
UVM_FATAL @ 10000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
9.i2c_target_stress_all_with_rand_reset.61578914439605908612901277442211072136711846577934749093925263238495356753140
Line 538, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 24986353140 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 24986353140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---