5fd4ecc0fc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.744m | 8.042ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 48.310s | 2.969ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.790s | 90.661us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.830s | 135.945us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.110s | 921.624us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.770s | 79.978us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.360s | 95.414us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.830s | 135.945us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.770s | 79.978us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 26.890s | 677.513us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 57.136m | 43.878ms | 15 | 50 | 30.00 |
| V2 | host_maxperf | i2c_host_perf | 18.152m | 26.121ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.760s | 90.255us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.485m | 22.534ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.547m | 2.577ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.400s | 610.348us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 32.230s | 2.408ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.910s | 888.394us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.766m | 10.566ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 43.240s | 1.822ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 7.720s | 687.617us | 16 | 50 | 32.00 |
| V2 | target_glitch | i2c_target_glitch | 12.000s | 2.399ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 40.654m | 55.821ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 8.640s | 2.386ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 55.990s | 1.270ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.410s | 1.770ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.140s | 318.678us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.890s | 3.265ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 34.939m | 55.049ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 55.990s | 1.270ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 10.156m | 20.826ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.330s | 6.902ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 3.990m | 4.190ms | 44 | 50 | 88.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.340s | 6.399ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 34.600s | 10.115ms | 25 | 50 | 50.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.800s | 1.474ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.930s | 858.144us | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 18.152m | 26.121ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 3.834m | 5.851ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 43.240s | 1.822ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 15.970s | 1.443ms | 48 | 50 | 96.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.370s | 634.743us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.000s | 2.524ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.660s | 686.760us | 38 | 50 | 76.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 28.460s | 1.417ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.680s | 528.623us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.700s | 45.067us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.750s | 15.499us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.040s | 55.158us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.040s | 55.158us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.790s | 90.661us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 135.945us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.770s | 79.978us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.270s | 131.410us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.790s | 90.661us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 135.945us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.770s | 79.978us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.270s | 131.410us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1676 | 1792 | 93.53 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.520s | 136.413us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.990s | 131.749us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.520s | 136.413us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 13.066m | 10.027ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.550s | 1.410ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 17.301m | 130.936ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1856 | 2042 | 90.89 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 30 | 61.22 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.10 | 96.88 | 89.61 | 97.22 | 71.43 | 93.90 | 98.44 | 90.21 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 43 failures:
0.i2c_host_stress_all.45616815088210175016317839531373431201044717880877589240996144278985018261089
Line 465, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 51124951046 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3272899
2.i2c_host_stress_all.76823706141280889743321088385205113094439694416397938317340759804290501533739
Line 340, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 75092452953 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4364611
... and 25 more failures.
1.i2c_host_mode_toggle.76490931968434470958421417908499921802754320956090111064783337950890671929744
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 83953401 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @17870
3.i2c_host_mode_toggle.101084477931781087484088586554708907160968491633248696181214916150887146770655
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 414723014 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @19110
... and 14 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 26 failures:
1.i2c_target_unexp_stop.66814632481592046309813933702295130433820861600201188825281100627700073886820
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 264749899 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 216 [0xd8])
UVM_INFO @ 264749899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.65660445019293831408391130737826259366238705849672074447298274893525897102390
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 46068541 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 62 [0x3e])
UVM_INFO @ 46068541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
2.i2c_target_stress_all_with_rand_reset.25963529088316727643402542804028091891299307026338947721003735939674695425455
Line 868, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 130936354873 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 136 [0x88])
UVM_INFO @ 130936354873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 25 failures:
0.i2c_target_hrst.48657864031449783369339914954397533118773790192202070503244708633003737811724
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10264249874 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10264249874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.49474785075743100565624792115878447471413278835785810276036676154849705504635
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10115043780 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10115043780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 14 failures:
2.i2c_host_mode_toggle.50122398761658631236963090944989629613695085143981898824488715024243123514504
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 77732505 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
8.i2c_host_mode_toggle.42868380335793828011219615386412606502291940907272671940957991414656263705752
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 137715691 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 12 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 13 failures:
3.i2c_target_unexp_stop.14586196369445317464440923299022588175917859669893477796761919570328839649455
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1409738609 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1409738609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_unexp_stop.48593933563750746445965534776844449078199461561640403226471315666960646750191
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 652040705 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 652040705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 12 failures:
0.i2c_target_unexp_stop.6889049136315069688708126781189872432228730089535551939908897421080536602474
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 145349427 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 145349427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_unexp_stop.97301747256584985826350421987144762326589713503113758155266481007631390195152
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 671872392 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 671872392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 12 failures:
0.i2c_host_stress_all_with_rand_reset.103796268503045204787234165697575158579625724072953006362971615051134517217478
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1669110618 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1669110618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_stress_all_with_rand_reset.112223668617926628376092589693185181096950688164939600423635914677004222738803
Line 384, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 54747332622 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 54747332622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
0.i2c_target_stress_all_with_rand_reset.42138359249403232020478918036712141875186980980691816592944715510659022591699
Line 278, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1446669587 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1446669587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.15570122808073085496848054268698723284342415998739039046865315896612765177810
Line 403, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 28089878654 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 28089878654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 12 failures:
0.i2c_target_nack_txstretch.107787029461019528922161337945745725326099678412841988360761832076393205458100
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 699842221 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 699842221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_nack_txstretch.56360394224598010485324171032137837570197457080984587863832977508615213450401
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 1091550745 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 1091550745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
Test i2c_host_stress_all_with_rand_reset has 2 failures.
1.i2c_host_stress_all_with_rand_reset.101019077972017256103745953288694281749731361754399005041735318790685879035580
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:d1c9f821-eb8b-4c35-a7cf-3d936505860c
8.i2c_host_stress_all_with_rand_reset.109469922714459917620602892424823023576119832593755472402870938495618344058460
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:3c1dbd1c-3812-4ff6-967e-39aed433615f
Test i2c_host_stress_all has 5 failures.
7.i2c_host_stress_all.82250426381223358402313277963810676353171364781351827612498066026932437346990
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
Job ID: smart:162c905a-543b-48db-bba7-c100583b5958
16.i2c_host_stress_all.758903218483304783391086369028509656168445861331474889899557922081548787824
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_stress_all/latest/run.log
Job ID: smart:59a57992-68a5-434e-a0dc-5a7bfdc5f81f
... and 3 more failures.
Test i2c_host_perf has 1 failures.
28.i2c_host_perf.4912423786411118378938958797490801797019015834713503795739418072124803042582
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_host_perf/latest/run.log
Job ID: smart:f8aeaac3-5989-4c7e-aeea-b38b46b8cfbc
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 6 failures:
0.i2c_target_stretch.88504446684494721515347493296904595172922616699827938396238901832086894057998
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10011497935 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10011497935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.i2c_target_stretch.52687370383198651832855354346556140140869660703963940437702454150546723870144
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10011749172 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10011749172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
24.i2c_host_mode_toggle.5160330242796485035942982496666488354146070645246861823476107536128849575215
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 216968808 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x2acef514, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 216968808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.i2c_host_mode_toggle.115512666508556790066861075166175545839342806542733577945672356226119745645457
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 72342867 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xccb3a694, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 72342867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
2.i2c_target_tx_stretch_ctrl.102581717400648931844845027786374161596026699871132864288305939338400862258177
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
38.i2c_target_tx_stretch_ctrl.17397985859945272216246345215724686990064468268819674792507183766111285666229
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (i2c_target_timeout_vseq.sv:48) [drv_pause] wait timeout occurred! has 2 failures:
3.i2c_target_stress_all_with_rand_reset.104358640187065757836873194879832166598786576454665802909230904156624013011823
Line 512, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 197396072733 ps: (i2c_target_timeout_vseq.sv:48) [drv_pause] wait timeout occurred!
UVM_INFO @ 197396072733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.2384065794635308862283228846601726592860186837893103494272554029389513503244
Line 348, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 17968775675 ps: (i2c_target_timeout_vseq.sv:48) [drv_pause] wait timeout occurred!
UVM_INFO @ 17968775675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:755) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
4.i2c_target_stress_all_with_rand_reset.20419151099879326145769958272310269756025842421135077907580856906382084726583
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1142547347 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1142547347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_stress_all_with_rand_reset.63133251935127594297997831763056340538253359964047975590196061598640299540943
Line 401, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15903612850 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 15903612850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:
38.i2c_host_stress_all.29686595984643379396270986848172384693622340027204507083912471003298704358270
Line 470, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 136291552310 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @41151711
45.i2c_host_stress_all.55991209619928728945903255384013003659162013750511779057184590105050952866223
Line 351, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 79339154803 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @18665899
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
4.i2c_host_stress_all_with_rand_reset.102485856419057047278479519622288462533211559806197182341849997886792298685555
Line 376, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 28711336763 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (4 [0x4] vs 3 [0x3])
UVM_INFO @ 28711336763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:497) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
6.i2c_same_csr_outstanding.18029558771673366804040478514204011783717008913621973599491545886693156505228
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 174878528 ps: (cip_base_vseq.sv:497) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 174878528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
11.i2c_host_stress_all.96152783133814357759639260481904499490285017566096335126941076796428222021120
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Error-[NOA] Null object access has 1 failures:
46.i2c_host_mode_toggle.45031579872467130313355305627762085117425573750167521561108911348073588676761
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.