bbf435ceff| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.855m | 2.252ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 40.830s | 5.415ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.830s | 18.800us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.850s | 41.903us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.520s | 419.621us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.000s | 101.358us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.500s | 32.499us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.850s | 41.903us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.000s | 101.358us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 13.860s | 4.500ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 51.181m | 87.450ms | 21 | 50 | 42.00 |
| V2 | host_maxperf | i2c_host_perf | 55.897m | 50.638ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.780s | 31.747us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.779m | 22.774ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.338m | 2.633ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.420s | 165.983us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 28.210s | 540.003us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 11.890s | 872.194us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.810m | 37.853ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 47.440s | 3.329ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 4.570s | 552.524us | 18 | 50 | 36.00 |
| V2 | target_glitch | i2c_target_glitch | 10.860s | 4.668ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 50.219m | 66.119ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 9.290s | 6.959ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.256m | 6.804ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.330s | 9.119ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.050s | 544.193us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.850s | 313.539us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 26.056m | 51.012ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.256m | 6.804ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 14.096m | 26.284ms | 49 | 50 | 98.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.490s | 3.163ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.105m | 2.683ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 9.250s | 3.867ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 33.650s | 10.015ms | 24 | 50 | 48.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.550s | 629.539us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.710s | 204.586us | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 55.897m | 50.638ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 3.208m | 24.642ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 47.440s | 3.329ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 19.400s | 1.764ms | 48 | 50 | 96.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.360s | 3.022ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.290s | 508.338us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.730s | 199.645us | 26 | 50 | 52.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 31.480s | 3.060ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.660s | 886.824us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.690s | 18.171us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.760s | 27.483us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.610s | 334.734us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.610s | 334.734us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.830s | 18.800us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.850s | 41.903us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.000s | 101.358us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.260s | 60.958us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.830s | 18.800us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.850s | 41.903us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.000s | 101.358us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.260s | 60.958us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1672 | 1792 | 93.30 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.470s | 156.173us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.970s | 338.529us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.470s | 156.173us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 8.117m | 77.797ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.850s | 1.721ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 17.217m | 600.000ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1852 | 2042 | 90.70 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 30 | 61.22 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.32 | 97.30 | 89.65 | 97.22 | 72.62 | 94.40 | 98.44 | 89.58 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 38 failures:
0.i2c_host_mode_toggle.96795639959976551102160677720622002274648817348666245779296742300722593601321
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 84330842 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @14298
1.i2c_host_mode_toggle.18102848327729605623497845875065893130322168976198301975810017182172813281313
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 144624364 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @8004
... and 16 more failures.
1.i2c_host_stress_all.3210318705548929323977336174587658445214210230548388821245176673629055231863
Line 496, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 22503075430 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2429117
3.i2c_host_stress_all.62700820138516611011411286262503698818601733056600421228798823404644859594656
Line 383, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 21358214969 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4784717
... and 18 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 35 failures:
0.i2c_target_unexp_stop.1689211468120854718607424086502070092143828242959982300438925637743074011160
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 443630180 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 68 [0x44])
UVM_INFO @ 443630180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.40404832736616722182792231429443449989057402831071444040859219559188189268303
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 118655515 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 247 [0xf7])
UVM_INFO @ 118655515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 33 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 26 failures:
0.i2c_target_hrst.14202132531495659882827216481919268112147527632808171692429103825342974470339
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10821793625 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10821793625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_hrst.20158029691337396444493799946428661918761730328568986932297600542629510951830
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10415285880 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10415285880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 24 failures:
0.i2c_target_nack_txstretch.115084499666534302877084814970178652560947583811360454289227619924184127088131
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 185929312 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 185929312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_nack_txstretch.24686880968175233328195285623613115524781200017931938009903693424728275764580
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 187201124 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 187201124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
0.i2c_host_stress_all_with_rand_reset.73582939406923576594584972144888560088088809095981685164075160811202355807317
Line 437, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11594467314 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11594467314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.106186076503840447053308086581983873042841215168826434939133780829493620904806
Line 329, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9240090812 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9240090812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
1.i2c_target_stress_all_with_rand_reset.98824335860254597226850645034111066881047002363175255562888461102555318432055
Line 688, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 38225679058 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 38225679058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.90466505789173959987222961032841770015980400655003938082573377341531760624680
Line 273, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3377899823 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3377899823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 10 failures:
1.i2c_target_unexp_stop.47929678674904148464112102227812509432197188322874281386325688372064718494005
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 80369233 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 80369233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.77788546098980685347184535982649096426468093684064485804055067950296842828246
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 30396769 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 30396769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 10 failures:
Test i2c_host_stress_all_with_rand_reset has 1 failures.
7.i2c_host_stress_all_with_rand_reset.98646528206056301095246070590200251530501864001113462206771787092746293250769
Line 270, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4749142943 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
Test i2c_host_mode_toggle has 9 failures.
9.i2c_host_mode_toggle.104733208187661636553229417680788586813723962305806593489683774058585788021699
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 51320653 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
15.i2c_host_mode_toggle.50921335253175564958774568166799601049859537455600536772406173736302150396230
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 73520643 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 5 failures:
0.i2c_host_stress_all.17836208748555171450452496761689852109777436639575420738721560384049912606521
Line 293, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 16205450688 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @7056925
2.i2c_host_stress_all.35375311788639922508706838348577082174914819679666818091664283557918288391976
Line 362, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 15349057672 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3161549
... and 3 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
Test i2c_target_stress_all_with_rand_reset has 2 failures.
0.i2c_target_stress_all_with_rand_reset.99791039483839485809688863921821458355244548429827929482563672155264066502741
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:0d809362-47ee-4c46-911b-236fd111b9fa
2.i2c_target_stress_all_with_rand_reset.60988943095043776054684290926547796467697276218216445054918049582805165805668
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:90108651-fffe-4ffe-a23a-d141e685b6e1
Test i2c_host_stress_all_with_rand_reset has 1 failures.
6.i2c_host_stress_all_with_rand_reset.29391735320192650355245787068658489361025679775072475727084670211264411693842
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:7e84358c-363a-493c-b30e-af7ccd02f2d9
Test i2c_host_stress_all has 2 failures.
8.i2c_host_stress_all.29763124069365420497929803216835479270800547534140617406535969340885558987626
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
Job ID: smart:f7623387-aafc-4e6e-a1dc-cdcf145204bb
41.i2c_host_stress_all.77973058968945926199007963382557210450952363642297280067434416145955699473726
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_host_stress_all/latest/run.log
Job ID: smart:d3899933-eb2d-4d4b-854d-3876a240be72
UVM_FATAL (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 5 failures:
2.i2c_host_mode_toggle.40312831809850372892063280402104551191131523319063123472711334197461279730397
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 71172526 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x585dd914, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 71172526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.i2c_host_mode_toggle.98168513283197847225867001069256536087469704530740813427438467647187495625756
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 179856195 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x3d99f414, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 179856195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
10.i2c_target_stretch.113614409484859366751452799760867975313863202189162182770550031845582508594612
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10005998130 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10005998130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_stretch.43648599855263663690665846693148047592495038732520739919296442341678739459889
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10004634281 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10004634281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 5 failures:
25.i2c_target_unexp_stop.28223023344346018058763186803372749787977021228460294702465669698497242784004
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 215625346 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 215625346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.i2c_target_unexp_stop.75043258337641630858153403527255432365928837044205199914612216196578991760562
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 2976820415 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 2976820415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
6.i2c_target_stress_all_with_rand_reset.103840557915615501537203591695524312405011313940228068980270834585436665296254
Line 546, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_stress_all has 1 failures.
22.i2c_host_stress_all.112411790993101259460661915658462566110021581606684540176398039567516555820624
Line 306, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
12.i2c_target_tx_stretch_ctrl.36437808412757804488508610071758678008283899011035664051649834177958457866033
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
33.i2c_target_tx_stretch_ctrl.30188169599304718593038323419344187100728291957906439175393858197164803884251
Line 305, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (cip_base_vseq.sv:755) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
9.i2c_target_stress_all_with_rand_reset.63126217065787915750378225894148036266200437855269110082611633967314947002611
Line 456, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 75080963035 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 75080963035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
10.i2c_target_intr_stress_wr.39402013829605461392905696462386424354001746302138966417411196696137345322527
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 42651019882 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 42651019882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:497) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
16.i2c_same_csr_outstanding.83245753654720871530779479651988834545006551699555561059983349722810207421468
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 158202385 ps: (cip_base_vseq.sv:497) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 158202385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
21.i2c_host_stress_all.31708368483949262101633155312735064562617204801126318545669308340863228076992
Line 332, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 17882253851 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------