3707c48f56| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.758m | 4.310ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 46.560s | 6.381ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.830s | 19.448us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.830s | 20.325us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.950s | 2.479ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.920s | 412.043us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.540s | 428.956us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.830s | 20.325us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.920s | 412.043us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 13.670s | 1.371ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 56.044m | 600.000ms | 17 | 50 | 34.00 |
| V2 | host_maxperf | i2c_host_perf | 18.478m | 26.270ms | 47 | 50 | 94.00 |
| V2 | host_override | i2c_host_override | 0.760s | 29.109us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.539m | 28.101ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.225m | 10.632ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.330s | 202.713us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 33.730s | 599.058us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.740s | 420.142us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.659m | 3.741ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 43.640s | 1.858ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 6.900s | 185.373us | 24 | 50 | 48.00 |
| V2 | target_glitch | i2c_target_glitch | 12.240s | 9.920ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 55.065m | 62.555ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 7.870s | 4.132ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.174m | 2.481ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.540s | 1.437ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.790s | 275.004us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.970s | 318.972us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 51.341m | 64.234ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.174m | 2.481ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 19.320m | 32.504ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.140s | 5.784ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.623m | 4.154ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.260s | 1.276ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 34.690s | 10.069ms | 30 | 50 | 60.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.850s | 1.404ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.610s | 312.690us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 18.478m | 26.270ms | 47 | 50 | 94.00 |
| i2c_host_perf_precise | 4.608m | 24.505ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 43.640s | 1.858ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 9.020s | 627.394us | 47 | 50 | 94.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.260s | 608.544us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.280s | 564.604us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.700s | 628.246us | 29 | 50 | 58.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 26.020s | 607.363us | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.790s | 587.161us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.680s | 15.797us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.800s | 19.305us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.860s | 134.078us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.860s | 134.078us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.830s | 19.448us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 20.325us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.920s | 412.043us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.230s | 208.047us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.830s | 19.448us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 20.325us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.920s | 412.043us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.230s | 208.047us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1679 | 1792 | 93.69 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.430s | 146.758us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.920s | 72.422us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.430s | 146.758us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 14.631m | 107.467ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 4.820s | 1.134ms | 1 | 50 | 2.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 10.737m | 51.575ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 1 | 70 | 1.43 | |||
| TOTAL | 1860 | 2042 | 91.09 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.46 | 97.37 | 89.65 | 97.22 | 73.21 | 94.54 | 98.44 | 89.79 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 37 failures:
0.i2c_host_stress_all.96533039005727125038021493527568809901986720441858786298436639732423565848392
Line 438, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 42335502774 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @920533
2.i2c_host_stress_all.106394334120303328711398208184653529026315797520283411346785051821384041569882
Line 399, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 20546982422 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5230785
... and 23 more failures.
16.i2c_host_mode_toggle.87737795417608697267907864364612855519216756192106588374712774269979033126149
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 118952664 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @27668
18.i2c_host_mode_toggle.80401992887481915862591940057123328661900638435093784673219768127092706935742
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 180427942 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @13488
... and 10 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 27 failures:
0.i2c_target_unexp_stop.20987929791793554402598771222952770652669546468493470707622149643847900393124
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 243766307 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 180 [0xb4])
UVM_INFO @ 243766307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.96146410700322074524722209564572289586402197272529888797877575690634777416267
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 189011748 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 106 [0x6a])
UVM_INFO @ 189011748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
5.i2c_target_stress_all_with_rand_reset.64414125400607022784184508869270834349005963121884262342064653579026070455655
Line 533, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 20167819286 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 204 [0xcc])
UVM_INFO @ 20167819286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 21 failures:
0.i2c_target_nack_txstretch.48179232869325648464672156076902228632183524123635976122000772000666168292158
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 1443639719 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 1443639719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_nack_txstretch.40363443796008801822827106674471630910910085469913130296647852814031536748713
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 198595398 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 198595398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 20 failures:
1.i2c_target_hrst.57208617441008942243679321499155744463331795891595030572759980803051669392116
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10175160608 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10175160608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_hrst.57647554596407155823290079023870165601524898023292831015090247646985711425208
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10062377653 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10062377653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 20 failures:
4.i2c_target_unexp_stop.39643512652567389531080662974470524359312540202060267178809697609991853402203
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 92525301 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 92525301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.26432186702082618261477128466769355302049567885476710573642571572388581886139
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 54965500 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 54965500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
0.i2c_host_stress_all_with_rand_reset.51197560459815848794602232775524564725981768462837896513140876331136777341192
Line 293, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9601848196 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9601848196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.22353199195800033067309248370308504917230662856271603672959542941547653094111
Line 288, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12356127793 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12356127793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.60260153385214765872048485783977527974324820293357305700918926445422887346627
Line 374, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 39328601748 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 39328601748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.25275002213547418564383009667642874282484117848779393391801682699490376447804
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 719712729 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 719712729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 10 failures:
3.i2c_host_mode_toggle.42757621128608771427130894097866359161880601975616559505155989324978442003136
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 41053196 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
10.i2c_host_mode_toggle.94740502970297460603862963597834508521035391355048619047500336398843705010805
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 86141696 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 8 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
1.i2c_host_perf.80275013547902964232262788930498755308036662580044125961402055579922960127086
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_perf/latest/run.log
Job ID: smart:042d71ec-078f-4b99-86f3-c58c88947b1d
5.i2c_host_perf.66678885963480546936275203665904522340523619683445906962417666042024126827891
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_perf/latest/run.log
Job ID: smart:84115fcd-a665-4049-a5c2-cdf722eecbb0
... and 1 more failures.
8.i2c_host_stress_all.111652709273664999873489764854258610792853208596063745417744649427856383713900
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
Job ID: smart:336e1b04-0af3-4412-b7b0-4f99fa25c6fb
16.i2c_host_stress_all.63300040467153457576718205317718744533835213843532685066622620961985077113855
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_stress_all/latest/run.log
Job ID: smart:d21fc9c5-0fa2-4512-be9b-b41ca3a68701
... and 2 more failures.
11.i2c_target_stress_all.91278634907503185537793156323299368814907937732677969814188692017594488389109
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
Job ID: smart:aa534dec-8aad-496c-9d79-2a416b05e56a
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
0.i2c_target_stretch.79929920478412277634201917677411849529891033468377145744502221092183632520603
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10011247282 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10011247282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stretch.16807341935251518917722773505894758002614951181252626199724597603766453120233
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10052392711 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10052392711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
24.i2c_target_tx_stretch_ctrl.60244969381391004803167821775163026091773827700521193376053608011919368154997
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
33.i2c_target_tx_stretch_ctrl.26547515691446594864649197406796988309235522874528825646038037387607453597452
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 1 more failures.
47.i2c_target_fifo_watermarks_tx.55755903739477302179408696354601809280851710232389819886058244227143886566924
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
5.i2c_host_mode_toggle.98025359222709048378173333985555716444994072997098710511464079230407009734432
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 38718428 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xf6b40494, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 38718428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_host_mode_toggle.69779416433256155465577642685026395732385124106888318413367534318200112236994
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 203498944 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xc1d9414, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 203498944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 3 failures:
7.i2c_target_unexp_stop.54564633969604591745459819713770635291059330812478827343053670987371251175256
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 233838164 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 233838164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_unexp_stop.84877894051775832778133690049462699113879579329705383569534356486957678525044
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 2151548580 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 2151548580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:
17.i2c_host_stress_all.66650218133991062423058416502445323658973038061603911700605741995318281539507
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 7733836506 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1990645
35.i2c_host_stress_all.93856265945913007306218973768588712873188622347911825876094624076446892553520
Line 502, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 120369396108 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @73853751
... and 1 more failures.
Exit reason: Error: User command failed Error-[NOA] Null object access has 1 failures:
4.i2c_host_mode_toggle.96893654222827786496428583175885974810748350145078272914549876006051163021767
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
14.i2c_host_stress_all.61152831128187232327062093614539034468423413684939449849079946263812490833640
Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:497) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
19.i2c_same_csr_outstanding.13788246002868518179712910992549806996305822998046981585819866918285418695491
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 169597338 ps: (cip_base_vseq.sv:497) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 169597338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---