07b417ef03| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.686m | 2.159ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 41.590s | 2.807ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.810s | 20.013us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.790s | 27.983us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.000s | 1.442ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.880s | 192.610us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.240s | 25.915us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.790s | 27.983us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.880s | 192.610us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 33.270s | 1.438ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 52.367m | 92.929ms | 14 | 50 | 28.00 |
| V2 | host_maxperf | i2c_host_perf | 22.707m | 12.425ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.750s | 52.230us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.481m | 10.165ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.495m | 2.642ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.280s | 901.593us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 33.070s | 620.314us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.610s | 221.061us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.401m | 3.563ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 51.370s | 4.955ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 8.120s | 849.842us | 14 | 50 | 28.00 |
| V2 | target_glitch | i2c_target_glitch | 11.200s | 2.024ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 57.394m | 55.910ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 7.630s | 1.991ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.406m | 1.620ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 7.670s | 1.296ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.670s | 249.275us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.980s | 1.116ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 47.662m | 63.499ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.406m | 1.620ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 11.868m | 23.426ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.700s | 1.395ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.719m | 3.158ms | 48 | 50 | 96.00 |
| V2 | bad_address | i2c_target_bad_addr | 8.320s | 3.319ms | 49 | 50 | 98.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 33.660s | 10.160ms | 22 | 50 | 44.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.480s | 4.214ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.710s | 204.317us | 47 | 50 | 94.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 22.707m | 12.425ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 28.450m | 24.341ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 51.370s | 4.955ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 16.070s | 1.299ms | 47 | 50 | 94.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.380s | 738.679us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.020s | 586.974us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.690s | 196.249us | 36 | 50 | 72.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 31.810s | 762.716us | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.760s | 595.035us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.700s | 34.602us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.730s | 20.474us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.570s | 640.030us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.570s | 640.030us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.810s | 20.013us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.790s | 27.983us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.880s | 192.610us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.190s | 94.829us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.810s | 20.013us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.790s | 27.983us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.880s | 192.610us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.190s | 94.829us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1667 | 1792 | 93.02 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.390s | 148.872us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.980s | 480.165us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.390s | 148.872us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 6.531m | 60.290ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 3.430s | 2.228ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 12.454m | 99.884ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1847 | 2042 | 90.45 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.20 | 97.15 | 89.46 | 97.22 | 72.02 | 94.11 | 98.44 | 90.00 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 44 failures:
0.i2c_host_stress_all.100552079549608240526393027022988537111692257660343886866037593960844016522571
Line 399, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 86811478295 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @6172843
1.i2c_host_stress_all.34423035646304309436583977157476292753674377807818570052042148905808727817684
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 31238845758 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1585365
... and 25 more failures.
0.i2c_host_mode_toggle.49829078047530098519759771953321438881508602373117045608656249760592985509316
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 107846983 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @17568
7.i2c_host_mode_toggle.72340119528132038843044562341335862269691920666575176598261703594761632919417
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 379116033 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @11078
... and 15 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 28 failures:
0.i2c_target_hrst.71722390765470826376607460570998139607094914778823924145242988969463654958610
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10066096713 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10066096713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_hrst.63237929646907354690038181177664779140904721399642730448383146126935090379499
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10354013871 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10354013871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 27 failures:
0.i2c_target_unexp_stop.69130720954621237619958864106323039876879471954373209457700523138737468558098
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 558322799 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 21 [0x15])
UVM_INFO @ 558322799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.44880196227837284858824611095656907228424956634439150976792706061089364221984
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 2228380602 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 198 [0xc6])
UVM_INFO @ 2228380602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
8.i2c_target_stress_all_with_rand_reset.61205319435978826676109596683911466575543826443525709060855740604096414196531
Line 542, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 22303754678 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 184 [0xb8])
UVM_INFO @ 22303754678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 17 failures:
1.i2c_target_unexp_stop.79145042789353864035042181520014077266629922544705567531620453941031586455251
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 361591369 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 361591369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.40695231074433919668554102655802716847553199681862521153832097002224599179447
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 246132880 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 246132880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 17 failures:
1.i2c_host_mode_toggle.73061088225688098442432326558212404362451971218824851408533093508889677162029
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 22522848 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
4.i2c_host_mode_toggle.62291265278223227567873019119745318743663772610779408899856791448917903600544
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 435842302 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 15 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
0.i2c_target_nack_txstretch.14093457569536876716905116596039316643967566167598039377051139556926111544254
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 610620609 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 610620609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_nack_txstretch.48786211407503179457650239210272080297412761548101146011661700133222865717661
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 187614795 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 187614795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
0.i2c_host_stress_all_with_rand_reset.37158957587611497303539824176114896011547778638076250237727391947352413641947
Line 427, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 60290340320 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 60290340320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.40780030097035770802922808237232053757932619034405385862128624530428844247352
Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 836369638 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 836369638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
0.i2c_target_stress_all_with_rand_reset.26297648541644930114717399595135596856618048855630662242002635613682577850545
Line 370, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13384011292 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 13384011292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.837663269719634400372835546135977143511008692063546854065866760024970289644
Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 645553044 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 645553044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
Test i2c_host_stress_all has 4 failures.
2.i2c_host_stress_all.37770057643636885552464460807345834792575094420647997021778830588949450706311
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
Job ID: smart:41b695be-e4a0-442d-8bb4-07f94bcc69c8
6.i2c_host_stress_all.113140885825531515682761024159829076130149409430533445222349034395078137928510
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
Job ID: smart:71da7b56-d916-4106-858f-8f29343eedbc
... and 2 more failures.
Test i2c_target_stress_all_with_rand_reset has 2 failures.
3.i2c_target_stress_all_with_rand_reset.6043552827855049813233701886695853393890851252647004452032942355023238512754
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:afc4643e-5745-43f5-84c5-284f964dbe0f
6.i2c_target_stress_all_with_rand_reset.79726378646347110425366161944550572689667427261523783350083209051441877588938
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:92eddd8d-3994-4f00-960c-2de1d5febb86
Test i2c_host_stress_all_with_rand_reset has 2 failures.
4.i2c_host_stress_all_with_rand_reset.23366662006492838051267409693228316151290748433712618343199944831439591618854
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:4e365a17-d5a0-4a27-af49-6c7a55e4dd3b
8.i2c_host_stress_all_with_rand_reset.106681164537999544837496588694486720686602819320176104869608948498198899145770
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:ec0f44f1-d04a-49f4-bdd6-dc04eb412d00
Test i2c_host_perf_precise has 1 failures.
8.i2c_host_perf_precise.38717020546889096887888627656408332208500244616321315054986998201114467147780
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_perf_precise/latest/run.log
Job ID: smart:871865ba-fe54-40a9-a5d0-e0d8c32d9d37
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 7 failures:
4.i2c_target_unexp_stop.77738500264106003727789421791965156244125436519201548528899312612111781367724
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 491740198 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 491740198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_target_unexp_stop.38365392025219069418627351809649474208506211570914911765443511604510401112493
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 529067629 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 529067629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 6 failures:
2.i2c_target_tx_stretch_ctrl.82896294384098261247662646343093151048371783822004266673880958355289817254672
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
11.i2c_target_tx_stretch_ctrl.107833488391517432047789742673357200289141621738674087433831807291840574015800
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 1 more failures.
16.i2c_target_fifo_watermarks_tx.49862143514590717031804078293986760268353119920096306134732603311459955583783
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
37.i2c_target_fifo_watermarks_tx.102284415684008710284816677069610489062096813079903921241987159589537585527622
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:
23.i2c_host_stress_all.7571955122728492786085791324637986629719453125774197915792499733008149669066
Line 507, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 51470844621 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3722745
31.i2c_host_stress_all.35320968937189498274671058560341611200163495021525613653986295383049040236099
Line 364, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 46231351114 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3553515
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test i2c_host_stress_all has 2 failures.
32.i2c_host_stress_all.34226392948740154103800745403647579461889751568494981203512822497065047738080
Line 345, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.i2c_host_stress_all.72214110334549465098535126130278673407327106051804310800136786970258760453903
Line 453, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_bad_addr has 1 failures.
48.i2c_target_bad_addr.18067538305095566250097129605515434820725579215440787414040663863804720427055
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 2 failures:
26.i2c_target_stretch.36139946699938608955997498325304521476687081887218543230973381020076745362553
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10010690746 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10010690746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.i2c_target_stretch.30113717401268989168378440781181572256816098679822666195642740699212382125028
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10004452142 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10004452142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
29.i2c_host_mode_toggle.94025628872220621587763470468723954273366925743922374317867151582740386371402
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 99777663 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xf2bf2414, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 99777663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.i2c_host_mode_toggle.73494759236521172443200937506576894254849926152643355998932229056111288704437
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 79675254 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xd4909f14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 79675254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:755) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
4.i2c_target_stress_all_with_rand_reset.25758765787224057353296282884797668814851752197441954551049416729950977051312
Line 482, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 99883741909 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 99883741909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
5.i2c_host_stress_all_with_rand_reset.15172452608361264291131185574419311127619576999983245949446609388964286216138
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2610766500 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (6 [0x6] vs 3 [0x3])
UVM_INFO @ 2610766500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
19.i2c_target_stress_all.39592464772690505769827177289132481857801245357521694758803225399790089222160
Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 70560799300 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 70560799300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---