07b417ef03| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.710m | 3.805ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 43.060s | 2.767ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.810s | 27.812us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.780s | 81.678us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.930s | 6.968ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.010s | 193.961us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.440s | 33.216us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.780s | 81.678us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.010s | 193.961us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 15.580s | 782.447us | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 59.060m | 35.559ms | 14 | 50 | 28.00 |
| V2 | host_maxperf | i2c_host_perf | 30.378m | 33.130ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.740s | 28.282us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.981m | 25.583ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.372m | 5.252ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.370s | 146.818us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 31.750s | 1.176ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.440s | 228.593us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.803m | 3.766ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 42.490s | 896.483us | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 7.490s | 374.150us | 20 | 50 | 40.00 |
| V2 | target_glitch | i2c_target_glitch | 11.290s | 2.174ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 55.329m | 66.877ms | 48 | 50 | 96.00 |
| V2 | target_maxperf | i2c_target_perf | 8.340s | 4.413ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.442m | 3.489ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.890s | 3.233ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.920s | 286.228us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.850s | 280.640us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 42.580m | 63.437ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.442m | 3.489ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 6.910m | 20.861ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 7.970s | 2.799ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.662m | 4.433ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.780s | 5.180ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 36.130s | 10.004ms | 24 | 50 | 48.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.500s | 2.890ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.650s | 288.122us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 30.378m | 33.130ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 28.898m | 24.334ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 42.490s | 896.483us | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 13.120s | 1.083ms | 47 | 50 | 94.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.290s | 2.656ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.100s | 1.529ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.760s | 153.962us | 37 | 50 | 74.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 38.520s | 3.598ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.770s | 6.968ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.710s | 31.007us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.780s | 20.260us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.830s | 463.424us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.830s | 463.424us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.810s | 27.812us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.780s | 81.678us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.010s | 193.961us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.260s | 142.933us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.810s | 27.812us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.780s | 81.678us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.010s | 193.961us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.260s | 142.933us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1674 | 1792 | 93.42 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.360s | 265.242us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.010s | 69.027us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.360s | 265.242us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 14.645m | 9.350ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 3.310s | 1.584ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 12.647m | 67.664ms | 1 | 10 | 10.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 1 | 70 | 1.43 | |||
| TOTAL | 1855 | 2042 | 90.84 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.26 | 97.21 | 89.65 | 97.22 | 72.02 | 94.26 | 98.44 | 90.00 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 40 failures:
2.i2c_host_mode_toggle.38013027776711780446445676090553223004217416716986336612328670440933652358296
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 59936113 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @10334
12.i2c_host_mode_toggle.33234817422340335871122898662430877135679478197901393495573638876976975221403
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 203153382 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @52572
... and 11 more failures.
3.i2c_host_stress_all.2134934862730144160024786280577054885514435399273397875722771197022458473535
Line 381, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 32340661574 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @8227223
4.i2c_host_stress_all.29739296371877078869467602819304578754851094039862164075964680909043945509119
Line 328, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 108129067554 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @9912121
... and 25 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 32 failures:
0.i2c_target_unexp_stop.18196418791897068803814798458766405792731099460235151869042409723364735026232
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 320469732 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 30 [0x1e])
UVM_INFO @ 320469732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.75848880182081731273246705975202019010350188806880621074334440507607428801071
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 168774923 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 59 [0x3b])
UVM_INFO @ 168774923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 26 failures:
0.i2c_target_hrst.46762703850759905791680973440295542802223876993088507583530476551258665688972
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10008037508 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10008037508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_hrst.114346316231323698748010728465239648187037851630682457264622449966244576972823
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10155008308 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10155008308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
0.i2c_host_stress_all_with_rand_reset.108581062186430288734980465557128445480311165472751806912146832153792033292375
Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 910039205 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 910039205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.77080659187299235247040570381462441347909622127063248541171461193213024809061
Line 270, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 981788261 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 981788261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
1.i2c_target_stress_all_with_rand_reset.72543486249714703687774852579830553861112147933500717150481735963211155346494
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27118771793 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 27118771793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.8338393433405226741906071213049689862784045575969939551546880582161643894832
Line 363, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 72942926186 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 72942926186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 13 failures:
1.i2c_host_mode_toggle.108097243918301436774079258123137361919735244000033823673701288389033031795843
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 121574156 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
3.i2c_host_mode_toggle.42187944177866294966708996076330438080752216236565673985165249855100372319603
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 74016556 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 11 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 13 failures:
1.i2c_target_nack_txstretch.37644047875157660623509527382686399640238934737428382510475411597633322725744
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 623697485 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 623697485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_nack_txstretch.15101589331087851271359547340711961379405843835680843431666568708220571919465
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 123614020 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 123614020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
1.i2c_host_stress_all.52302790130090907508985424476897163789687981012937421459892665250303060199787
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:dd6cbbc3-c453-426a-a9c4-81d6dada4e4d
13.i2c_host_stress_all.101342569933798080797151304483650871552635584446912951203868200480098191655898
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_stress_all/latest/run.log
Job ID: smart:104f16da-3d73-49f2-8723-fed5b637b09a
... and 4 more failures.
3.i2c_target_stress_all_with_rand_reset.71000318195750809879880927480603005135607387236909680463647769900958452930692
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:3ae3877b-347e-4b80-9b57-a94cf351aaf3
8.i2c_target_stress_all_with_rand_reset.27831876479492584865816966052459364998006158603229038909438215603293779506526
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:4866ffc0-9d4c-4259-b19c-d79063afbf31
... and 1 more failures.
25.i2c_host_error_intr.102033842273819500839299910745061287550021418728601718351782899790797164687686
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_host_error_intr/latest/run.log
Job ID: smart:fb90e0c7-a21f-4f1d-8c9f-02508f47f14e
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 9 failures:
1.i2c_target_unexp_stop.71162458049995298658985213532858638756533069819036102898846841736781921108115
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 133222561 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 133222561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_unexp_stop.3187147238378058947429731916053417598845931704664178073844546838484991085684
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 175674946 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 175674946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 9 failures:
6.i2c_target_unexp_stop.62315484577214073392281055392631163641977973600892562042312608579125570962537
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 2715383052 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 2715383052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_unexp_stop.10543620598439071306831802977521419604834868190357739377438374483335686499719
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 328288535 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 328288535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
0.i2c_target_stretch.19579973071967414914565491217214528135825433186794890285829334686750935202138
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10009572975 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10009572975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stretch.73757822613469633133207167977194218239124926400343462084967364734449158454342
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10051886193 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10051886193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
16.i2c_target_tx_stretch_ctrl.65185044314548111459130270761540086216003787278743345616917733116315904837894
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
20.i2c_target_tx_stretch_ctrl.8915769011378915207174416640794515034567961781682893751149377514255651734210
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 1 more failures.
36.i2c_target_fifo_watermarks_tx.43493375191644587949086756250953155428364257351828956672070260316061007704091
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:
0.i2c_host_stress_all.51922611316131655687510128424667383364043321583443805147696166430440891339565
Line 349, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 33932503826 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @7335715
28.i2c_host_stress_all.73950384148193183531976064510888153003768054255594811405904790092853026422085
Line 383, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 71822946469 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @8392503
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
20.i2c_host_mode_toggle.36130058536806997992448718684851223534570102331566256180254795356028456564504
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 226059148 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x72125a14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 226059148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.i2c_host_mode_toggle.72740504871075375951882185754361676045444092261124927879668613613910346770314
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 38450046 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x5d028114, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 38450046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
38.i2c_target_stress_all.52165801633551284015589388823342897681653112809160510131520088203399815235359
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 45900185314 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 45900185314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.i2c_target_stress_all.84232006981978964332728081042644369434193725654449419122806246456352457180290
Line 279, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 24905906734 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 24905906734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Error-[NOA] Null object access has 1 failures:
6.i2c_host_mode_toggle.20886923662145381253872200188854349667359143804346337354680518977197582187961
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
35.i2c_host_perf_precise.32804836515661836330756401447059244319564311302624049697040612740593365120887
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_host_perf_precise/latest/run.log
UVM_ERROR @ 98146518 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------