07b417ef03| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.562m | 1.907ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 47.720s | 1.742ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.790s | 27.509us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.820s | 26.038us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.510s | 5.735ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.090s | 96.951us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.470s | 33.503us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.820s | 26.038us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.090s | 96.951us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 10.340s | 414.235us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 58.295m | 126.840ms | 17 | 50 | 34.00 |
| V2 | host_maxperf | i2c_host_perf | 59.568m | 49.619ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 0.760s | 112.566us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.423m | 26.739ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.264m | 10.519ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.400s | 644.014us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 33.030s | 1.674ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 10.750s | 1.991ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 5.097m | 13.969ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 46.230s | 1.017ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 6.460s | 168.462us | 18 | 50 | 36.00 |
| V2 | target_glitch | i2c_target_glitch | 12.740s | 2.666ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 47.170m | 64.326ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 7.500s | 3.879ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.392m | 29.789ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.900s | 1.789ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.880s | 256.476us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.860s | 2.694ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 46.139m | 68.762ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.392m | 29.789ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 15.952m | 28.882ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.150s | 1.426ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 3.195m | 3.652ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 8.170s | 6.073ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 34.300s | 10.163ms | 23 | 50 | 46.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.560s | 1.238ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.620s | 579.459us | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 59.568m | 49.619ms | 48 | 50 | 96.00 |
| i2c_host_perf_precise | 29.865m | 23.144ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 46.230s | 1.017ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 9.450s | 760.608us | 46 | 50 | 92.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.350s | 614.573us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 2.990s | 2.223ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.790s | 366.756us | 29 | 50 | 58.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 35.890s | 843.838us | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.680s | 531.108us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.720s | 16.024us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.730s | 14.524us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.030s | 302.449us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.030s | 302.449us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.790s | 27.509us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 26.038us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.090s | 96.951us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.240s | 202.366us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.790s | 27.509us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.820s | 26.038us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.090s | 96.951us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.240s | 202.366us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1667 | 1792 | 93.02 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.380s | 191.238us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.960s | 59.711us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.380s | 191.238us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 17.617m | 22.109ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.210s | 618.486us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 7.674m | 34.518ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1847 | 2042 | 90.45 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 30 | 61.22 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.28 | 97.21 | 89.46 | 97.22 | 72.02 | 94.26 | 98.44 | 90.32 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 37 failures:
0.i2c_host_stress_all.4774298428844375674674123551722765189270750477548856984252744428104094953834
Line 368, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 27474169199 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @458493
3.i2c_host_stress_all.20416893206541668621651711904229931104195440283522898794061265875924930820116
Line 388, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 65190614580 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3417875
... and 19 more failures.
3.i2c_host_mode_toggle.3340417212939418819573473093362946295341560310366714774354745618949748833812
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 290778225 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @18544
4.i2c_host_mode_toggle.109920784821289316758138907270078718858794209402966461742983597972374372383855
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 82987024 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @15820
... and 14 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 32 failures:
1.i2c_target_unexp_stop.6002960053960700875780398128782300505050042435260856884777382540502398970579
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 130820886 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 243 [0xf3])
UVM_INFO @ 130820886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.41907009302308763080565706331853104684896805511975162899167897297315315760627
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 113021742 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 27 [0x1b])
UVM_INFO @ 113021742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
1.i2c_target_stress_all_with_rand_reset.62304557385260976177267135910524837071941267636945602502497221658190925174465
Line 270, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 99397403 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 16 [0x10])
UVM_INFO @ 99397403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.100593137379760636149787452702070294637167325273339781611650267241161942594464
Line 426, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8881438339 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 20 [0x14])
UVM_INFO @ 8881438339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 27 failures:
0.i2c_target_hrst.13929769496440126204667014928139913686171049567237502252639629412374953021179
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10047503778 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10047503778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_hrst.108211167057279491835407504358593871872548695738794878552768135960080038499748
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10301981880 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10301981880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 21 failures:
3.i2c_target_nack_txstretch.26137631589350115824402161848450612106471537414567309180808286989377018699061
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 702467240 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 702467240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_nack_txstretch.32913123559347994327627712824507065285849507754543950606377541525155594640152
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 423451506 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 423451506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
0.i2c_host_stress_all_with_rand_reset.55906867986986966046348939508783729178649143988353038222329733301548717394079
Line 583, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 22109336275 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 22109336275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.69378860162904115706781369971135351436043895721534500848387643629781150048173
Line 287, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5918730571 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5918730571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
0.i2c_target_stress_all_with_rand_reset.109916808583784851913876007167025181633448393882795232113176770586182329500463
Line 328, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 30287342472 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 30287342472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.47065134536635784547177580825432954626469594063294500706797728133362451193679
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2377205113 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2377205113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 14 failures:
0.i2c_host_mode_toggle.103216035818307618158918306181781079961329350069534822091910120716641090408526
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 68407244 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
1.i2c_host_mode_toggle.107765918564531842215311757002680443634914476453178098923371658892108927607552
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 232797310 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 12 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 11 failures:
0.i2c_target_unexp_stop.46129173433972851570615031287859220333579105505431099743104406426984894361923
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1083961428 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1083961428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.46003653216312660761164769701963587803840698056120281963405213028364388365539
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1763500091 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1763500091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
Test i2c_host_stress_all_with_rand_reset has 1 failures.
4.i2c_host_stress_all_with_rand_reset.3057788065852044124753823336891043806148186029161408102642370005446980185876
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:d009ab77-4465-46c1-8903-cfb29967f487
Test i2c_target_stress_all_with_rand_reset has 1 failures.
5.i2c_target_stress_all_with_rand_reset.86750088068277538937239650237611655149330701533188191634498797612590857898935
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:625d1270-ec95-4909-a6f8-53f626441786
Test i2c_host_perf has 2 failures.
7.i2c_host_perf.67969837146708011404529086539462646018208314219761756822166287032374628768048
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_perf/latest/run.log
Job ID: smart:f27751e6-e4b0-4e82-9105-eb61a72fd10d
17.i2c_host_perf.65620954070806256214436763155567802741366979809911812379288252312890291856529
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_perf/latest/run.log
Job ID: smart:7316e516-af2c-4c8e-895d-8191fb8d0a69
Test i2c_host_stress_all has 7 failures.
7.i2c_host_stress_all.37033916561645301094833670479733813965360086344968084788384770416137971018316
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
Job ID: smart:178a1a8a-be85-4719-b62a-1e5a61e26d44
9.i2c_host_stress_all.115320088151069176431966351221707824252970158039846811966855496930591375708388
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
Job ID: smart:5a011e9a-28ab-472f-b10c-3616621a4c81
... and 5 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 10 failures:
2.i2c_target_unexp_stop.8777918219538258345093116695786757214637957423982839879804521224078025947269
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 113479453 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 113479453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_unexp_stop.80735498792645305991498380232890264823239586173578393417736353565561415669330
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 207620470 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 207620470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
13.i2c_target_stretch.57587858028379250730215633380633086616087984403613524887365019262610431326985
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10005019794 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10005019794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.i2c_target_stretch.38720727083889118472412207463298777492028000291599900969521475237528838099481
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10023249745 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10023249745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
10.i2c_target_tx_stretch_ctrl.84866323579113784013074131665462496331879749403443724052767820617884913440097
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
15.i2c_target_tx_stretch_ctrl.92505642510644640310734384957163010953158988869678934448129891071705284221144
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:
5.i2c_host_stress_all.28341542234499061765225634198705487431518476997085049979734490607486382704313
Line 377, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 14757259126 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4146921
32.i2c_host_stress_all.15279906430915840240067380833550185957937780814725777712553094608580170392352
Line 295, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 43971924188 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @25064733
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
20.i2c_host_mode_toggle.84733087100187460794454402168303882912507956767358989020903248564571153581905
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 157487545 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xa9499a94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 157487545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.i2c_host_mode_toggle.22497866215438339744953407159740418220948627946068979030967907189979127077246
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 231911354 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x701b994, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 231911354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
1.i2c_host_stress_all.18024812253289026717206514868098978754086417726939155316379847982161847983819
Line 299, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:755) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
3.i2c_target_stress_all_with_rand_reset.6170296156918918344051284929613872293028931623838609172630608165828200790728
Line 308, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13229418358 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 13229418358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:497) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
7.i2c_same_csr_outstanding.63971132182535475210912104547099392263109067139012931167567648910778885088903
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 59504333 ps: (cip_base_vseq.sv:497) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 59504333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3172) has 1 failures:
36.i2c_host_stress_all.3711819855528388717849218081540953401403402712054032202648754648719370926667
Line 434, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 159996286640 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=0xc7c1b794, Comparison=CompareOpEq, exp_data=0x0, call_count=3172)
UVM_INFO @ 159996286640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---