c082b8981f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.717m | 2.167ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 46.890s | 7.401ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.810s | 49.659us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.790s | 33.846us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.020s | 3.480ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.880s | 303.943us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.670s | 151.560us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.790s | 33.846us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.880s | 303.943us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 10.560s | 590.033us | 48 | 50 | 96.00 |
| V2 | host_stress_all | i2c_host_stress_all | 41.222m | 25.730ms | 17 | 50 | 34.00 |
| V2 | host_maxperf | i2c_host_perf | 39.069m | 48.678ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.740s | 30.487us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.781m | 5.061ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.394m | 5.272ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.430s | 186.064us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 26.370s | 918.192us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.120s | 845.546us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.976m | 8.896ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 41.160s | 3.532ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 6.630s | 508.646us | 16 | 50 | 32.00 |
| V2 | target_glitch | i2c_target_glitch | 11.210s | 4.765ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 57.568m | 72.499ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 9.310s | 1.193ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.225m | 6.613ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 10.080s | 6.375ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.710s | 425.228us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.790s | 323.499us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 52.432m | 63.932ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.225m | 6.613ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 19.005m | 31.596ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.760s | 1.745ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 3.932m | 4.331ms | 44 | 50 | 88.00 |
| V2 | bad_address | i2c_target_bad_addr | 7.240s | 1.422ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 32.590s | 10.177ms | 20 | 50 | 40.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.700s | 1.377ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.800s | 780.734us | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 39.069m | 48.678ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 15.048m | 600.000ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 41.160s | 3.532ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 22.580s | 2.001ms | 49 | 50 | 98.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.310s | 608.825us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.070s | 1.131ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.790s | 541.445us | 35 | 50 | 70.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 37.130s | 1.801ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.760s | 594.792us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.740s | 70.692us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.760s | 22.663us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.000s | 131.542us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.000s | 131.542us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.810s | 49.659us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.790s | 33.846us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.880s | 303.943us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.200s | 49.760us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.810s | 49.659us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.790s | 33.846us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.880s | 303.943us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.200s | 49.760us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1669 | 1792 | 93.14 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.310s | 176.197us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.990s | 79.896us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.310s | 176.197us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 1.027m | 4.400ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 1.930s | 2.014ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 32.090s | 851.847us | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1849 | 2042 | 90.55 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 29 | 59.18 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.14 | 97.15 | 89.39 | 97.22 | 71.43 | 94.11 | 98.44 | 90.21 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 38 failures:
3.i2c_host_stress_all.25430798980528517811369603608797186616772463985885630743670234214476073989950
Line 462, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 5572766200 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4657405
6.i2c_host_stress_all.49411451030279510695529732288818317958943277816996384377189857863289757643190
Line 310, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 36607217957 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1346115
... and 18 more failures.
4.i2c_host_mode_toggle.8271951384633173025483563739926662572218885832379401407231390733622518997032
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 73824296 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @17138
8.i2c_host_mode_toggle.93016594982141296256989972926866706263345723333735063350815281561169318340256
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 186778704 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @52392
... and 16 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 30 failures:
1.i2c_target_hrst.32349884469161195875150236558585879954860431053983754660079499331408542994569
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10146389783 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10146389783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_hrst.104317335095899953622375931269110621357048017652493864705729546513274164723140
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10082237713 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10082237713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 29 failures:
1.i2c_target_unexp_stop.66042763107917436602197654546311896443502140494987092182480546031340304743899
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 269942604 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 183 [0xb7])
UVM_INFO @ 269942604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.18621969649531554488526813663999160719846231678373084000706603533828826950166
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 95870084 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 199 [0xc7])
UVM_INFO @ 95870084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
7.i2c_target_stress_all_with_rand_reset.97411827825581755034667368667409031995827030642008523486145482778035741519179
Line 287, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 466693578 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (189 [0xbd] vs 0 [0x0])
UVM_INFO @ 466693578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:848) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
0.i2c_host_stress_all_with_rand_reset.62187960347738464218238878921331360630242006958508365300596326080116201063585
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 418116758 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 418116758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.80209132679595562715396637117092394802515135879691808462445045176661709276290
Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2804971666 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2804971666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.114538847272761789548581106797585057946653633885842686737980504832902028021409
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 325179326 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 325179326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.104539641173030929630475141608541503694591511037729473805811958453554532517907
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1377539984 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1377539984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 16 failures:
0.i2c_target_unexp_stop.15247760640300522894493907700309454359263931760395283761504428515765419711369
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 19320712 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 19320712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.86868951775182141555492913071753406170218137971992153883052414322946639610551
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 45846184 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 45846184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 15 failures:
7.i2c_target_nack_txstretch.41091655702580036545675575665811082974211814988291882523742001730843751468765
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 318078023 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 318078023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_nack_txstretch.26708574277780141740646673657682865567896848125669284383501121350207841333206
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 241241965 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 241241965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 14 failures:
0.i2c_host_mode_toggle.95250909071088797860263170599334663257972482296182812584166055864411281142110
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 88375201 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
1.i2c_host_mode_toggle.16414917039267025626577838800782674727406442781045067552301077601157863166133
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 70447601 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 12 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
1.i2c_host_stress_all.114333143143367906900186873451532898996344454654170076246670001681428447973934
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:a63c83e3-f829-41af-acca-b43e22480d3c
7.i2c_host_stress_all.73720096471319578656467777639841346318004681843220173967988851720163124403088
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
Job ID: smart:0228107f-7591-4f84-848d-6b7692e970af
... and 5 more failures.
45.i2c_host_error_intr.17173544608591422432236311984974258347712426515527603167859862569269698345016
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_host_error_intr/latest/run.log
Job ID: smart:37040e45-96b0-4fae-9259-90acf2a4200d
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 6 failures:
0.i2c_host_stress_all.42620524487118515484711676566314948034845772306617727782908648130865258563641
Line 475, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 10105936851 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @9449491
2.i2c_host_stress_all.75179793805611273769046964903047078857938952361009332215426512341312408953790
Line 376, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 30620959449 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4950243
... and 4 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:
5.i2c_target_unexp_stop.53458248526178887050458089762198254825013388472950290094607084454286152104426
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 258666618 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 258666618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_unexp_stop.76797661125056456869079307891651076999174550282854720384424115242013790477289
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 173825720 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 173825720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 6 failures:
6.i2c_target_stretch.13280790248118960940881584655420934070382822411323574002437953626306172912447
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10010003153 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10010003153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.i2c_target_stretch.89049890523473308370191192867020346919283096046810287476871788412170887839746
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10011557000 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10011557000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
18.i2c_host_mode_toggle.11763512818767321288774409225466041399658228635873121138870752194778417880801
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 123229384 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xda497c14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 123229384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.i2c_host_mode_toggle.88087589135158045886030352876667869233725344054562238775609495888708920505196
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 55205740 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x948fc294, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 55205740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:501) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
1.i2c_same_csr_outstanding.7738824424085605029153939058825609296384095205269693275972253543247353366310
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 61023383 ps: (cip_base_vseq.sv:501) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 61023383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:767) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
4.i2c_target_stress_all_with_rand_reset.55108109921759702884092115118848643989289151327890328457311469235125462064549
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 851847268 ps: (cip_base_vseq.sv:767) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 851847268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
6.i2c_host_perf_precise.87559237438721411152074542996469889597456654241968319871073942041796588561886
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_perf_precise/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
31.i2c_host_error_intr.82485671613678562927118736894073714978062838936156916958830873708487976276729
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 7550428 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
49.i2c_target_tx_stretch_ctrl.36057689616396667819116131712299951373147812224706785119514551675870426250717
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/49.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.