098010d125| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.822m | 9.676ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 47.620s | 1.584ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.840s | 45.614us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.830s | 26.356us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.000s | 356.586us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.960s | 415.388us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.380s | 56.932us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.830s | 26.356us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.960s | 415.388us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 12.240s | 1.337ms | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 58.691m | 600.000ms | 14 | 50 | 28.00 |
| V2 | host_maxperf | i2c_host_perf | 27.844m | 50.862ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.740s | 77.317us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.009m | 32.444ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.241m | 9.739ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.490s | 161.616us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 28.430s | 1.092ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.390s | 465.477us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.863m | 61.370ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 40.810s | 3.589ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 5.880s | 449.139us | 19 | 50 | 38.00 |
| V2 | target_glitch | i2c_target_glitch | 10.970s | 9.476ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 49.181m | 59.117ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 6.840s | 867.242us | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.212m | 6.600ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.690s | 3.538ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.000s | 857.980us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.870s | 777.532us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 51.829m | 64.899ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.212m | 6.600ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 34.671m | 47.978ms | 49 | 50 | 98.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.390s | 1.609ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.925m | 2.300ms | 41 | 50 | 82.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.970s | 1.408ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 34.570s | 10.009ms | 26 | 50 | 52.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.690s | 662.748us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.650s | 628.579us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 27.844m | 50.862ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 14.825m | 600.000ms | 47 | 50 | 94.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 40.810s | 3.589ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 10.010s | 698.460us | 47 | 50 | 94.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.250s | 593.752us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.140s | 647.018us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.650s | 577.771us | 35 | 50 | 70.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 27.400s | 1.420ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.610s | 1.123ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.720s | 17.695us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.790s | 25.867us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.530s | 494.291us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.530s | 494.291us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.840s | 45.614us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 26.356us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.960s | 415.388us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 3.260s | 1.845ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.840s | 45.614us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 26.356us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.960s | 415.388us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 3.260s | 1.845ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1666 | 1792 | 92.97 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.340s | 139.287us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.960s | 63.924us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.340s | 139.287us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 1.098m | 1.900ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.490s | 509.588us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 33.930s | 3.468ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1846 | 2042 | 90.40 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 26 | 53.06 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.28 | 97.30 | 89.61 | 97.22 | 72.02 | 94.33 | 98.44 | 90.00 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 44 failures:
0.i2c_host_mode_toggle.7859840297708165015316191160644463546488713889790191586773220189479190798966
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 107483172 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @84594
1.i2c_host_mode_toggle.105361154387300851911251910689001003454242011470895679551032747621347232618320
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 144159817 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @121798
... and 15 more failures.
2.i2c_host_stress_all.91299676283598344013697202168106854824935419495176594504000702261753619270332
Line 490, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 155751872113 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @8179499
4.i2c_host_stress_all.31053153596014670277015796919211260921002598001905923489054711856048048282907
Line 374, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 12184818267 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2405627
... and 25 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 28 failures:
Test i2c_target_stress_all_with_rand_reset has 2 failures.
0.i2c_target_stress_all_with_rand_reset.69872660281512536530718400143940561511902382831304535010534864319958071474470
Line 302, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 646760472 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 193 [0xc1])
UVM_INFO @ 646760472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.6822878560904171057043652263382795281788004864993764930505140741589210615837
Line 279, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 768098029 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 145 [0x91])
UVM_INFO @ 768098029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_unexp_stop has 26 failures.
3.i2c_target_unexp_stop.45487404252818701330801229389845928377297207090809113400878364358525928799813
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 254606859 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 125 [0x7d])
UVM_INFO @ 254606859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.58250079641532211811786344726429423124080014697681899977687074665668837177705
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 95735737 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 222 [0xde])
UVM_INFO @ 95735737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 24 failures:
0.i2c_target_hrst.59540166858400167662765507894712727006610556389831404555240574334856736189992
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10844316224 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10844316224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_hrst.105590868984632499892872784537390321716389948615525440591308598873407572123028
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_hrst/latest/run.log
UVM_FATAL @ 11013367306 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 11013367306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 18 failures:
0.i2c_target_unexp_stop.71567992652418065882312386120746364090408469629438836427501619407217535187383
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 76167728 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 76167728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.10620183906618368151944550419127785626678443952710557832644307869676518727665
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 198433141 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 198433141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
0.i2c_host_stress_all_with_rand_reset.34771753024187220185991774237697396092219147991285377226922831549078781685137
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 566676721 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 566676721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.53123182321168415475372668734044959104429351501955835095765635346960551854754
Line 277, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3576038833 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3576038833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
1.i2c_target_stress_all_with_rand_reset.108220192516000848996228381146570279006911266699111278899869063576417514113270
Line 285, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2768997555 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2768997555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.64781119952396836651181240426918775904079232721842398624542775419456128005926
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3468448584 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3468448584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 15 failures:
2.i2c_target_nack_txstretch.34664348648759932729149906329083908004171776146964069548046015595303463698943
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 562271628 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 562271628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_nack_txstretch.48472097428425090906168800573420666164703732027313702932834599433170849165272
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 1963292922 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 1963292922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 11 failures:
3.i2c_host_mode_toggle.92560608203419708555107237238512591301962709308923189907019232163867309171572
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 106539949 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
4.i2c_host_mode_toggle.39594696381754557055107291517764184555296333596297170397649577041655722166914
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 80818114 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 9 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 9 failures:
9.i2c_target_stretch.106059913853811339503747373687693195909356682744795090480463710035636764244821
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10048798668 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10048798668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.i2c_target_stretch.111422244971919206871284353223103655934928046246499375531861123804637371561022
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10227252911 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10227252911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
Test i2c_host_stress_all has 6 failures.
1.i2c_host_stress_all.102498471644360966677122654992670813549581760419280113613161175208913173484548
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:e9f6d569-7b3a-475f-83e7-be12bc4b96fe
18.i2c_host_stress_all.14706682540975701575855290880851387849102611879407331131787316919713601425958
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log
Job ID: smart:5109e0b2-1fcd-478c-901c-06dc5649ae42
... and 4 more failures.
Test i2c_host_perf has 1 failures.
31.i2c_host_perf.108137529913867097445278446230346875379784960734841981996733730396819862629334
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_host_perf/latest/run.log
Job ID: smart:05fe00e3-e536-40a1-bd8d-48a1b752a765
Test i2c_host_error_intr has 1 failures.
40.i2c_host_error_intr.115499897804089737750227863953525879068774786057596875856883107396309665745545
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_host_error_intr/latest/run.log
Job ID: smart:55240ced-22ff-4e1a-aadd-6b851be274cc
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:
1.i2c_target_unexp_stop.41025198062183189180660781426842154462506114427101190822546437618197644075858
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 176448205 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 176448205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_unexp_stop.53878984331538125479570642165729782834885340152348785027748548250058260799859
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 96756556 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 96756556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
Test i2c_host_stress_all has 2 failures.
12.i2c_host_stress_all.38884138068540092495794274746664420021640258185699339454912203586945127815759
Line 310, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.i2c_host_stress_all.83034056533827941135586298179357785092003321894166866827942398389743120094086
Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_perf_precise has 3 failures.
14.i2c_host_perf_precise.114108641926231121688867220938051858150129240697846333903011786135783728093540
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_perf_precise/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_host_perf_precise.15008437970990297457827143142358232533466256493935228128001822376807251472288
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_perf_precise/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
0.i2c_target_tx_stretch_ctrl.60053524860924518789502546777784885822203336471905166799963033541295833325575
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
14.i2c_target_tx_stretch_ctrl.79626512252540368855555199438358767797471383561568841337645029370112421118762
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 1 more failures.
49.i2c_target_fifo_watermarks_tx.73654470203717793266576657201373461549290359062253785326407643364463504106820
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/49.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
9.i2c_host_mode_toggle.41620073324820054217551934659765719481058628173007217262544681210493576822961
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 191444289 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xc3571014, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 191444289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_host_mode_toggle.70752875373631872064330315641633062429888366311572075445276057768032588720602
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 106481191 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xbb0cba14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 106481191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
Test i2c_target_stress_all has 1 failures.
5.i2c_target_stress_all.79674031849920004284296664349356885795391906371378208137835436079117717743289
Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 24900298026 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 24900298026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_intr_stress_wr has 1 failures.
13.i2c_target_intr_stress_wr.50761251947853617555955199221872365326274294761120760826099215840066201241134
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 47977687075 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 47977687075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:
3.i2c_host_stress_all.110583564102138639588286742738065236527230087468613231619716706344090819385588
Line 386, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 44506108409 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5047743