d09e282b26| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.742m | 2.223ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 53.930s | 1.680ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.840s | 21.398us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.830s | 19.857us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.370s | 1.087ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.980s | 184.725us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.800s | 228.846us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.830s | 19.857us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.980s | 184.725us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 13.600s | 627.557us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 57.225m | 88.421ms | 14 | 50 | 28.00 |
| V2 | host_maxperf | i2c_host_perf | 16.682m | 74.524ms | 47 | 50 | 94.00 |
| V2 | host_override | i2c_host_override | 0.740s | 17.741us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.700m | 11.122ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.989m | 2.337ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.320s | 1.689ms | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 29.150s | 2.107ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 11.510s | 791.761us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.067m | 4.103ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 47.760s | 1.108ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 6.910s | 188.101us | 17 | 50 | 34.00 |
| V2 | target_glitch | i2c_target_glitch | 10.870s | 3.762ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 55.033m | 57.082ms | 48 | 50 | 96.00 |
| V2 | target_maxperf | i2c_target_perf | 8.570s | 4.243ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.257m | 1.634ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.500s | 5.885ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.040s | 317.985us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.810s | 255.165us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 52.406m | 64.874ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.257m | 1.634ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 20.599m | 32.287ms | 48 | 50 | 96.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.950s | 26.252ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 4.366m | 4.758ms | 44 | 50 | 88.00 |
| V2 | bad_address | i2c_target_bad_addr | 9.480s | 7.661ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 36.070s | 10.092ms | 26 | 50 | 52.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.790s | 647.465us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.750s | 147.470us | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 16.682m | 74.524ms | 47 | 50 | 94.00 |
| i2c_host_perf_precise | 14.994m | 23.171ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 47.760s | 1.108ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 11.780s | 1.118ms | 45 | 50 | 90.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.400s | 598.052us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.110s | 2.551ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.790s | 526.885us | 37 | 50 | 74.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 31.200s | 740.586us | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.710s | 548.047us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.690s | 22.994us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.790s | 35.930us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.130s | 596.422us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.130s | 596.422us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.840s | 21.398us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 19.857us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.980s | 184.725us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.250s | 216.885us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.840s | 21.398us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 19.857us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.980s | 184.725us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.250s | 216.885us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1667 | 1792 | 93.02 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.490s | 161.883us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.960s | 122.860us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.490s | 161.883us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 50.660s | 6.057ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.880s | 483.380us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 1.361m | 2.880ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1847 | 2042 | 90.45 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.14 | 97.21 | 89.57 | 97.22 | 71.43 | 94.18 | 98.44 | 89.89 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 48 failures:
0.i2c_host_stress_all.5711213175272984718395177643668166647834009530552287967547837722106903501419
Line 485, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 15244997951 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3064607
7.i2c_host_stress_all.85914564484688640141769275857694923743282153955828830857580303155023451358174
Line 458, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 82505728263 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @7155123
... and 25 more failures.
5.i2c_host_mode_toggle.25499677367134406913882988478610099918697309566049000122061134525158087526899
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 127791844 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @26988
6.i2c_host_mode_toggle.19148068298290785854002221937918630447440502074962609059344246027322341403683
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 491388432 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @115094
... and 19 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 33 failures:
0.i2c_target_unexp_stop.16336573527617180949718028732237623901510597715871352171514349525508973662661
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 254861430 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 165 [0xa5])
UVM_INFO @ 254861430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.1877264097135271361063637331365880440120713395751958831487481882131944298801
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 156408566 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 111 [0x6f])
UVM_INFO @ 156408566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
7.i2c_target_stress_all_with_rand_reset.67133113057223180181193503223264638785782595678286945251550693104455324556871
Line 384, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2880339239 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 79 [0x4f])
UVM_INFO @ 2880339239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 24 failures:
0.i2c_target_hrst.31546874730936085451013406568304134101466366480234796418532854184064051079148
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10004984986 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10004984986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_hrst.23553648449572454622493243185095013548671214496326513992753818435796630665315
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10218961010 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10218961010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
0.i2c_host_stress_all_with_rand_reset.101938692486188961791939611964143873351361299025801175493302668599630613474436
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2520058178 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2520058178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.85801290031307898795475951627371397642148427716058202757450532394320438220481
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2928970804 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2928970804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.97084774441301967954838018835534317486159768945709420073443606254508372643069
Line 299, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2590212311 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2590212311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.96100655605616264268261459174726050180812218222442901176677112346491182342555
Line 333, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6491406101 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6491406101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 13 failures:
2.i2c_target_nack_txstretch.22154127569910579389396423251604920358078559266054917465782624405975481197113
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 693857487 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 693857487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_nack_txstretch.110582610287913659614138133693511637792482377655888429881509763219151151653131
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 142790335 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 142790335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
2.i2c_host_stress_all.25169311295940786277729419719824413293931150108206796663630518714843025152898
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
Job ID: smart:bec920a0-9ca0-4d46-903a-5f5ee41d58b5
9.i2c_host_stress_all.3961563571502150023948994415672382529103195862472280770865807151355082522020
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
Job ID: smart:6095eb6d-de29-47dd-98ce-5cd145a2ae4f
... and 5 more failures.
5.i2c_host_perf.10873528520326649642564844838887589727910335821839357520711468363992555544801
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_perf/latest/run.log
Job ID: smart:64a98c74-c55f-47e7-818e-2f3d7379aa02
35.i2c_host_perf.110270809710156042313135447798795622744183743417832616229837455936240918007048
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_host_perf/latest/run.log
Job ID: smart:3ed91906-6c43-4eaf-b4d0-df850ab7d8c7
... and 1 more failures.
5.i2c_target_stress_all.78136297923257348516054191224688603337863506411317342117505777482377786436442
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
Job ID: smart:c111d391-8f78-4fc9-ab8b-df11fe57eee6
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 10 failures:
2.i2c_target_unexp_stop.101091935201348084482871539207113283485808361929139899005266120686579257181101
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 85601554 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 85601554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.95391529875530756277741919585385497992741083197525544196703120873786535480675
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 46426070 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 46426070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 9 failures:
1.i2c_host_mode_toggle.92199872502421826079609060707304604915916685899496215717945557579961959762179
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 169552013 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
3.i2c_host_mode_toggle.85624062539007483134965722409622136612474995965824751414723072783214007566202
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 133719420 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 7 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 8 failures:
1.i2c_target_unexp_stop.59422640155628380536525608933145963266314042668276410039378168447340969894521
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 96062079 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 96062079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.9022420608500435450229249628512794329019440660844793118143482537324659831312
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 135950157 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 135950157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 6 failures:
2.i2c_target_stretch.72733521635487979636835031531819152933499600426574780087622941865387728916959
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10025176273 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10025176273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stretch.21831548536736628716512274268485432200722562317341528418388863440165560118620
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10002720823 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10002720823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 5 failures:
3.i2c_target_tx_stretch_ctrl.20332236847091293232040105168494553375823311099565601707867934625827467940655
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
28.i2c_target_tx_stretch_ctrl.106597423256787057659949173198014390887006596979565800101801387451372314975923
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
2.i2c_host_mode_toggle.89664535871769755905963708761146497027845573520243915860952644751633467786098
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 52555364 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xe382ae14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 52555364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_host_mode_toggle.38955028534063935688916763052431420969431114992659801091749074569089248884392
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 36462474 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x2f3f6114, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 36462474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 3 failures:
Test i2c_target_intr_stress_wr has 2 failures.
8.i2c_target_intr_stress_wr.22785860343873875403734314784909829744768999552240895282800686576688951738383
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 11906322268 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 11906322268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.i2c_target_intr_stress_wr.42651543396158715320051903478694570319455781842953251032615753987425765643796
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 41653662156 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 41653662156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 1 failures.
40.i2c_target_stress_all.29045170297035057555957773777455555145734189555706498665994923100709169911440
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 19998188080 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 19998188080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:
6.i2c_host_stress_all.43953740252205327520863573007492495405326889755415742928128239121849473891993
Line 382, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 61842807979 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @16886631
21.i2c_host_stress_all.73496133398776022396620979995050039613445655292899611996503166472130445154115
Line 400, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 87316970560 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @14921087
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
5.i2c_target_stress_all_with_rand_reset.89585060076508710087315449567414146179362090472841205390770982298821437445391
Line 281, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 50332921 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 50332921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:501) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
6.i2c_same_csr_outstanding.80193236660871269724265103637175038734552232191942931396482923298295354731030
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 123700978 ps: (cip_base_vseq.sv:501) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 123700978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---