76588857da| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.126m | 4.700ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 47.210s | 1.467ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.770s | 23.614us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.810s | 23.578us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.270s | 10.199ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.800s | 181.734us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.480s | 59.011us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.810s | 23.578us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.800s | 181.734us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 14.790s | 1.009ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 49.602m | 83.198ms | 18 | 50 | 36.00 |
| V2 | host_maxperf | i2c_host_perf | 28.392m | 29.300ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.760s | 47.735us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.961m | 6.352ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.199m | 2.422ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.390s | 626.009us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 26.530s | 623.692us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.600s | 632.214us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.517m | 3.419ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 43.100s | 928.019us | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 4.470s | 93.547us | 12 | 50 | 24.00 |
| V2 | target_glitch | i2c_target_glitch | 12.490s | 2.326ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 54.807m | 62.318ms | 48 | 50 | 96.00 |
| V2 | target_maxperf | i2c_target_perf | 8.210s | 8.036ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.358m | 3.450ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 10.340s | 1.694ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.030s | 557.643us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.950s | 351.950us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 54.658m | 67.337ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.358m | 3.450ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 7.990m | 22.231ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.180s | 3.282ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 4.117m | 5.296ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 8.730s | 1.591ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 34.930s | 10.054ms | 27 | 50 | 54.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 4.030s | 2.927ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.730s | 694.213us | 48 | 50 | 96.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 28.392m | 29.300ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 35.931m | 600.000ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 43.100s | 928.019us | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 16.610s | 1.345ms | 49 | 50 | 98.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.410s | 2.591ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.410s | 1.289ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.750s | 593.050us | 36 | 50 | 72.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 35.540s | 3.486ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.620s | 1.371ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.770s | 28.909us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.740s | 20.619us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.070s | 162.864us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.070s | 162.864us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.770s | 23.614us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.810s | 23.578us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.800s | 181.734us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.190s | 73.287us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.770s | 23.614us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.810s | 23.578us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.800s | 181.734us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.190s | 73.287us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1673 | 1792 | 93.36 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.330s | 133.451us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.120s | 232.560us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.330s | 133.451us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 58.000s | 1.111ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.380s | 1.496ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 43.130s | 1.093ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1853 | 2042 | 90.74 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.22 | 97.27 | 89.50 | 97.22 | 72.02 | 94.33 | 98.44 | 89.79 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 41 failures:
2.i2c_host_stress_all.19038347858802373121072659940229756193452270395824541069577320472038631431365
Line 371, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 14984761611 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @15970153
5.i2c_host_stress_all.38433263088583518128461557050811421309073304047314637532868248369186735613961
Line 406, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 80653560724 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5937585
... and 19 more failures.
3.i2c_host_mode_toggle.20368198728216457258984336711929347365785368762076262510710605733034719080187
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 105087253 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @7510
5.i2c_host_mode_toggle.16466439713538624123196397285975066365706752728184511185645699106702878744732
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 58972407 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @10974
... and 18 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 25 failures:
2.i2c_target_unexp_stop.68249163652765192658378003541154528772393216161932993356547723290731403083745
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 293613268 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 48 [0x30])
UVM_INFO @ 293613268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.99473265678463727595374528578313184706236093248411792941917732848040682053888
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 156776627 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 235 [0xeb])
UVM_INFO @ 156776627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
2.i2c_target_stress_all_with_rand_reset.56531269601247140821808751754248484564619334369144083395041458071397965445094
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27922848 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (187 [0xbb] vs 186 [0xba])
UVM_INFO @ 27922848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 23 failures:
2.i2c_target_hrst.54068740921805664261455906603212793450485980546301720791330545498263459128103
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10247900449 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10247900449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_hrst.36091552054765380067391398777663163239052059107463009290797501851267030015147
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10003699830 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10003699830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 20 failures:
1.i2c_target_unexp_stop.62825560554167892080848283164980602757927142619484823913076082901346689667046
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 114022462 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 114022462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.92982853333651712380327869116201179727604509870409566158190250530926410143581
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 205133457 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 205133457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
0.i2c_host_stress_all_with_rand_reset.15278998703980119591175633430178300181534937276051756499041663789583985877648
Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1859456239 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1859456239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.79876096801429259884687433937992369230942763131479971742977249681254561921423
Line 293, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 952807102 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 952807102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.74905383924580334900914293941536185712641955586702339066843584160930464816959
Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 699917345 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 699917345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.60045391613286324656382406948242288211763098435603115336530080407819408127248
Line 280, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 451638339 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 451638339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
1.i2c_target_nack_txstretch.41384749591045149031187402854701255703285394672461134653878745450431064723334
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 154814728 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 154814728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_nack_txstretch.64762800498264250973831789656315026854509116264285888779303758990347032703225
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 606584383 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 606584383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 14 failures:
13.i2c_host_mode_toggle.20863238587131606254350432356679776894505457790497201988487236284890075341402
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 38621804 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
15.i2c_host_mode_toggle.39328917646940362206341652861324616270591225738829383223489723096766902799283
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 74504594 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 11 more failures.
21.i2c_host_perf.103385717790169865351427507721875135150465485617088115913324256041050151984804
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_perf/latest/run.log
UVM_ERROR @ 6296991714 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
Test i2c_host_stress_all has 9 failures.
1.i2c_host_stress_all.1420604667191402702486592058789474900930451732293624429888588054162226811030
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:827fda05-6571-4217-87a9-a0e88380e70a
3.i2c_host_stress_all.78136034256387377112189031243068463360434770074042524990806905060340670591651
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
Job ID: smart:a9c521ad-adbf-48e8-8b3a-599cdf2fb4b7
... and 7 more failures.
Test i2c_target_stress_all_with_rand_reset has 2 failures.
5.i2c_target_stress_all_with_rand_reset.28731364048595467993859988561071488791730889442438407085424344406841574951976
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:791465b7-0395-4c26-aa20-9081f40d18fb
8.i2c_target_stress_all_with_rand_reset.18111869871117614371729363712551609024982989478227318821843014909055775276357
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
Job ID: smart:b71db4ad-07fe-475b-8be2-4d5efcab134f
Test i2c_target_stress_all has 1 failures.
36.i2c_target_stress_all.10855945041048260655347066203737004565169925938377961299032861803802740855525
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stress_all/latest/run.log
Job ID: smart:7422fb87-135e-43af-a479-c18aa905d4e4
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:
0.i2c_target_unexp_stop.59250783761311465738202944948817529943627128959139923080148716861601029759566
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 54471428 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 54471428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_unexp_stop.79496323985529173357107631706399757559618838165988710711825924807695953172816
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 1077038180 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 1077038180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
0.i2c_target_stretch.70322991833218829920606747907471722016504697232444254141834758187290817088694
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10001315754 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10001315754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stretch.38644545756594047190077702924788696598526382467352851354274753370330799475334
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10001884198 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10001884198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 5 failures:
10.i2c_host_mode_toggle.109659420981325682294284388943122154943769921542780032939634422402949323850751
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 39454368 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x89b7aa94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 39454368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.i2c_host_mode_toggle.17541836441966659003877327690801957029104736022124181742256396459064781018209
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 41413192 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x356c4514, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 41413192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
3.i2c_target_stress_all_with_rand_reset.50137876019829643045220282646706847018954610654129639114757337045453277843964
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 503968563 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 503968563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.1201847221025778212321354068143121267641434008352662813463873662207027724618
Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 776837118 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 776837118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
Test i2c_target_fifo_watermarks_tx has 2 failures.
12.i2c_target_fifo_watermarks_tx.75666199712574669704586964364727044881790061832419373051081374314106551461225
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
16.i2c_target_fifo_watermarks_tx.105685839204170606773327979388101528987228174547710844264460860126313346975671
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_tx_stretch_ctrl has 1 failures.
15.i2c_target_tx_stretch_ctrl.115078599872681686109069880133828093521760766539421670547630448782780106052687
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test i2c_host_perf_precise has 1 failures.
21.i2c_host_perf_precise.29916876876441843175620457287564441926955895633944410503145163312255934872273
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_host_perf_precise/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_stress_all has 1 failures.
32.i2c_host_stress_all.37072399164471693977793316079468885335782424761324616412585012691003697885871
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
4.i2c_target_stress_all.105660879643904643051372986585752074777426217044490617216716950667907552722183
Line 279, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 31646013785 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 31646013785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:
9.i2c_host_stress_all.16123509325352733991891104105252738301730009453123564924107387965260390117690
Line 337, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 45469906330 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @7223925