76588857da| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.896m | 9.401ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 47.690s | 1.556ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.800s | 327.800us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.800s | 24.430us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.920s | 355.666us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.910s | 159.187us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.590s | 36.520us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.800s | 24.430us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.910s | 159.187us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 13.730s | 3.657ms | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 32.581m | 183.469ms | 12 | 50 | 24.00 |
| V2 | host_maxperf | i2c_host_perf | 39.687m | 51.425ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.750s | 28.078us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.457m | 5.167ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.361m | 10.555ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.390s | 169.404us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 31.300s | 1.055ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.660s | 1.038ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.026m | 3.555ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 44.030s | 978.350us | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 7.250s | 730.237us | 22 | 50 | 44.00 |
| V2 | target_glitch | i2c_target_glitch | 12.210s | 2.502ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 51.088m | 73.901ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 8.010s | 2.145ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.198m | 1.920ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.940s | 1.640ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.010s | 291.243us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.730s | 473.959us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 55.808m | 65.751ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.198m | 1.920ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 9.132m | 22.025ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.180s | 9.518ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.809m | 2.411ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 8.030s | 6.529ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 36.160s | 10.153ms | 24 | 50 | 48.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.740s | 2.991ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.660s | 185.258us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 39.687m | 51.425ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 10.662m | 23.219ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 44.030s | 978.350us | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 22.710s | 1.957ms | 49 | 50 | 98.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.350s | 2.568ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 2.900s | 1.063ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.670s | 706.743us | 36 | 50 | 72.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 27.960s | 677.020us | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.690s | 1.152ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.690s | 16.182us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.840s | 15.879us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.580s | 485.486us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.580s | 485.486us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.800s | 327.800us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.800s | 24.430us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.910s | 159.187us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.220s | 67.997us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.800s | 327.800us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.800s | 24.430us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.910s | 159.187us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.220s | 67.997us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1676 | 1792 | 93.53 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.400s | 412.159us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.980s | 216.523us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.400s | 412.159us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 58.770s | 1.981ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.440s | 591.410us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 59.860s | 2.233ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1856 | 2042 | 90.89 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 27 | 55.10 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.38 | 97.30 | 89.69 | 97.22 | 72.62 | 94.40 | 98.44 | 90.00 |
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 37 failures:
1.i2c_target_unexp_stop.84649813575999165442160132381004317104767000703110455723244824309441613250753
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 16440813 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 29 [0x1d])
UVM_INFO @ 16440813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.65775196271670247693203329174658890893152758227400529322538562833518171881966
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 130311965 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 230 [0xe6])
UVM_INFO @ 130311965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 35 more failures.
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 33 failures:
0.i2c_host_stress_all.92607873388323276484468844688845269499261336859403248095292959014690299112455
Line 518, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 14258283391 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2312165
3.i2c_host_stress_all.15057901015089988433169246762324774740464962880611525813276496140037117117524
Line 338, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 12125738627 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @13290995
... and 22 more failures.
0.i2c_host_mode_toggle.112184540798059571469277525966496897213648691468152935974518986561720615665285
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 142889679 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @114856
5.i2c_host_mode_toggle.16981077006814509176146043845338120488209026537570536759456269889178326162572
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 417442591 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @35008
... and 7 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 26 failures:
0.i2c_target_hrst.64604158708460750866873485038464517950389076192616994435210093669117579258368
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10061764245 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10061764245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_hrst.27561122885652827113791115523738873158347975441612295528184030009109052473092
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10017158889 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10017158889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
0.i2c_host_stress_all_with_rand_reset.110843602350162715596439535801384515055006194786446455844970983061526454677924
Line 290, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1431916992 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1431916992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.50121254507100083534577190681038959385471214757923482986352175227325516157054
Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2520591870 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2520591870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.51024590711217435550413510900592989004587609610083846253797351386487187677978
Line 322, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2232688894 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2232688894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.63676298516946759350169864278059363789914776322230098692941006304504047882368
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6519530806 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6519530806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 15 failures:
2.i2c_host_mode_toggle.15417399685171419920179202920089272236759942979735481368498353644860738223462
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 53272303 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
4.i2c_host_mode_toggle.88911660401638951990652420285894690756232956160072805591173454398585064706034
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 67758337 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 13 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
1.i2c_target_nack_txstretch.48309611729171905163106467150453611283429286626711259022281005622539354684851
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 605577685 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 605577685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_nack_txstretch.34188781417227933238726660936533410268275929584161764776044980667639542586831
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 124209193 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 124209193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
1.i2c_host_stress_all.27156079442671751966966346672984278330886819248814973296898307745579607608320
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job ID: smart:bc87597f-d40d-4262-87ad-d0df01fd103e
14.i2c_host_stress_all.99030850398048728836433862209565635763250506450932645876439284133761033001121
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log
Job ID: smart:e0f2f458-126d-4ff3-8b29-00c50fb28689
... and 8 more failures.
25.i2c_host_error_intr.101126774470529202720683763651440732166943591519970072652786789595687451740992
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_host_error_intr/latest/run.log
Job ID: smart:7ec90ee9-fb8d-45d9-b6e9-581d84075df2
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 10 failures:
8.i2c_target_unexp_stop.104706139753435492115245557363910281268183345916015461611395391433084891086132
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 292485868 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 292485868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.i2c_target_unexp_stop.26557992327083861322242981451026424226811128645374218651515607108802594959252
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 71425973 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 71425973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
35.i2c_target_stretch.73382354015476221274639200500953535273442964258130805593242602398224903745142
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10001981110 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10001981110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.i2c_target_stretch.10478159996319333287571107425843643000839562241676717231804184432271813487665
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10050034529 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10050034529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 3 failures:
0.i2c_target_unexp_stop.67125852678329684478879011932838054304958645395423255246677231599188729108212
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 533212341 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 533212341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.i2c_target_unexp_stop.28200673258694790229620597844298986013860380723483656593349827758579018870345
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 106180821 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 106180821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:
8.i2c_host_stress_all.13277085392252431806815494302215994553162217960010539648691099646776729464827
Line 469, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 17114703437 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4637209
31.i2c_host_stress_all.7946954760709101391118921905657451891686130548855287194806687828411038640821
Line 467, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 11704680571 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3563801
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
1.i2c_target_stress_all_with_rand_reset.50347671517321832518575059057130753474679664831152703453023359662962100176403
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 525592041 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 525592041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.69462307082918790396186806562117938405058604443227822603256823110908408439017
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 301837015 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 301837015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
Test i2c_target_tx_stretch_ctrl has 1 failures.
5.i2c_target_tx_stretch_ctrl.41441572968420257957573464755300507868523030031105734976476302858161737251413
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_fifo_watermarks_tx has 1 failures.
30.i2c_target_fifo_watermarks_tx.2465085457384655419298892446014037690213535416762433788831547193025923685230
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Exit reason: Error: User command failed Error-[NOA] Null object access has 2 failures:
22.i2c_host_mode_toggle.4667413465609155058098524681375701855053640328294541903462419959900714666448
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
42.i2c_host_mode_toggle.104499108542922878220546486921767909981992930677584782023446744347181397134512
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
32.i2c_host_mode_toggle.5089089218927475051335862576956014318677698446301441711167026974582035374668
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 197770126 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x51512814, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 197770126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.i2c_host_mode_toggle.72737422180607436525034134522688286908158084972118567552819110812558429533221
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 60843746 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x7d2c7314, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 60843746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_smoke_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
4.i2c_target_stress_all_with_rand_reset.11383085947603248435514330933121777786851816695492658331299788213335411919454
Line 270, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 48080577 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_smoke_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 48080577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:501) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
5.i2c_same_csr_outstanding.70777062997795827494081442041397554862151700206084831462138981475794484800213
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 55082563 ps: (cip_base_vseq.sv:501) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 55082563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
9.i2c_target_stress_all_with_rand_reset.5522071344691134493613961968024863955644018492035962648962144462188247833118
Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1681540931 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 1681540931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1112) has 1 failures:
10.i2c_host_stress_all.12582130263765456771609575062426363872797624730367363928727094115080443286241
Line 328, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 51168360517 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=0xb5c7ce14, Comparison=CompareOpEq, exp_data=0x0, call_count=1112)
UVM_INFO @ 51168360517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
31.i2c_target_stress_all.103514813742553803488841540175278308727846667598617595044623209968797708069266
Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 56878560378 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 56878560378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
35.i2c_host_perf.61095319327000151904672913781253926529303645833268119779970309215356369898396
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_host_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---