f1535c5540| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.120m | 9.044ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 49.030s | 1.566ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.810s | 43.553us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 2.360s | 1.001ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.060s | 952.111us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.790s | 643.703us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.600s | 33.593us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 2.360s | 1.001ms | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.790s | 643.703us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 8.970s | 498.128us | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 59.712m | 43.530ms | 13 | 50 | 26.00 |
| V2 | host_maxperf | i2c_host_perf | 29.631m | 48.094ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.740s | 54.085us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.571m | 19.287ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.649m | 10.413ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.420s | 156.323us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 33.650s | 2.734ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 14.500s | 278.736us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.944m | 25.692ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 50.800s | 1.410ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 5.970s | 616.755us | 13 | 50 | 26.00 |
| V2 | target_glitch | i2c_target_glitch | 10.990s | 4.279ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 28.470m | 41.558ms | 48 | 50 | 96.00 |
| V2 | target_maxperf | i2c_target_perf | 7.030s | 971.062us | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.647m | 2.107ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.810s | 2.826ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.800s | 271.901us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.980s | 304.281us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 53.981m | 64.950ms | 49 | 50 | 98.00 |
| i2c_target_stress_rd | 1.647m | 2.107ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 12.002m | 22.481ms | 48 | 50 | 96.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.260s | 1.462ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 4.697m | 4.740ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 8.470s | 8.500ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 36.290s | 10.144ms | 23 | 50 | 46.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 4.120s | 679.878us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.690s | 175.366us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 29.631m | 48.094ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 7.857m | 5.883ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 50.800s | 1.410ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 14.500s | 1.290ms | 46 | 50 | 92.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.310s | 1.244ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.240s | 3.129ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.750s | 921.646us | 33 | 50 | 66.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 32.820s | 3.229ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.810s | 564.415us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.700s | 49.672us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.760s | 17.952us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.010s | 176.166us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.010s | 176.166us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.810s | 43.553us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.360s | 1.001ms | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.790s | 643.703us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.200s | 639.531us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.810s | 43.553us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.360s | 1.001ms | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.790s | 643.703us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.200s | 639.531us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1658 | 1792 | 92.52 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.420s | 1.405ms | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.030s | 490.224us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.420s | 1.405ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 16.840s | 892.066us | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 3.440s | 2.443ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 40.670s | 9.481ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1838 | 2042 | 90.01 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 26 | 53.06 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.22 | 97.27 | 89.46 | 97.22 | 72.02 | 94.33 | 98.44 | 89.79 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 41 failures:
0.i2c_host_stress_all.24103154859360708342543164119640828577164500620758081147158481497578688058785
Line 369, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 8403527269 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3098003
2.i2c_host_stress_all.35143868353775548347179008281904740570986836787212544465601594166153046535901
Line 459, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 32933371938 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @7380787
... and 22 more failures.
13.i2c_host_mode_toggle.27693276537971686230795000065518929731623542020241044491169397270606582249582
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 105920841 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @18724
15.i2c_host_mode_toggle.77092050683507016527337606258902452985264641778391451989704445293133075437564
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 491415677 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @33404
... and 15 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 27 failures:
0.i2c_target_hrst.59896775331858404075383793614686555759894505206045666139050750380101524834528
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10139332560 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10139332560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.92419549663548094511946492798086020715354399319307408166616176754559047669023
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10241699654 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10241699654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 26 failures:
0.i2c_target_unexp_stop.100110906940951903505474623243442000834408961286067887923687613311397453922819
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 138157703 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 147 [0x93])
UVM_INFO @ 138157703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.37080200917967211319452071946091471067989975236636213214684875255052308560862
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 165687986 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 149 [0x95])
UVM_INFO @ 165687986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 20 failures:
3.i2c_target_unexp_stop.109666939799814420238555356065643164785764208899329512083693858764413991465411
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 52692343 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 52692343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.229197637096942724673828230439463850592056289634293632540804902701100303737
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 427136912 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 427136912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
0.i2c_host_stress_all_with_rand_reset.10306572311585015782131106801176429753777741189538537306217441542976899959629
Line 270, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 781779793 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 781779793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.60570835069744582442801496206385762622726835554115591850426859078236720871179
Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 470120438 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 470120438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.52052461449134765218519411124697659170185262166424316096055474359524066609632
Line 270, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 394261201 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 394261201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.42264755909346012762820709408811609812763018468821353687854836589841365929860
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4155514123 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4155514123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 17 failures:
2.i2c_target_nack_txstretch.108769778575618295845177736642938543772772476987517371749354438389679327585417
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 660871422 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 660871422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_nack_txstretch.43249640671240652255547413556228858972832023291833512151486148681987632078228
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 578067807 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 578067807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 15 failures:
0.i2c_host_mode_toggle.82665048277967405689089332112917098805437023443512032468371549604208861035380
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 130349400 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
1.i2c_host_mode_toggle.12638928310273430111875427240058823090382341767198266781383486171202796636910
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 18385578 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 13 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
Test i2c_host_perf has 1 failures.
5.i2c_host_perf.97036623041347373836541759006018627479116002746890857391478213671677673970249
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_perf/latest/run.log
Job ID: smart:11867dd1-f7f3-4f32-834d-7627c005d3f6
Test i2c_host_stress_all has 8 failures.
9.i2c_host_stress_all.98340035343432290735996949634480251656885286452287053031785249436681265363766
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
Job ID: smart:037c4c96-b628-4d2b-b850-21bcf4cc539a
13.i2c_host_stress_all.3081890410891270554827610528800085839006547590397850420664217394721772762199
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_stress_all/latest/run.log
Job ID: smart:4e9343d3-2d79-4912-88e0-2490c3288e11
... and 6 more failures.
Test i2c_target_stress_wr has 1 failures.
21.i2c_target_stress_wr.2443025013244549447145145430960587658845281302029378491379525343990150435023
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stress_wr/latest/run.log
Job ID: smart:e0a75bb1-c162-423a-bc0b-189befae1e23
Test i2c_target_stress_all has 1 failures.
35.i2c_target_stress_all.90339998511895718447670139635540084253883598028648280049051877964265682893808
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_all/latest/run.log
Job ID: smart:03beaa22-3c68-492c-a4ec-56a5b73c4417
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 5 failures:
1.i2c_host_stress_all.65613508958285558832225460040528391708831476035848202647846158935977244709099
Line 367, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 17877758123 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4684037
10.i2c_host_stress_all.94059577761005924540572856986574926504983492836090660148342286897939522667897
Line 372, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 233327161592 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @21191849
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 5 failures:
2.i2c_host_mode_toggle.53232905121286631320505061517481883340481568042133023911324720311423420091043
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 104695421 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xc9faf794, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 104695421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_host_mode_toggle.65963742342647313586729946025677420197869021759849742435726234554756440516580
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 110199547 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x7a509f94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 110199547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 5 failures:
4.i2c_target_tx_stretch_ctrl.11960877535794428118444850255431111066031677664145396753251310687011959521399
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
8.i2c_target_tx_stretch_ctrl.11212149036204655579335752009696402475665384047477208555792447622765963089617
Line 297, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 2 more failures.
38.i2c_target_fifo_watermarks_tx.101945643031778761442471531392738594949198972114151997460538224463139011920583
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
7.i2c_target_stretch.52071433474963740438079421555027280364467376948250135920857288612268889523781
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10012498493 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10012498493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_stretch.12093928032758380773065637003790011782464668752453182527843968228668777537063
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10012898980 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10012898980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 4 failures:
29.i2c_target_unexp_stop.99459385975156847720754816881124175718929034758791800940292620335890185592302
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 185989699 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 185989699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.i2c_target_unexp_stop.15139681861276810729433604338417824232099202360542604503304169150130986040903
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 2442784201 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 2442784201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 3 failures:
Test i2c_target_stress_all has 1 failures.
5.i2c_target_stress_all.100762426043993412362124746592859054375252491100896131022068755148641964621635
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 15639300406 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 15639300406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_intr_stress_wr has 2 failures.
6.i2c_target_intr_stress_wr.31796438844035645203133167017830064632744796829336756571321103126504067801672
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 11412129780 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 11412129780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_intr_stress_wr.22514676731478572175022923798775690251931397524917223880358022247325881792565
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 18537970600 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 18537970600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
0.i2c_host_error_intr.78338996176297155631160064468278523529510949461859516392669226583626458656691
Line 260, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 68395886 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
UVM_ERROR (cip_base_vseq.sv:771) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
6.i2c_target_stress_all_with_rand_reset.82041148448681826772996735235644798665138320492678014851327945137678973256900
Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1325209550 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1325209550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---