34b8fc33e3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.582m | 2.302ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 42.230s | 2.552ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 1.200s | 19.466us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 1.170s | 134.377us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 6.140s | 115.867us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.420s | 196.776us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 2.050s | 30.904us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 1.170s | 134.377us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.420s | 196.776us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 11.820s | 302.048us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 57.297m | 116.426ms | 18 | 50 | 36.00 |
| V2 | host_maxperf | i2c_host_perf | 36.498m | 29.680ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 1.140s | 30.668us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 4.947m | 4.812ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.024m | 2.701ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.180s | 709.590us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 25.370s | 2.865ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.500s | 385.245us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.252m | 15.983ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 44.650s | 3.848ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 6.440s | 343.074us | 14 | 50 | 28.00 |
| V2 | target_glitch | i2c_target_glitch | 12.050s | 2.075ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 22.706m | 55.490ms | 48 | 50 | 96.00 |
| V2 | target_maxperf | i2c_target_perf | 10.420s | 965.822us | 49 | 50 | 98.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.245m | 1.763ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 13.350s | 1.430ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 3.570s | 296.335us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.620s | 1.119ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 19.658m | 60.507ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.245m | 1.763ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 6.726m | 25.337ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 13.370s | 6.167ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.958m | 5.481ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 11.160s | 1.038ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 54.090s | 10.257ms | 25 | 50 | 50.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 5.210s | 2.253ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 2.550s | 139.360us | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 36.498m | 29.680ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 13.161m | 23.223ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 44.650s | 3.848ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 20.910s | 1.178ms | 46 | 50 | 92.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 5.590s | 592.084us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.700s | 552.554us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 2.950s | 206.935us | 37 | 50 | 74.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 36.110s | 3.203ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 4.800s | 723.512us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 1.050s | 19.457us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 1.090s | 19.181us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 4.250s | 285.314us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 4.250s | 285.314us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 1.200s | 19.466us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.170s | 134.377us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.420s | 196.776us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 4.510s | 1.407ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 1.200s | 19.466us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.170s | 134.377us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.420s | 196.776us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 4.510s | 1.407ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1673 | 1792 | 93.36 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.160s | 441.986us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.380s | 210.181us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.160s | 441.986us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 57.100s | 3.355ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 5.000s | 1.866ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 49.930s | 22.938ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1853 | 2042 | 90.74 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 29 | 59.18 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.40 | 97.30 | 89.91 | 97.22 | 72.62 | 94.40 | 98.44 | 89.89 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 41 failures:
0.i2c_host_stress_all.7771455132775365656505090965282673951568209217287985268988245977055162237470
Line 173, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 50627606471 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @58801
2.i2c_host_stress_all.58524366413810631488484796316060120269184997981403315977567276357851348668266
Line 158, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 16906690831 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4336607
... and 21 more failures.
0.i2c_host_mode_toggle.49514987016305893900589432584165185013959603206797800190859039923919377796657
Line 72, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 309195545 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @11134
1.i2c_host_mode_toggle.25772133796700584082049597972978562536665222147626846969705607510795657014411
Line 72, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 296106582 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @8610
... and 16 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 36 failures:
0.i2c_target_unexp_stop.7602586603718883661422765024938780747334308281618731733788931275337679297434
Line 65, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 109771422 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 76 [0x4c])
UVM_INFO @ 109771422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.98471350711274195560619653826047937009355662102101939148584172455328914747305
Line 65, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 308940289 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 29 [0x1d])
UVM_INFO @ 308940289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 34 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 25 failures:
4.i2c_target_hrst.5506932965078049169283214727709244278055640834982242851120149049627194054628
Line 66, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10003525106 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10003525106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_hrst.53610644754126283873381903531968546463015580979758477147443063637594188796952
Line 66, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10159548981 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10159548981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
0.i2c_host_stress_all_with_rand_reset.43780643964416693842091700915967634919674477689905188337036678004128636999313
Line 79, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1471992770 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1471992770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.68887684865289891138717192818044831200990123195691784331665718481690464859917
Line 73, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 476312009 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 476312009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.64639543694685750498879444327105108038876363611365346694448679111259470286757
Line 80, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 987109155 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 987109155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.87955710011368905583576128310517245181710671727468184876526304498938082102026
Line 71, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 353285423 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 353285423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 13 failures:
1.i2c_target_nack_txstretch.108543218743533450422781132539362021332936626855200742228777804364723156840974
Line 65, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 129487695 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 129487695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_nack_txstretch.30904448978692799837355622185904104263178827344769646768683881727519230565455
Line 65, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 153499795 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 153499795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 12 failures:
1.i2c_target_unexp_stop.97107040377364070138028323649125665591098329340580347392142613320574287701350
Line 65, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 226898808 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 226898808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_unexp_stop.13772731360245302857190484344305629956127538167869611393963606399029273744128
Line 65, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 382810281 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 382810281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 10 failures:
4.i2c_host_mode_toggle.23253684412420141765029851545866612771384257640221035359982865659395028377474
Line 74, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 274437798 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
8.i2c_host_mode_toggle.80840455194174816694607141619745648469128138137905926157222390268906919310150
Line 74, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 196321040 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 8 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
0.i2c_target_stretch.97294200890565485007213372754732195308549107155258075365204315894921438704268
Line 65, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10012521720 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10012521720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stretch.6321897925697760623708141639198536061568931545481807659606588773175852767619
Line 65, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10004552607 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10004552607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Job timed out after * minutes has 5 failures:
1.i2c_host_stress_all.60203498297065415410967621231564436905285242427552721278963646192227711789870
Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
5.i2c_host_stress_all.71063266079380479985371325026802324148775434102022135283131709351498332856313
Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
... and 2 more failures.
6.i2c_host_perf.23243826366943624605712395793288594924617082444801193931441020896978979865648
Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_host_perf/latest/run.log
Job timed out after 60 minutes
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 5 failures:
5.i2c_host_mode_toggle.76494272305300311228076219030485108903975343669642955986679556906109018408062
Line 66, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 74977582 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x8aa30b14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 74977582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_host_mode_toggle.99703999618638723434521350719995260516239560858089631905208324939524709801615
Line 66, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 141554303 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xf528394, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 141554303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 5 failures:
8.i2c_host_stress_all.52000494012325810832840778020615826479756994056035180683274752409597023895322
Line 182, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 102818315927 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4074625
27.i2c_host_stress_all.101815760688045991539407266875761772739588038477032225342815834416823342580706
Line 158, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 29147371196 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @408757
... and 3 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
6.i2c_target_tx_stretch_ctrl.7566295690742931127452245450504337525021664986775951746630346052584811212449
Line 111, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
14.i2c_target_tx_stretch_ctrl.32265524348669415666064862256329064079833180694870228538281671339273275290046
Line 111, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 2 more failures.
Error-[NOA] Null object access has 3 failures:
13.i2c_host_mode_toggle.115712079579985688588042161771442067990171122085188137313893023942983480470790
Line 73, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
14.i2c_host_mode_toggle.23651149921959068502792568485819268514705223898602270158401169219797733546664
Line 73, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
... and 1 more failures.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
12.i2c_target_stress_all.13512316055067936439709767948355305660109430568725951250241460493711769042411
Line 80, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 39844499349 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 39844499349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.i2c_target_stress_all.46548813672076532935179941304523908876266748878840023387222605825876385716285
Line 76, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 55405842995 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 55405842995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 2 failures:
13.i2c_target_unexp_stop.41131573830797581949657858960863703902433201482733604718003325782546417525258
Line 66, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 367525496 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 367525496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.i2c_target_unexp_stop.81483752840115010501450461600996591538145478773927622821899265748443431792043
Line 66, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 149091101 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 149091101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:771) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
1.i2c_target_stress_all_with_rand_reset.67503982121272253395549364416981617453075960288815352584815108854135595204027
Line 117, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 22937859049 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 22937859049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
15.i2c_target_perf.113248316941141112295022167714526093896423265390277579479850229215394386630227
Line 65, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---