0825c81be0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.531m | 2.181ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 41.520s | 5.850ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.710s | 83.804us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.740s | 38.138us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.580s | 754.509us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.780s | 359.682us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.370s | 31.280us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.740s | 38.138us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.780s | 359.682us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 6.650s | 339.063us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 45.180m | 91.044ms | 20 | 50 | 40.00 |
| V2 | host_maxperf | i2c_host_perf | 53.215m | 48.082ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.630s | 47.469us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 4.333m | 6.061ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.313m | 3.302ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.240s | 162.774us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 23.860s | 1.072ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 10.520s | 874.121us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.215m | 3.705ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 44.840s | 4.586ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 6.770s | 392.490us | 17 | 50 | 34.00 |
| V2 | target_glitch | i2c_target_glitch | 12.070s | 32.609ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 16.133m | 87.327ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 7.130s | 2.079ms | 49 | 50 | 98.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.049m | 7.327ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.250s | 7.752ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.800s | 1.130ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.940s | 274.196us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 14.372m | 55.773ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.049m | 7.327ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 5.794m | 25.719ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 7.440s | 5.860ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.116m | 2.620ms | 44 | 50 | 88.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.790s | 2.360ms | 48 | 50 | 96.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 37.780s | 10.081ms | 25 | 50 | 50.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.660s | 3.463ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.540s | 193.338us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 53.215m | 48.082ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 4.639m | 23.258ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 44.840s | 4.586ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 26.530s | 2.648ms | 49 | 50 | 98.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.240s | 664.359us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 2.830s | 1.374ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 1.680s | 496.498us | 30 | 50 | 60.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 30.110s | 869.555us | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.520s | 547.985us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.620s | 29.986us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.710s | 53.702us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.700s | 256.922us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.700s | 256.922us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.710s | 83.804us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.740s | 38.138us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.780s | 359.682us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.080s | 190.355us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.710s | 83.804us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.740s | 38.138us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.780s | 359.682us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.080s | 190.355us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1672 | 1792 | 93.30 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.220s | 464.247us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.930s | 111.298us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.220s | 464.247us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 30.950s | 740.128us | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.300s | 1.350ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 1.303m | 12.401ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1852 | 2042 | 90.70 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.23 | 97.27 | 89.65 | 97.22 | 72.02 | 94.33 | 98.44 | 89.68 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 41 failures:
0.i2c_host_stress_all.57640307174488579946461786427113183412247171003317325658379621591860890006737
Line 185, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 18904530046 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @12031401
4.i2c_host_stress_all.77950371259092251709811158859972878548608513856938104545866197181984881691731
Line 162, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 21899199535 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1851609
... and 22 more failures.
2.i2c_host_mode_toggle.48369892812756414313462017206194674523514017646745109079850653365541710815937
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 228003266 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @19786
3.i2c_host_mode_toggle.63674375594908341597699843595048371639767511913505521475031064740850667389287
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 106012515 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @17878
... and 15 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 32 failures:
0.i2c_target_unexp_stop.37291929730273672407593253650575460521682684207760727075095982883094646099432
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 101280490 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 112 [0x70])
UVM_INFO @ 101280490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.79477671649230835067064225577108062279587150025328637379938228120128660544614
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 133528106 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 20 [0x14])
UVM_INFO @ 133528106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
1.i2c_target_stress_all_with_rand_reset.73890660392636969889708777433262114958305755140118598489562080593706776606541
Line 101, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1365854863 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 167 [0xa7])
UVM_INFO @ 1365854863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.69053850963154982159522572742502267836376255555653620245182714398712957716600
Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2044099585 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 80 [0x50])
UVM_INFO @ 2044099585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 25 failures:
0.i2c_target_hrst.114049274438168161845218953328403233928947047687371640621468173554600335706675
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10024662167 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10024662167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_hrst.68335952234574431626807506739201828075985908208630851121437544980851459110333
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/4.i2c_target_hrst/latest/run.log
UVM_FATAL @ 11195922516 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 11195922516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 20 failures:
0.i2c_target_nack_txstretch.51296117776226774065471142283943168514571221252721759976589440731284469285748
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 659109549 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 659109549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_nack_txstretch.41813421608404624339508682632482842082428563957523053163135982222679601248951
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 179644673 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 179644673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
0.i2c_host_stress_all_with_rand_reset.77778879441031681777869051557371442010146108501825686848024935054795658045258
Line 88, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1874656871 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1874656871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.77453448982380145193759319492094445913900913681716648733097183167044481790184
Line 81, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 740128027 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 740128027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
2.i2c_target_stress_all_with_rand_reset.94654633543553553340462045081279488151074124264828778896798242117415735432499
Line 100, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1054484042 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1054484042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.48900803701581908815571040901783468085421818533388886095023743357674318686733
Line 97, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 433886010 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 433886010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 15 failures:
3.i2c_target_unexp_stop.82092015195614320180220305425152933853991963313034190057011705937442552277385
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1604192641 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1604192641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_unexp_stop.102225143569671194299138927450311385002269174425937371680465772917750611026677
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 18156968 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 18156968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 12 failures:
1.i2c_host_mode_toggle.106989835511591227368364373875975139606164345725794717596561294626910148124304
Line 74, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 92857292 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
5.i2c_host_mode_toggle.2246064128364849236105897587135250225425053114519305070904528390445591977281
Line 74, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 49297452 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 10 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 6 failures:
1.i2c_target_stretch.10714821738740367685435391611099946281944396521448192965782902395289832417234
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/1.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10011837135 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10011837135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stretch.42365752493738546788153838076938688717168774209478280913345954078078760436178
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10002140534 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10002140534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 5 failures:
6.i2c_target_unexp_stop.94939237865730537339608616392657344169714671014558555284910941724223748651730
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 101298547 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 101298547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_unexp_stop.88538228852829497228514872232450332057653611476264905512001264808468891971461
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 2321320100 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 2321320100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
Test i2c_target_bad_addr has 2 failures.
4.i2c_target_bad_addr.58019949794736588516889751861702648280039394769343253493939090930566720427074
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/4.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_bad_addr.86623412045951342477539476470260549486443062395334066295531850966406103362855
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/6.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_perf has 1 failures.
29.i2c_target_perf.39638679357569439219886104253692619311711231911232272227296246538292835532857
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/29.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_stress_all has 1 failures.
48.i2c_host_stress_all.47800643149935669739554082310266077200364316518056308437708350523597208085080
Line 126, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/48.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes has 3 failures:
9.i2c_host_stress_all.48896139131995249122893588579463593849157846732520382602667518517925486085083
Log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
37.i2c_host_stress_all.51430147668203325659154093676541790273395332136703311799195315707787931208640
Log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/37.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
25.i2c_host_mode_toggle.99760650048892962838416887982169132435135866608197508890069771890650030091478
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/25.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 139268499 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x4b4b1394, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 139268499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.i2c_host_mode_toggle.69858131420182256498309388631523965234555839801600927150279563660953318070054
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/30.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 122429792 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xc7f0b314, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 122429792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
0.i2c_target_stress_all_with_rand_reset.50671654486643143117366217198981626866320751254273696375187271543498465503222
Line 153, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12400859871 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 12400859871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.111439540334385264462695186991830109631062519942555175660047225441836661843318
Line 82, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3050870205 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3050870205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:
3.i2c_host_stress_all.31330601886819644426706336328722265335294362797256181090250107655612577422633
Line 211, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 10289984372 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3244657
16.i2c_host_stress_all.29001813932936602134118065173567102280070040538934394564063281315083764166470
Line 150, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/16.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 6390169379 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1349353
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
Test i2c_target_tx_stretch_ctrl has 1 failures.
13.i2c_target_tx_stretch_ctrl.54739347011195268020056562953476858459213544217135579775391181352202046721421
Line 117, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/13.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_fifo_watermarks_tx has 1 failures.
47.i2c_target_fifo_watermarks_tx.99154798910309708607751374145825033136318590601774849098188342603792523006053
Line 108, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/47.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
5.i2c_target_stress_all.55744769708941215369683778999171611223752170978832878652713666844039523446179
Line 100, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 141901823794 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 141901823794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
8.i2c_target_stress_all_with_rand_reset.704304264532328523801086209199389944033527118734006667759270454790935680641
Line 130, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3288937841 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 3288937841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access has 1 failures:
22.i2c_host_mode_toggle.100048852609400924617686771973714724664406720267297263037729774980384099471149
Line 73, in log /workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/22.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.