e733a8ef8a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.092m | 8.167ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 51.320s | 1.359ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 1.180s | 17.949us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 1.270s | 121.335us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 7.390s | 766.965us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.800s | 1.502ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 2.330s | 39.689us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 1.270s | 121.335us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.800s | 1.502ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 16.090s | 4.358ms | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 51.046m | 86.308ms | 16 | 50 | 32.00 |
| V2 | host_maxperf | i2c_host_perf | 38.007m | 51.264ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 1.170s | 32.404us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.024m | 19.727ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.638m | 6.100ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.190s | 660.125us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 30.820s | 2.002ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 15.220s | 2.402ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.713m | 3.762ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 47.520s | 855.929us | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 9.650s | 380.137us | 17 | 50 | 34.00 |
| V2 | target_glitch | i2c_target_glitch | 18.090s | 9.835ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 28.914m | 58.442ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 11.230s | 1.015ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.598m | 3.322ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 14.800s | 6.050ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 3.190s | 346.868us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 2.830s | 2.553ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 39.774m | 69.546ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.598m | 3.322ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 15.147m | 34.566ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 15.720s | 1.917ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.896m | 3.703ms | 43 | 50 | 86.00 |
| V2 | bad_address | i2c_target_bad_addr | 14.770s | 1.760ms | 49 | 50 | 98.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 1.153m | 10.210ms | 28 | 50 | 56.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 6.300s | 1.526ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 2.790s | 1.473ms | 47 | 50 | 94.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 38.007m | 51.264ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 42.760m | 24.362ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 47.520s | 855.929us | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 21.230s | 1.001ms | 48 | 50 | 96.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 6.190s | 1.242ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 6.200s | 1.231ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 2.970s | 199.964us | 34 | 50 | 68.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 37.330s | 2.777ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 5.110s | 3.813ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 1.070s | 41.349us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 1.220s | 108.210us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 4.330s | 114.030us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 4.330s | 114.030us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 1.180s | 17.949us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.270s | 121.335us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.800s | 1.502ms | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.770s | 124.282us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 1.180s | 17.949us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.270s | 121.335us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.800s | 1.502ms | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.770s | 124.282us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1672 | 1792 | 93.30 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.670s | 249.703us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.460s | 66.141us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.670s | 249.703us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 55.580s | 724.142us | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 5.110s | 874.151us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 50.240s | 6.104ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1852 | 2042 | 90.70 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.23 | 97.21 | 89.46 | 97.22 | 72.02 | 94.26 | 98.44 | 90.00 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 45 failures:
0.i2c_host_stress_all.18239836858733009793632730833063767672362187609466893872940374407954139431113
Line 160, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 13010293638 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @11526839
1.i2c_host_stress_all.109652652785246013827885122252411359442771049518615937709822492784626761332714
Line 199, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 29576264273 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @7403485
... and 25 more failures.
5.i2c_host_mode_toggle.95167546393927060694153681963926983041070593769491531755256714564104349057276
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 122375306 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @106374
11.i2c_host_mode_toggle.56615432736701804025597025351276529000209090703851652886344162797289857259690
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 409538081 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @20776
... and 16 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 32 failures:
1.i2c_target_unexp_stop.110849712009864059467856912999664531972663552822037535792305118598251533454619
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 111771950 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 9 [0x9])
UVM_INFO @ 111771950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.1244789471149612696067021682052892736410472557503136472273326207212499986270
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 252750802 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 50 [0x32])
UVM_INFO @ 252750802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 22 failures:
1.i2c_target_hrst.26931194156598932384514949924050344528511141844428561498207559520970952687895
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10463051792 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10463051792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_hrst.68263243213058742202382118340293748330297420832978467617960996329436668565840
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10110674257 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10110674257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
0.i2c_host_stress_all_with_rand_reset.69048975211231775556520291223241299192119310281352726773907211374327016708002
Line 73, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4252379523 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4252379523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.86493574763503265465710673666454126574939738023232516703718397346589189693240
Line 79, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2670315601 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2670315601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.92217308457717545227151669050706439639434569723713753362480201127039595601808
Line 71, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1850691397 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1850691397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.99452418731988566826081904518567360626336406441409704806430523868961701098548
Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 540828213 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 540828213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 16 failures:
3.i2c_target_nack_txstretch.10600201992339322205684169652966786450099440551742589573250019508473424944910
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 530827568 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 530827568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_nack_txstretch.56102071499012044638310197891124827061710190169082846519468294071364229529592
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 214464325 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 214464325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 12 failures:
0.i2c_target_unexp_stop.69543253991881768849212478359006042278690607914340033261879933353863657593386
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 390873180 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 390873180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.i2c_target_unexp_stop.91934839699826543191733707623423068465832113508913341847847742780861833229514
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/12.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 156808221 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 156808221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 12 failures:
1.i2c_host_mode_toggle.78334082802837698166342286257250035072552226228820871429243937643049054058402
Line 74, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 70093569 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
7.i2c_host_mode_toggle.64243224105422241682046196595700299847889719085672026774767839904644748241747
Line 74, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 81153407 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 10 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 7 failures:
6.i2c_target_stretch.4695556624568652701388253021410615970554936116054980422331184882966568621595
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10002796604 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10002796604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_stretch.70255774237328038414448049371349035610987172061791437811753384394149570773532
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/13.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10012943721 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10012943721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:
3.i2c_target_unexp_stop.95039145572125137954699275200377706142255336523688210855402672358186145831350
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 836965065 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 836965065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_unexp_stop.39596097521141257905988620751543575592130812202134424334989068428302728050775
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 95947685 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 95947685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 5 failures:
0.i2c_target_fifo_watermarks_tx.50200512027850610267320231976237356300016400259121709255752971572182920172947
Line 108, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/0.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
5.i2c_target_fifo_watermarks_tx.99710263325911708158863647526116173576295829818117530092855137761226863501582
Line 108, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/5.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 1 more failures.
4.i2c_target_tx_stretch_ctrl.10009730911529574328301264324769782793721956626998281187761202706613658507578
Line 111, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/4.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
14.i2c_target_tx_stretch_ctrl.89957707090244571307154798256052522796769253664770755523644903310632508533068
Line 111, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/14.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 4 failures:
36.i2c_host_stress_all.94312860614702466082887458732517700057602973864758535476081580901979539133809
Line 114, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/36.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 13368125221 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @14597619
40.i2c_host_stress_all.40788043008816408937447383751781849158734258123424353928074618449471248011015
Line 117, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/40.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 26669724407 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3983085
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
1.i2c_target_stress_all_with_rand_reset.28580923062591801218828777021254905713027993410128661736258548450315051704981
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1065421554 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1065421554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.38688595061721686190419514103337847974656935202737413174731582027102213276293
Line 115, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6103802477 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 6103802477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
3.i2c_host_mode_toggle.105799463309083563790814690020782219138374696892099380485366661113140759628668
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 238621339 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x9165c294, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 238621339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.i2c_host_mode_toggle.43301372780015210850094952170360929619453486586569300741022282481541823278083
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 25442037 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x3cefcc94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 25442037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job timed out after * minutes has 3 failures:
Test i2c_host_perf has 1 failures.
19.i2c_host_perf.20398912881651993623710658288665730352530681668758224392205106013604861609644
Log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/19.i2c_host_perf/latest/run.log
Job timed out after 60 minutes
Test i2c_host_stress_all has 2 failures.
24.i2c_host_stress_all.7735547225461842939541342631650022260460470583095867721622951674325224161713
Log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/24.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
47.i2c_host_stress_all.90225252669035549323510271752117006565251562443209392547320860436589387994515
Log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/47.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
3.i2c_target_bad_addr.65199495894992530127447264614525726172838483408669563661213222930817163974208
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/3.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3042) has 1 failures:
33.i2c_host_stress_all.93455218215083747576174554157008359308787747651094578693711406160326010297195
Line 208, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/33.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 139777420282 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=0x16c9af94, Comparison=CompareOpEq, exp_data=0x0, call_count=3042)
UVM_INFO @ 139777420282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
45.i2c_host_error_intr.8076242621708955471929515137212823094171736932548696647317257495305812990160
Line 75, in log /workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/45.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 88980103 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------