I2C Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.976m	9.087ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	52.700s	10.605ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.220s	29.640us	5	5	100.00
V1	csr_rw	i2c_csr_rw	1.220s	17.943us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.880s	951.993us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.810s	226.864us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.940s	32.474us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.220s	17.943us	20	20	100.00
		i2c_csr_aliasing	2.810s	226.864us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	14.470s	303.991us	49	50	98.00
V2	host_stress_all	i2c_host_stress_all	45.814m	170.675ms	16	50	32.00
V2	host_maxperf	i2c_host_perf	14.899m	25.172ms	50	50	100.00
V2	host_override	i2c_host_override	1.090s	148.430us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.239m	19.436ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.710m	9.580ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.020s	593.002us	50	50	100.00
		i2c_host_fifo_fmt_empty	26.730s	398.096us	50	50	100.00
		i2c_host_fifo_reset_rx	14.690s	1.109ms	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.477m	14.171ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	49.880s	1.093ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	9.440s	368.866us	19	50	38.00
V2	target_glitch	i2c_target_glitch	10.670s	6.921ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	27.237m	67.488ms	50	50	100.00
V2	target_maxperf	i2c_target_perf	11.220s	7.458ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.260m	2.997ms	50	50	100.00
		i2c_target_intr_smoke	12.530s	1.236ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.830s	993.798us	50	50	100.00
		i2c_target_fifo_reset_tx	4.210s	348.388us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	28.659m	67.576ms	50	50	100.00
		i2c_target_stress_rd	1.260m	2.997ms	50	50	100.00
		i2c_target_intr_stress_wr	8.216m	24.902ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	14.960s	1.457ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	2.569m	3.873ms	46	50	92.00
V2	bad_address	i2c_target_bad_addr	12.390s	2.480ms	49	50	98.00
V2	target_mode_glitch	i2c_target_hrst	1.069m	10.348ms	31	50	62.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	6.780s	4.248ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	2.850s	320.992us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	14.899m	25.172ms	50	50	100.00
		i2c_host_perf_precise	14.606m	23.246ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	49.880s	1.093ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	13.750s	603.723us	47	50	94.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.360s	528.792us	50	50	100.00
		i2c_target_nack_acqfull_addr	5.790s	1.113ms	50	50	100.00
		i2c_target_nack_txstretch	2.910s	472.078us	33	50	66.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	33.540s	1.825ms	50	50	100.00
V2	target_mode_n_byte_ack_control	target_mode_n_byte_ack_control			0	0	--
V2	target_mode_bus_timeout	target_mode_bus_timeout			0	0	--
V2	controller_mode_bus_timeout	controller_mode_bus_timeout			0	0	--
V2	controller_mode_bus_idle_delay	controller_mode_bus_idle_delay			0	0	--
V2	loopback_test	loopback_test			0	0	--
V2	multi_controller_clock_synchronization	multi_controller_clock_synchronization			0	0	--
V2	multi_controller_arbitration_lost_interference	multi_controller_arbitration_lost_interference			0	0	--
V2	multi_controller_arbitration_lost	multi_controller_arbitration_lost			0	0	--
V2	target_mode_arbitration_lost_interference	target_mode_arbitration_lost_interference			0	0	--
V2	target_mode_arbitration_lost	target_mode_arbitration_lost			0	0	--
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.490s	5.689ms	50	50	100.00
V2	alert_test	i2c_alert_test	1.010s	17.613us	50	50	100.00
V2	intr_test	i2c_intr_test	1.130s	18.854us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.800s	264.847us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.800s	264.847us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.220s	29.640us	5	5	100.00
		i2c_csr_rw	1.220s	17.943us	20	20	100.00
		i2c_csr_aliasing	2.810s	226.864us	5	5	100.00
		i2c_same_csr_outstanding	1.820s	280.397us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.220s	29.640us	5	5	100.00
		i2c_csr_rw	1.220s	17.943us	20	20	100.00
		i2c_csr_aliasing	2.810s	226.864us	5	5	100.00
		i2c_same_csr_outstanding	1.820s	280.397us	20	20	100.00
V2		TOTAL			1682	1792	93.86
V2S	tl_intg_err	i2c_tl_intg_err	3.630s	588.789us	20	20	100.00
		i2c_sec_cm	1.420s	67.639us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.630s	588.789us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	42.930s	3.105ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.690s	561.100us	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	54.580s	3.559ms	0	10	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	70	0.00
		TOTAL			1862	2042	91.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	49	38	30	61.22
V2S	2	2	2	100.00
V3	4	3	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.42	97.37	89.65	97.22	72.62	94.47	98.44	90.21

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 40 failures:

Test i2c_host_mode_toggle has 13 failures.

0.i2c_host_mode_toggle.46273194224401905416579809418920026626256491864638020227385025736858842586319
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 801898423 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @95338

3.i2c_host_mode_toggle.39017565439007427377850858102250929926361828021743791550915489923462168232023
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 420578639 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @11662

... and 11 more failures.

Test i2c_host_stress_all has 27 failures.

2.i2c_host_stress_all.4134212041904867888932191211893724868438978944793180250788746011592279276802
Line 199, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 170675303420 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @52344821

3.i2c_host_stress_all.55789750912089431621979945878166206810547487377098586539009457579953980456296
Line 233, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 21783624482 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3621555

... and 25 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 27 failures:
- Test i2c_target_unexp_stop has 27 failures.
  - 0.i2c_target_unexp_stop.97825861059948886851135470068867966668769887430429073555327646792213417122820
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 106998998 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 52 [0x34])
  UVM_INFO @ 106998998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_unexp_stop.22638643194970216913402518653367148779759855254277642848842947496785674439004
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  41193012 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 217 [0xd9])
  UVM_INFO @  41193012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 19 failures:
- Test i2c_target_hrst has 19 failures.
  - 1.i2c_target_hrst.56275758090724060897692711435327854342482178207269481563742857455608376264296
    Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10130252064 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10130252064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.i2c_target_hrst.48451414637310698322307664889371503417720532177537534529504082222143346439345
    Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10049807472 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10049807472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.

UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.9573886197795875298062929771308454563338623125077734924811936803823955615876
Line 86, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1310965109 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1310965109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.57742655295490251193268814626075820259225310979984660241569232116099143570168
Line 75, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3561494949 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3561494949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 7 failures.

1.i2c_target_stress_all_with_rand_reset.7389782843525053377242852926649387043586612795072787436145708131951724114678
Line 123, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 960759202 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 960759202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all_with_rand_reset.27356153061277884078758785510241632776763515853873080097533140601191475910679
Line 71, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 360225152 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 360225152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 17 failures:
- Test i2c_target_unexp_stop has 17 failures.
  - 5.i2c_target_unexp_stop.97141051651126763009253228062704695316316269977501396463812277027932013503683
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  93114520 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  93114520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.i2c_target_unexp_stop.14660269991440821876498131179435043531635550135051087024393774808852189730944
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 301602909 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 301602909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 17 failures:
- Test i2c_target_nack_txstretch has 17 failures.
  - 7.i2c_target_nack_txstretch.108276709231579411166600713451177940421027576260030181281870520621326695772319
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 324033344 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 324033344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.i2c_target_nack_txstretch.46736799612712191373961395292101797766710049352053947829095043563953590088283
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 204588190 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 204588190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 13 failures:

Test i2c_host_mode_toggle has 13 failures.

2.i2c_host_mode_toggle.69241080184897727487194425306809696451319472106867436876347403889312432863338
Line 74, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 118915802 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

4.i2c_host_mode_toggle.59501478062295923632509469206732239837198643924298272172305341241131510164219
Line 74, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  68481326 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 11 more failures.

Job timed out after * minutes has 6 failures:
- Test i2c_host_stress_all has 6 failures.
  - 15.i2c_host_stress_all.32704182165165397232339292320586201707364863983296163586739369833581838037912
    Log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 18.i2c_host_stress_all.111767588422138371211861981563997626112582082593315620704608261069242651643571
    Log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 4 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:

Test i2c_target_unexp_stop has 6 failures.

30.i2c_target_unexp_stop.102079289170732233552783427588518944306328263939614383174938649698080047299246
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 361405704 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 361405704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.i2c_target_unexp_stop.99775703682606088085038538365189123912496708327773964822462167166838263883013
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 354664712 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 354664712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
- Test i2c_target_stretch has 4 failures.
  - 1.i2c_target_stretch.26120626298293204836668321482029832797828987721034332808131805075819489321797
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10002308817 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10002308817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.i2c_target_stretch.22467383329153067039807458177233394595965368794668466920010966000128251990335
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10011607091 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10011607091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 0.i2c_target_stress_all_with_rand_reset.35662146372267797196546304034018673578484348284043978483007776684179065755921
    Line 102, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1691047443 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1691047443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.i2c_target_stress_all_with_rand_reset.109168333348446627718780107401653416701177313425610806544334602486406535441661
    Line 83, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12681622827 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 12681622827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
- Test i2c_target_tx_stretch_ctrl has 3 failures.
  - 5.i2c_target_tx_stretch_ctrl.113985704115636393913824099032842569087906498287617236921230049714648688068905
    Line 117, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 34.i2c_target_tx_stretch_ctrl.7255704895789636666949507854828282173419990695150174362337745469929194567151
    Line 111, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
- Test i2c_host_mode_toggle has 3 failures.
  - 23.i2c_host_mode_toggle.14289046022712815170993002983078219591926271582149866889500313284407996425008
    Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 231019765 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x43f48114, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 231019765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.i2c_host_mode_toggle.74881422370739219872618157232580970551878332094580398251580822145295045543997
    Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 212150329 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xbaba4894, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 212150329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Error-[NOA] Null object access has 2 failures:
- Test i2c_host_mode_toggle has 2 failures.
  - 14.i2c_host_mode_toggle.29760722432213304253594899101357362468175164659407759909656036397690598024355
    Line 73, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  ../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
  - 44.i2c_host_mode_toggle.6517741853360572002712433532010064443320046376363400585593360175021272785518
    Line 73, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  ../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
- Test i2c_host_error_intr has 1 failures.
  - 13.i2c_host_error_intr.52558048361971910601668196479878555374556125548237481844505010763875043251661
    Line 75, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_host_error_intr/latest/run.log
```
  UVM_ERROR @  65997381 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_target_bad_addr has 1 failures.
  - 29.i2c_target_bad_addr.76165208719188142133985562024179832027380088517562390110401584259637502374803
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 35.i2c_host_stress_all.77111038359451374987288751483027564610032063430131302891603048294402073515535
    Line 229, in log /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 21112838381 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2170857
```