a861deb3de| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.706m | 1.794ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 44.330s | 5.598ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 1.160s | 20.395us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 1.160s | 50.837us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 6.260s | 138.805us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 3.270s | 128.519us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 2.250s | 54.784us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 1.160s | 50.837us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 3.270s | 128.519us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 12.980s | 836.281us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 40.546m | 33.654ms | 15 | 50 | 30.00 |
| V2 | host_maxperf | i2c_host_perf | 38.938m | 52.152ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 1.100s | 89.719us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 5.918m | 5.316ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.005m | 2.578ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.310s | 163.559us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 34.090s | 1.018ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 17.080s | 993.755us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.192m | 10.702ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 58.130s | 1.031ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 9.570s | 230.456us | 14 | 50 | 28.00 |
| V2 | target_glitch | i2c_target_glitch | 14.620s | 9.461ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 19.973m | 49.685ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 11.600s | 5.798ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.463m | 3.188ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 14.690s | 1.831ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.930s | 378.926us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.150s | 1.090ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 22.074m | 60.430ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.463m | 3.188ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 15.492m | 41.502ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 14.340s | 5.187ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.893m | 2.647ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 11.900s | 5.539ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 59.060s | 10.281ms | 20 | 50 | 40.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 6.520s | 2.715ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 2.800s | 371.780us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 38.938m | 52.152ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 11.643m | 24.235ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 58.130s | 1.031ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 17.630s | 836.754us | 46 | 50 | 92.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 5.870s | 2.875ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.390s | 552.795us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 3.110s | 227.845us | 30 | 50 | 60.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 33.710s | 5.174ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 4.980s | 564.821us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 1.040s | 16.283us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 1.130s | 58.018us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.890s | 209.680us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.890s | 209.680us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 1.160s | 20.395us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.160s | 50.837us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 3.270s | 128.519us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.870s | 110.920us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 1.160s | 20.395us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.160s | 50.837us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 3.270s | 128.519us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.870s | 110.920us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1659 | 1792 | 92.58 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.680s | 895.212us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.570s | 1.306ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.680s | 895.212us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 1.314m | 19.457ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 3.320s | 276.870us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 43.220s | 4.645ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1839 | 2042 | 90.06 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 29 | 59.18 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.42 | 97.30 | 89.84 | 97.22 | 72.62 | 94.40 | 98.44 | 90.11 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 50 failures:
0.i2c_host_stress_all.51076057367811329756555978250744886557031911885745249208023177625326379703102
Line 147, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 24142729016 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @28378989
1.i2c_host_stress_all.80873898054231606414966608881512411389613874724438460739947911181849205508947
Line 202, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 23561619669 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @8460493
... and 28 more failures.
0.i2c_host_mode_toggle.25066592458870471347607861359410886666059950696155884225520814972921525358956
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 380772434 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @75262
3.i2c_host_mode_toggle.100231424570464964525952177749199104923195321792974793444367061344848067513880
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 277428074 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @27448
... and 18 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 30 failures:
2.i2c_target_hrst.81818127167899294537769127727996597264084063538857558421803934313916169247907
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10294905845 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10294905845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_hrst.83034739456987802932812328399125107535674051778416694228504815463592787075805
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10225505116 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10225505116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 23 failures:
3.i2c_target_unexp_stop.39103878126725128284944127264258420045397714757456747532499770991126754295419
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 276870183 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 13 [0xd])
UVM_INFO @ 276870183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.50448208546717695460184434073654531363761554485181689505595464167632431303983
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 218225039 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 145 [0x91])
UVM_INFO @ 218225039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
9.i2c_target_stress_all_with_rand_reset.39285500568626005598386020239351025245437676602625290732801709646806175807802
Line 116, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 856600806 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 74 [0x4a])
UVM_INFO @ 856600806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 20 failures:
0.i2c_target_nack_txstretch.108453501998696047438639200174933443111028488309146777794232542213395670823793
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 755010521 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 755010521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_nack_txstretch.78490165394483289192911645090733700573931693692904997319645398552947959076671
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 288134725 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 288134725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 18 failures:
0.i2c_target_unexp_stop.75661971613139832926481016630468648479337632183127453392225512669220050640435
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 151798554 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 151798554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.69825968017027722051426034004335830917323871701388222018312794109138224126552
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 125838153 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 125838153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
0.i2c_host_stress_all_with_rand_reset.34396312008144898053318682024417341955655409630122693410682878102065677327906
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 415623588 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 415623588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.37800375901634609563627963855524002726240526101374946878143425725967592986206
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 505871194 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 505871194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.43117333478067592645633870992019626464371867595485279273889938179881972299248
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2651305148 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2651305148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.52245164469099080715183048845047288522726446206923548368944734810143050558339
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 571253673 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 571253673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 13 failures:
1.i2c_host_mode_toggle.83807322065097481466105522017063509333156460785478061196999503834765839062227
Line 74, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 41951556 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
7.i2c_host_mode_toggle.20103619025028328645724684494698685676723693443734014849245268490470036712609
Line 74, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 33034916 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 11 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 10 failures:
7.i2c_target_unexp_stop.72856934571034761572091671948116325934597071443666672753312105055092476394755
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 96223861 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 96223861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.i2c_target_unexp_stop.37601828072513136064211702456963671749230632731375001667345650498407688405089
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 159485168 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 159485168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 5 failures:
Test i2c_target_fifo_watermarks_tx has 1 failures.
2.i2c_target_fifo_watermarks_tx.437955608974938228206032185147741231369222131656418972595438876056301560979
Line 108, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_tx_stretch_ctrl has 4 failures.
20.i2c_target_tx_stretch_ctrl.47298173021838957220092716509357760262607858878940615878165714398175760994411
Line 111, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
37.i2c_target_tx_stretch_ctrl.56250398323543353022747870454495869617626531884491109967380012367927987761003
Line 117, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
5.i2c_target_stretch.72693324378439850484624545418659196897430026737635879685054191330454611311139
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10004665839 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10004665839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.i2c_target_stretch.92525866550066848383127243875956704788602589246591910910643958792889771439
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10018874776 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10018874776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
2.i2c_host_mode_toggle.58112418803638754970229381096310041201959840854587134759160193890557975355812
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 154068117 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xccc4a614, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 154068117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.i2c_host_mode_toggle.59805110146518062237283139191694598361570936397472138832397030583142600572620
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 102889668 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xe1fb7f14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 102889668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
1.i2c_target_stress_all_with_rand_reset.74145684158396858810276515772470611453534911317798479632051322691085438228020
Line 97, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 603632541 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 603632541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.8412357868586089633187754154805749726715882862459388814787867010584625735251
Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 838121576 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 838121576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_smoke_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 2 failures:
2.i2c_target_stress_all_with_rand_reset.113414139175356853294606903838014836577806182062864273095255213555922734088588
Line 94, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 55566733 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_smoke_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 55566733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.39776079935135266002694884922882491024364678406458609412947462066163840720204
Line 91, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 230700782 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_smoke_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 230700782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes has 2 failures:
8.i2c_host_stress_all.81148969963543941174330195902493687878673488035699765472669049146043831103211
Log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
10.i2c_host_stress_all.53548090344872174284846958079510419313692432130100108880003668485829097289559
Log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:
18.i2c_host_stress_all.25194883983586529061470099978936926405130840081266386999183037585939706051664
Line 116, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 11342475392 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2686351
19.i2c_host_stress_all.5298670479003223075555807508120661793537287849981312916678793057740001635250
Line 265, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 11502898366 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2635191
UVM_ERROR (cip_base_vseq.sv:501) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
8.i2c_same_csr_outstanding.31937958045034325763920773327397228385887531490124126774021935523199533809766
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 44542190 ps: (cip_base_vseq.sv:501) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 44542190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
24.i2c_host_stress_all.96601153772210123108307520366177295643978785481832084611067972057466790732777
Line 71, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=66) has 1 failures:
43.i2c_host_perf_precise.108912176909973956588149320827901181992535658881096403279535082626591887231589
Line 67, in log /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_host_perf_precise/latest/run.log
UVM_FATAL @ 10135211064 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=0xf0a7f094, Comparison=CompareOpEq, exp_data=0x0, call_count=66)
UVM_INFO @ 10135211064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---