ed1c41cd0f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.061m | 9.601ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 44.650s | 1.049ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 1.180s | 21.298us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 1.180s | 67.207us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 6.240s | 647.051us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.820s | 108.097us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.810s | 98.941us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 1.180s | 67.207us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.820s | 108.097us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 24.840s | 2.123ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 56.514m | 68.309ms | 14 | 50 | 28.00 |
| V2 | host_maxperf | i2c_host_perf | 34.350m | 49.041ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 1.110s | 29.036us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 5.226m | 4.531ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.126m | 2.649ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.310s | 786.966us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 30.430s | 480.906us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 15.770s | 920.050us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.106m | 17.537ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 1.057m | 1.095ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 7.930s | 805.168us | 16 | 50 | 32.00 |
| V2 | target_glitch | i2c_target_glitch | 19.560s | 2.118ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 16.323m | 43.107ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 11.310s | 1.800ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.869m | 2.001ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 15.160s | 3.259ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 3.600s | 1.035ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.660s | 478.689us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 36.755m | 70.285ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.869m | 2.001ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 10.626m | 31.033ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 14.850s | 6.461ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.350m | 4.010ms | 49 | 50 | 98.00 |
| V2 | bad_address | i2c_target_bad_addr | 13.350s | 1.514ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 1.154m | 10.083ms | 24 | 50 | 48.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 5.430s | 3.816ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 3.180s | 3.037ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 34.350m | 49.041ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 12.615m | 23.267ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 1.057m | 1.095ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 15.930s | 1.022ms | 45 | 50 | 90.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 5.700s | 477.613us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.450s | 1.097ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 2.850s | 170.248us | 36 | 50 | 72.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 23.030s | 1.052ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 4.850s | 622.958us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 1.050s | 19.921us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 1.150s | 21.393us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.770s | 146.888us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.770s | 146.888us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 1.180s | 21.298us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.180s | 67.207us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.820s | 108.097us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.900s | 224.039us | 18 | 20 | 90.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 1.180s | 21.298us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.180s | 67.207us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.820s | 108.097us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.900s | 224.039us | 18 | 20 | 90.00 | ||
| V2 | TOTAL | 1673 | 1792 | 93.36 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.220s | 131.726us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.470s | 93.857us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.220s | 131.726us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 56.320s | 929.089us | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 5.370s | 463.513us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 1.549m | 7.272ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1853 | 2042 | 90.74 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 30 | 61.22 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.20 | 97.21 | 89.46 | 97.22 | 72.02 | 94.26 | 98.44 | 89.79 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 33 failures:
0.i2c_host_stress_all.99705822889629724865207790563647160163172509118950411290422787190744374849528
Line 182, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 120660815283 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2674351
5.i2c_host_stress_all.67488532901900602131017948486289720282384774847301199838739504722725037944664
Line 156, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 16513460181 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @8016605
... and 17 more failures.
0.i2c_host_mode_toggle.64512149589516745656582278616794661357012110993331096066049303640528922002858
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 446035467 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @25068
5.i2c_host_mode_toggle.75312274255920973469629430485156729726035258108049318045097332126554950780635
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 133155903 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @112790
... and 12 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 26 failures:
0.i2c_target_hrst.69321206938107410334786079118342751972926223703136695395330117328433086216868
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10015085427 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10015085427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.80339398281461304991594257402635912570377249103537746373093678485820161665864
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10232283415 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10232283415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 24 failures:
1.i2c_target_unexp_stop.17534010524256386026082655271423787373859196711183813039379632494088733046423
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 291946758 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 127 [0x7f])
UVM_INFO @ 291946758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.3236588393331331601310299551713882255867187139038833313430804250598781348283
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 149483676 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 232 [0xe8])
UVM_INFO @ 149483676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
1.i2c_target_stress_all_with_rand_reset.72043860118287980027700140735237801505978306929507482190170506221987722659250
Line 86, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1747292752 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 93 [0x5d])
UVM_INFO @ 1747292752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 17 failures:
0.i2c_target_unexp_stop.46393356257214721084845153237533211009822194733115959050476218122387806557606
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 88229635 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 88229635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.52634905615438635994173509488156695593078083702668137154470345651557241958062
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 656338643 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 656338643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
0.i2c_host_stress_all_with_rand_reset.7821029017799869281129037822635345964866247278953739530735326641704211589248
Line 73, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 409041149 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 409041149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.37016963438510100161284413250352457650428943919520539202161417706961129391600
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1135698399 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1135698399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.77056676298906734437400420513329003559042287350539277022395758734473704155598
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1292153380 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1292153380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.104117812632561541601913190337740588233707107868928545504859832978079234189417
Line 120, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5716865158 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5716865158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 15 failures:
2.i2c_host_mode_toggle.81282153298960367352622651121826375909507776520879029778303903515752496425350
Line 74, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 49189140 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
3.i2c_host_mode_toggle.23142933390161546969187356962358425521616850314580761728063464285735805346905
Line 74, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 63064278 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 12 more failures.
22.i2c_host_stress_all.103606453737343147939509632653197273651648199216703253623728046654490800029878
Line 73, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 3368930032 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
1.i2c_target_nack_txstretch.14506793375543497905770417626171549261744587067642361393631410786661938102442
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 1328589959 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 1328589959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_nack_txstretch.3646293874060902669418348903863254352558124130205664155960571830446544975210
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 608695966 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 608695966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 10 failures:
3.i2c_target_unexp_stop.9742176499090680413559905227592782194201732682763053004012015211986773379354
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 644457456 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 644457456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_unexp_stop.74474075526163573105867169764212020405584611405060020507616958748192241161011
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 286599912 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 286599912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Job timed out after * minutes has 9 failures:
2.i2c_host_stress_all.31651016398513316671869078222389840383362041553255456557278103381467807601004
Log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
12.i2c_host_stress_all.1950978445574821502803185651507288005835644334948293918908434816270386721062
Log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
... and 6 more failures.
6.i2c_host_perf.58531441816458957651358258045978981286853971252781772068408717765208540084966
Log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/6.i2c_host_perf/latest/run.log
Job timed out after 60 minutes
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 7 failures:
8.i2c_host_stress_all.54923974894250070868717237809015294944868542879578265524095924060444102681570
Line 260, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 40395301267 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2844535
10.i2c_host_stress_all.74185034569598253561920451511005705715752657482170163234478763698716821665010
Line 206, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 33876737898 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @18587249
... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 6 failures:
4.i2c_host_mode_toggle.100136464624393212385261687486951655481646260156068822821840886392649231301423
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 78440225 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x6d131314, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 78440225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_host_mode_toggle.107310667376215960624803329701399472831277462225766454864278284496020203176252
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 221953214 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xeee3a594, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 221953214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 5 failures:
5.i2c_target_tx_stretch_ctrl.68673852340034919991875687882243111938133351703350244177624493241812283319492
Line 117, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/5.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
13.i2c_target_tx_stretch_ctrl.66404414115565503704223605609414304514809937647325579104508251459284143293510
Line 111, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/13.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
2.i2c_target_stress_all_with_rand_reset.114756696441155338002747108943713091841207923136807295778455999275243552307525
Line 202, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7271894594 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 7271894594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.114719029671983444681009807959972046345890608629708862816482228167811838714384
Line 71, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 213296829 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 213296829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:501) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:
4.i2c_same_csr_outstanding.43484195336656611063549529477502908367682894276592977980903299769442844907809
Line 67, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/4.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 43347590 ps: (cip_base_vseq.sv:501) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 43347590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.i2c_same_csr_outstanding.71475907124301520358471940978182196698956339963821353230344380301674094597259
Line 64, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/19.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 106726373 ps: (cip_base_vseq.sv:501) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 106726373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
3.i2c_target_stress_all_with_rand_reset.25463638487727597876181195502475722976264201837599490834087867014575869923709
Line 94, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 284490821 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 284490821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
4.i2c_host_stress_all.106464875512048054244157270298377172510479478784415876664999505887622067938237
Line 121, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 38622444848 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 1 failures:
45.i2c_target_stretch.52258743712415164933419963423961466929538093417825649569673270821061439908777
Line 65, in log /workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/45.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10012561529 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10012561529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---