372a6306e0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.907m | 1.984ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 51.250s | 1.559ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 1.230s | 71.227us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 1.190s | 24.721us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 6.110s | 218.721us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 3.120s | 220.313us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.710s | 56.082us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 1.190s | 24.721us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 3.120s | 220.313us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 18.820s | 2.135ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 39.595m | 97.777ms | 16 | 50 | 32.00 |
| V2 | host_maxperf | i2c_host_perf | 33.503m | 49.687ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 1.120s | 38.341us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 5.027m | 21.399ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.151m | 2.754ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.260s | 260.194us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 29.880s | 3.988ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.870s | 210.818us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.010m | 3.470ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 46.880s | 1.022ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 8.360s | 209.663us | 13 | 50 | 26.00 |
| V2 | target_glitch | i2c_target_glitch | 12.740s | 2.285ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 23.000m | 62.360ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 11.400s | 1.078ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.362m | 1.790ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 13.540s | 1.441ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 3.190s | 445.967us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 2.650s | 357.395us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 24.871m | 67.845ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.362m | 1.790ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 4.919m | 20.918ms | 48 | 50 | 96.00 | ||
| V2 | target_timeout | i2c_target_timeout | 14.400s | 1.555ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.499m | 4.977ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 13.180s | 7.246ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 45.530s | 10.246ms | 27 | 50 | 54.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 6.080s | 606.137us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 2.730s | 187.688us | 48 | 50 | 96.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 33.503m | 49.687ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 14.478m | 23.164ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 46.880s | 1.022ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 13.230s | 511.910us | 49 | 50 | 98.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 5.720s | 1.633ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.370s | 2.382ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 2.910s | 213.598us | 26 | 50 | 52.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 34.430s | 5.844ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 4.770s | 1.046ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 1.070s | 17.415us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 1.140s | 16.554us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.250s | 47.886us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.250s | 47.886us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 1.230s | 71.227us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.190s | 24.721us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 3.120s | 220.313us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.730s | 65.581us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 1.230s | 71.227us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.190s | 24.721us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 3.120s | 220.313us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.730s | 65.581us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1663 | 1792 | 92.80 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.280s | 168.629us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.490s | 235.324us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.280s | 168.629us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 28.640s | 1.130ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 3.300s | 299.151us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 35.630s | 1.917ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1843 | 2042 | 90.25 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.17 | 97.15 | 89.65 | 97.22 | 71.43 | 94.11 | 98.44 | 90.21 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 45 failures:
1.i2c_host_stress_all.109367497639564152067307303459303007230759743716411100344818902905904031918883
Line 191, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 19679739045 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @10289211
2.i2c_host_stress_all.3406393277060763849883712026546653645627399664602555490117279618329439593989
Line 177, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 9188835688 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @9486421
... and 27 more failures.
2.i2c_host_mode_toggle.103029153464619964554426653633640065863068716729072733820372778573953005483965
Line 72, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 418188814 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @94240
3.i2c_host_mode_toggle.73200056893316176515960599107867750844856408165146914082476513808909305224305
Line 72, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 459853304 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @83122
... and 14 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 32 failures:
0.i2c_target_unexp_stop.31240503022205391951674721679094836727368457801949430013415339974328571300377
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 98689761 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 25 [0x19])
UVM_INFO @ 98689761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.103432572537464040012209187467940205472558115916001114123944073001655472602529
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 142676191 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 252 [0xfc])
UVM_INFO @ 142676191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 29 more failures.
4.i2c_target_stress_all_with_rand_reset.29336147473866129256081870619466918508102041359890701593250705437643667483788
Line 162, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5771018821 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 6 [0x6])
UVM_INFO @ 5771018821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 24 failures:
1.i2c_target_nack_txstretch.87484032639649536896304755201203495313675118751400785901746000619372477715635
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 144620383 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 144620383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_nack_txstretch.100590711751221989147221238817169735136496660781633999281943004356311033496513
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 158910159 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 158910159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 23 failures:
0.i2c_target_hrst.10681444804933745512209554178243133580842643616910333129333426970067854752921
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10072219579 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10072219579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.90153291742308009449141605106403452578553130242622747471944754512881502619099
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10161630282 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10161630282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
0.i2c_host_stress_all_with_rand_reset.53284687971595183339285860533631838295747504675266446016904125918940984638700
Line 78, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2225625836 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2225625836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.102600379717706749106552454644909338882531773591445035205098441979930647889613
Line 73, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 161604381 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 161604381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.93315735236731343767110316459981571124777698732222276971153842277214292372408
Line 71, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1314647914 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1314647914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.47670116342391945200713868268623998003979278199519347546305290093501237318587
Line 78, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 873829939 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 873829939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 16 failures:
1.i2c_host_mode_toggle.99790026388323070755171390636220629175096514710532162647984509328356798662921
Line 74, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 55137282 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
7.i2c_host_mode_toggle.96149579801667824556626527017221248328579727729575870971165012563491901365483
Line 74, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 40089850 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 14 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 13 failures:
1.i2c_target_unexp_stop.67296973417228884712707685112130378961718727219298142710337867787704255419520
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1032923470 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1032923470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.40362098956017458751334845872317968653364275935000435852536188293255293589260
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 208551064 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 208551064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:
2.i2c_target_unexp_stop.16178179265614834178124382056194434995875018760325521345121431304212071278230
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 565365050 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 565365050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_unexp_stop.72006419625867515974430898741369839394698483037064749674483536441206098618180
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 282900835 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 282900835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 4 failures:
0.i2c_host_stress_all.25226865659100718465342690162708863475421052897801153194086727639791409149806
Line 151, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 27323361759 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5060581
6.i2c_host_stress_all.16173122920132534354544304873848425109455090975984606068806861754229060338513
Line 334, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 16736879410 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @17502877
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
6.i2c_host_mode_toggle.78680739649564073121680264653883624300031207795542173724510496042906525419501
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 93964627 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x1d73ac14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 93964627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.i2c_host_mode_toggle.4601923649892420538966747363401500153600556180784988424581687148857951079553
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/14.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 48931232 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x32b57714, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 48931232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
25.i2c_target_stretch.97831846274722633636713086317411291474914679254284466755445959902932610793115
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/25.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10001370490 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10001370490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.i2c_target_stretch.24688770730441343632586891981999132663471921709888879737498194318609237992841
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/30.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10022897582 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10022897582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 3 failures:
Test i2c_target_intr_stress_wr has 2 failures.
20.i2c_target_intr_stress_wr.65115906470336489457631272046475312423199412175031944217755150125937178507809
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/20.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 38904557938 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 38904557938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.i2c_target_intr_stress_wr.60388031810100570476389257467978979554346334831027216470386821250052712591543
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/30.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 20432707421 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 20432707421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 1 failures.
42.i2c_target_stress_all.8296616244124124742167305772010925905965190735985098018515148854634288988555
Line 68, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/42.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 56077311393 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 56077311393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
Test i2c_target_fifo_watermarks_tx has 2 failures.
20.i2c_target_fifo_watermarks_tx.107421660173429591778555893162919270288334101261642878620103774517655544554858
Line 108, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/20.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
48.i2c_target_fifo_watermarks_tx.101233872455308707815416737581790252564139256503828709731466192517026630001060
Line 108, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/48.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_tx_stretch_ctrl has 1 failures.
24.i2c_target_tx_stretch_ctrl.112109508468546824332987425627863851543672271888297036626144995897735018012577
Line 111, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/24.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (cip_base_vseq.sv:771) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
2.i2c_target_stress_all_with_rand_reset.34759102605245714177207331485297030060584831789479071361673898616726654706783
Line 72, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1540389408 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1540389408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.83571888243799926974532100973969399007022229498588356300923645332179841282441
Line 90, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 486226774 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 486226774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
1.i2c_target_stress_all_with_rand_reset.61582748652164325579503980342945634685682146914309641062002019284566248798924
Line 105, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7933854988 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 7933854988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:501) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
11.i2c_same_csr_outstanding.43028642306158331578620473575304901649068867367919775980011691773891507362856
Line 64, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/11.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 28900496 ps: (cip_base_vseq.sv:501) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 28900496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes has 1 failures:
18.i2c_host_stress_all.10661093936740666849198621864364191361110632235390223165223689179660606646587
Log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
Error-[NOA] Null object access has 1 failures:
20.i2c_host_mode_toggle.64297377737810236856696782507640207934097063099493051085139015039745092580358
Line 73, in log /workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/20.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.