af2d1709f9| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.788m | 2.232ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 46.290s | 8.340ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 1.170s | 61.703us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 1.420s | 410.459us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 7.100s | 374.182us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.910s | 650.876us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 2.300s | 53.284us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 1.420s | 410.459us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.910s | 650.876us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 34.020s | 2.875ms | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 42.110m | 45.502ms | 14 | 50 | 28.00 |
| V2 | host_maxperf | i2c_host_perf | 50.686m | 72.066ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 1.150s | 30.080us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 4.899m | 35.524ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.632m | 4.727ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.090s | 181.943us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 35.270s | 2.194ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 16.280s | 324.190us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.002m | 6.502ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 1.022m | 2.689ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 11.610s | 892.785us | 16 | 50 | 32.00 |
| V2 | target_glitch | i2c_target_glitch | 13.470s | 2.625ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 23.640m | 71.279ms | 48 | 50 | 96.00 |
| V2 | target_maxperf | i2c_target_perf | 11.460s | 4.875ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.264m | 1.616ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 13.330s | 2.885ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 3.800s | 320.382us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.030s | 242.241us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 24.487m | 68.615ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.264m | 1.616ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 13.126m | 41.470ms | 49 | 50 | 98.00 | ||
| V2 | target_timeout | i2c_target_timeout | 13.850s | 1.434ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 4.340m | 5.532ms | 44 | 50 | 88.00 |
| V2 | bad_address | i2c_target_bad_addr | 12.090s | 2.246ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 56.110s | 10.102ms | 23 | 50 | 46.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 6.060s | 552.551us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 2.830s | 640.908us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 50.686m | 72.066ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 14.190m | 24.293ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 1.022m | 2.689ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 20.310s | 1.361ms | 47 | 50 | 94.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 5.790s | 641.774us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.670s | 7.887ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 2.830s | 122.922us | 37 | 50 | 74.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 33.510s | 2.928ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 4.970s | 577.832us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 1.050s | 19.121us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 1.180s | 19.388us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.740s | 120.849us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.740s | 120.849us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 1.170s | 61.703us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.420s | 410.459us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.910s | 650.876us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.690s | 174.184us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 1.170s | 61.703us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.420s | 410.459us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.910s | 650.876us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.690s | 174.184us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1668 | 1792 | 93.08 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.430s | 501.415us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.440s | 85.840us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.430s | 501.415us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 43.540s | 3.542ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 5.240s | 1.645ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 41.300s | 10.109ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1848 | 2042 | 90.50 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.09 | 97.15 | 89.39 | 97.22 | 71.43 | 94.11 | 98.44 | 89.89 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 43 failures:
0.i2c_host_stress_all.23867418447158143552273233115967677798457018147602266992398476282716457846672
Line 257, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 42076600941 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1953297
3.i2c_host_stress_all.8967488832268028630946594756101950114907346704784127592587389552875836597395
Line 126, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 19936752694 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4572377
... and 24 more failures.
0.i2c_host_mode_toggle.54677868982611185858457050507724420754986829064959376809182372621989194764423
Line 72, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 90559251 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @22030
2.i2c_host_mode_toggle.27460582739646103573282354383214004180389606656286904658489836111761689958995
Line 72, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 68366900 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @22830
... and 15 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 33 failures:
2.i2c_target_unexp_stop.2812525941878789073859336637725970144170881435601971556806063996955329240115
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 762298240 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 173 [0xad])
UVM_INFO @ 762298240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.104887318278675854684171008867091391559211808171385455742657484537984353010932
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1159381036 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 197 [0xc5])
UVM_INFO @ 1159381036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
3.i2c_target_stress_all_with_rand_reset.57117588410038236251778282781035160015801092074312028831026591920025001848664
Line 76, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19071392 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (29 [0x1d] vs 0 [0x0])
UVM_INFO @ 19071392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 27 failures:
0.i2c_target_hrst.81764156050629159653605703777395028823417403531467336112992146521082104281364
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10004035153 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10004035153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_hrst.39204062321295895681026983119059533179178326348345908017936427212212796213720
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10409143191 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10409143191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
0.i2c_host_stress_all_with_rand_reset.51919800608231936364574749104050748062807455345333184812384529555276924921765
Line 117, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1206073063 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1206073063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.111247872579333817665878680623782709823809052894904269465835896915859031222754
Line 73, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 809208302 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 809208302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.45480488382421002901920621479512094360883040183088008563368808738132716712592
Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 946199716 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 946199716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.46129058970587240813568809874528218600841368035525419451275510786283735088494
Line 94, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1970650698 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1970650698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 13 failures:
0.i2c_target_nack_txstretch.60398602246227175266084078462840849676239183688677739883551318288135173477815
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 905360991 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 905360991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_nack_txstretch.31144814813776945058681433251062453213779794241681292205309845148335334876959
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 226667207 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 226667207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 11 failures:
0.i2c_target_unexp_stop.98560786774442936844926078324653982159698922830342942248044022139616640295867
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 502011296 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 502011296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_unexp_stop.91935769847527360910479423208539214546754325301884128871994980574019409284640
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 164384846 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 164384846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 10 failures:
1.i2c_host_mode_toggle.71481148862280004906276361140245557786484029205859221892143751919487418075863
Line 74, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 435018022 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
4.i2c_host_mode_toggle.69738874261521872367283128906722004038835745262268325587714785252741177044729
Line 74, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 104917286 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 8 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 7 failures:
1.i2c_target_unexp_stop.50047799988498293611976563196821916249302812513016328469827223547315953707332
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 479009238 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 479009238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.39656452897755688368614061415535195746396270586449045219345563764985690028680
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 552415183 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 552415183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 7 failures:
12.i2c_host_stress_all.5869181931993000786789774241701892181661692162752199247596544290884702256118
Line 243, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 82012059581 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @8292785
19.i2c_host_stress_all.39383081150691629161250804537542821064285838263560306354317851859182632712986
Line 194, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/19.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 36285252274 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2106323
... and 5 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 6 failures:
4.i2c_target_stretch.51344396353742374934254727515508285269295472425229119468023809860717967978976
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10025313033 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10025313033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_target_stretch.9725369475730579839239757370984830558334764980056932807594003163842064408832
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/21.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10061511962 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10061511962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
3.i2c_target_tx_stretch_ctrl.14836067905023236468839045633813665959411561682203777204788492568947701630996
Line 117, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/3.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
12.i2c_target_tx_stretch_ctrl.109363225675517662062811163498181668623335237405324486566280380767511380899776
Line 117, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 1 more failures.
40.i2c_target_fifo_watermarks_tx.54258293842471405489131767087397504606200186149194471862556309812835210509770
Line 108, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/40.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
29.i2c_host_mode_toggle.105939601871645336570633340163354590306647594892146134554361111962379589830297
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/29.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 192709127 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xdca4f094, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 192709127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.i2c_host_mode_toggle.97367484583207335809599090926401672426787695809312743541884820399219603445363
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/39.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 282832237 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x9b05fa14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 282832237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Error-[NOA] Null object access has 3 failures:
3.i2c_host_mode_toggle.4486046553267229318636915314335411487385757159450723478244857042416806413575
Line 73, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
38.i2c_host_mode_toggle.107323588619623474363811986207571149413273017487083070932733657086867848748725
Line 73, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/38.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
... and 1 more failures.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 3 failures:
Test i2c_target_intr_stress_wr has 1 failures.
5.i2c_target_intr_stress_wr.83822834217981902495980636338533076679709327541408437414093947169208575990367
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/5.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 41470465708 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 41470465708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 2 failures.
18.i2c_target_stress_all.65625359751837133565121912780665020973268414813196744962129407266729771186413
Line 100, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/18.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 118551388117 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 118551388117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.i2c_target_stress_all.85398830971111477831611687368943090299933513820325122321191494389714373678599
Line 96, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/29.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 87591113778 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 87591113778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes has 2 failures:
6.i2c_host_stress_all.59218877708531033688800529813833695843001578490995000102249722460608503532530
Log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
40.i2c_host_stress_all.18148107914206783503273720858064951322981754849087931836218424432498383950807
Log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/40.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
UVM_ERROR (cip_base_vseq.sv:771) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
5.i2c_target_stress_all_with_rand_reset.22557023467217015271807916893644497891413389283829548985390298967613930988041
Line 70, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 607525054 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 607525054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
13.i2c_host_stress_all.30238602366078481279513805753833606756178778362261975295761110990265199760985
Line 120, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/13.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
25.i2c_host_error_intr.32653709595434283466105062112448987026229286153146287014801019734509836295543
Line 75, in log /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/25.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 6535434 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------