25b1acbf68| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.898m | 9.608ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 51.510s | 1.320ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 1.210s | 19.070us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 1.230s | 24.097us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.810s | 445.935us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.800s | 146.714us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 2.170s | 29.296us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 1.230s | 24.097us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.800s | 146.714us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 14.290s | 474.994us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 28.986m | 18.535ms | 11 | 50 | 22.00 |
| V2 | host_maxperf | i2c_host_perf | 43.989m | 49.651ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 1.120s | 16.388us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 5.150m | 5.683ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.966m | 10.888ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.120s | 715.423us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 32.810s | 811.353us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.790s | 367.133us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.762m | 14.888ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 50.230s | 1.832ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 9.020s | 1.085ms | 20 | 50 | 40.00 |
| V2 | target_glitch | i2c_target_glitch | 19.290s | 2.299ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 32.468m | 64.684ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 12.930s | 1.055ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.599m | 6.670ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 15.100s | 3.091ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 3.140s | 259.287us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.060s | 768.862us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 27.657m | 71.796ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.599m | 6.670ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 3.984m | 40.482ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 15.030s | 5.884ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.587m | 3.427ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 15.190s | 7.111ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 59.520s | 10.106ms | 23 | 50 | 46.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 6.470s | 602.786us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 2.810s | 1.817ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 43.989m | 49.651ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 14.980m | 23.201ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 50.230s | 1.832ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 17.710s | 1.222ms | 46 | 50 | 92.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 5.880s | 1.957ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.890s | 632.138us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 2.820s | 776.116us | 36 | 50 | 72.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 30.490s | 591.560us | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 4.850s | 1.093ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 1.070s | 18.268us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 1.150s | 20.692us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 4.130s | 473.944us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 4.130s | 473.944us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 1.210s | 19.070us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.230s | 24.097us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.800s | 146.714us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.940s | 67.178us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 1.210s | 19.070us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.230s | 24.097us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.800s | 146.714us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.940s | 67.178us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1673 | 1792 | 93.36 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.150s | 79.401us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.550s | 63.585us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.150s | 79.401us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 31.600s | 658.452us | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 3.780s | 545.594us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 38.900s | 5.240ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1853 | 2042 | 90.74 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 31 | 63.27 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.23 | 97.21 | 89.54 | 97.22 | 72.02 | 94.26 | 98.44 | 89.89 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 48 failures:
0.i2c_host_mode_toggle.83642804746808679151779794570736594788640700329567191646850288550203524713046
Line 72, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 455296630 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @95158
2.i2c_host_mode_toggle.14576637315421462364853128863885021468566787361094322808301437472373673104155
Line 72, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 241828332 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @32414
... and 13 more failures.
2.i2c_host_stress_all.79811087411849174732589240852495182994478292894146138051123864259140349903079
Line 268, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 29450745356 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @37334903
3.i2c_host_stress_all.12404694837928232061181167895656607663563719858180674073104553157755125193076
Line 274, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 76988255382 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @17764921
... and 31 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 31 failures:
0.i2c_target_unexp_stop.6902533906352253926043686846665750945533888452625158968221144619697350822954
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 205251874 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 187 [0xbb])
UVM_INFO @ 205251874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.115037495144319507993236861880467987549612589038375230665574470247497619759831
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 172061378 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 32 [0x20])
UVM_INFO @ 172061378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
3.i2c_target_stress_all_with_rand_reset.54938006935543635568445982663030975725139211016536475279487284877428199073366
Line 94, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6378551399 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 235 [0xeb])
UVM_INFO @ 6378551399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.89121782818408065171538502121026933716098066883113289739776305195575422107344
Line 122, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1392484607 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 146 [0x92])
UVM_INFO @ 1392484607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 27 failures:
0.i2c_target_hrst.50792620710244646789343822194900594697329766569317105242742075537475382894188
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10373553771 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10373553771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_hrst.86596826681642830580733736828663069958573457733171426736400681450329111508799
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_FATAL @ 11958577580 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 11958577580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 19 failures:
4.i2c_target_unexp_stop.18058662785051689317405101156472720831620052627670973703397817576079482916260
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 242212659 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 242212659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.37744902747661761159012364398068407375382210022361070965061854439128005546934
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 203641939 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 203641939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
0.i2c_host_stress_all_with_rand_reset.53183782798587371489759580410980184449898670470477082782503852022190080320950
Line 77, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 658452440 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 658452440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.51501611938327655204087009636101951542556313319257016517799361999435307100573
Line 73, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 989900771 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 989900771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.24535500527842960506506391512827618591278207318227067949049737680570134501195
Line 84, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5240455713 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5240455713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.87079065564839290323261274322537420086490661836415441183901821373030512373747
Line 99, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2719092723 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2719092723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
1.i2c_target_nack_txstretch.76420637107290248512418001682884577904626780855030901517243532506204711977610
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 621132717 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 621132717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_nack_txstretch.43097067201439926323034295941835497294214808685879985253259253330295654488523
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 600176724 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 600176724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 10 failures:
4.i2c_host_mode_toggle.78641494525460193701897941457967265746830454239158241585370864640783864207334
Line 74, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 68523447 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
7.i2c_host_mode_toggle.15232880455790673367064110846615219217877776628741327735121476628770365341229
Line 74, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 38020879 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 8 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 5 failures:
Test i2c_target_fifo_watermarks_tx has 1 failures.
3.i2c_target_fifo_watermarks_tx.105328108088332878308518640538426218744820507941028250284201032232918621148733
Line 108, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/3.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_tx_stretch_ctrl has 4 failures.
16.i2c_target_tx_stretch_ctrl.2851867033295285427253721508576255188241316956846039876127244430219150441397
Line 111, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/16.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
22.i2c_target_tx_stretch_ctrl.38670239225630537139625466895034202253906613004156814525934717372897385991233
Line 117, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/22.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
1.i2c_target_stretch.76391742112833180792676298763054244543018632610867514437351227959522818216525
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/1.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10001282928 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10001282928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_target_stretch.111272832604794082964152144020112146232204139642784107854764181367876948756827
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/17.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10003929511 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10003929511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Job timed out after * minutes has 3 failures:
9.i2c_host_stress_all.56650934704443670380171582147431981465800094761155656031088039568570859749302
Log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
13.i2c_host_stress_all.68448446755718614229373037502985934944061748257010917230056971212260549790556
Log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/13.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
13.i2c_host_mode_toggle.66662308739130769305679367558630815315899329668796519568970972879246781687145
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/13.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 38052613 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xb32ec894, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 38052613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_host_mode_toggle.87992224589357729080783649210274482490724570390812671481688956661049656612135
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/21.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 122527501 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x7f0db694, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 122527501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 2 failures:
26.i2c_target_unexp_stop.27656201259911403597837338914432519807406486732693207684711723879639774046856
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/26.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 702821322 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 702821322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.i2c_target_unexp_stop.112224355240247425128605395384779798487580758722241375768400327842643362153662
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/43.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 184067049 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 184067049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:
28.i2c_host_stress_all.11216833886418151361816418927680743708858144893648044911573741521810462779992
Line 138, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/28.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 25155700209 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @6063799
35.i2c_host_stress_all.71083381677952089398982855724552425338930254111285952074903949049826179627570
Line 153, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/35.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 8924563866 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @288835
Error-[NOA] Null object access has 2 failures:
29.i2c_host_mode_toggle.45619482816834382179131843647596031258723566334405186169261245258668353807517
Line 73, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/29.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
44.i2c_host_mode_toggle.34658325993188299760662466845946160682913740947347342790606528633491634961347
Line 73, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/44.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=94) has 1 failures:
48.i2c_host_stress_all.62185807893562219357634320454921832929334405873102298331041897219314521185821
Line 78, in log /workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/48.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 47816941268 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=0x322ef414, Comparison=CompareOpEq, exp_data=0x0, call_count=94)
UVM_INFO @ 47816941268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---