| T1083 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_alert_test.3557289581 |
|
|
Oct 02 08:47:01 PM UTC 24 |
Oct 02 08:47:03 PM UTC 24 |
55411143 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull_addr.1576663029 |
|
|
Oct 02 08:47:00 PM UTC 24 |
Oct 02 08:47:04 PM UTC 24 |
1257962205 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_override.126559973 |
|
|
Oct 02 08:47:02 PM UTC 24 |
Oct 02 08:47:04 PM UTC 24 |
43845835 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_fmt.3149012451 |
|
|
Oct 02 08:47:04 PM UTC 24 |
Oct 02 08:47:06 PM UTC 24 |
961185608 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_rx.2838094659 |
|
|
Oct 02 08:47:04 PM UTC 24 |
Oct 02 08:47:09 PM UTC 24 |
1304891263 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_perf_precise.2626669657 |
|
|
Oct 02 08:47:07 PM UTC 24 |
Oct 02 08:47:11 PM UTC 24 |
228620276 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_stress_all.3783729994 |
|
|
Oct 02 08:45:22 PM UTC 24 |
Oct 02 08:47:11 PM UTC 24 |
11524157800 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_stress_all.2737691554 |
|
|
Oct 02 08:41:07 PM UTC 24 |
Oct 02 08:47:12 PM UTC 24 |
23553547995 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_intr_stress_wr.4289621952 |
|
|
Oct 02 08:46:47 PM UTC 24 |
Oct 02 08:47:12 PM UTC 24 |
22330124406 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_perf.3059663300 |
|
|
Oct 02 08:46:33 PM UTC 24 |
Oct 02 08:47:17 PM UTC 24 |
5252409266 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_fmt_empty.3897188633 |
|
|
Oct 02 08:47:04 PM UTC 24 |
Oct 02 08:47:19 PM UTC 24 |
563390366 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_stress_rd.2421762797 |
|
|
Oct 02 08:46:03 PM UTC 24 |
Oct 02 08:47:21 PM UTC 24 |
2853581501 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_full.1843621553 |
|
|
Oct 02 08:44:50 PM UTC 24 |
Oct 02 08:47:23 PM UTC 24 |
3274045836 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_intr_smoke.2861319854 |
|
|
Oct 02 08:47:18 PM UTC 24 |
Oct 02 08:47:24 PM UTC 24 |
10597370948 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_stress_wr.847103183 |
|
|
Oct 02 08:43:05 PM UTC 24 |
Oct 02 08:47:26 PM UTC 24 |
35785616614 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_acq.2624701948 |
|
|
Oct 02 08:47:25 PM UTC 24 |
Oct 02 08:47:28 PM UTC 24 |
619834013 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_stretch.694440245 |
|
|
Oct 02 08:47:16 PM UTC 24 |
Oct 02 08:47:29 PM UTC 24 |
1368510228 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_stretch_timeout.4115592346 |
|
|
Oct 02 08:47:10 PM UTC 24 |
Oct 02 08:47:29 PM UTC 24 |
1251184552 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_smoke.53067988 |
|
|
Oct 02 08:47:12 PM UTC 24 |
Oct 02 08:47:30 PM UTC 24 |
2286296212 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_tx.2109586709 |
|
|
Oct 02 08:47:27 PM UTC 24 |
Oct 02 08:47:30 PM UTC 24 |
689546886 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_intr_stress_wr.480131695 |
|
|
Oct 02 08:47:21 PM UTC 24 |
Oct 02 08:47:31 PM UTC 24 |
2468844588 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_host_perf_precise.2028888406 |
|
|
Oct 02 08:44:07 PM UTC 24 |
Oct 02 08:47:32 PM UTC 24 |
5852488490 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_timeout.4025752181 |
|
|
Oct 02 08:47:22 PM UTC 24 |
Oct 02 08:47:33 PM UTC 24 |
5854159623 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_hrst.3044599848 |
|
|
Oct 02 08:47:30 PM UTC 24 |
Oct 02 08:47:34 PM UTC 24 |
1062928275 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_perf.183787885 |
|
|
Oct 02 08:47:28 PM UTC 24 |
Oct 02 08:47:36 PM UTC 24 |
456613875 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_tx.2215016939 |
|
|
Oct 02 08:47:33 PM UTC 24 |
Oct 02 08:47:36 PM UTC 24 |
83874062 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_host_perf_precise.190316537 |
|
|
Oct 02 08:36:05 PM UTC 24 |
Oct 02 08:47:37 PM UTC 24 |
23156641857 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_acq.286908584 |
|
|
Oct 02 08:47:33 PM UTC 24 |
Oct 02 08:47:37 PM UTC 24 |
870885433 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_bad_addr.2897485893 |
|
|
Oct 02 08:47:29 PM UTC 24 |
Oct 02 08:47:38 PM UTC 24 |
7343899148 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_tx_stretch_ctrl.1602594563 |
|
|
Oct 02 08:47:34 PM UTC 24 |
Oct 02 08:47:38 PM UTC 24 |
118805932 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_overflow.3946239469 |
|
|
Oct 02 08:45:42 PM UTC 24 |
Oct 02 08:47:38 PM UTC 24 |
1690969965 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_error_intr.1100260620 |
|
|
Oct 02 08:47:42 PM UTC 24 |
Oct 02 08:47:45 PM UTC 24 |
345903386 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_smbus_maxlen.3717760342 |
|
|
Oct 02 08:47:35 PM UTC 24 |
Oct 02 08:47:40 PM UTC 24 |
1544953552 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_alert_test.2025829310 |
|
|
Oct 02 08:47:39 PM UTC 24 |
Oct 02 08:47:41 PM UTC 24 |
34046935 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull.720804152 |
|
|
Oct 02 08:47:36 PM UTC 24 |
Oct 02 08:47:41 PM UTC 24 |
2123089422 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_override.3229243917 |
|
|
Oct 02 08:47:39 PM UTC 24 |
Oct 02 08:47:41 PM UTC 24 |
30391234 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_nack_txstretch.3165747037 |
|
|
Oct 02 08:47:37 PM UTC 24 |
Oct 02 08:47:41 PM UTC 24 |
580267566 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_overflow.624886884 |
|
|
Oct 02 08:46:31 PM UTC 24 |
Oct 02 08:47:41 PM UTC 24 |
4591233416 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_fmt.2912983228 |
|
|
Oct 02 08:47:41 PM UTC 24 |
Oct 02 08:47:44 PM UTC 24 |
107535349 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_fmt_empty.3873923904 |
|
|
Oct 02 08:47:41 PM UTC 24 |
Oct 02 08:47:47 PM UTC 24 |
330504213 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_watermark.942380173 |
|
|
Oct 02 08:43:51 PM UTC 24 |
Oct 02 08:47:53 PM UTC 24 |
85093106587 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_stress_all.2731050581 |
|
|
Oct 02 08:46:19 PM UTC 24 |
Oct 02 08:47:54 PM UTC 24 |
46273429527 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_rx.253235013 |
|
|
Oct 02 08:47:42 PM UTC 24 |
Oct 02 08:47:55 PM UTC 24 |
464502605 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_smoke.960876476 |
|
|
Oct 02 08:47:45 PM UTC 24 |
Oct 02 08:47:58 PM UTC 24 |
980554301 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_intr_smoke.3364793816 |
|
|
Oct 02 08:47:50 PM UTC 24 |
Oct 02 08:47:58 PM UTC 24 |
3074121307 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_stretch.2478911062 |
|
|
Oct 02 08:47:48 PM UTC 24 |
Oct 02 08:48:00 PM UTC 24 |
476814606 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_tx.1307849189 |
|
|
Oct 02 08:47:59 PM UTC 24 |
Oct 02 08:48:02 PM UTC 24 |
112772575 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_acq.4275296297 |
|
|
Oct 02 08:47:59 PM UTC 24 |
Oct 02 08:48:02 PM UTC 24 |
561375707 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_smoke.2367829805 |
|
|
Oct 02 08:47:01 PM UTC 24 |
Oct 02 08:48:05 PM UTC 24 |
4149814720 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_perf.3591262866 |
|
|
Oct 02 08:47:42 PM UTC 24 |
Oct 02 08:48:05 PM UTC 24 |
3569176693 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_intr_stress_wr.3945829534 |
|
|
Oct 02 08:47:54 PM UTC 24 |
Oct 02 08:48:07 PM UTC 24 |
4844113332 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_mode_toggle.2486455425 |
|
|
Oct 02 08:48:06 PM UTC 24 |
Oct 02 08:48:09 PM UTC 24 |
267066739 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_perf.1378518540 |
|
|
Oct 02 08:48:01 PM UTC 24 |
Oct 02 08:48:10 PM UTC 24 |
613291119 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_timeout.1674730019 |
|
|
Oct 02 08:47:54 PM UTC 24 |
Oct 02 08:48:10 PM UTC 24 |
1359352900 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_stretch_timeout.3116871765 |
|
|
Oct 02 08:47:42 PM UTC 24 |
Oct 02 08:48:10 PM UTC 24 |
957630118 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_stress_rd.2502764358 |
|
|
Oct 02 08:47:14 PM UTC 24 |
Oct 02 08:48:10 PM UTC 24 |
4673089195 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_tx.46213440 |
|
|
Oct 02 08:48:09 PM UTC 24 |
Oct 02 08:48:12 PM UTC 24 |
166501379 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_acq.1821951119 |
|
|
Oct 02 08:48:08 PM UTC 24 |
Oct 02 08:48:13 PM UTC 24 |
757294248 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_bad_addr.3175779437 |
|
|
Oct 02 08:48:03 PM UTC 24 |
Oct 02 08:48:13 PM UTC 24 |
1234325137 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_tx_stretch_ctrl.2095386505 |
|
|
Oct 02 08:48:10 PM UTC 24 |
Oct 02 08:48:13 PM UTC 24 |
104793879 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_may_nack.3099431611 |
|
|
Oct 02 08:48:06 PM UTC 24 |
Oct 02 08:48:16 PM UTC 24 |
1618552821 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_smbus_maxlen.647998129 |
|
|
Oct 02 08:48:11 PM UTC 24 |
Oct 02 08:48:17 PM UTC 24 |
3012254815 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_alert_test.703738942 |
|
|
Oct 02 08:48:15 PM UTC 24 |
Oct 02 08:48:17 PM UTC 24 |
18316090 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull_addr.373351835 |
|
|
Oct 02 08:48:12 PM UTC 24 |
Oct 02 08:48:17 PM UTC 24 |
1600383231 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_override.1630475820 |
|
|
Oct 02 08:48:15 PM UTC 24 |
Oct 02 08:48:17 PM UTC 24 |
49655935 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_nack_txstretch.2402427853 |
|
|
Oct 02 08:48:14 PM UTC 24 |
Oct 02 08:48:17 PM UTC 24 |
2165210970 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull.1257807223 |
|
|
Oct 02 08:48:11 PM UTC 24 |
Oct 02 08:48:18 PM UTC 24 |
2170064676 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_intr_stress_wr.3963733323 |
|
|
Oct 02 08:45:11 PM UTC 24 |
Oct 02 08:48:19 PM UTC 24 |
22856687525 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_fmt.3930227593 |
|
|
Oct 02 08:48:17 PM UTC 24 |
Oct 02 08:48:20 PM UTC 24 |
99542751 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_intr_stress_wr.2708285217 |
|
|
Oct 02 08:42:28 PM UTC 24 |
Oct 02 08:48:22 PM UTC 24 |
17427553015 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_perf_precise.2365598066 |
|
|
Oct 02 08:48:21 PM UTC 24 |
Oct 02 08:48:25 PM UTC 24 |
73965251 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_rx.2229765267 |
|
|
Oct 02 08:48:18 PM UTC 24 |
Oct 02 08:48:29 PM UTC 24 |
1651965938 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_watermark.744679244 |
|
|
Oct 02 08:46:29 PM UTC 24 |
Oct 02 08:48:30 PM UTC 24 |
4164385271 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_error_intr.3522351417 |
|
|
Oct 02 08:48:23 PM UTC 24 |
Oct 02 08:48:31 PM UTC 24 |
302039937 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_stretch_timeout.2296430697 |
|
|
Oct 02 08:48:21 PM UTC 24 |
Oct 02 08:48:36 PM UTC 24 |
2211190408 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_intr_stress_wr.2812113612 |
|
|
Oct 02 08:43:15 PM UTC 24 |
Oct 02 08:48:36 PM UTC 24 |
21861936341 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_overflow.3038625769 |
|
|
Oct 02 08:47:40 PM UTC 24 |
Oct 02 08:48:39 PM UTC 24 |
1797686336 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_smoke.838650685 |
|
|
Oct 02 08:48:15 PM UTC 24 |
Oct 02 08:48:39 PM UTC 24 |
2487950830 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_fmt_empty.453738529 |
|
|
Oct 02 08:48:18 PM UTC 24 |
Oct 02 08:48:40 PM UTC 24 |
1253206576 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_stress_all.2046802300 |
|
|
Oct 02 08:43:26 PM UTC 24 |
Oct 02 08:48:44 PM UTC 24 |
27477873330 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_full.2500278411 |
|
|
Oct 02 08:46:32 PM UTC 24 |
Oct 02 08:48:46 PM UTC 24 |
3700769433 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_intr_smoke.2932916297 |
|
|
Oct 02 08:49:08 PM UTC 24 |
Oct 02 08:49:21 PM UTC 24 |
3277453210 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_acq.3204441239 |
|
|
Oct 02 08:48:45 PM UTC 24 |
Oct 02 08:48:47 PM UTC 24 |
461417566 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_intr_smoke.3057691414 |
|
|
Oct 02 08:48:37 PM UTC 24 |
Oct 02 08:48:47 PM UTC 24 |
5321007801 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_perf.798810450 |
|
|
Oct 02 08:48:19 PM UTC 24 |
Oct 02 08:48:48 PM UTC 24 |
3003331305 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_tx.7011850 |
|
|
Oct 02 08:48:46 PM UTC 24 |
Oct 02 08:48:50 PM UTC 24 |
5483222714 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_stress_rd.4255329678 |
|
|
Oct 02 08:48:31 PM UTC 24 |
Oct 02 08:48:50 PM UTC 24 |
761565723 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_perf.2718013880 |
|
|
Oct 02 08:45:52 PM UTC 24 |
Oct 02 08:48:52 PM UTC 24 |
30653365840 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_full.2988745375 |
|
|
Oct 02 08:47:42 PM UTC 24 |
Oct 02 08:48:52 PM UTC 24 |
2294159617 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_timeout.584482664 |
|
|
Oct 02 08:48:40 PM UTC 24 |
Oct 02 08:48:53 PM UTC 24 |
1911099111 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_tx.3528895993 |
|
|
Oct 02 08:48:51 PM UTC 24 |
Oct 02 08:48:54 PM UTC 24 |
234049148 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_perf.3651612558 |
|
|
Oct 02 08:48:47 PM UTC 24 |
Oct 02 08:48:55 PM UTC 24 |
2827307951 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_watermark.1034530329 |
|
|
Oct 02 08:45:41 PM UTC 24 |
Oct 02 08:48:56 PM UTC 24 |
3144506689 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_acq.1743030977 |
|
|
Oct 02 08:48:50 PM UTC 24 |
Oct 02 08:48:56 PM UTC 24 |
1048667201 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_smbus_maxlen.3014331881 |
|
|
Oct 02 08:48:53 PM UTC 24 |
Oct 02 08:48:58 PM UTC 24 |
1734908670 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull.1717814310 |
|
|
Oct 02 08:48:54 PM UTC 24 |
Oct 02 08:48:59 PM UTC 24 |
913058964 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_alert_test.617885052 |
|
|
Oct 02 08:48:57 PM UTC 24 |
Oct 02 08:48:59 PM UTC 24 |
48059784 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.1022882961 |
|
|
Oct 02 08:47:46 PM UTC 24 |
Oct 02 08:49:20 PM UTC 24 |
69498795229 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_stress_rd.3633583716 |
|
|
Oct 02 08:47:47 PM UTC 24 |
Oct 02 08:49:00 PM UTC 24 |
3269091050 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_override.608843948 |
|
|
Oct 02 08:48:58 PM UTC 24 |
Oct 02 08:49:00 PM UTC 24 |
57715267 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_may_nack.3740504147 |
|
|
Oct 02 08:48:49 PM UTC 24 |
Oct 02 08:49:02 PM UTC 24 |
2788812835 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull_addr.3467673564 |
|
|
Oct 02 08:48:56 PM UTC 24 |
Oct 02 08:49:02 PM UTC 24 |
516218393 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_bad_addr.4158003364 |
|
|
Oct 02 08:48:48 PM UTC 24 |
Oct 02 08:49:02 PM UTC 24 |
2390703110 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_fmt.3552835241 |
|
|
Oct 02 08:49:00 PM UTC 24 |
Oct 02 08:49:03 PM UTC 24 |
415293674 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_tx_stretch_ctrl.4230491484 |
|
|
Oct 02 08:48:53 PM UTC 24 |
Oct 02 08:49:05 PM UTC 24 |
526409428 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_smoke.1753266263 |
|
|
Oct 02 08:48:29 PM UTC 24 |
Oct 02 08:49:06 PM UTC 24 |
12103945049 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_perf_precise.3970727479 |
|
|
Oct 02 08:49:03 PM UTC 24 |
Oct 02 08:49:06 PM UTC 24 |
875592833 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_perf.946221018 |
|
|
Oct 02 08:47:05 PM UTC 24 |
Oct 02 08:49:07 PM UTC 24 |
5179325862 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_stress_all.4128974989 |
|
|
Oct 02 08:48:01 PM UTC 24 |
Oct 02 08:49:12 PM UTC 24 |
12412719279 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_rx.1441673205 |
|
|
Oct 02 08:49:02 PM UTC 24 |
Oct 02 08:49:14 PM UTC 24 |
200606058 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_smoke.1934043585 |
|
|
Oct 02 08:47:39 PM UTC 24 |
Oct 02 08:49:15 PM UTC 24 |
1686072156 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_stress_all.3441982536 |
|
|
Oct 02 08:48:48 PM UTC 24 |
Oct 02 08:49:15 PM UTC 24 |
4056269488 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_acq.817668618 |
|
|
Oct 02 08:49:16 PM UTC 24 |
Oct 02 08:49:19 PM UTC 24 |
534571788 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_stretch_timeout.3627024256 |
|
|
Oct 02 08:49:03 PM UTC 24 |
Oct 02 08:49:19 PM UTC 24 |
5161053472 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_stretch.999423862 |
|
|
Oct 02 08:49:08 PM UTC 24 |
Oct 02 08:49:20 PM UTC 24 |
4412259739 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_tx.2447200524 |
|
|
Oct 02 08:49:20 PM UTC 24 |
Oct 02 08:49:23 PM UTC 24 |
401265905 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_timeout.1678063699 |
|
|
Oct 02 08:49:15 PM UTC 24 |
Oct 02 08:49:27 PM UTC 24 |
4424070101 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_stress_all.523257265 |
|
|
Oct 02 08:47:28 PM UTC 24 |
Oct 02 08:49:28 PM UTC 24 |
58506364095 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_perf.3101995997 |
|
|
Oct 02 08:49:03 PM UTC 24 |
Oct 02 08:49:29 PM UTC 24 |
6894670952 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_fmt_empty.3116042441 |
|
|
Oct 02 08:49:00 PM UTC 24 |
Oct 02 08:49:31 PM UTC 24 |
1451613813 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_stress_rd.3105093563 |
|
|
Oct 02 08:49:07 PM UTC 24 |
Oct 02 08:49:31 PM UTC 24 |
539759070 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_perf.53918980 |
|
|
Oct 02 08:49:20 PM UTC 24 |
Oct 02 08:49:31 PM UTC 24 |
1973310307 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_tx.3543029537 |
|
|
Oct 02 08:49:29 PM UTC 24 |
Oct 02 08:49:32 PM UTC 24 |
176526789 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_bad_addr.747946130 |
|
|
Oct 02 08:49:21 PM UTC 24 |
Oct 02 08:49:33 PM UTC 24 |
4712454715 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_smbus_maxlen.619449971 |
|
|
Oct 02 08:49:30 PM UTC 24 |
Oct 02 08:49:34 PM UTC 24 |
432733397 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_acq.3716018747 |
|
|
Oct 02 08:49:29 PM UTC 24 |
Oct 02 08:49:34 PM UTC 24 |
587132254 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_alert_test.38746641 |
|
|
Oct 02 08:49:33 PM UTC 24 |
Oct 02 08:49:35 PM UTC 24 |
16276809 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_nack_txstretch.275341453 |
|
|
Oct 02 08:49:32 PM UTC 24 |
Oct 02 08:49:35 PM UTC 24 |
567315127 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_override.2045087974 |
|
|
Oct 02 08:49:34 PM UTC 24 |
Oct 02 08:49:36 PM UTC 24 |
28220914 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull.701382464 |
|
|
Oct 02 08:49:32 PM UTC 24 |
Oct 02 08:49:37 PM UTC 24 |
610717565 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull_addr.3868946677 |
|
|
Oct 02 08:49:32 PM UTC 24 |
Oct 02 08:49:38 PM UTC 24 |
2174964907 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_tx_stretch_ctrl.4089225210 |
|
|
Oct 02 08:49:29 PM UTC 24 |
Oct 02 08:49:43 PM UTC 24 |
883081888 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_smoke.2340935428 |
|
|
Oct 02 08:49:06 PM UTC 24 |
Oct 02 08:49:44 PM UTC 24 |
2268245641 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_fmt.1369410828 |
|
|
Oct 02 08:49:45 PM UTC 24 |
Oct 02 08:49:47 PM UTC 24 |
107489547 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_stretch.1804908608 |
|
|
Oct 02 08:48:36 PM UTC 24 |
Oct 02 08:49:49 PM UTC 24 |
4635521820 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_may_nack.2397944052 |
|
|
Oct 02 08:49:23 PM UTC 24 |
Oct 02 08:49:50 PM UTC 24 |
2294909248 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_watermark.1356462659 |
|
|
Oct 02 08:47:02 PM UTC 24 |
Oct 02 08:49:51 PM UTC 24 |
11587112956 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_rx.2921075452 |
|
|
Oct 02 08:49:45 PM UTC 24 |
Oct 02 08:49:57 PM UTC 24 |
769889588 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_stretch.2786023457 |
|
|
Oct 02 08:49:52 PM UTC 24 |
Oct 02 08:49:57 PM UTC 24 |
3007917850 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_stretch_timeout.3026058628 |
|
|
Oct 02 08:49:45 PM UTC 24 |
Oct 02 08:49:58 PM UTC 24 |
656295907 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_fmt_empty.2591255717 |
|
|
Oct 02 08:49:45 PM UTC 24 |
Oct 02 08:49:59 PM UTC 24 |
1765505727 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_acq.3829599424 |
|
|
Oct 02 08:49:59 PM UTC 24 |
Oct 02 08:50:03 PM UTC 24 |
379710954 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_intr_smoke.361107231 |
|
|
Oct 02 08:49:58 PM UTC 24 |
Oct 02 08:50:05 PM UTC 24 |
1350236372 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_tx.656972380 |
|
|
Oct 02 08:50:02 PM UTC 24 |
Oct 02 08:50:07 PM UTC 24 |
1081750185 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_smoke.1757716355 |
|
|
Oct 02 08:49:50 PM UTC 24 |
Oct 02 08:50:07 PM UTC 24 |
1471590837 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_smoke.1209008603 |
|
|
Oct 02 08:49:33 PM UTC 24 |
Oct 02 08:50:10 PM UTC 24 |
7107676886 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_stress_wr.1168920490 |
|
|
Oct 02 08:49:50 PM UTC 24 |
Oct 02 08:50:10 PM UTC 24 |
7655889789 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_timeout.3277916702 |
|
|
Oct 02 08:49:58 PM UTC 24 |
Oct 02 08:50:11 PM UTC 24 |
1285501809 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_perf.3067754001 |
|
|
Oct 02 08:50:03 PM UTC 24 |
Oct 02 08:50:11 PM UTC 24 |
632074257 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_smoke.1687419046 |
|
|
Oct 02 08:48:57 PM UTC 24 |
Oct 02 08:50:11 PM UTC 24 |
5482064542 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_stress_all.1428115294 |
|
|
Oct 02 08:26:40 PM UTC 24 |
Oct 02 08:50:14 PM UTC 24 |
26820935971 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_full.1184198008 |
|
|
Oct 02 08:47:05 PM UTC 24 |
Oct 02 08:50:15 PM UTC 24 |
6448312514 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_watermark.1734396671 |
|
|
Oct 02 08:48:59 PM UTC 24 |
Oct 02 08:50:15 PM UTC 24 |
2941986266 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_tx.2430612960 |
|
|
Oct 02 08:50:15 PM UTC 24 |
Oct 02 08:50:18 PM UTC 24 |
1241876856 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_bad_addr.256610806 |
|
|
Oct 02 08:50:07 PM UTC 24 |
Oct 02 08:50:18 PM UTC 24 |
1045546697 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_full.1992680032 |
|
|
Oct 02 08:49:45 PM UTC 24 |
Oct 02 08:50:51 PM UTC 24 |
5124599699 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_stress_rd.3999132219 |
|
|
Oct 02 08:49:51 PM UTC 24 |
Oct 02 08:50:19 PM UTC 24 |
2847138700 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_smbus_maxlen.2534556342 |
|
|
Oct 02 08:50:15 PM UTC 24 |
Oct 02 08:50:20 PM UTC 24 |
489284045 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull.3940797219 |
|
|
Oct 02 08:50:15 PM UTC 24 |
Oct 02 08:50:20 PM UTC 24 |
1089053249 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_alert_test.1791020620 |
|
|
Oct 02 08:50:19 PM UTC 24 |
Oct 02 08:50:21 PM UTC 24 |
16951604 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_acq.3773308189 |
|
|
Oct 02 08:50:15 PM UTC 24 |
Oct 02 08:50:21 PM UTC 24 |
2153977291 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_mode_toggle.1470623381 |
|
|
Oct 02 08:50:15 PM UTC 24 |
Oct 02 08:50:21 PM UTC 24 |
119462079 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_override.1207265749 |
|
|
Oct 02 08:50:20 PM UTC 24 |
Oct 02 08:50:22 PM UTC 24 |
18930645 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull_addr.1678127385 |
|
|
Oct 02 08:50:16 PM UTC 24 |
Oct 02 08:50:22 PM UTC 24 |
494612761 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_overflow.3010662750 |
|
|
Oct 02 08:47:03 PM UTC 24 |
Oct 02 08:50:22 PM UTC 24 |
3002899365 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_full.1120968901 |
|
|
Oct 02 08:48:18 PM UTC 24 |
Oct 02 08:50:24 PM UTC 24 |
3307862961 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_fmt.1608614141 |
|
|
Oct 02 08:50:21 PM UTC 24 |
Oct 02 08:50:24 PM UTC 24 |
135414833 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_intr_stress_wr.3157897571 |
|
|
Oct 02 08:49:14 PM UTC 24 |
Oct 02 08:50:25 PM UTC 24 |
20717865567 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_tx_stretch_ctrl.2730829813 |
|
|
Oct 02 08:50:15 PM UTC 24 |
Oct 02 08:50:25 PM UTC 24 |
407143211 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_watermark.3340304195 |
|
|
Oct 02 08:48:16 PM UTC 24 |
Oct 02 08:50:29 PM UTC 24 |
5072860362 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_perf.620676524 |
|
|
Oct 02 08:31:44 PM UTC 24 |
Oct 02 08:50:31 PM UTC 24 |
29441055745 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_may_nack.351561827 |
|
|
Oct 02 08:50:15 PM UTC 24 |
Oct 02 08:50:32 PM UTC 24 |
5724604072 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_overflow.2143924292 |
|
|
Oct 02 08:48:17 PM UTC 24 |
Oct 02 08:50:32 PM UTC 24 |
14357089213 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_rx.631488678 |
|
|
Oct 02 08:50:21 PM UTC 24 |
Oct 02 08:50:32 PM UTC 24 |
164695894 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_stress_wr.679062292 |
|
|
Oct 02 08:50:26 PM UTC 24 |
Oct 02 08:50:36 PM UTC 24 |
9369899360 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_fmt_empty.283615563 |
|
|
Oct 02 08:50:21 PM UTC 24 |
Oct 02 08:50:37 PM UTC 24 |
635124789 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_stretch_timeout.992096876 |
|
|
Oct 02 08:50:24 PM UTC 24 |
Oct 02 08:50:38 PM UTC 24 |
3441758385 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_acq.3013012621 |
|
|
Oct 02 08:50:36 PM UTC 24 |
Oct 02 08:50:38 PM UTC 24 |
243240675 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_smoke.1629497743 |
|
|
Oct 02 08:50:26 PM UTC 24 |
Oct 02 08:50:39 PM UTC 24 |
1760813293 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_tx.1891785015 |
|
|
Oct 02 08:50:37 PM UTC 24 |
Oct 02 08:50:41 PM UTC 24 |
895427057 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_full.2293519257 |
|
|
Oct 02 08:49:02 PM UTC 24 |
Oct 02 08:50:41 PM UTC 24 |
4881575698 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_hrst.1360338826 |
|
|
Oct 02 08:50:39 PM UTC 24 |
Oct 02 08:50:45 PM UTC 24 |
595772646 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_perf.3445727446 |
|
|
Oct 02 08:50:38 PM UTC 24 |
Oct 02 08:50:45 PM UTC 24 |
1895196583 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_timeout.4096271507 |
|
|
Oct 02 08:50:36 PM UTC 24 |
Oct 02 08:50:46 PM UTC 24 |
1329099647 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_intr_smoke.3013520795 |
|
|
Oct 02 08:50:36 PM UTC 24 |
Oct 02 08:50:47 PM UTC 24 |
9294013407 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_tx.2535289200 |
|
|
Oct 02 08:50:45 PM UTC 24 |
Oct 02 08:50:48 PM UTC 24 |
129367742 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_acq.1174540466 |
|
|
Oct 02 08:50:43 PM UTC 24 |
Oct 02 08:50:48 PM UTC 24 |
1578485098 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_bad_addr.3047069761 |
|
|
Oct 02 08:50:39 PM UTC 24 |
Oct 02 08:50:49 PM UTC 24 |
867130740 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_tx_stretch_ctrl.534119847 |
|
|
Oct 02 08:50:46 PM UTC 24 |
Oct 02 08:50:49 PM UTC 24 |
86256651 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_may_nack.3979576855 |
|
|
Oct 02 08:50:42 PM UTC 24 |
Oct 02 08:50:51 PM UTC 24 |
2091332467 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_smbus_maxlen.3100650921 |
|
|
Oct 02 08:50:46 PM UTC 24 |
Oct 02 08:50:51 PM UTC 24 |
464150390 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_alert_test.392384529 |
|
|
Oct 02 08:50:49 PM UTC 24 |
Oct 02 08:50:51 PM UTC 24 |
44201903 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull_addr.1312709403 |
|
|
Oct 02 08:50:47 PM UTC 24 |
Oct 02 08:50:52 PM UTC 24 |
9684245104 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_overflow.2197684272 |
|
|
Oct 02 08:49:35 PM UTC 24 |
Oct 02 08:50:52 PM UTC 24 |
2488296723 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_override.1083718110 |
|
|
Oct 02 08:50:50 PM UTC 24 |
Oct 02 08:50:53 PM UTC 24 |
113697945 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull.3595906854 |
|
|
Oct 02 08:50:47 PM UTC 24 |
Oct 02 08:50:53 PM UTC 24 |
1804329852 ps |
| T1269 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_fmt.1255312119 |
|
|
Oct 02 08:50:53 PM UTC 24 |
Oct 02 08:50:56 PM UTC 24 |
222241810 ps |
| T1270 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_watermark.4206095364 |
|
|
Oct 02 08:47:39 PM UTC 24 |
Oct 02 08:50:57 PM UTC 24 |
3401313868 ps |
| T1271 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_perf_precise.2195840597 |
|
|
Oct 02 08:50:54 PM UTC 24 |
Oct 02 08:50:57 PM UTC 24 |
94112581 ps |
| T1272 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_overflow.3180376810 |
|
|
Oct 02 08:49:00 PM UTC 24 |
Oct 02 08:50:58 PM UTC 24 |
9336231973 ps |
| T1273 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_stress_wr.19342649 |
|
|
Oct 02 08:47:12 PM UTC 24 |
Oct 02 08:50:59 PM UTC 24 |
58177149411 ps |
| T1274 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_stretch.2699509632 |
|
|
Oct 02 08:50:36 PM UTC 24 |
Oct 02 08:50:59 PM UTC 24 |
4245569777 ps |
| T1275 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_rx.3142958584 |
|
|
Oct 02 08:50:53 PM UTC 24 |
Oct 02 08:51:03 PM UTC 24 |
1642395120 ps |
| T1276 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_fmt_empty.3998337925 |
|
|
Oct 02 08:50:53 PM UTC 24 |
Oct 02 08:51:05 PM UTC 24 |
676291171 ps |
| T1277 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_stretch_timeout.4034792819 |
|
|
Oct 02 08:50:54 PM UTC 24 |
Oct 02 08:51:08 PM UTC 24 |
577041463 ps |
| T1278 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_intr_smoke.453501543 |
|
|
Oct 02 08:51:00 PM UTC 24 |
Oct 02 08:51:08 PM UTC 24 |
1479612236 ps |
| T1279 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_perf.13323822 |
|
|
Oct 02 08:50:22 PM UTC 24 |
Oct 02 08:51:10 PM UTC 24 |
13141514970 ps |
| T1280 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_tx.2347582064 |
|
|
Oct 02 08:51:08 PM UTC 24 |
Oct 02 08:51:11 PM UTC 24 |
146797421 ps |
| T1281 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_watermark.2637402336 |
|
|
Oct 02 08:49:35 PM UTC 24 |
Oct 02 08:51:11 PM UTC 24 |
13296009789 ps |
| T1282 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_acq.3556077250 |
|
|
Oct 02 08:51:08 PM UTC 24 |
Oct 02 08:51:12 PM UTC 24 |
298584313 ps |
| T1283 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_intr_stress_wr.1567336161 |
|
|
Oct 02 08:51:07 PM UTC 24 |
Oct 02 08:51:16 PM UTC 24 |
4177033456 ps |
| T1284 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_perf.397782310 |
|
|
Oct 02 08:51:09 PM UTC 24 |
Oct 02 08:51:16 PM UTC 24 |
1156686108 ps |
| T1285 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_hrst.3239694188 |
|
|
Oct 02 08:51:11 PM UTC 24 |
Oct 02 08:51:17 PM UTC 24 |
550179382 ps |
| T1286 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_tx.2370602271 |
|
|
Oct 02 08:51:17 PM UTC 24 |
Oct 02 08:51:20 PM UTC 24 |
440045096 ps |
| T1287 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_timeout.1787513420 |
|
|
Oct 02 08:51:08 PM UTC 24 |
Oct 02 08:51:20 PM UTC 24 |
5373054259 ps |
| T1288 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_smoke.1727147672 |
|
|
Oct 02 08:50:20 PM UTC 24 |
Oct 02 08:51:21 PM UTC 24 |
4475817462 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_smoke.3001194309 |
|
|
Oct 02 08:50:57 PM UTC 24 |
Oct 02 08:51:22 PM UTC 24 |
2381596746 ps |
| T1289 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_acq.2555036464 |
|
|
Oct 02 08:51:17 PM UTC 24 |
Oct 02 08:51:22 PM UTC 24 |
1023166787 ps |
| T1290 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_bad_addr.3619531035 |
|
|
Oct 02 08:51:11 PM UTC 24 |
Oct 02 08:51:22 PM UTC 24 |
1192534632 ps |
| T1291 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_stress_wr.2059004565 |
|
|
Oct 02 08:50:59 PM UTC 24 |
Oct 02 08:51:23 PM UTC 24 |
12188648370 ps |
| T1292 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_may_nack.4190612210 |
|
|
Oct 02 08:51:13 PM UTC 24 |
Oct 02 08:51:24 PM UTC 24 |
2136681906 ps |
| T1293 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_intr_stress_wr.3521217548 |
|
|
Oct 02 08:50:36 PM UTC 24 |
Oct 02 08:51:24 PM UTC 24 |
19486104040 ps |
| T1294 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_alert_test.1488819934 |
|
|
Oct 02 08:51:22 PM UTC 24 |
Oct 02 08:51:24 PM UTC 24 |
25966639 ps |
| T1295 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_smbus_maxlen.388680036 |
|
|
Oct 02 08:51:21 PM UTC 24 |
Oct 02 08:51:25 PM UTC 24 |
517215040 ps |
| T1296 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_fmt_empty.3121689076 |
|
|
Oct 02 08:51:38 PM UTC 24 |
Oct 02 08:51:58 PM UTC 24 |
1658010333 ps |
| T1297 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_tx_stretch_ctrl.3738492902 |
|
|
Oct 02 08:51:18 PM UTC 24 |
Oct 02 08:51:26 PM UTC 24 |
246636850 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull_addr.1397656998 |
|
|
Oct 02 08:51:21 PM UTC 24 |
Oct 02 08:51:26 PM UTC 24 |
545989124 ps |
| T1298 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull.3648083095 |
|
|
Oct 02 08:51:21 PM UTC 24 |
Oct 02 08:51:27 PM UTC 24 |
437068566 ps |
| T1299 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_perf.212767232 |
|
|
Oct 02 08:50:54 PM UTC 24 |
Oct 02 08:51:27 PM UTC 24 |
2896469488 ps |
| T1300 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_overflow.438323352 |
|
|
Oct 02 08:50:21 PM UTC 24 |
Oct 02 08:51:27 PM UTC 24 |
2255121694 ps |
| T1301 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_stress_rd.1899342989 |
|
|
Oct 02 08:50:36 PM UTC 24 |
Oct 02 08:51:31 PM UTC 24 |
1037759308 ps |
| T1302 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_stress_wr.2278542953 |
|
|
Oct 02 08:49:07 PM UTC 24 |
Oct 02 08:51:34 PM UTC 24 |
34909143301 ps |
| T1303 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_full.3446226673 |
|
|
Oct 02 08:50:22 PM UTC 24 |
Oct 02 08:51:34 PM UTC 24 |
25287695494 ps |
| T1304 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_override.3351906422 |
|
|
Oct 02 08:51:33 PM UTC 24 |
Oct 02 08:51:35 PM UTC 24 |
21557516 ps |
| T1305 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_stretch.1544897414 |
|
|
Oct 02 08:51:00 PM UTC 24 |
Oct 02 08:51:35 PM UTC 24 |
1843364341 ps |
| T1306 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_intr_stress_wr.1049827042 |
|
|
Oct 02 08:49:58 PM UTC 24 |
Oct 02 08:51:38 PM UTC 24 |
15846810511 ps |
| T1307 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_stress_rd.1582928867 |
|
|
Oct 02 08:51:00 PM UTC 24 |
Oct 02 08:51:38 PM UTC 24 |
3791961850 ps |
| T1308 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_smoke.420011273 |
|
|
Oct 02 08:50:50 PM UTC 24 |
Oct 02 08:51:40 PM UTC 24 |
898392729 ps |
| T1309 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_fmt.1649225406 |
|
|
Oct 02 08:51:38 PM UTC 24 |
Oct 02 08:51:40 PM UTC 24 |
472636929 ps |
| T1310 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_error_intr.3749661713 |
|
|
Oct 02 08:51:38 PM UTC 24 |
Oct 02 08:51:41 PM UTC 24 |
248816117 ps |
| T1311 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_perf_precise.2167115871 |
|
|
Oct 02 08:51:38 PM UTC 24 |
Oct 02 08:51:41 PM UTC 24 |
358246668 ps |
| T1312 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_acq.622171000 |
|
|
Oct 02 08:51:40 PM UTC 24 |
Oct 02 08:51:42 PM UTC 24 |
326748922 ps |
| T1313 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_rx.2152864081 |
|
|
Oct 02 08:51:38 PM UTC 24 |
Oct 02 08:51:43 PM UTC 24 |
247417028 ps |
| T1314 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_tx.1318736488 |
|
|
Oct 02 08:51:41 PM UTC 24 |
Oct 02 08:51:44 PM UTC 24 |
154264692 ps |
| T1315 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_mode_toggle.4280529062 |
|
|
Oct 02 08:51:44 PM UTC 24 |
Oct 02 08:51:48 PM UTC 24 |
300277635 ps |
| T1316 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_hrst.3420254714 |
|
|
Oct 02 08:51:43 PM UTC 24 |
Oct 02 08:51:48 PM UTC 24 |
297892693 ps |
| T1317 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_bad_addr.3790196561 |
|
|
Oct 02 08:51:42 PM UTC 24 |
Oct 02 08:51:49 PM UTC 24 |
1597024655 ps |
| T1318 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_perf.1451513401 |
|
|
Oct 02 08:51:41 PM UTC 24 |
Oct 02 08:51:50 PM UTC 24 |
615825333 ps |
| T1319 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_timeout.356564031 |
|
|
Oct 02 08:51:38 PM UTC 24 |
Oct 02 08:51:50 PM UTC 24 |
5948669400 ps |
| T1320 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_acq.2362959657 |
|
|
Oct 02 08:51:44 PM UTC 24 |
Oct 02 08:51:50 PM UTC 24 |
612509199 ps |