| T1564 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.4268346923 |
|
|
Oct 02 08:56:10 PM UTC 24 |
Oct 02 08:56:34 PM UTC 24 |
5613903699 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_perf.1974722831 |
|
|
Oct 02 08:56:13 PM UTC 24 |
Oct 02 08:56:44 PM UTC 24 |
6693002412 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.137238182 |
|
|
Oct 02 08:56:34 PM UTC 24 |
Oct 02 08:56:45 PM UTC 24 |
3318715574 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.3705510513 |
|
|
Oct 02 08:56:22 PM UTC 24 |
Oct 02 08:56:45 PM UTC 24 |
1253197302 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.835597831 |
|
|
Oct 02 08:56:11 PM UTC 24 |
Oct 02 08:56:45 PM UTC 24 |
513705773 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.4076049495 |
|
|
Oct 02 08:55:32 PM UTC 24 |
Oct 02 08:56:46 PM UTC 24 |
4277663816 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.1246939861 |
|
|
Oct 02 08:56:25 PM UTC 24 |
Oct 02 08:56:46 PM UTC 24 |
11334032074 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.3644431684 |
|
|
Oct 02 08:56:46 PM UTC 24 |
Oct 02 08:56:49 PM UTC 24 |
430009767 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_stress_wr.2149234066 |
|
|
Oct 02 08:27:51 PM UTC 24 |
Oct 02 08:58:07 PM UTC 24 |
61103163453 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.3666615109 |
|
|
Oct 02 08:56:46 PM UTC 24 |
Oct 02 08:56:49 PM UTC 24 |
366572932 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.4197650847 |
|
|
Oct 02 08:56:39 PM UTC 24 |
Oct 02 08:56:50 PM UTC 24 |
1150622889 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.731217745 |
|
|
Oct 02 08:54:37 PM UTC 24 |
Oct 02 08:56:50 PM UTC 24 |
49079824730 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_host_perf.3534703660 |
|
|
Oct 02 08:42:01 PM UTC 24 |
Oct 02 08:56:51 PM UTC 24 |
24130817514 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.2825727225 |
|
|
Oct 02 08:56:14 PM UTC 24 |
Oct 02 08:56:52 PM UTC 24 |
2338461642 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_perf.2966559208 |
|
|
Oct 02 08:56:47 PM UTC 24 |
Oct 02 08:56:53 PM UTC 24 |
3844561681 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.387391279 |
|
|
Oct 02 08:56:47 PM UTC 24 |
Oct 02 08:56:55 PM UTC 24 |
1454317886 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.1083046912 |
|
|
Oct 02 08:56:50 PM UTC 24 |
Oct 02 08:56:56 PM UTC 24 |
1704762280 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_mode_toggle.836395638 |
|
|
Oct 02 08:56:50 PM UTC 24 |
Oct 02 08:56:56 PM UTC 24 |
142102695 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.3689314447 |
|
|
Oct 02 08:55:57 PM UTC 24 |
Oct 02 08:56:57 PM UTC 24 |
7127628129 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.2957650349 |
|
|
Oct 02 08:56:51 PM UTC 24 |
Oct 02 08:56:57 PM UTC 24 |
1998345231 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.2386896091 |
|
|
Oct 02 08:56:54 PM UTC 24 |
Oct 02 08:56:58 PM UTC 24 |
951680725 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_nack_txstretch.69422072 |
|
|
Oct 02 08:56:55 PM UTC 24 |
Oct 02 08:56:58 PM UTC 24 |
287652483 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_alert_test.1686365452 |
|
|
Oct 02 08:56:56 PM UTC 24 |
Oct 02 08:56:58 PM UTC 24 |
22910438 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.2078638553 |
|
|
Oct 02 08:55:28 PM UTC 24 |
Oct 02 08:56:58 PM UTC 24 |
1897747563 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_override.2149099619 |
|
|
Oct 02 08:56:57 PM UTC 24 |
Oct 02 08:56:59 PM UTC 24 |
39502816 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.4140937901 |
|
|
Oct 02 08:56:54 PM UTC 24 |
Oct 02 08:57:00 PM UTC 24 |
2111064996 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.1266887518 |
|
|
Oct 02 08:56:58 PM UTC 24 |
Oct 02 08:57:01 PM UTC 24 |
1020179754 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.226910098 |
|
|
Oct 02 08:56:50 PM UTC 24 |
Oct 02 08:57:04 PM UTC 24 |
573409658 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.632021256 |
|
|
Oct 02 08:56:51 PM UTC 24 |
Oct 02 08:57:08 PM UTC 24 |
1272119237 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.802295392 |
|
|
Oct 02 08:56:59 PM UTC 24 |
Oct 02 08:57:09 PM UTC 24 |
445351639 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.2455591464 |
|
|
Oct 02 08:57:05 PM UTC 24 |
Oct 02 08:57:09 PM UTC 24 |
155413029 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_stress_wr.4194744770 |
|
|
Oct 02 08:48:31 PM UTC 24 |
Oct 02 08:57:09 PM UTC 24 |
63519347728 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.721807529 |
|
|
Oct 02 08:57:01 PM UTC 24 |
Oct 02 08:57:11 PM UTC 24 |
152862629 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.2821428484 |
|
|
Oct 02 08:56:58 PM UTC 24 |
Oct 02 08:57:15 PM UTC 24 |
1038242434 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_perf.32916231 |
|
|
Oct 02 08:55:33 PM UTC 24 |
Oct 02 08:57:17 PM UTC 24 |
6864036951 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_stress_all.841587477 |
|
|
Oct 02 08:50:05 PM UTC 24 |
Oct 02 08:57:18 PM UTC 24 |
41791130882 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.2304709756 |
|
|
Oct 02 08:56:12 PM UTC 24 |
Oct 02 08:58:11 PM UTC 24 |
34412397700 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.1596269879 |
|
|
Oct 02 08:57:10 PM UTC 24 |
Oct 02 08:57:20 PM UTC 24 |
1807852859 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.3308006511 |
|
|
Oct 02 08:57:11 PM UTC 24 |
Oct 02 08:57:22 PM UTC 24 |
2863867105 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.3975058649 |
|
|
Oct 02 08:57:21 PM UTC 24 |
Oct 02 08:57:23 PM UTC 24 |
218057649 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.1819247008 |
|
|
Oct 02 08:57:21 PM UTC 24 |
Oct 02 08:57:24 PM UTC 24 |
384084186 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_perf.2771119914 |
|
|
Oct 02 08:58:01 PM UTC 24 |
Oct 02 08:58:11 PM UTC 24 |
2364950701 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.2426547342 |
|
|
Oct 02 08:56:11 PM UTC 24 |
Oct 02 08:57:26 PM UTC 24 |
20617112620 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.662520322 |
|
|
Oct 02 08:57:18 PM UTC 24 |
Oct 02 08:57:27 PM UTC 24 |
16938746755 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.65290021 |
|
|
Oct 02 08:57:09 PM UTC 24 |
Oct 02 08:57:27 PM UTC 24 |
826158682 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.2031665942 |
|
|
Oct 02 08:57:02 PM UTC 24 |
Oct 02 08:57:28 PM UTC 24 |
12049296105 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_hrst.2800222133 |
|
|
Oct 02 08:57:24 PM UTC 24 |
Oct 02 08:57:29 PM UTC 24 |
828335753 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.1764067631 |
|
|
Oct 02 08:57:44 PM UTC 24 |
Oct 02 08:58:12 PM UTC 24 |
1536205471 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_perf.2891901408 |
|
|
Oct 02 08:57:23 PM UTC 24 |
Oct 02 08:57:30 PM UTC 24 |
758685050 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.1713122414 |
|
|
Oct 02 08:57:29 PM UTC 24 |
Oct 02 08:57:31 PM UTC 24 |
271637079 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.1554854812 |
|
|
Oct 02 08:57:27 PM UTC 24 |
Oct 02 08:57:34 PM UTC 24 |
558574188 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.2448444673 |
|
|
Oct 02 08:57:31 PM UTC 24 |
Oct 02 08:57:35 PM UTC 24 |
1770860383 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.3576573011 |
|
|
Oct 02 08:57:30 PM UTC 24 |
Oct 02 08:57:35 PM UTC 24 |
3010488240 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.1945730693 |
|
|
Oct 02 08:57:24 PM UTC 24 |
Oct 02 08:57:36 PM UTC 24 |
17804661912 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.598464745 |
|
|
Oct 02 08:57:32 PM UTC 24 |
Oct 02 08:57:36 PM UTC 24 |
368699529 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.288363930 |
|
|
Oct 02 08:57:15 PM UTC 24 |
Oct 02 08:57:37 PM UTC 24 |
32102098703 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.1264979001 |
|
|
Oct 02 08:57:31 PM UTC 24 |
Oct 02 08:57:37 PM UTC 24 |
8015498744 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_alert_test.578719957 |
|
|
Oct 02 08:57:35 PM UTC 24 |
Oct 02 08:57:37 PM UTC 24 |
199991260 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.3200759385 |
|
|
Oct 02 08:56:10 PM UTC 24 |
Oct 02 08:57:38 PM UTC 24 |
12882534247 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_override.3882256662 |
|
|
Oct 02 08:57:36 PM UTC 24 |
Oct 02 08:57:38 PM UTC 24 |
43708981 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.1922410773 |
|
|
Oct 02 08:54:51 PM UTC 24 |
Oct 02 08:57:39 PM UTC 24 |
2934379321 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.4293937797 |
|
|
Oct 02 08:57:30 PM UTC 24 |
Oct 02 08:57:40 PM UTC 24 |
384119472 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.3052956908 |
|
|
Oct 02 08:57:38 PM UTC 24 |
Oct 02 08:57:40 PM UTC 24 |
512397518 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.3266066534 |
|
|
Oct 02 08:57:10 PM UTC 24 |
Oct 02 08:57:41 PM UTC 24 |
6387514328 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.281602503 |
|
|
Oct 02 08:57:40 PM UTC 24 |
Oct 02 08:57:43 PM UTC 24 |
147084298 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.558987966 |
|
|
Oct 02 08:57:38 PM UTC 24 |
Oct 02 08:57:43 PM UTC 24 |
300391306 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.2094404523 |
|
|
Oct 02 08:57:38 PM UTC 24 |
Oct 02 08:57:43 PM UTC 24 |
869312339 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.3475006828 |
|
|
Oct 02 08:57:41 PM UTC 24 |
Oct 02 08:57:44 PM UTC 24 |
212879248 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.389367335 |
|
|
Oct 02 08:56:59 PM UTC 24 |
Oct 02 08:57:44 PM UTC 24 |
3787465683 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.1398864693 |
|
|
Oct 02 08:57:27 PM UTC 24 |
Oct 02 08:57:46 PM UTC 24 |
3323677733 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_host_perf.3427459537 |
|
|
Oct 02 08:51:56 PM UTC 24 |
Oct 02 08:57:49 PM UTC 24 |
25529888645 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.3317004261 |
|
|
Oct 02 08:57:43 PM UTC 24 |
Oct 02 08:57:54 PM UTC 24 |
4702853226 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.612778888 |
|
|
Oct 02 08:54:48 PM UTC 24 |
Oct 02 08:58:14 PM UTC 24 |
3326918471 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.998131657 |
|
|
Oct 02 08:57:46 PM UTC 24 |
Oct 02 08:58:00 PM UTC 24 |
1338160009 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.569334016 |
|
|
Oct 02 08:55:29 PM UTC 24 |
Oct 02 08:58:02 PM UTC 24 |
5155533774 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.3811473766 |
|
|
Oct 02 08:57:50 PM UTC 24 |
Oct 02 08:58:02 PM UTC 24 |
5088407684 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.605011419 |
|
|
Oct 02 08:57:59 PM UTC 24 |
Oct 02 08:58:02 PM UTC 24 |
177198831 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.4259590095 |
|
|
Oct 02 08:58:01 PM UTC 24 |
Oct 02 08:58:05 PM UTC 24 |
960382255 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.757844670 |
|
|
Oct 02 08:58:13 PM UTC 24 |
Oct 02 08:58:16 PM UTC 24 |
54870123 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.2209767064 |
|
|
Oct 02 08:58:13 PM UTC 24 |
Oct 02 08:58:17 PM UTC 24 |
620742468 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.1975033972 |
|
|
Oct 02 08:58:13 PM UTC 24 |
Oct 02 08:58:17 PM UTC 24 |
9971636979 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.3378366498 |
|
|
Oct 02 08:58:14 PM UTC 24 |
Oct 02 08:58:18 PM UTC 24 |
939713018 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.1388320930 |
|
|
Oct 02 08:57:44 PM UTC 24 |
Oct 02 08:58:19 PM UTC 24 |
30287957290 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_alert_test.3893297373 |
|
|
Oct 02 08:58:17 PM UTC 24 |
Oct 02 08:58:19 PM UTC 24 |
19569741 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.423291621 |
|
|
Oct 02 08:56:57 PM UTC 24 |
Oct 02 08:58:19 PM UTC 24 |
6905753857 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_override.2412369793 |
|
|
Oct 02 08:58:18 PM UTC 24 |
Oct 02 08:58:20 PM UTC 24 |
29158135 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_stress_all.1178268031 |
|
|
Oct 02 08:50:57 PM UTC 24 |
Oct 02 09:09:54 PM UTC 24 |
14954368165 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_stress_all.1844959720 |
|
|
Oct 02 08:52:10 PM UTC 24 |
Oct 02 09:23:56 PM UTC 24 |
65712703786 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.4156662124 |
|
|
Oct 02 08:58:15 PM UTC 24 |
Oct 02 08:58:21 PM UTC 24 |
595836622 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.1146276333 |
|
|
Oct 02 08:58:19 PM UTC 24 |
Oct 02 08:58:22 PM UTC 24 |
299229790 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.152258778 |
|
|
Oct 02 08:58:16 PM UTC 24 |
Oct 02 08:58:22 PM UTC 24 |
1923685187 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.2640897505 |
|
|
Oct 02 08:58:13 PM UTC 24 |
Oct 02 08:58:23 PM UTC 24 |
217113905 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.2345780123 |
|
|
Oct 02 08:57:40 PM UTC 24 |
Oct 02 08:58:23 PM UTC 24 |
823628990 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_full.2705309516 |
|
|
Oct 02 08:54:12 PM UTC 24 |
Oct 02 08:58:24 PM UTC 24 |
7552667634 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.633940034 |
|
|
Oct 02 08:58:23 PM UTC 24 |
Oct 02 08:58:28 PM UTC 24 |
227150263 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.563703006 |
|
|
Oct 02 08:58:20 PM UTC 24 |
Oct 02 08:58:29 PM UTC 24 |
402272400 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_perf.3369856229 |
|
|
Oct 02 08:57:39 PM UTC 24 |
Oct 02 08:58:31 PM UTC 24 |
2485833426 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.2918304776 |
|
|
Oct 02 08:55:33 PM UTC 24 |
Oct 02 08:58:32 PM UTC 24 |
6051558705 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.2476794388 |
|
|
Oct 02 08:58:22 PM UTC 24 |
Oct 02 08:58:32 PM UTC 24 |
911147979 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.1473084756 |
|
|
Oct 02 08:56:58 PM UTC 24 |
Oct 02 08:58:33 PM UTC 24 |
1227560762 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.2326092955 |
|
|
Oct 02 08:58:23 PM UTC 24 |
Oct 02 08:58:35 PM UTC 24 |
3511787844 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.870386054 |
|
|
Oct 02 08:57:36 PM UTC 24 |
Oct 02 08:58:36 PM UTC 24 |
1250456361 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.2717695305 |
|
|
Oct 02 08:58:36 PM UTC 24 |
Oct 02 08:58:40 PM UTC 24 |
229172039 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.3582174325 |
|
|
Oct 02 08:58:31 PM UTC 24 |
Oct 02 08:58:40 PM UTC 24 |
993262086 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.230165491 |
|
|
Oct 02 08:58:37 PM UTC 24 |
Oct 02 08:58:40 PM UTC 24 |
221835397 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.643292154 |
|
|
Oct 02 08:58:33 PM UTC 24 |
Oct 02 08:58:41 PM UTC 24 |
11337403551 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.4196193445 |
|
|
Oct 02 08:57:36 PM UTC 24 |
Oct 02 08:58:43 PM UTC 24 |
2910254557 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.350330479 |
|
|
Oct 02 08:58:30 PM UTC 24 |
Oct 02 08:58:43 PM UTC 24 |
2384774095 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.717911684 |
|
|
Oct 02 08:57:36 PM UTC 24 |
Oct 02 08:58:43 PM UTC 24 |
9335137999 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.577621713 |
|
|
Oct 02 08:58:24 PM UTC 24 |
Oct 02 08:58:43 PM UTC 24 |
3718432115 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.3512812646 |
|
|
Oct 02 08:58:33 PM UTC 24 |
Oct 02 08:58:44 PM UTC 24 |
3361323005 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.2957585171 |
|
|
Oct 02 08:58:44 PM UTC 24 |
Oct 02 08:58:46 PM UTC 24 |
380304919 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_host_stress_all.2483609856 |
|
|
Oct 02 08:40:16 PM UTC 24 |
Oct 02 09:27:20 PM UTC 24 |
53523414885 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.1054095700 |
|
|
Oct 02 08:57:39 PM UTC 24 |
Oct 02 08:58:47 PM UTC 24 |
32149949531 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.973400714 |
|
|
Oct 02 08:58:43 PM UTC 24 |
Oct 02 08:58:48 PM UTC 24 |
2975833252 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.2217876250 |
|
|
Oct 02 08:58:45 PM UTC 24 |
Oct 02 08:58:48 PM UTC 24 |
786200103 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_perf.2801741727 |
|
|
Oct 02 08:58:38 PM UTC 24 |
Oct 02 08:58:49 PM UTC 24 |
852115265 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.2274021956 |
|
|
Oct 02 08:58:41 PM UTC 24 |
Oct 02 08:58:49 PM UTC 24 |
798315756 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_alert_test.3955475675 |
|
|
Oct 02 08:58:48 PM UTC 24 |
Oct 02 08:58:50 PM UTC 24 |
15803975 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.3685854799 |
|
|
Oct 02 08:58:46 PM UTC 24 |
Oct 02 08:58:51 PM UTC 24 |
390691271 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.3755299206 |
|
|
Oct 02 08:58:22 PM UTC 24 |
Oct 02 08:58:52 PM UTC 24 |
631819444 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.3662310618 |
|
|
Oct 02 08:58:47 PM UTC 24 |
Oct 02 08:58:52 PM UTC 24 |
1054995431 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_host_stress_all.795574095 |
|
|
Oct 02 08:51:57 PM UTC 24 |
Oct 02 08:58:55 PM UTC 24 |
48289113428 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.3541670888 |
|
|
Oct 02 08:57:23 PM UTC 24 |
Oct 02 08:58:56 PM UTC 24 |
90649196773 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.1337868468 |
|
|
Oct 02 08:57:48 PM UTC 24 |
Oct 02 08:58:56 PM UTC 24 |
5737692988 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.1015033 |
|
|
Oct 02 08:56:57 PM UTC 24 |
Oct 02 08:58:59 PM UTC 24 |
16574705329 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.3627868979 |
|
|
Oct 02 08:58:18 PM UTC 24 |
Oct 02 08:59:00 PM UTC 24 |
7581938306 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_perf.3014092582 |
|
|
Oct 02 08:51:38 PM UTC 24 |
Oct 02 08:59:01 PM UTC 24 |
18299821647 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.490823360 |
|
|
Oct 02 08:58:28 PM UTC 24 |
Oct 02 08:59:04 PM UTC 24 |
814747304 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.3097226063 |
|
|
Oct 02 08:58:02 PM UTC 24 |
Oct 02 08:59:05 PM UTC 24 |
50380011586 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.2977565659 |
|
|
Oct 02 08:58:43 PM UTC 24 |
Oct 02 08:59:07 PM UTC 24 |
2128820530 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_perf.1093143735 |
|
|
Oct 02 08:58:22 PM UTC 24 |
Oct 02 08:59:15 PM UTC 24 |
4869139251 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.769954690 |
|
|
Oct 02 08:57:10 PM UTC 24 |
Oct 02 08:59:21 PM UTC 24 |
48414822677 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.3018559188 |
|
|
Oct 02 08:53:58 PM UTC 24 |
Oct 02 08:59:25 PM UTC 24 |
31728049040 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.3112200829 |
|
|
Oct 02 08:58:40 PM UTC 24 |
Oct 02 08:59:34 PM UTC 24 |
11185904988 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.433728928 |
|
|
Oct 02 08:56:47 PM UTC 24 |
Oct 02 08:59:35 PM UTC 24 |
14956253797 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.1088954841 |
|
|
Oct 02 08:56:22 PM UTC 24 |
Oct 02 08:59:40 PM UTC 24 |
29111076898 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.120256134 |
|
|
Oct 02 08:58:22 PM UTC 24 |
Oct 02 08:59:53 PM UTC 24 |
8466987984 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.852067798 |
|
|
Oct 02 08:55:41 PM UTC 24 |
Oct 02 08:59:56 PM UTC 24 |
44329992383 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.2060632882 |
|
|
Oct 02 08:58:19 PM UTC 24 |
Oct 02 09:00:16 PM UTC 24 |
22594297466 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.1063238223 |
|
|
Oct 02 08:58:19 PM UTC 24 |
Oct 02 09:00:23 PM UTC 24 |
4040869245 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.2057443809 |
|
|
Oct 02 08:58:25 PM UTC 24 |
Oct 02 09:00:38 PM UTC 24 |
39876827604 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_perf_precise.4062795665 |
|
|
Oct 02 08:55:34 PM UTC 24 |
Oct 02 09:00:39 PM UTC 24 |
6152397093 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.3720627580 |
|
|
Oct 02 08:55:18 PM UTC 24 |
Oct 02 09:00:49 PM UTC 24 |
41467300758 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_host_perf.1166548457 |
|
|
Oct 02 08:54:52 PM UTC 24 |
Oct 02 09:01:16 PM UTC 24 |
27554666119 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_stress_all.3748265964 |
|
|
Oct 02 08:46:00 PM UTC 24 |
Oct 02 09:01:30 PM UTC 24 |
17935259009 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_host_perf.1892857431 |
|
|
Oct 02 08:54:12 PM UTC 24 |
Oct 02 09:01:38 PM UTC 24 |
12739576003 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_host_stress_all.1199517147 |
|
|
Oct 02 08:53:04 PM UTC 24 |
Oct 02 09:02:21 PM UTC 24 |
15910922898 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_stress_all.985809861 |
|
|
Oct 02 08:48:26 PM UTC 24 |
Oct 02 09:02:23 PM UTC 24 |
80817074461 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.2822147898 |
|
|
Oct 02 08:54:59 PM UTC 24 |
Oct 02 09:02:51 PM UTC 24 |
40721632521 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.1194070586 |
|
|
Oct 02 08:56:35 PM UTC 24 |
Oct 02 09:03:53 PM UTC 24 |
22781697764 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_stress_wr.1555472594 |
|
|
Oct 02 08:41:30 PM UTC 24 |
Oct 02 09:04:01 PM UTC 24 |
57840184217 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_stress_all.3104024817 |
|
|
Oct 02 08:55:36 PM UTC 24 |
Oct 02 09:04:41 PM UTC 24 |
8093263949 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_stress_all.2167647732 |
|
|
Oct 02 08:46:51 PM UTC 24 |
Oct 02 09:06:18 PM UTC 24 |
55280296420 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_host_perf.3766954562 |
|
|
Oct 02 08:53:37 PM UTC 24 |
Oct 02 09:08:27 PM UTC 24 |
29277808726 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_stress_all.501673374 |
|
|
Oct 02 08:57:09 PM UTC 24 |
Oct 02 09:08:45 PM UTC 24 |
21412782903 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_stress_wr.738066994 |
|
|
Oct 02 08:52:31 PM UTC 24 |
Oct 02 09:15:38 PM UTC 24 |
65485298061 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.1253358329 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:39 PM UTC 24 |
20614225 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.378812752 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:51 PM UTC 24 |
97052006 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.2377274278 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:40 PM UTC 24 |
21242176 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.1540494330 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:40 PM UTC 24 |
94717949 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1087579812 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:40 PM UTC 24 |
64593359 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.3232720634 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:40 PM UTC 24 |
25133381 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.2263865334 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:40 PM UTC 24 |
84133220 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.2834697437 |
|
|
Oct 02 07:05:48 PM UTC 24 |
Oct 02 07:05:50 PM UTC 24 |
48019839 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.257010341 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:40 PM UTC 24 |
51807460 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2336427053 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:40 PM UTC 24 |
86997062 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.105212896 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:40 PM UTC 24 |
22203163 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.3870760111 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:40 PM UTC 24 |
63656513 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.22147051 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:40 PM UTC 24 |
46189401 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.763177896 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:40 PM UTC 24 |
79116920 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.1934091779 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:40 PM UTC 24 |
57854611 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.2545443972 |
|
|
Oct 02 07:05:39 PM UTC 24 |
Oct 02 07:05:41 PM UTC 24 |
26238303 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.802363346 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:41 PM UTC 24 |
87646621 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.1744747202 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:41 PM UTC 24 |
147731509 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.163899074 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:41 PM UTC 24 |
28247953 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.532263346 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:41 PM UTC 24 |
274719167 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.504506391 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:41 PM UTC 24 |
190910646 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.2368721856 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:41 PM UTC 24 |
153876985 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.4697543 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:42 PM UTC 24 |
272452281 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.2174089047 |
|
|
Oct 02 07:05:39 PM UTC 24 |
Oct 02 07:05:42 PM UTC 24 |
191242516 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.2816008737 |
|
|
Oct 02 07:05:41 PM UTC 24 |
Oct 02 07:05:43 PM UTC 24 |
20038131 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3829779344 |
|
|
Oct 02 07:05:41 PM UTC 24 |
Oct 02 07:05:43 PM UTC 24 |
31843386 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.1648084839 |
|
|
Oct 02 07:05:41 PM UTC 24 |
Oct 02 07:05:43 PM UTC 24 |
47146076 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3781617860 |
|
|
Oct 02 07:05:41 PM UTC 24 |
Oct 02 07:05:43 PM UTC 24 |
202843881 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1345821168 |
|
|
Oct 02 07:05:42 PM UTC 24 |
Oct 02 07:05:43 PM UTC 24 |
116830584 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.1295018185 |
|
|
Oct 02 07:05:41 PM UTC 24 |
Oct 02 07:05:43 PM UTC 24 |
35650188 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.100910699 |
|
|
Oct 02 07:05:41 PM UTC 24 |
Oct 02 07:05:43 PM UTC 24 |
169904507 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.2879342528 |
|
|
Oct 02 07:05:42 PM UTC 24 |
Oct 02 07:05:43 PM UTC 24 |
24918148 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3159702049 |
|
|
Oct 02 07:05:42 PM UTC 24 |
Oct 02 07:05:44 PM UTC 24 |
325990788 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.3996695097 |
|
|
Oct 02 07:05:42 PM UTC 24 |
Oct 02 07:05:44 PM UTC 24 |
22852570 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.1765839021 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:44 PM UTC 24 |
487613994 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.290993171 |
|
|
Oct 02 07:05:42 PM UTC 24 |
Oct 02 07:05:44 PM UTC 24 |
25489445 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.3445398821 |
|
|
Oct 02 07:05:41 PM UTC 24 |
Oct 02 07:05:44 PM UTC 24 |
241158624 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.1278533724 |
|
|
Oct 02 07:05:41 PM UTC 24 |
Oct 02 07:05:44 PM UTC 24 |
33392235 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.4266492341 |
|
|
Oct 02 07:05:38 PM UTC 24 |
Oct 02 07:05:44 PM UTC 24 |
2085069688 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.3093617740 |
|
|
Oct 02 07:05:41 PM UTC 24 |
Oct 02 07:05:44 PM UTC 24 |
89677507 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.3525647040 |
|
|
Oct 02 07:05:42 PM UTC 24 |
Oct 02 07:05:45 PM UTC 24 |
73074895 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.3114681876 |
|
|
Oct 02 07:05:42 PM UTC 24 |
Oct 02 07:05:45 PM UTC 24 |
118917914 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.1107446232 |
|
|
Oct 02 07:05:41 PM UTC 24 |
Oct 02 07:05:45 PM UTC 24 |
69183709 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.3066787704 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:47 PM UTC 24 |
17094711 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.3925462710 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:47 PM UTC 24 |
23275842 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.555862135 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:47 PM UTC 24 |
16621500 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3128647712 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:47 PM UTC 24 |
62714732 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.4221898323 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:47 PM UTC 24 |
125903268 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.1481536744 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:51 PM UTC 24 |
19518661 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.3796701232 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:47 PM UTC 24 |
67644680 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3698051030 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:47 PM UTC 24 |
77662874 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.4163894990 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:50 PM UTC 24 |
45699583 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.2580522468 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:47 PM UTC 24 |
17580412 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3091005741 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:47 PM UTC 24 |
25127071 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1866915550 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:47 PM UTC 24 |
26194389 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.4123237166 |
|
|
Oct 02 07:05:46 PM UTC 24 |
Oct 02 07:05:47 PM UTC 24 |
42601675 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.3167847570 |
|
|
Oct 02 07:05:46 PM UTC 24 |
Oct 02 07:05:47 PM UTC 24 |
40148859 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.1852403117 |
|
|
Oct 02 07:05:46 PM UTC 24 |
Oct 02 07:05:47 PM UTC 24 |
44716405 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.1048432412 |
|
|
Oct 02 07:05:46 PM UTC 24 |
Oct 02 07:05:48 PM UTC 24 |
38022853 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.2876091367 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:48 PM UTC 24 |
77817288 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.665537426 |
|
|
Oct 02 07:05:46 PM UTC 24 |
Oct 02 07:05:48 PM UTC 24 |
32358727 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.2814585283 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:48 PM UTC 24 |
39244526 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.994383845 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:48 PM UTC 24 |
37999470 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.4193929369 |
|
|
Oct 02 07:05:42 PM UTC 24 |
Oct 02 07:05:48 PM UTC 24 |
10194648875 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.1448557180 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:48 PM UTC 24 |
96963992 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.1442365726 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:48 PM UTC 24 |
184524937 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2764213457 |
|
|
Oct 02 07:05:46 PM UTC 24 |
Oct 02 07:05:48 PM UTC 24 |
80897247 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2370752252 |
|
|
Oct 02 07:05:46 PM UTC 24 |
Oct 02 07:05:48 PM UTC 24 |
24483060 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.3549345940 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:48 PM UTC 24 |
96160352 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.442182566 |
|
|
Oct 02 07:05:46 PM UTC 24 |
Oct 02 07:05:48 PM UTC 24 |
192903974 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.1403677673 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:48 PM UTC 24 |
86262047 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.348343306 |
|
|
Oct 02 07:05:45 PM UTC 24 |
Oct 02 07:05:49 PM UTC 24 |
150722034 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.498627824 |
|
|
Oct 02 07:05:46 PM UTC 24 |
Oct 02 07:05:49 PM UTC 24 |
335875822 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.3400937574 |
|
|
Oct 02 07:05:48 PM UTC 24 |
Oct 02 07:05:50 PM UTC 24 |
22947189 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.147355102 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:50 PM UTC 24 |
28104063 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.2335437637 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:50 PM UTC 24 |
38466130 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1310495709 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:51 PM UTC 24 |
53914646 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.895337953 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:51 PM UTC 24 |
230826010 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.634024593 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:51 PM UTC 24 |
47503441 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.3233465483 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:51 PM UTC 24 |
34948373 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.183182382 |
|
|
Oct 02 07:05:48 PM UTC 24 |
Oct 02 07:05:51 PM UTC 24 |
247186263 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.3025092805 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:51 PM UTC 24 |
17612405 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.2263438337 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:51 PM UTC 24 |
31674184 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.386155414 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:52 PM UTC 24 |
19345592 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3748414608 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:51 PM UTC 24 |
81445204 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.1041033410 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:51 PM UTC 24 |
49577216 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.1932306584 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:51 PM UTC 24 |
17566265 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.678474277 |
|
|
Oct 02 07:05:48 PM UTC 24 |
Oct 02 07:05:52 PM UTC 24 |
126468424 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3734887039 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:51 PM UTC 24 |
39261954 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.873834493 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:51 PM UTC 24 |
48404435 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.1474943334 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:51 PM UTC 24 |
49771891 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2034961630 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:51 PM UTC 24 |
66704167 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.4223360529 |
|
|
Oct 02 07:05:49 PM UTC 24 |
Oct 02 07:05:52 PM UTC 24 |
1078809107 ps |