| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 91.19 | 97.14 | 89.39 | 97.22 | 72.02 | 94.08 | 98.47 | 90.00 |
| T1756 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.3413051982 | Oct 02 07:05:49 PM UTC 24 | Oct 02 07:05:52 PM UTC 24 | 105807482 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.296744018 | Oct 02 07:05:49 PM UTC 24 | Oct 02 07:05:52 PM UTC 24 | 135040786 ps | ||
| T1757 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.472417960 | Oct 02 07:05:49 PM UTC 24 | Oct 02 07:05:53 PM UTC 24 | 511062028 ps | ||
| T1758 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.3804060628 | Oct 02 07:05:49 PM UTC 24 | Oct 02 07:05:53 PM UTC 24 | 481960206 ps | ||
| T1759 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.4151903631 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 42425318 ps | ||
| T1760 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.563168017 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 110525302 ps | ||
| T1761 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.839176167 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 18407526 ps | ||
| T1762 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.2763846318 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 22592264 ps | ||
| T1763 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1316663451 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 23491138 ps | ||
| T1764 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.1901743333 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 83748073 ps | ||
| T1765 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.1385621519 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 136197884 ps | ||
| T1766 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.828903994 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 44415953 ps | ||
| T1767 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1748948112 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 100015081 ps | ||
| T1768 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.1991955592 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 43264960 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.1282131220 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 87134146 ps | ||
| T1769 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.1451605037 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 18241008 ps | ||
| T1770 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.4164840155 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 21630050 ps | ||
| T1771 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.740438234 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 94456101 ps | ||
| T1772 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.3630645015 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 59524192 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.2150151061 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 140276920 ps | ||
| T1773 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2485720918 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 190706658 ps | ||
| T1774 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3132705036 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 33311133 ps | ||
| T1775 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1580465325 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:54 PM UTC 24 | 78606460 ps | ||
| T1776 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2592232822 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:55 PM UTC 24 | 32697627 ps | ||
| T1777 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1603710581 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:55 PM UTC 24 | 53919917 ps | ||
| T1778 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.1849573948 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:55 PM UTC 24 | 165476343 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.4133114355 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:55 PM UTC 24 | 59066032 ps | ||
| T1779 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.1612663228 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:55 PM UTC 24 | 649683732 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.3872411698 | Oct 02 07:05:52 PM UTC 24 | Oct 02 07:05:55 PM UTC 24 | 540131389 ps | ||
| T1780 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.2682868692 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 78709932 ps | ||
| T1781 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.1287883157 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 18751227 ps | ||
| T1782 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.135879338 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 17098585 ps | ||
| T1783 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1928077124 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 36297747 ps | ||
| T1784 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.3810708634 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 34998831 ps | ||
| T1785 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.4241662710 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 26383449 ps | ||
| T1786 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.2114818607 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 18277523 ps | ||
| T1787 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2175219439 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 136093748 ps | ||
| T1788 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.2387073337 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 18098497 ps | ||
| T1789 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.1098478574 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 15965354 ps | ||
| T1790 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.2431551131 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 80350290 ps | ||
| T1791 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.3946501507 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 18904433 ps | ||
| T1792 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.1560472593 | Oct 02 07:05:56 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 18212699 ps | ||
| T1793 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.518467351 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 22051284 ps | ||
| T1794 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.1825310382 | Oct 02 07:05:56 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 18381498 ps | ||
| T1795 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.2683118000 | Oct 02 07:05:56 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 32872488 ps | ||
| T1796 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.4053309742 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 26257367 ps | ||
| T1797 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3919823143 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:57 PM UTC 24 | 334236959 ps | ||
| T1798 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.442545203 | Oct 02 07:05:56 PM UTC 24 | Oct 02 07:05:58 PM UTC 24 | 17656441 ps | ||
| T1799 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.1502566432 | Oct 02 07:05:56 PM UTC 24 | Oct 02 07:05:58 PM UTC 24 | 143429967 ps | ||
| T1800 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.2805187407 | Oct 02 07:05:56 PM UTC 24 | Oct 02 07:05:58 PM UTC 24 | 32377704 ps | ||
| T1801 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.3819818368 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:58 PM UTC 24 | 152000163 ps | ||
| T1802 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.1006073165 | Oct 02 07:05:56 PM UTC 24 | Oct 02 07:05:58 PM UTC 24 | 22679823 ps | ||
| T1803 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.2375795587 | Oct 02 07:05:56 PM UTC 24 | Oct 02 07:05:58 PM UTC 24 | 31250824 ps | ||
| T1804 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.1973518629 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:58 PM UTC 24 | 236804546 ps | ||
| T1805 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.1364059839 | Oct 02 07:05:55 PM UTC 24 | Oct 02 07:05:58 PM UTC 24 | 353948860 ps | ||
| T1806 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.1778187563 | Oct 02 07:05:58 PM UTC 24 | Oct 02 07:06:00 PM UTC 24 | 35346077 ps | ||
| T1807 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.2678084779 | Oct 02 07:05:58 PM UTC 24 | Oct 02 07:06:00 PM UTC 24 | 17678641 ps | ||
| T1808 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.3145345791 | Oct 02 07:05:58 PM UTC 24 | Oct 02 07:06:00 PM UTC 24 | 40949046 ps | ||
| T1809 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.2934922783 | Oct 02 07:05:58 PM UTC 24 | Oct 02 07:06:00 PM UTC 24 | 49926589 ps | ||
| T1810 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.260504523 | Oct 02 07:05:58 PM UTC 24 | Oct 02 07:06:00 PM UTC 24 | 19989852 ps | ||
| T1811 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.553462702 | Oct 02 07:05:58 PM UTC 24 | Oct 02 07:06:00 PM UTC 24 | 126523060 ps | ||
| T1812 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.2729732357 | Oct 02 07:05:58 PM UTC 24 | Oct 02 07:06:00 PM UTC 24 | 49434798 ps | ||
| T1813 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.1561022802 | Oct 02 07:05:58 PM UTC 24 | Oct 02 07:06:00 PM UTC 24 | 15379864 ps | ||
| T1814 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.877899576 | Oct 02 07:05:58 PM UTC 24 | Oct 02 07:06:00 PM UTC 24 | 22868667 ps | ||
| T1815 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.3941566711 | Oct 02 07:05:58 PM UTC 24 | Oct 02 07:06:00 PM UTC 24 | 28243402 ps | ||
| T1816 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.2713872489 | Oct 02 07:05:58 PM UTC 24 | Oct 02 07:06:00 PM UTC 24 | 18903501 ps | ||
| T1817 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.3292846706 | Oct 02 07:05:58 PM UTC 24 | Oct 02 07:06:00 PM UTC 24 | 17988160 ps | ||
| T1818 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.3175451970 | Oct 02 07:05:58 PM UTC 24 | Oct 02 07:06:00 PM UTC 24 | 40753463 ps | ||
| T1819 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.1431217457 | Oct 02 07:05:58 PM UTC 24 | Oct 02 07:06:00 PM UTC 24 | 85126126 ps | ||
| T1820 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.3738473608 | Oct 02 07:05:58 PM UTC 24 | Oct 02 07:06:00 PM UTC 24 | 20299699 ps | ||
| T1821 | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.2813905002 | Oct 02 07:05:58 PM UTC 24 | Oct 02 07:06:00 PM UTC 24 | 22795706 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_smoke.1470424066 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8827799646 ps |
| CPU time | 31.04 seconds |
| Started | Oct 02 08:18:02 PM UTC 24 |
| Finished | Oct 02 08:18:34 PM UTC 24 |
| Peak memory | 314216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470424066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.1470424066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_glitch.2661990416 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 8713106328 ps |
| CPU time | 19.32 seconds |
| Started | Oct 02 08:19:15 PM UTC 24 |
| Finished | Oct 02 08:19:36 PM UTC 24 |
| Peak memory | 226088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661990416 -assert nopostproc +UVM_TESTNAME=i 2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2661990416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_stress_all.3316821969 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 49325901813 ps |
| CPU time | 559.56 seconds |
| Started | Oct 02 08:23:21 PM UTC 24 |
| Finished | Oct 02 08:32:48 PM UTC 24 |
| Peak memory | 662440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316821969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.3316821969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_host_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_bad_addr.1924473719 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 2352188067 ps |
| CPU time | 7.62 seconds |
| Started | Oct 02 08:19:53 PM UTC 24 |
| Finished | Oct 02 08:20:02 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1924473719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1924473719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.2368721856 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 153876985 ps |
| CPU time | 2 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:41 PM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368721856 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.2368721856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_watermark.1175611294 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5428754241 ps |
| CPU time | 74.57 seconds |
| Started | Oct 02 08:18:33 PM UTC 24 |
| Finished | Oct 02 08:19:50 PM UTC 24 |
| Peak memory | 910108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175611294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1175611294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_error_intr.2967281546 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6740065377 ps |
| CPU time | 24.1 seconds |
| Started | Oct 02 08:25:16 PM UTC 24 |
| Finished | Oct 02 08:25:42 PM UTC 24 |
| Peak memory | 248632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967281546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.2967281546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_nack_txstretch.450601019 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 138239982 ps |
| CPU time | 2.2 seconds |
| Started | Oct 02 08:20:07 PM UTC 24 |
| Finished | Oct 02 08:20:10 PM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4506010 19 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_txstretch.450601019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_override.4238579233 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 166722122 ps |
| CPU time | 1.12 seconds |
| Started | Oct 02 08:20:12 PM UTC 24 |
| Finished | Oct 02 08:20:14 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238579233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.4238579233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_may_nack.2362844651 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 976650767 ps |
| CPU time | 13.43 seconds |
| Started | Oct 02 08:24:35 PM UTC 24 |
| Finished | Oct 02 08:24:49 PM UTC 24 |
| Peak memory | 215240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362844651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.2362844651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_stress_all.4112821389 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 43298189256 ps |
| CPU time | 61.19 seconds |
| Started | Oct 02 08:19:53 PM UTC 24 |
| Finished | Oct 02 08:20:56 PM UTC 24 |
| Peak memory | 240504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411282 1389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_all.4112821389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.1488989341 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 40820567 ps |
| CPU time | 1.42 seconds |
| Started | Oct 02 08:20:10 PM UTC 24 |
| Finished | Oct 02 08:20:12 PM UTC 24 |
| Peak memory | 244508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488989341 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1488989341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_stress_all.1219208528 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 98830676756 ps |
| CPU time | 371.86 seconds |
| Started | Oct 02 08:46:35 PM UTC 24 |
| Finished | Oct 02 08:52:52 PM UTC 24 |
| Peak memory | 1919768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219208528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.1219208528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_host_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull_addr.2657574135 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 420808931 ps |
| CPU time | 4.38 seconds |
| Started | Oct 02 08:28:34 PM UTC 24 |
| Finished | Oct 02 08:28:39 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657574 135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.2657574135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_fmt.3986780437 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 653377150 ps |
| CPU time | 1.9 seconds |
| Started | Oct 02 08:18:36 PM UTC 24 |
| Finished | Oct 02 08:18:39 PM UTC 24 |
| Peak memory | 214868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986780437 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt.3986780437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.2545443972 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 26238303 ps |
| CPU time | 0.93 seconds |
| Started | Oct 02 07:05:39 PM UTC 24 |
| Finished | Oct 02 07:05:41 PM UTC 24 |
| Peak memory | 214676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545443972 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2545443972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_error_intr.3838884243 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 813607934 ps |
| CPU time | 9.76 seconds |
| Started | Oct 02 08:31:46 PM UTC 24 |
| Finished | Oct 02 08:31:57 PM UTC 24 |
| Peak memory | 229700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838884243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.3838884243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.1403677673 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 86262047 ps |
| CPU time | 2.11 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:48 PM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403677673 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.1403677673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_stress_all.3307156113 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 21874864682 ps |
| CPU time | 204.01 seconds |
| Started | Oct 02 08:22:33 PM UTC 24 |
| Finished | Oct 02 08:26:00 PM UTC 24 |
| Peak memory | 2556964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330715 6113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_all.3307156113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull_addr.2946687529 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 979087561 ps |
| CPU time | 5.51 seconds |
| Started | Oct 02 08:20:06 PM UTC 24 |
| Finished | Oct 02 08:20:12 PM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946687 529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.2946687529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull.2174915421 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 3640604194 ps |
| CPU time | 3.04 seconds |
| Started | Oct 02 08:38:12 PM UTC 24 |
| Finished | Oct 02 08:38:16 PM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174915 421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_acqfull.2174915421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_overflow.3458799685 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 5196504450 ps |
| CPU time | 257.1 seconds |
| Started | Oct 02 08:18:34 PM UTC 24 |
| Finished | Oct 02 08:22:56 PM UTC 24 |
| Peak memory | 850736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458799685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.3458799685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.1253358329 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 20614225 ps |
| CPU time | 0.84 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:39 PM UTC 24 |
| Peak memory | 214288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253358329 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1253358329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.2816008737 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 20038131 ps |
| CPU time | 0.83 seconds |
| Started | Oct 02 07:05:41 PM UTC 24 |
| Finished | Oct 02 07:05:43 PM UTC 24 |
| Peak memory | 214612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816008737 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.2816008737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_rx.55740023 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 404105012 ps |
| CPU time | 4.5 seconds |
| Started | Oct 02 08:23:11 PM UTC 24 |
| Finished | Oct 02 08:23:16 PM UTC 24 |
| Peak memory | 230112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55740023 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.55740023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_stress_all.1898501225 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 14377520021 ps |
| CPU time | 670.41 seconds |
| Started | Oct 02 08:30:27 PM UTC 24 |
| Finished | Oct 02 08:41:45 PM UTC 24 |
| Peak memory | 2284384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898501225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.1898501225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_host_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_alert_test.3187394098 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 15617047 ps |
| CPU time | 0.94 seconds |
| Started | Oct 02 08:20:11 PM UTC 24 |
| Finished | Oct 02 08:20:13 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187394098 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.3187394098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_acq.3594626323 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 689039015 ps |
| CPU time | 3.3 seconds |
| Started | Oct 02 08:20:00 PM UTC 24 |
| Finished | Oct 02 08:20:05 PM UTC 24 |
| Peak memory | 215236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594626 323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_watermark s_acq.3594626323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_host_may_nack.1446059509 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2123443288 ps |
| CPU time | 27.12 seconds |
| Started | Oct 02 08:36:33 PM UTC 24 |
| Finished | Oct 02 08:37:02 PM UTC 24 |
| Peak memory | 215184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446059509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.1446059509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_fmt.3298981934 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 105581383 ps |
| CPU time | 1.76 seconds |
| Started | Oct 02 08:36:42 PM UTC 24 |
| Finished | Oct 02 08:36:45 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298981934 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fmt.3298981934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_perf.1540529846 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 27639271239 ps |
| CPU time | 350.03 seconds |
| Started | Oct 02 08:29:15 PM UTC 24 |
| Finished | Oct 02 08:35:10 PM UTC 24 |
| Peak memory | 533204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540529846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1540529846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_host_mode_toggle.2956638452 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 293991515 ps |
| CPU time | 1.35 seconds |
| Started | Oct 02 08:41:11 PM UTC 24 |
| Finished | Oct 02 08:41:13 PM UTC 24 |
| Peak memory | 224840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956638452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.2956638452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_host_mode_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_watermark.3122188159 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 5942091839 ps |
| CPU time | 54.71 seconds |
| Started | Oct 02 08:31:29 PM UTC 24 |
| Finished | Oct 02 08:32:26 PM UTC 24 |
| Peak memory | 940848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122188159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.3122188159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_smoke.2807245417 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 4286468032 ps |
| CPU time | 28.81 seconds |
| Started | Oct 02 08:37:01 PM UTC 24 |
| Finished | Oct 02 08:37:31 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807245417 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smoke.2807245417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull_addr.567454786 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2724438120 ps |
| CPU time | 4.15 seconds |
| Started | Oct 02 08:40:45 PM UTC 24 |
| Finished | Oct 02 08:40:50 PM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5674547 86 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_acqfull_addr.567454786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_acq.3204441239 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 461417566 ps |
| CPU time | 1.35 seconds |
| Started | Oct 02 08:48:45 PM UTC 24 |
| Finished | Oct 02 08:48:47 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204441 239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_acq.3204441239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_stress_all.501673374 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 21412782903 ps |
| CPU time | 687.88 seconds |
| Started | Oct 02 08:57:09 PM UTC 24 |
| Finished | Oct 02 09:08:45 PM UTC 24 |
| Peak memory | 2677464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501673374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.501673374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_host_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.4697543 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 272452281 ps |
| CPU time | 2.32 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:42 PM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4697543 -assert nopostproc +UVM_TESTNAME=i2 c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.4697543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.296744018 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 135040786 ps |
| CPU time | 2.07 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:52 PM UTC 24 |
| Peak memory | 215228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296744018 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.296744018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_hrst.755062630 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 445233814 ps |
| CPU time | 5.12 seconds |
| Started | Oct 02 08:39:48 PM UTC 24 |
| Finished | Oct 02 08:39:54 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7550626 30 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_hrst.755062630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_tx_stretch_ctrl.396070951 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 468173480 ps |
| CPU time | 10.07 seconds |
| Started | Oct 02 08:21:26 PM UTC 24 |
| Finished | Oct 02 08:21:37 PM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960709 51 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.396070951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_stress_rd.1400274713 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 5194341913 ps |
| CPU time | 64.14 seconds |
| Started | Oct 02 08:32:09 PM UTC 24 |
| Finished | Oct 02 08:33:15 PM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400274713 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_rd.1400274713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_tx.3079851380 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 723260072 ps |
| CPU time | 2.99 seconds |
| Started | Oct 02 08:34:33 PM UTC 24 |
| Finished | Oct 02 08:34:37 PM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079851 380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_tx.3079851380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_host_may_nack.1615343735 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 450317481 ps |
| CPU time | 19.11 seconds |
| Started | Oct 02 08:39:18 PM UTC 24 |
| Finished | Oct 02 08:39:38 PM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615343735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.1615343735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_may_nack.1519444658 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 516789536 ps |
| CPU time | 9.69 seconds |
| Started | Oct 02 08:47:32 PM UTC 24 |
| Finished | Oct 02 08:47:43 PM UTC 24 |
| Peak memory | 215184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519444658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.1519444658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.634024593 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 47503441 ps |
| CPU time | 1.26 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:51 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634024593 -assert nopostproc +UVM_TESTNAME=i2c_base_tes t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.634024593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.1474943334 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 49771891 ps |
| CPU time | 1.61 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:51 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474943334 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1474943334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.3872411698 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 540131389 ps |
| CPU time | 2.22 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:55 PM UTC 24 |
| Peak memory | 215232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872411698 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.3872411698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3781617860 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 202843881 ps |
| CPU time | 1.09 seconds |
| Started | Oct 02 07:05:41 PM UTC 24 |
| Finished | Oct 02 07:05:43 PM UTC 24 |
| Peak memory | 214648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781617860 -assert nopostproc +UVM _TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_outstanding.3781617860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_may_nack.424587006 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 344245608 ps |
| CPU time | 18.2 seconds |
| Started | Oct 02 08:32:25 PM UTC 24 |
| Finished | Oct 02 08:32:45 PM UTC 24 |
| Peak memory | 215316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424587006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.424587006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_host_mode_toggle.4057370116 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 110411163 ps |
| CPU time | 4.56 seconds |
| Started | Oct 02 08:33:05 PM UTC 24 |
| Finished | Oct 02 08:33:10 PM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057370116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.4057370116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_host_mode_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.3870760111 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 63656513 ps |
| CPU time | 1.36 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:40 PM UTC 24 |
| Peak memory | 214524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870760111 -assert nopostproc +UVM_TESTNAME=i2 c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.3870760111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.1765839021 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 487613994 ps |
| CPU time | 4.8 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:44 PM UTC 24 |
| Peak memory | 215336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765839021 -assert nopostproc +UVM_TESTNAME=i2 c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.1765839021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.2377274278 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 21242176 ps |
| CPU time | 0.89 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:40 PM UTC 24 |
| Peak memory | 214552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377274278 -assert nopostproc +UVM_TESTNAME=i2 c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2377274278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1087579812 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 64593359 ps |
| CPU time | 1.02 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:40 PM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1087579812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1087579812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.1540494330 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 94717949 ps |
| CPU time | 0.96 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:40 PM UTC 24 |
| Peak memory | 214676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540494330 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1540494330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2336427053 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 86997062 ps |
| CPU time | 1.18 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:40 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336427053 -assert nopostproc +UVM _TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_outstanding.2336427053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.2263865334 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 84133220 ps |
| CPU time | 1.49 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:40 PM UTC 24 |
| Peak memory | 214728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263865334 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2263865334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.1744747202 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 147731509 ps |
| CPU time | 2.23 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:41 PM UTC 24 |
| Peak memory | 215104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744747202 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.1744747202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.504506391 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 190910646 ps |
| CPU time | 2.14 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:41 PM UTC 24 |
| Peak memory | 214776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504506391 -assert nopostproc +UVM_TESTNAME=i2c _base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i 2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.504506391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.4266492341 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 2085069688 ps |
| CPU time | 5.11 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:44 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266492341 -assert nopostproc +UVM_TESTNAME=i2 c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.4266492341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.257010341 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 51807460 ps |
| CPU time | 0.98 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:40 PM UTC 24 |
| Peak memory | 214676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257010341 -assert nopostproc +UVM_TESTNAME=i2c _base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i 2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.257010341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.802363346 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 87646621 ps |
| CPU time | 1.33 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:41 PM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =802363346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.802363346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.105212896 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 22203163 ps |
| CPU time | 0.96 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:40 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105212896 -assert nopostproc +UVM_TESTNAME=i2c_base_ test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.105212896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.3232720634 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 25133381 ps |
| CPU time | 0.78 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:40 PM UTC 24 |
| Peak memory | 214552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232720634 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3232720634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.763177896 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 79116920 ps |
| CPU time | 1.1 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:40 PM UTC 24 |
| Peak memory | 214744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763177896 -assert nopostproc +UVM_ TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_outstanding.763177896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.163899074 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 28247953 ps |
| CPU time | 1.87 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:41 PM UTC 24 |
| Peak memory | 214672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163899074 -assert nopostproc +UVM_TESTNAME=i2c_base_tes t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.163899074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.532263346 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 274719167 ps |
| CPU time | 2.16 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:41 PM UTC 24 |
| Peak memory | 215268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532263346 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.532263346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.895337953 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 230826010 ps |
| CPU time | 1.04 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:51 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =895337953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.895337953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.2335437637 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 38466130 ps |
| CPU time | 0.79 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:50 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335437637 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.2335437637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.4163894990 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 45699583 ps |
| CPU time | 0.73 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:50 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163894990 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.4163894990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3748414608 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 81445204 ps |
| CPU time | 1.03 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:51 PM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3748414608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3748414608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.3025092805 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 17612405 ps |
| CPU time | 0.95 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:51 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025092805 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3025092805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.3233465483 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 34948373 ps |
| CPU time | 0.9 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:51 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233465483 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3233465483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.873834493 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 48404435 ps |
| CPU time | 1.27 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:51 PM UTC 24 |
| Peak memory | 214676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873834493 -assert nopostproc +UVM_ TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_outstanding.873834493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.378812752 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 97052006 ps |
| CPU time | 1.34 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:51 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378812752 -assert nopostproc +UVM_TESTNAME=i2c_base_tes t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.378812752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2034961630 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 66704167 ps |
| CPU time | 1.14 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:51 PM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2034961630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.2034961630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.2263438337 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 31674184 ps |
| CPU time | 0.74 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:51 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263438337 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2263438337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.1932306584 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 17566265 ps |
| CPU time | 0.95 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:51 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932306584 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.1932306584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3734887039 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 39261954 ps |
| CPU time | 0.98 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:51 PM UTC 24 |
| Peak memory | 214740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734887039 -assert nopostproc +UVM _TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_outstanding.3734887039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.472417960 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 511062028 ps |
| CPU time | 2.61 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:53 PM UTC 24 |
| Peak memory | 215116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472417960 -assert nopostproc +UVM_TESTNAME=i2c_base_tes t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.472417960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.4223360529 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 1078809107 ps |
| CPU time | 1.43 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:52 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223360529 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.4223360529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.563168017 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 110525302 ps |
| CPU time | 0.86 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =563168017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.563168017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.1481536744 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 19518661 ps |
| CPU time | 0.86 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:51 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481536744 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1481536744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.1041033410 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 49577216 ps |
| CPU time | 0.77 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:51 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041033410 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1041033410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.386155414 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 19345592 ps |
| CPU time | 0.98 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:52 PM UTC 24 |
| Peak memory | 214740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386155414 -assert nopostproc +UVM_ TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_outstanding.386155414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.3804060628 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 481960206 ps |
| CPU time | 2.47 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:53 PM UTC 24 |
| Peak memory | 225108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804060628 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3804060628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.3413051982 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 105807482 ps |
| CPU time | 1.42 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:52 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413051982 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.3413051982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3132705036 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 33311133 ps |
| CPU time | 1.59 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3132705036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3132705036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.4151903631 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 42425318 ps |
| CPU time | 0.75 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151903631 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.4151903631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.839176167 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 18407526 ps |
| CPU time | 0.8 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839176167 -assert nopostproc +UVM_TESTNAME=i2c_base_tes t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.839176167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1316663451 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 23491138 ps |
| CPU time | 0.94 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316663451 -assert nopostproc +UVM _TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_outstanding.1316663451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.1385621519 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 136197884 ps |
| CPU time | 1.25 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385621519 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1385621519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.1282131220 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 87134146 ps |
| CPU time | 1.44 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282131220 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1282131220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.740438234 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 94456101 ps |
| CPU time | 1.22 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =740438234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.740438234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.1901743333 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 83748073 ps |
| CPU time | 0.89 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901743333 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1901743333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.2763846318 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 22592264 ps |
| CPU time | 0.78 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763846318 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2763846318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1748948112 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 100015081 ps |
| CPU time | 1.02 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748948112 -assert nopostproc +UVM _TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_outstanding.1748948112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.1849573948 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 165476343 ps |
| CPU time | 1.82 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:55 PM UTC 24 |
| Peak memory | 214648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849573948 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.1849573948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.2150151061 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 140276920 ps |
| CPU time | 1.46 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150151061 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2150151061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1580465325 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 78606460 ps |
| CPU time | 1.13 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1580465325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1580465325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.1991955592 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 43264960 ps |
| CPU time | 0.92 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991955592 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1991955592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.828903994 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 44415953 ps |
| CPU time | 0.94 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828903994 -assert nopostproc +UVM_TESTNAME=i2c_base_tes t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.828903994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1603710581 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 53919917 ps |
| CPU time | 1.31 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:55 PM UTC 24 |
| Peak memory | 214648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603710581 -assert nopostproc +UVM _TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_outstanding.1603710581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.3630645015 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 59524192 ps |
| CPU time | 1.17 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630645015 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.3630645015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2485720918 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 190706658 ps |
| CPU time | 0.87 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2485720918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.2485720918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.4164840155 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 21630050 ps |
| CPU time | 0.76 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164840155 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.4164840155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.1451605037 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 18241008 ps |
| CPU time | 0.73 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:54 PM UTC 24 |
| Peak memory | 214556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451605037 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1451605037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2592232822 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 32697627 ps |
| CPU time | 1.03 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:55 PM UTC 24 |
| Peak memory | 214740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592232822 -assert nopostproc +UVM _TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_outstanding.2592232822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.1612663228 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 649683732 ps |
| CPU time | 1.89 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:55 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612663228 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1612663228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.4133114355 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 59066032 ps |
| CPU time | 1.46 seconds |
| Started | Oct 02 07:05:52 PM UTC 24 |
| Finished | Oct 02 07:05:55 PM UTC 24 |
| Peak memory | 214656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133114355 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.4133114355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2175219439 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 136093748 ps |
| CPU time | 1.1 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2175219439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2175219439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.1287883157 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 18751227 ps |
| CPU time | 0.74 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287883157 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.1287883157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.2682868692 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 78709932 ps |
| CPU time | 0.68 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682868692 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2682868692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1928077124 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 36297747 ps |
| CPU time | 0.93 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928077124 -assert nopostproc +UVM _TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_outstanding.1928077124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.1364059839 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 353948860 ps |
| CPU time | 2.35 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:58 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364059839 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1364059839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.2431551131 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 80350290 ps |
| CPU time | 1.43 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431551131 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2431551131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3919823143 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 334236959 ps |
| CPU time | 1.24 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3919823143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3919823143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.4241662710 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 26383449 ps |
| CPU time | 0.96 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241662710 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.4241662710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.135879338 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 17098585 ps |
| CPU time | 0.72 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135879338 -assert nopostproc +UVM_TESTNAME=i2c_base_tes t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.135879338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.4053309742 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 26257367 ps |
| CPU time | 1.2 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053309742 -assert nopostproc +UVM _TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_outstanding.4053309742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.3819818368 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 152000163 ps |
| CPU time | 1.51 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:58 PM UTC 24 |
| Peak memory | 214648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819818368 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3819818368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.1973518629 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 236804546 ps |
| CPU time | 2.05 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:58 PM UTC 24 |
| Peak memory | 215236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973518629 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1973518629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.100910699 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 169904507 ps |
| CPU time | 1.27 seconds |
| Started | Oct 02 07:05:41 PM UTC 24 |
| Finished | Oct 02 07:05:43 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100910699 -assert nopostproc +UVM_TESTNAME=i2c _base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i 2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.100910699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.2174089047 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 191242516 ps |
| CPU time | 2.72 seconds |
| Started | Oct 02 07:05:39 PM UTC 24 |
| Finished | Oct 02 07:05:42 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174089047 -assert nopostproc +UVM_TESTNAME=i2 c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2174089047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.1934091779 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 57854611 ps |
| CPU time | 0.96 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:40 PM UTC 24 |
| Peak memory | 224472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934091779 -assert nopostproc +UVM_TESTNAME=i2 c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1934091779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3829779344 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 31843386 ps |
| CPU time | 0.98 seconds |
| Started | Oct 02 07:05:41 PM UTC 24 |
| Finished | Oct 02 07:05:43 PM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3829779344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3829779344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.22147051 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 46189401 ps |
| CPU time | 0.79 seconds |
| Started | Oct 02 07:05:38 PM UTC 24 |
| Finished | Oct 02 07:05:40 PM UTC 24 |
| Peak memory | 214328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22147051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.22147051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.3810708634 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 34998831 ps |
| CPU time | 0.73 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810708634 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3810708634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.2114818607 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 18277523 ps |
| CPU time | 0.75 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114818607 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.2114818607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.2387073337 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 18098497 ps |
| CPU time | 0.76 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387073337 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.2387073337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.3946501507 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 18904433 ps |
| CPU time | 0.91 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946501507 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3946501507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.518467351 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 22051284 ps |
| CPU time | 0.78 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518467351 -assert nopostproc +UVM_TESTNAME=i2c_base_tes t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.518467351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.1098478574 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 15965354 ps |
| CPU time | 0.77 seconds |
| Started | Oct 02 07:05:55 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098478574 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1098478574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.1825310382 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 18381498 ps |
| CPU time | 0.8 seconds |
| Started | Oct 02 07:05:56 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825310382 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1825310382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.1560472593 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 18212699 ps |
| CPU time | 0.76 seconds |
| Started | Oct 02 07:05:56 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560472593 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.1560472593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.2683118000 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 32872488 ps |
| CPU time | 0.82 seconds |
| Started | Oct 02 07:05:56 PM UTC 24 |
| Finished | Oct 02 07:05:57 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683118000 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2683118000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.1502566432 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 143429967 ps |
| CPU time | 0.77 seconds |
| Started | Oct 02 07:05:56 PM UTC 24 |
| Finished | Oct 02 07:05:58 PM UTC 24 |
| Peak memory | 214320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502566432 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1502566432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.3445398821 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 241158624 ps |
| CPU time | 1.42 seconds |
| Started | Oct 02 07:05:41 PM UTC 24 |
| Finished | Oct 02 07:05:44 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445398821 -assert nopostproc +UVM_TESTNAME=i2 c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3445398821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.1107446232 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 69183709 ps |
| CPU time | 2.56 seconds |
| Started | Oct 02 07:05:41 PM UTC 24 |
| Finished | Oct 02 07:05:45 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107446232 -assert nopostproc +UVM_TESTNAME=i2 c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1107446232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.1295018185 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 35650188 ps |
| CPU time | 0.99 seconds |
| Started | Oct 02 07:05:41 PM UTC 24 |
| Finished | Oct 02 07:05:43 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295018185 -assert nopostproc +UVM_TESTNAME=i2 c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1295018185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3159702049 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 325990788 ps |
| CPU time | 0.98 seconds |
| Started | Oct 02 07:05:42 PM UTC 24 |
| Finished | Oct 02 07:05:44 PM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3159702049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3159702049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.1648084839 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 47146076 ps |
| CPU time | 0.85 seconds |
| Started | Oct 02 07:05:41 PM UTC 24 |
| Finished | Oct 02 07:05:43 PM UTC 24 |
| Peak memory | 214676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648084839 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1648084839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1345821168 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 116830584 ps |
| CPU time | 0.82 seconds |
| Started | Oct 02 07:05:42 PM UTC 24 |
| Finished | Oct 02 07:05:43 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345821168 -assert nopostproc +UVM _TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_outstanding.1345821168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.1278533724 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 33392235 ps |
| CPU time | 1.68 seconds |
| Started | Oct 02 07:05:41 PM UTC 24 |
| Finished | Oct 02 07:05:44 PM UTC 24 |
| Peak memory | 224604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278533724 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1278533724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.3093617740 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 89677507 ps |
| CPU time | 2.2 seconds |
| Started | Oct 02 07:05:41 PM UTC 24 |
| Finished | Oct 02 07:05:44 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093617740 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3093617740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.2375795587 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 31250824 ps |
| CPU time | 0.86 seconds |
| Started | Oct 02 07:05:56 PM UTC 24 |
| Finished | Oct 02 07:05:58 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375795587 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2375795587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.2805187407 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 32377704 ps |
| CPU time | 0.78 seconds |
| Started | Oct 02 07:05:56 PM UTC 24 |
| Finished | Oct 02 07:05:58 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805187407 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2805187407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.442545203 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 17656441 ps |
| CPU time | 0.79 seconds |
| Started | Oct 02 07:05:56 PM UTC 24 |
| Finished | Oct 02 07:05:58 PM UTC 24 |
| Peak memory | 214552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442545203 -assert nopostproc +UVM_TESTNAME=i2c_base_tes t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.442545203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.1006073165 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 22679823 ps |
| CPU time | 0.78 seconds |
| Started | Oct 02 07:05:56 PM UTC 24 |
| Finished | Oct 02 07:05:58 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006073165 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1006073165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.2678084779 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 17678641 ps |
| CPU time | 0.78 seconds |
| Started | Oct 02 07:05:58 PM UTC 24 |
| Finished | Oct 02 07:06:00 PM UTC 24 |
| Peak memory | 214556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678084779 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2678084779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.1778187563 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 35346077 ps |
| CPU time | 0.71 seconds |
| Started | Oct 02 07:05:58 PM UTC 24 |
| Finished | Oct 02 07:06:00 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778187563 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1778187563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.2934922783 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 49926589 ps |
| CPU time | 0.77 seconds |
| Started | Oct 02 07:05:58 PM UTC 24 |
| Finished | Oct 02 07:06:00 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934922783 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.2934922783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.260504523 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 19989852 ps |
| CPU time | 0.75 seconds |
| Started | Oct 02 07:05:58 PM UTC 24 |
| Finished | Oct 02 07:06:00 PM UTC 24 |
| Peak memory | 214552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260504523 -assert nopostproc +UVM_TESTNAME=i2c_base_tes t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.260504523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.553462702 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 126523060 ps |
| CPU time | 0.71 seconds |
| Started | Oct 02 07:05:58 PM UTC 24 |
| Finished | Oct 02 07:06:00 PM UTC 24 |
| Peak memory | 214552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553462702 -assert nopostproc +UVM_TESTNAME=i2c_base_tes t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.553462702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.3145345791 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 40949046 ps |
| CPU time | 0.71 seconds |
| Started | Oct 02 07:05:58 PM UTC 24 |
| Finished | Oct 02 07:06:00 PM UTC 24 |
| Peak memory | 213752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145345791 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3145345791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.2814585283 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 39244526 ps |
| CPU time | 1.72 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:48 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814585283 -assert nopostproc +UVM_TESTNAME=i2 c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2814585283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.4193929369 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 10194648875 ps |
| CPU time | 4.9 seconds |
| Started | Oct 02 07:05:42 PM UTC 24 |
| Finished | Oct 02 07:05:48 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193929369 -assert nopostproc +UVM_TESTNAME=i2 c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.4193929369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.3996695097 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 22852570 ps |
| CPU time | 0.85 seconds |
| Started | Oct 02 07:05:42 PM UTC 24 |
| Finished | Oct 02 07:05:44 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996695097 -assert nopostproc +UVM_TESTNAME=i2 c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3996695097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.994383845 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 37999470 ps |
| CPU time | 1.76 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:48 PM UTC 24 |
| Peak memory | 224640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =994383845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.994383845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.290993171 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 25489445 ps |
| CPU time | 1 seconds |
| Started | Oct 02 07:05:42 PM UTC 24 |
| Finished | Oct 02 07:05:44 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290993171 -assert nopostproc +UVM_TESTNAME=i2c_base_ test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.290993171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.2879342528 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 24918148 ps |
| CPU time | 0.72 seconds |
| Started | Oct 02 07:05:42 PM UTC 24 |
| Finished | Oct 02 07:05:43 PM UTC 24 |
| Peak memory | 214612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879342528 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.2879342528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3698051030 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 77662874 ps |
| CPU time | 1.37 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:47 PM UTC 24 |
| Peak memory | 214648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698051030 -assert nopostproc +UVM _TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_outstanding.3698051030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.3525647040 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 73074895 ps |
| CPU time | 2.14 seconds |
| Started | Oct 02 07:05:42 PM UTC 24 |
| Finished | Oct 02 07:05:45 PM UTC 24 |
| Peak memory | 225408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525647040 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3525647040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.3114681876 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 118917914 ps |
| CPU time | 2.29 seconds |
| Started | Oct 02 07:05:42 PM UTC 24 |
| Finished | Oct 02 07:05:45 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114681876 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3114681876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.2729732357 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 49434798 ps |
| CPU time | 0.72 seconds |
| Started | Oct 02 07:05:58 PM UTC 24 |
| Finished | Oct 02 07:06:00 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729732357 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2729732357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.1561022802 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 15379864 ps |
| CPU time | 0.82 seconds |
| Started | Oct 02 07:05:58 PM UTC 24 |
| Finished | Oct 02 07:06:00 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561022802 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1561022802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.877899576 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 22868667 ps |
| CPU time | 0.79 seconds |
| Started | Oct 02 07:05:58 PM UTC 24 |
| Finished | Oct 02 07:06:00 PM UTC 24 |
| Peak memory | 214552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877899576 -assert nopostproc +UVM_TESTNAME=i2c_base_tes t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.877899576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.3292846706 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 17988160 ps |
| CPU time | 0.78 seconds |
| Started | Oct 02 07:05:58 PM UTC 24 |
| Finished | Oct 02 07:06:00 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292846706 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3292846706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.2713872489 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 18903501 ps |
| CPU time | 0.76 seconds |
| Started | Oct 02 07:05:58 PM UTC 24 |
| Finished | Oct 02 07:06:00 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713872489 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2713872489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.3175451970 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 40753463 ps |
| CPU time | 0.82 seconds |
| Started | Oct 02 07:05:58 PM UTC 24 |
| Finished | Oct 02 07:06:00 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175451970 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.3175451970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.3941566711 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 28243402 ps |
| CPU time | 0.68 seconds |
| Started | Oct 02 07:05:58 PM UTC 24 |
| Finished | Oct 02 07:06:00 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941566711 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.3941566711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.1431217457 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 85126126 ps |
| CPU time | 0.75 seconds |
| Started | Oct 02 07:05:58 PM UTC 24 |
| Finished | Oct 02 07:06:00 PM UTC 24 |
| Peak memory | 214556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431217457 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1431217457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.3738473608 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 20299699 ps |
| CPU time | 0.77 seconds |
| Started | Oct 02 07:05:58 PM UTC 24 |
| Finished | Oct 02 07:06:00 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738473608 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3738473608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.2813905002 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 22795706 ps |
| CPU time | 0.76 seconds |
| Started | Oct 02 07:05:58 PM UTC 24 |
| Finished | Oct 02 07:06:00 PM UTC 24 |
| Peak memory | 214556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813905002 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2813905002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.4221898323 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 125903268 ps |
| CPU time | 1 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:47 PM UTC 24 |
| Peak memory | 214808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4221898323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.4221898323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.3925462710 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 23275842 ps |
| CPU time | 0.77 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:47 PM UTC 24 |
| Peak memory | 214636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925462710 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3925462710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.3066787704 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 17094711 ps |
| CPU time | 0.72 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:47 PM UTC 24 |
| Peak memory | 214568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066787704 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3066787704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3128647712 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 62714732 ps |
| CPU time | 0.93 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:47 PM UTC 24 |
| Peak memory | 214680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128647712 -assert nopostproc +UVM _TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_outstanding.3128647712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.1448557180 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 96963992 ps |
| CPU time | 1.78 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:48 PM UTC 24 |
| Peak memory | 214644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448557180 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.1448557180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.2876091367 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 77817288 ps |
| CPU time | 1.48 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:48 PM UTC 24 |
| Peak memory | 214528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876091367 -assert nopostproc +UVM_TESTNAME =i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.2876091367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3091005741 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 25127071 ps |
| CPU time | 1.05 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:47 PM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3091005741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3091005741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.2580522468 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 17580412 ps |
| CPU time | 1.02 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:47 PM UTC 24 |
| Peak memory | 214676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580522468 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2580522468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.555862135 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 16621500 ps |
| CPU time | 0.68 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:47 PM UTC 24 |
| Peak memory | 214556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555862135 -assert nopostproc +UVM_TESTNAME=i2c_base_tes t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.555862135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1866915550 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 26194389 ps |
| CPU time | 1.03 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:47 PM UTC 24 |
| Peak memory | 214648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866915550 -assert nopostproc +UVM _TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_outstanding.1866915550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.1442365726 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 184524937 ps |
| CPU time | 1.7 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:48 PM UTC 24 |
| Peak memory | 214644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442365726 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1442365726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.4123237166 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 42601675 ps |
| CPU time | 0.84 seconds |
| Started | Oct 02 07:05:46 PM UTC 24 |
| Finished | Oct 02 07:05:47 PM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4123237166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.4123237166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.3167847570 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 40148859 ps |
| CPU time | 0.98 seconds |
| Started | Oct 02 07:05:46 PM UTC 24 |
| Finished | Oct 02 07:05:47 PM UTC 24 |
| Peak memory | 214676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167847570 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3167847570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.3796701232 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 67644680 ps |
| CPU time | 0.78 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:47 PM UTC 24 |
| Peak memory | 214612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796701232 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.3796701232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.665537426 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 32358727 ps |
| CPU time | 0.97 seconds |
| Started | Oct 02 07:05:46 PM UTC 24 |
| Finished | Oct 02 07:05:48 PM UTC 24 |
| Peak memory | 214744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665537426 -assert nopostproc +UVM_ TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_outstanding.665537426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.3549345940 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 96160352 ps |
| CPU time | 1.7 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:48 PM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549345940 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3549345940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.348343306 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 150722034 ps |
| CPU time | 2.43 seconds |
| Started | Oct 02 07:05:45 PM UTC 24 |
| Finished | Oct 02 07:05:49 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348343306 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.348343306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2370752252 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 24483060 ps |
| CPU time | 1.18 seconds |
| Started | Oct 02 07:05:46 PM UTC 24 |
| Finished | Oct 02 07:05:48 PM UTC 24 |
| Peak memory | 214692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2370752252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2370752252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.1852403117 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 44716405 ps |
| CPU time | 0.75 seconds |
| Started | Oct 02 07:05:46 PM UTC 24 |
| Finished | Oct 02 07:05:47 PM UTC 24 |
| Peak memory | 214676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852403117 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1852403117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.1048432412 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 38022853 ps |
| CPU time | 0.7 seconds |
| Started | Oct 02 07:05:46 PM UTC 24 |
| Finished | Oct 02 07:05:48 PM UTC 24 |
| Peak memory | 214612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048432412 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1048432412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2764213457 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 80897247 ps |
| CPU time | 1.11 seconds |
| Started | Oct 02 07:05:46 PM UTC 24 |
| Finished | Oct 02 07:05:48 PM UTC 24 |
| Peak memory | 214696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764213457 -assert nopostproc +UVM _TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_outstanding.2764213457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.498627824 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 335875822 ps |
| CPU time | 2.63 seconds |
| Started | Oct 02 07:05:46 PM UTC 24 |
| Finished | Oct 02 07:05:49 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498627824 -assert nopostproc +UVM_TESTNAME=i2c_base_tes t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.498627824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.442182566 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 192903974 ps |
| CPU time | 1.54 seconds |
| Started | Oct 02 07:05:46 PM UTC 24 |
| Finished | Oct 02 07:05:48 PM UTC 24 |
| Peak memory | 214624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442182566 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.442182566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.147355102 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 28104063 ps |
| CPU time | 0.88 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:50 PM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =147355102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.147355102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.3400937574 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 22947189 ps |
| CPU time | 0.65 seconds |
| Started | Oct 02 07:05:48 PM UTC 24 |
| Finished | Oct 02 07:05:50 PM UTC 24 |
| Peak memory | 214676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400937574 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.3400937574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.2834697437 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 48019839 ps |
| CPU time | 0.67 seconds |
| Started | Oct 02 07:05:48 PM UTC 24 |
| Finished | Oct 02 07:05:50 PM UTC 24 |
| Peak memory | 214612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834697437 -assert nopostproc +UVM_TESTNAME=i2c_base_te st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2834697437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1310495709 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 53914646 ps |
| CPU time | 1.25 seconds |
| Started | Oct 02 07:05:49 PM UTC 24 |
| Finished | Oct 02 07:05:51 PM UTC 24 |
| Peak memory | 214688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310495709 -assert nopostproc +UVM _TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_outstanding.1310495709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.678474277 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 126468424 ps |
| CPU time | 2.27 seconds |
| Started | Oct 02 07:05:48 PM UTC 24 |
| Finished | Oct 02 07:05:52 PM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678474277 -assert nopostproc +UVM_TESTNAME=i2c_base_tes t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.678474277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.183182382 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 247186263 ps |
| CPU time | 1.55 seconds |
| Started | Oct 02 07:05:48 PM UTC 24 |
| Finished | Oct 02 07:05:51 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183182382 -assert nopostproc +UVM_TESTNAME= i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.183182382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_error_intr.4183636140 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 134718253 ps |
| CPU time | 2.22 seconds |
| Started | Oct 02 08:19:12 PM UTC 24 |
| Finished | Oct 02 08:19:15 PM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183636140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.4183636140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_fmt_empty.1091979822 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 251697373 ps |
| CPU time | 4.85 seconds |
| Started | Oct 02 08:18:36 PM UTC 24 |
| Finished | Oct 02 08:18:42 PM UTC 24 |
| Peak memory | 246500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091979822 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty.1091979822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_full.2839522041 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3908309254 ps |
| CPU time | 174.5 seconds |
| Started | Oct 02 08:18:43 PM UTC 24 |
| Finished | Oct 02 08:21:41 PM UTC 24 |
| Peak memory | 858904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839522041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.2839522041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_rx.2142313328 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1499244504 ps |
| CPU time | 7.63 seconds |
| Started | Oct 02 08:18:40 PM UTC 24 |
| Finished | Oct 02 08:18:49 PM UTC 24 |
| Peak memory | 215448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142313328 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.2142313328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_may_nack.1627304903 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 610369583 ps |
| CPU time | 5.69 seconds |
| Started | Oct 02 08:19:59 PM UTC 24 |
| Finished | Oct 02 08:20:06 PM UTC 24 |
| Peak memory | 215180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627304903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.1627304903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_override.3859210543 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 93270668 ps |
| CPU time | 1.09 seconds |
| Started | Oct 02 08:18:31 PM UTC 24 |
| Finished | Oct 02 08:18:33 PM UTC 24 |
| Peak memory | 214260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859210543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3859210543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_perf.3120454559 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 6474696082 ps |
| CPU time | 20.16 seconds |
| Started | Oct 02 08:18:49 PM UTC 24 |
| Finished | Oct 02 08:19:11 PM UTC 24 |
| Peak memory | 326504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120454559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3120454559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_perf_precise.3114096106 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 248525913 ps |
| CPU time | 4.98 seconds |
| Started | Oct 02 08:18:57 PM UTC 24 |
| Finished | Oct 02 08:19:03 PM UTC 24 |
| Peak memory | 225372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114096106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.3114096106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_host_stretch_timeout.2580313826 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9638131140 ps |
| CPU time | 15.38 seconds |
| Started | Oct 02 08:19:04 PM UTC 24 |
| Finished | Oct 02 08:19:20 PM UTC 24 |
| Peak memory | 232416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580313826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.2580313826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_acq.2787648562 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 162252049 ps |
| CPU time | 1.74 seconds |
| Started | Oct 02 08:19:50 PM UTC 24 |
| Finished | Oct 02 08:19:52 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787648 562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_acq.2787648562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_tx.3597568931 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 590816692 ps |
| CPU time | 2.09 seconds |
| Started | Oct 02 08:19:51 PM UTC 24 |
| Finished | Oct 02 08:19:54 PM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597568 931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_tx.3597568931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_tx.3493264647 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 451024804 ps |
| CPU time | 2.05 seconds |
| Started | Oct 02 08:20:01 PM UTC 24 |
| Finished | Oct 02 08:20:04 PM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493264 647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_watermarks _tx.3493264647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_hrst.2897150654 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 780967399 ps |
| CPU time | 3.43 seconds |
| Started | Oct 02 08:19:55 PM UTC 24 |
| Finished | Oct 02 08:20:00 PM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897150 654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_hrst.2897150654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_intr_smoke.1493540130 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2260836048 ps |
| CPU time | 11.56 seconds |
| Started | Oct 02 08:19:37 PM UTC 24 |
| Finished | Oct 02 08:19:50 PM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149354 0130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_smoke.1493540130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_intr_stress_wr.3833390283 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 8267848626 ps |
| CPU time | 39.53 seconds |
| Started | Oct 02 08:19:43 PM UTC 24 |
| Finished | Oct 02 08:20:25 PM UTC 24 |
| Peak memory | 1096676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3833390283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_stress _wr.3833390283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull.2054006824 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1352762876 ps |
| CPU time | 4.85 seconds |
| Started | Oct 02 08:20:06 PM UTC 24 |
| Finished | Oct 02 08:20:11 PM UTC 24 |
| Peak memory | 225704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054006 824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_acqfull.2054006824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_perf.1695452100 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 410713002 ps |
| CPU time | 5.1 seconds |
| Started | Oct 02 08:19:51 PM UTC 24 |
| Finished | Oct 02 08:19:57 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695452 100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_perf.1695452100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_smbus_maxlen.3106794640 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 912080534 ps |
| CPU time | 4.3 seconds |
| Started | Oct 02 08:20:05 PM UTC 24 |
| Finished | Oct 02 08:20:11 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106794 640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smbus_maxlen.3106794640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_smoke.3347217829 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 741582713 ps |
| CPU time | 10.87 seconds |
| Started | Oct 02 08:19:22 PM UTC 24 |
| Finished | Oct 02 08:19:35 PM UTC 24 |
| Peak memory | 217308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347217829 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smoke.3347217829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_stress_rd.2795925134 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1248426163 ps |
| CPU time | 11.25 seconds |
| Started | Oct 02 08:19:36 PM UTC 24 |
| Finished | Oct 02 08:19:48 PM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795925134 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_rd.2795925134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_stress_wr.1457837465 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 72970022483 ps |
| CPU time | 956.11 seconds |
| Started | Oct 02 08:19:22 PM UTC 24 |
| Finished | Oct 02 08:35:29 PM UTC 24 |
| Peak memory | 9337768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457837465 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_wr.1457837465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/0.i2c_target_timeout.1407455215 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1063362192 ps |
| CPU time | 10.18 seconds |
| Started | Oct 02 08:19:46 PM UTC 24 |
| Finished | Oct 02 08:19:58 PM UTC 24 |
| Peak memory | 232424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407455 215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_timeout.1407455215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_alert_test.3002373751 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 19520551 ps |
| CPU time | 0.92 seconds |
| Started | Oct 02 08:21:38 PM UTC 24 |
| Finished | Oct 02 08:21:40 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002373751 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.3002373751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_fmt_empty.206640321 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 970360818 ps |
| CPU time | 23.94 seconds |
| Started | Oct 02 08:20:15 PM UTC 24 |
| Finished | Oct 02 08:20:40 PM UTC 24 |
| Peak memory | 306012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206640321 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty.206640321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_full.1087734404 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11591894632 ps |
| CPU time | 108.72 seconds |
| Started | Oct 02 08:20:19 PM UTC 24 |
| Finished | Oct 02 08:22:10 PM UTC 24 |
| Peak memory | 709544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087734404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.1087734404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_overflow.1917415271 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1782372660 ps |
| CPU time | 46.82 seconds |
| Started | Oct 02 08:20:13 PM UTC 24 |
| Finished | Oct 02 08:21:01 PM UTC 24 |
| Peak memory | 576168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917415271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.1917415271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_fmt.332581459 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 83136558 ps |
| CPU time | 1.19 seconds |
| Started | Oct 02 08:20:13 PM UTC 24 |
| Finished | Oct 02 08:20:15 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332581459 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt.332581459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_rx.2658606450 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 172579964 ps |
| CPU time | 5.66 seconds |
| Started | Oct 02 08:20:16 PM UTC 24 |
| Finished | Oct 02 08:20:23 PM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658606450 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.2658606450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_watermark.554741435 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 5103766565 ps |
| CPU time | 315.63 seconds |
| Started | Oct 02 08:20:13 PM UTC 24 |
| Finished | Oct 02 08:25:33 PM UTC 24 |
| Peak memory | 1442580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554741435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.554741435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_may_nack.4002570119 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 656371032 ps |
| CPU time | 26.36 seconds |
| Started | Oct 02 08:21:20 PM UTC 24 |
| Finished | Oct 02 08:21:48 PM UTC 24 |
| Peak memory | 215448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002570119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.4002570119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_perf.3523674614 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 27057571302 ps |
| CPU time | 80.16 seconds |
| Started | Oct 02 08:20:22 PM UTC 24 |
| Finished | Oct 02 08:21:45 PM UTC 24 |
| Peak memory | 215312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523674614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.3523674614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_perf_precise.4144383991 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 23213860342 ps |
| CPU time | 2100.09 seconds |
| Started | Oct 02 08:20:23 PM UTC 24 |
| Finished | Oct 02 08:55:44 PM UTC 24 |
| Peak memory | 3734240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144383991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.4144383991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_smoke.2856510188 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2021285714 ps |
| CPU time | 117.13 seconds |
| Started | Oct 02 08:20:12 PM UTC 24 |
| Finished | Oct 02 08:22:11 PM UTC 24 |
| Peak memory | 363240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856510188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2856510188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_host_stretch_timeout.3356387833 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3072889682 ps |
| CPU time | 38.73 seconds |
| Started | Oct 02 08:20:25 PM UTC 24 |
| Finished | Oct 02 08:21:05 PM UTC 24 |
| Peak memory | 225772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356387833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.3356387833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_sec_cm.2565424453 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 190173134 ps |
| CPU time | 1.34 seconds |
| Started | Oct 02 08:21:38 PM UTC 24 |
| Finished | Oct 02 08:21:41 PM UTC 24 |
| Peak memory | 244508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565424453 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2565424453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_bad_addr.2866156872 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 17118911895 ps |
| CPU time | 9.01 seconds |
| Started | Oct 02 08:21:10 PM UTC 24 |
| Finished | Oct 02 08:21:20 PM UTC 24 |
| Peak memory | 232304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2866156872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.2866156872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_acq.2702653911 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 233774376 ps |
| CPU time | 2.59 seconds |
| Started | Oct 02 08:21:06 PM UTC 24 |
| Finished | Oct 02 08:21:10 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702653 911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_acq.2702653911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_tx.1131563616 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 151947847 ps |
| CPU time | 1.67 seconds |
| Started | Oct 02 08:21:06 PM UTC 24 |
| Finished | Oct 02 08:21:09 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131563 616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_tx.1131563616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_acq.4176014834 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 855947130 ps |
| CPU time | 5.61 seconds |
| Started | Oct 02 08:21:24 PM UTC 24 |
| Finished | Oct 02 08:21:30 PM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176014 834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_watermark s_acq.4176014834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_tx.2222934752 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 443408074 ps |
| CPU time | 1.6 seconds |
| Started | Oct 02 08:21:24 PM UTC 24 |
| Finished | Oct 02 08:21:26 PM UTC 24 |
| Peak memory | 214784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222934 752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_watermarks _tx.2222934752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_glitch.3635757911 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2107207931 ps |
| CPU time | 19.82 seconds |
| Started | Oct 02 08:20:34 PM UTC 24 |
| Finished | Oct 02 08:20:55 PM UTC 24 |
| Peak memory | 225952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635757911 -assert nopostproc +UVM_TESTNAME=i 2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.3635757911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_hrst.1017880887 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 643777932 ps |
| CPU time | 3.9 seconds |
| Started | Oct 02 08:21:14 PM UTC 24 |
| Finished | Oct 02 08:21:19 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017880 887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_hrst.1017880887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_intr_smoke.1556064920 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1799084097 ps |
| CPU time | 8.1 seconds |
| Started | Oct 02 08:20:55 PM UTC 24 |
| Finished | Oct 02 08:21:05 PM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155606 4920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_smoke.1556064920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_intr_stress_wr.3384049637 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 27221868712 ps |
| CPU time | 188.64 seconds |
| Started | Oct 02 08:20:57 PM UTC 24 |
| Finished | Oct 02 08:24:08 PM UTC 24 |
| Peak memory | 2810856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3384049637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_stress _wr.3384049637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull.2339295110 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 885274263 ps |
| CPU time | 5.7 seconds |
| Started | Oct 02 08:21:31 PM UTC 24 |
| Finished | Oct 02 08:21:38 PM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339295 110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_acqfull.2339295110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull_addr.2516193114 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2250163361 ps |
| CPU time | 3.38 seconds |
| Started | Oct 02 08:21:33 PM UTC 24 |
| Finished | Oct 02 08:21:38 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516193 114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.2516193114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_perf.568463531 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1089620519 ps |
| CPU time | 6.77 seconds |
| Started | Oct 02 08:21:07 PM UTC 24 |
| Finished | Oct 02 08:21:15 PM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5684635 31 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_perf.568463531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_smbus_maxlen.1378968796 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 7934588816 ps |
| CPU time | 3.91 seconds |
| Started | Oct 02 08:21:27 PM UTC 24 |
| Finished | Oct 02 08:21:32 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378968 796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smbus_maxlen.1378968796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_smoke.1039185150 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 812200581 ps |
| CPU time | 15.2 seconds |
| Started | Oct 02 08:20:34 PM UTC 24 |
| Finished | Oct 02 08:20:50 PM UTC 24 |
| Peak memory | 225768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039185150 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smoke.1039185150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_stress_all.2175964361 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 52896452408 ps |
| CPU time | 122.68 seconds |
| Started | Oct 02 08:21:10 PM UTC 24 |
| Finished | Oct 02 08:23:15 PM UTC 24 |
| Peak memory | 1381152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217596 4361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_all.2175964361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_stress_rd.2493538935 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 3433726148 ps |
| CPU time | 41.55 seconds |
| Started | Oct 02 08:20:51 PM UTC 24 |
| Finished | Oct 02 08:21:35 PM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493538935 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_rd.2493538935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_stress_wr.3202883554 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 41367296537 ps |
| CPU time | 399.78 seconds |
| Started | Oct 02 08:20:41 PM UTC 24 |
| Finished | Oct 02 08:27:26 PM UTC 24 |
| Peak memory | 5219368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202883554 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_wr.3202883554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_stretch.2247383360 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 547134210 ps |
| CPU time | 7.04 seconds |
| Started | Oct 02 08:20:54 PM UTC 24 |
| Finished | Oct 02 08:21:03 PM UTC 24 |
| Peak memory | 226100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247383360 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stretch.2247383360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/1.i2c_target_timeout.3851787890 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 4387696926 ps |
| CPU time | 10.77 seconds |
| Started | Oct 02 08:21:02 PM UTC 24 |
| Finished | Oct 02 08:21:14 PM UTC 24 |
| Peak memory | 244580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851787 890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_timeout.3851787890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_alert_test.2949397779 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 37693949 ps |
| CPU time | 0.89 seconds |
| Started | Oct 02 08:32:32 PM UTC 24 |
| Finished | Oct 02 08:32:34 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949397779 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.2949397779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_fmt_empty.1649640371 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 465601135 ps |
| CPU time | 10.16 seconds |
| Started | Oct 02 08:31:39 PM UTC 24 |
| Finished | Oct 02 08:31:50 PM UTC 24 |
| Peak memory | 322280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649640371 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empty.1649640371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_full.2399055778 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2712942318 ps |
| CPU time | 69.66 seconds |
| Started | Oct 02 08:31:41 PM UTC 24 |
| Finished | Oct 02 08:32:52 PM UTC 24 |
| Peak memory | 642020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399055778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2399055778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_overflow.2207717929 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 2560294122 ps |
| CPU time | 84.32 seconds |
| Started | Oct 02 08:31:37 PM UTC 24 |
| Finished | Oct 02 08:33:04 PM UTC 24 |
| Peak memory | 838448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207717929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.2207717929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_fmt.1890992992 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 285006144 ps |
| CPU time | 1.26 seconds |
| Started | Oct 02 08:31:38 PM UTC 24 |
| Finished | Oct 02 08:31:40 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890992992 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fmt.1890992992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_rx.2073871940 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 199008828 ps |
| CPU time | 5.22 seconds |
| Started | Oct 02 08:31:39 PM UTC 24 |
| Finished | Oct 02 08:31:45 PM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073871940 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.2073871940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_override.1064408345 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 110477457 ps |
| CPU time | 0.96 seconds |
| Started | Oct 02 08:31:28 PM UTC 24 |
| Finished | Oct 02 08:31:30 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064408345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.1064408345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_perf.620676524 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 29441055745 ps |
| CPU time | 1113.16 seconds |
| Started | Oct 02 08:31:44 PM UTC 24 |
| Finished | Oct 02 08:50:31 PM UTC 24 |
| Peak memory | 369516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620676524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.620676524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_perf_precise.1781091039 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 865997378 ps |
| CPU time | 35.46 seconds |
| Started | Oct 02 08:31:45 PM UTC 24 |
| Finished | Oct 02 08:32:22 PM UTC 24 |
| Peak memory | 215180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781091039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.1781091039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_smoke.845950506 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 15391284116 ps |
| CPU time | 48.71 seconds |
| Started | Oct 02 08:31:28 PM UTC 24 |
| Finished | Oct 02 08:32:19 PM UTC 24 |
| Peak memory | 326424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845950506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.845950506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_host_stretch_timeout.3398880521 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1816863552 ps |
| CPU time | 26.19 seconds |
| Started | Oct 02 08:31:46 PM UTC 24 |
| Finished | Oct 02 08:32:14 PM UTC 24 |
| Peak memory | 225244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398880521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.3398880521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_bad_addr.3199415521 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 4405657578 ps |
| CPU time | 8.45 seconds |
| Started | Oct 02 08:32:22 PM UTC 24 |
| Finished | Oct 02 08:32:32 PM UTC 24 |
| Peak memory | 232304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3199415521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_ad dr.3199415521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_acq.1693363085 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 267952002 ps |
| CPU time | 2.37 seconds |
| Started | Oct 02 08:32:18 PM UTC 24 |
| Finished | Oct 02 08:32:22 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693363 085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_acq.1693363085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_tx.3463315155 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 284676830 ps |
| CPU time | 1.33 seconds |
| Started | Oct 02 08:32:19 PM UTC 24 |
| Finished | Oct 02 08:32:22 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463315 155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_tx.3463315155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_acq.4224387269 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 943149140 ps |
| CPU time | 2.68 seconds |
| Started | Oct 02 08:32:27 PM UTC 24 |
| Finished | Oct 02 08:32:30 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224387 269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_watermar ks_acq.4224387269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_tx.1898041244 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 167537569 ps |
| CPU time | 2.27 seconds |
| Started | Oct 02 08:32:27 PM UTC 24 |
| Finished | Oct 02 08:32:30 PM UTC 24 |
| Peak memory | 215240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898041 244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_watermark s_tx.1898041244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_hrst.4201029153 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1081751869 ps |
| CPU time | 3.43 seconds |
| Started | Oct 02 08:32:22 PM UTC 24 |
| Finished | Oct 02 08:32:27 PM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201029 153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_hrst.4201029153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_intr_smoke.408378088 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 837482050 ps |
| CPU time | 7.57 seconds |
| Started | Oct 02 08:32:10 PM UTC 24 |
| Finished | Oct 02 08:32:18 PM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408378 088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_smoke.408378088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_intr_stress_wr.2815376424 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 11550194236 ps |
| CPU time | 19.91 seconds |
| Started | Oct 02 08:32:10 PM UTC 24 |
| Finished | Oct 02 08:32:31 PM UTC 24 |
| Peak memory | 361240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2815376424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_stres s_wr.2815376424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull.2404552267 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1226042389 ps |
| CPU time | 3.87 seconds |
| Started | Oct 02 08:32:29 PM UTC 24 |
| Finished | Oct 02 08:32:34 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404552 267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_acqfull.2404552267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull_addr.3842640368 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 1086866182 ps |
| CPU time | 3.58 seconds |
| Started | Oct 02 08:32:31 PM UTC 24 |
| Finished | Oct 02 08:32:36 PM UTC 24 |
| Peak memory | 214804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842640 368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_acqfull_ad dr.3842640368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_nack_txstretch.1802745027 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 261875350 ps |
| CPU time | 1.57 seconds |
| Started | Oct 02 08:32:31 PM UTC 24 |
| Finished | Oct 02 08:32:33 PM UTC 24 |
| Peak memory | 231120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802745 027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_txstretch.1802745027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_perf.1438049884 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 424641558 ps |
| CPU time | 4.09 seconds |
| Started | Oct 02 08:32:20 PM UTC 24 |
| Finished | Oct 02 08:32:25 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438049 884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_perf.1438049884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_smbus_maxlen.598328722 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1970595342 ps |
| CPU time | 4.61 seconds |
| Started | Oct 02 08:32:28 PM UTC 24 |
| Finished | Oct 02 08:32:33 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5983287 22 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smbus_maxlen.598328722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_smoke.1073353403 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 759195115 ps |
| CPU time | 26.21 seconds |
| Started | Oct 02 08:32:04 PM UTC 24 |
| Finished | Oct 02 08:32:32 PM UTC 24 |
| Peak memory | 225768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073353403 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smoke.1073353403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_stress_all.3274143596 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 28489174614 ps |
| CPU time | 72.16 seconds |
| Started | Oct 02 08:32:21 PM UTC 24 |
| Finished | Oct 02 08:33:35 PM UTC 24 |
| Peak memory | 353324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327414 3596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_all.3274143596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_stress_wr.2900929056 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 50005076816 ps |
| CPU time | 319.41 seconds |
| Started | Oct 02 08:32:09 PM UTC 24 |
| Finished | Oct 02 08:37:33 PM UTC 24 |
| Peak memory | 3730400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900929056 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_wr.2900929056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_stretch.1955180419 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2622191104 ps |
| CPU time | 24.72 seconds |
| Started | Oct 02 08:32:10 PM UTC 24 |
| Finished | Oct 02 08:32:36 PM UTC 24 |
| Peak memory | 301996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955180419 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stretch.1955180419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_timeout.2452366538 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 6068534387 ps |
| CPU time | 13.74 seconds |
| Started | Oct 02 08:32:10 PM UTC 24 |
| Finished | Oct 02 08:32:25 PM UTC 24 |
| Peak memory | 232376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452366 538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_timeout.2452366538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/10.i2c_target_tx_stretch_ctrl.337359343 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 127808564 ps |
| CPU time | 4.4 seconds |
| Started | Oct 02 08:32:28 PM UTC 24 |
| Finished | Oct 02 08:32:33 PM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373593 43 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.337359343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_alert_test.252697004 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 15884413 ps |
| CPU time | 0.98 seconds |
| Started | Oct 02 08:33:15 PM UTC 24 |
| Finished | Oct 02 08:33:17 PM UTC 24 |
| Peak memory | 214316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252697004 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.252697004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_host_error_intr.3144420989 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 118371302 ps |
| CPU time | 3.03 seconds |
| Started | Oct 02 08:32:38 PM UTC 24 |
| Finished | Oct 02 08:32:42 PM UTC 24 |
| Peak memory | 225520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144420989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.3144420989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_fmt_empty.3657807570 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 451594559 ps |
| CPU time | 23.88 seconds |
| Started | Oct 02 08:32:34 PM UTC 24 |
| Finished | Oct 02 08:33:00 PM UTC 24 |
| Peak memory | 271256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657807570 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empty.3657807570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_full.1638016275 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1900367140 ps |
| CPU time | 54.76 seconds |
| Started | Oct 02 08:32:36 PM UTC 24 |
| Finished | Oct 02 08:33:32 PM UTC 24 |
| Peak memory | 580516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638016275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1638016275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_overflow.4148628365 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 3904470045 ps |
| CPU time | 127.33 seconds |
| Started | Oct 02 08:32:34 PM UTC 24 |
| Finished | Oct 02 08:34:44 PM UTC 24 |
| Peak memory | 633576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148628365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.4148628365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_fmt.3797575762 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 224585325 ps |
| CPU time | 1.81 seconds |
| Started | Oct 02 08:32:34 PM UTC 24 |
| Finished | Oct 02 08:32:37 PM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797575762 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fmt.3797575762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_rx.2167476907 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 175874670 ps |
| CPU time | 6.47 seconds |
| Started | Oct 02 08:32:34 PM UTC 24 |
| Finished | Oct 02 08:32:42 PM UTC 24 |
| Peak memory | 248540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167476907 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.2167476907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_watermark.447660495 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 7913902269 ps |
| CPU time | 240.69 seconds |
| Started | Oct 02 08:32:33 PM UTC 24 |
| Finished | Oct 02 08:36:38 PM UTC 24 |
| Peak memory | 1233724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447660495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.447660495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_host_may_nack.1735882474 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1580525353 ps |
| CPU time | 17.97 seconds |
| Started | Oct 02 08:33:06 PM UTC 24 |
| Finished | Oct 02 08:33:25 PM UTC 24 |
| Peak memory | 215236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735882474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.1735882474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_host_override.762742174 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 19215228 ps |
| CPU time | 1.09 seconds |
| Started | Oct 02 08:32:33 PM UTC 24 |
| Finished | Oct 02 08:32:36 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762742174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.762742174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_host_perf.1350069408 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 4995468137 ps |
| CPU time | 77.16 seconds |
| Started | Oct 02 08:32:37 PM UTC 24 |
| Finished | Oct 02 08:33:56 PM UTC 24 |
| Peak memory | 748392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350069408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.1350069408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_host_perf_precise.62409167 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 863583035 ps |
| CPU time | 20.79 seconds |
| Started | Oct 02 08:32:37 PM UTC 24 |
| Finished | Oct 02 08:32:59 PM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62409167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho st_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.62409167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_host_smoke.661723524 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 1228899635 ps |
| CPU time | 60.83 seconds |
| Started | Oct 02 08:32:32 PM UTC 24 |
| Finished | Oct 02 08:33:35 PM UTC 24 |
| Peak memory | 363420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661723524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.661723524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_host_stress_all.809866745 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 24221590057 ps |
| CPU time | 363.99 seconds |
| Started | Oct 02 08:32:42 PM UTC 24 |
| Finished | Oct 02 08:38:51 PM UTC 24 |
| Peak memory | 1334052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809866745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.809866745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_host_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_host_stretch_timeout.3045153259 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 836139500 ps |
| CPU time | 17.4 seconds |
| Started | Oct 02 08:32:37 PM UTC 24 |
| Finished | Oct 02 08:32:56 PM UTC 24 |
| Peak memory | 231708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045153259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.3045153259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_bad_addr.15264650 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 3964192286 ps |
| CPU time | 9.45 seconds |
| Started | Oct 02 08:33:04 PM UTC 24 |
| Finished | Oct 02 08:33:14 PM UTC 24 |
| Peak memory | 225840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=15264650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.15264650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_acq.1165190753 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 151910125 ps |
| CPU time | 1.61 seconds |
| Started | Oct 02 08:33:00 PM UTC 24 |
| Finished | Oct 02 08:33:03 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165190 753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_acq.1165190753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_tx.1126941340 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 133659777 ps |
| CPU time | 1.43 seconds |
| Started | Oct 02 08:33:00 PM UTC 24 |
| Finished | Oct 02 08:33:03 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126941 340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_tx.1126941340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_acq.1813835537 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 386293666 ps |
| CPU time | 3.95 seconds |
| Started | Oct 02 08:33:07 PM UTC 24 |
| Finished | Oct 02 08:33:12 PM UTC 24 |
| Peak memory | 215380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813835 537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_watermar ks_acq.1813835537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_tx.3258944320 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 383809320 ps |
| CPU time | 1.69 seconds |
| Started | Oct 02 08:33:08 PM UTC 24 |
| Finished | Oct 02 08:33:11 PM UTC 24 |
| Peak memory | 214780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258944 320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_watermark s_tx.3258944320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_hrst.577941001 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 5137144570 ps |
| CPU time | 2.9 seconds |
| Started | Oct 02 08:33:04 PM UTC 24 |
| Finished | Oct 02 08:33:07 PM UTC 24 |
| Peak memory | 225768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5779410 01 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_hrst.577941001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_intr_smoke.1752048271 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1412826530 ps |
| CPU time | 6.49 seconds |
| Started | Oct 02 08:32:53 PM UTC 24 |
| Finished | Oct 02 08:33:01 PM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175204 8271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_smoke.1752048271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_intr_stress_wr.2108359248 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 11746941574 ps |
| CPU time | 21.04 seconds |
| Started | Oct 02 08:32:58 PM UTC 24 |
| Finished | Oct 02 08:33:20 PM UTC 24 |
| Peak memory | 422760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2108359248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_stres s_wr.2108359248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull.4170392507 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 2254747611 ps |
| CPU time | 5.97 seconds |
| Started | Oct 02 08:33:12 PM UTC 24 |
| Finished | Oct 02 08:33:19 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170392 507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_acqfull.4170392507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull_addr.2417684880 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 664342687 ps |
| CPU time | 4.44 seconds |
| Started | Oct 02 08:33:12 PM UTC 24 |
| Finished | Oct 02 08:33:18 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417684 880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_acqfull_ad dr.2417684880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_nack_txstretch.1991759517 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 560747398 ps |
| CPU time | 2.33 seconds |
| Started | Oct 02 08:33:13 PM UTC 24 |
| Finished | Oct 02 08:33:17 PM UTC 24 |
| Peak memory | 232360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991759 517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_txstretch.1991759517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_perf.4110789639 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 698947674 ps |
| CPU time | 9.12 seconds |
| Started | Oct 02 08:33:01 PM UTC 24 |
| Finished | Oct 02 08:33:12 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110789 639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_perf.4110789639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_smbus_maxlen.1199781067 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 2133502255 ps |
| CPU time | 4.5 seconds |
| Started | Oct 02 08:33:11 PM UTC 24 |
| Finished | Oct 02 08:33:17 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199781 067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smbus_maxlen.1199781067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_smoke.2547636030 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 611854072 ps |
| CPU time | 14.36 seconds |
| Started | Oct 02 08:32:43 PM UTC 24 |
| Finished | Oct 02 08:32:59 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547636030 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smoke.2547636030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_stress_rd.2789564845 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1653091171 ps |
| CPU time | 17.24 seconds |
| Started | Oct 02 08:32:46 PM UTC 24 |
| Finished | Oct 02 08:33:05 PM UTC 24 |
| Peak memory | 231700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789564845 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_rd.2789564845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_stress_wr.2855344070 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 28120746959 ps |
| CPU time | 39.07 seconds |
| Started | Oct 02 08:32:43 PM UTC 24 |
| Finished | Oct 02 08:33:24 PM UTC 24 |
| Peak memory | 594920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855344070 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_wr.2855344070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_stretch.3328162666 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 1761809305 ps |
| CPU time | 31.54 seconds |
| Started | Oct 02 08:32:49 PM UTC 24 |
| Finished | Oct 02 08:33:22 PM UTC 24 |
| Peak memory | 549664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328162666 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stretch.3328162666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_timeout.3896758726 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2307015566 ps |
| CPU time | 11.04 seconds |
| Started | Oct 02 08:32:58 PM UTC 24 |
| Finished | Oct 02 08:33:10 PM UTC 24 |
| Peak memory | 232220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896758 726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_timeout.3896758726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/11.i2c_target_tx_stretch_ctrl.264410925 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 616535715 ps |
| CPU time | 9.5 seconds |
| Started | Oct 02 08:33:11 PM UTC 24 |
| Finished | Oct 02 08:33:22 PM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644109 25 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.264410925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_alert_test.4285833643 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 46162753 ps |
| CPU time | 0.93 seconds |
| Started | Oct 02 08:34:06 PM UTC 24 |
| Finished | Oct 02 08:34:08 PM UTC 24 |
| Peak memory | 214256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285833643 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.4285833643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_host_error_intr.1850050366 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 105337148 ps |
| CPU time | 3.84 seconds |
| Started | Oct 02 08:33:32 PM UTC 24 |
| Finished | Oct 02 08:33:37 PM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850050366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.1850050366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_fmt_empty.1990419792 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 389243583 ps |
| CPU time | 7.61 seconds |
| Started | Oct 02 08:33:30 PM UTC 24 |
| Finished | Oct 02 08:33:39 PM UTC 24 |
| Peak memory | 297824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990419792 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empty.1990419792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_full.2295886539 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 10364689906 ps |
| CPU time | 154.33 seconds |
| Started | Oct 02 08:33:31 PM UTC 24 |
| Finished | Oct 02 08:36:08 PM UTC 24 |
| Peak memory | 555872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295886539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.2295886539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_overflow.4152249059 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 6466138402 ps |
| CPU time | 78.62 seconds |
| Started | Oct 02 08:33:18 PM UTC 24 |
| Finished | Oct 02 08:34:38 PM UTC 24 |
| Peak memory | 762744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152249059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.4152249059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_fmt.2180527584 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 176059368 ps |
| CPU time | 1.55 seconds |
| Started | Oct 02 08:33:18 PM UTC 24 |
| Finished | Oct 02 08:33:20 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180527584 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fmt.2180527584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_rx.1856665924 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 885413958 ps |
| CPU time | 13.03 seconds |
| Started | Oct 02 08:33:31 PM UTC 24 |
| Finished | Oct 02 08:33:45 PM UTC 24 |
| Peak memory | 215372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856665924 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.1856665924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_watermark.3537087038 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 39844911708 ps |
| CPU time | 328.62 seconds |
| Started | Oct 02 08:33:18 PM UTC 24 |
| Finished | Oct 02 08:38:51 PM UTC 24 |
| Peak memory | 1311608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537087038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.3537087038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_host_may_nack.1771001373 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 410281808 ps |
| CPU time | 17.22 seconds |
| Started | Oct 02 08:33:48 PM UTC 24 |
| Finished | Oct 02 08:34:06 PM UTC 24 |
| Peak memory | 215232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771001373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.1771001373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_host_mode_toggle.3762817492 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 94673562 ps |
| CPU time | 2.05 seconds |
| Started | Oct 02 08:33:48 PM UTC 24 |
| Finished | Oct 02 08:33:51 PM UTC 24 |
| Peak memory | 232284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762817492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.3762817492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_host_mode_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_host_override.1064221653 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 21959423 ps |
| CPU time | 0.94 seconds |
| Started | Oct 02 08:33:17 PM UTC 24 |
| Finished | Oct 02 08:33:18 PM UTC 24 |
| Peak memory | 214008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064221653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.1064221653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_host_perf.1478018722 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 12905447873 ps |
| CPU time | 179.47 seconds |
| Started | Oct 02 08:33:32 PM UTC 24 |
| Finished | Oct 02 08:36:34 PM UTC 24 |
| Peak memory | 215380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478018722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.1478018722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_host_perf_precise.3802490818 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 141325852 ps |
| CPU time | 3.78 seconds |
| Started | Oct 02 08:33:32 PM UTC 24 |
| Finished | Oct 02 08:33:37 PM UTC 24 |
| Peak memory | 240220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802490818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.3802490818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_host_smoke.2159847421 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1652284898 ps |
| CPU time | 35.85 seconds |
| Started | Oct 02 08:33:16 PM UTC 24 |
| Finished | Oct 02 08:33:54 PM UTC 24 |
| Peak memory | 428708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159847421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.2159847421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_host_stretch_timeout.2206690050 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1001382206 ps |
| CPU time | 12.97 seconds |
| Started | Oct 02 08:33:32 PM UTC 24 |
| Finished | Oct 02 08:33:46 PM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206690050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.2206690050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_bad_addr.2480254382 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 4148357608 ps |
| CPU time | 7.6 seconds |
| Started | Oct 02 08:33:46 PM UTC 24 |
| Finished | Oct 02 08:33:55 PM UTC 24 |
| Peak memory | 232308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2480254382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_ad dr.2480254382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_acq.294373978 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 517860068 ps |
| CPU time | 1.86 seconds |
| Started | Oct 02 08:33:44 PM UTC 24 |
| Finished | Oct 02 08:33:47 PM UTC 24 |
| Peak memory | 214784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943739 78 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_acq.294373978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_tx.1649558441 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 191618008 ps |
| CPU time | 1.52 seconds |
| Started | Oct 02 08:33:44 PM UTC 24 |
| Finished | Oct 02 08:33:47 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649558 441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_tx.1649558441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_acq.2615964271 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 977010512 ps |
| CPU time | 2.61 seconds |
| Started | Oct 02 08:33:48 PM UTC 24 |
| Finished | Oct 02 08:33:52 PM UTC 24 |
| Peak memory | 215236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615964 271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_watermar ks_acq.2615964271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_tx.4048702239 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 585428191 ps |
| CPU time | 2.42 seconds |
| Started | Oct 02 08:33:49 PM UTC 24 |
| Finished | Oct 02 08:33:53 PM UTC 24 |
| Peak memory | 215304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048702 239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_watermark s_tx.4048702239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_intr_smoke.3270350714 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 1678344892 ps |
| CPU time | 3.3 seconds |
| Started | Oct 02 08:33:36 PM UTC 24 |
| Finished | Oct 02 08:33:41 PM UTC 24 |
| Peak memory | 225624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327035 0714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_smoke.3270350714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_intr_stress_wr.2969016137 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 4871365482 ps |
| CPU time | 20.66 seconds |
| Started | Oct 02 08:33:37 PM UTC 24 |
| Finished | Oct 02 08:33:59 PM UTC 24 |
| Peak memory | 215372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2969016137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_stres s_wr.2969016137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull.2098367933 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 519829581 ps |
| CPU time | 4.66 seconds |
| Started | Oct 02 08:33:54 PM UTC 24 |
| Finished | Oct 02 08:34:00 PM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098367 933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_acqfull.2098367933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull_addr.1304886856 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 480254967 ps |
| CPU time | 5.01 seconds |
| Started | Oct 02 08:33:54 PM UTC 24 |
| Finished | Oct 02 08:34:00 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304886 856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_acqfull_ad dr.1304886856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_perf.4245712977 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1558896584 ps |
| CPU time | 8.79 seconds |
| Started | Oct 02 08:33:44 PM UTC 24 |
| Finished | Oct 02 08:33:54 PM UTC 24 |
| Peak memory | 232416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245712 977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_perf.4245712977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_smbus_maxlen.1699863167 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 2046786871 ps |
| CPU time | 4.31 seconds |
| Started | Oct 02 08:33:52 PM UTC 24 |
| Finished | Oct 02 08:33:58 PM UTC 24 |
| Peak memory | 215020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699863 167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smbus_maxlen.1699863167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_smoke.4051936885 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1069702823 ps |
| CPU time | 29.27 seconds |
| Started | Oct 02 08:33:32 PM UTC 24 |
| Finished | Oct 02 08:34:03 PM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051936885 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smoke.4051936885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_stress_all.1161490498 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 37353795633 ps |
| CPU time | 59.79 seconds |
| Started | Oct 02 08:33:45 PM UTC 24 |
| Finished | Oct 02 08:34:46 PM UTC 24 |
| Peak memory | 248752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116149 0498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_all.1161490498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_stress_rd.3914530101 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 838623711 ps |
| CPU time | 7.74 seconds |
| Started | Oct 02 08:33:33 PM UTC 24 |
| Finished | Oct 02 08:33:42 PM UTC 24 |
| Peak memory | 215312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914530101 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_rd.3914530101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_stress_wr.2744434133 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 49543291142 ps |
| CPU time | 384.32 seconds |
| Started | Oct 02 08:33:32 PM UTC 24 |
| Finished | Oct 02 08:40:01 PM UTC 24 |
| Peak memory | 3910624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744434133 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_wr.2744434133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_stretch.3973751033 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 5111547681 ps |
| CPU time | 4.96 seconds |
| Started | Oct 02 08:33:35 PM UTC 24 |
| Finished | Oct 02 08:33:41 PM UTC 24 |
| Peak memory | 246756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973751033 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stretch.3973751033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_timeout.2268951818 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2057482319 ps |
| CPU time | 9.91 seconds |
| Started | Oct 02 08:33:37 PM UTC 24 |
| Finished | Oct 02 08:33:48 PM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268951 818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_timeout.2268951818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/12.i2c_target_tx_stretch_ctrl.1669273147 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 514822346 ps |
| CPU time | 10.09 seconds |
| Started | Oct 02 08:33:52 PM UTC 24 |
| Finished | Oct 02 08:34:04 PM UTC 24 |
| Peak memory | 215248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669273 147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.1669273147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_alert_test.3956286159 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 27462571 ps |
| CPU time | 0.84 seconds |
| Started | Oct 02 08:34:49 PM UTC 24 |
| Finished | Oct 02 08:34:51 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956286159 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.3956286159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_host_error_intr.1129852884 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 75582373 ps |
| CPU time | 2.89 seconds |
| Started | Oct 02 08:34:24 PM UTC 24 |
| Finished | Oct 02 08:34:28 PM UTC 24 |
| Peak memory | 225660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129852884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.1129852884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_fmt_empty.1866524869 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 171609679 ps |
| CPU time | 7.85 seconds |
| Started | Oct 02 08:34:23 PM UTC 24 |
| Finished | Oct 02 08:34:33 PM UTC 24 |
| Peak memory | 214744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866524869 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empty.1866524869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_full.2240726917 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 3748823524 ps |
| CPU time | 53.1 seconds |
| Started | Oct 02 08:34:24 PM UTC 24 |
| Finished | Oct 02 08:35:18 PM UTC 24 |
| Peak memory | 422716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240726917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.2240726917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_overflow.3374677847 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 38607041863 ps |
| CPU time | 83.7 seconds |
| Started | Oct 02 08:34:23 PM UTC 24 |
| Finished | Oct 02 08:35:49 PM UTC 24 |
| Peak memory | 818100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374677847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3374677847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_fmt.406688715 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 460315537 ps |
| CPU time | 1.84 seconds |
| Started | Oct 02 08:34:23 PM UTC 24 |
| Finished | Oct 02 08:34:26 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406688715 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_fmt.406688715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_rx.2918427600 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 243869134 ps |
| CPU time | 8.51 seconds |
| Started | Oct 02 08:34:24 PM UTC 24 |
| Finished | Oct 02 08:34:33 PM UTC 24 |
| Peak memory | 263076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918427600 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.2918427600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_watermark.3771955352 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 5624997123 ps |
| CPU time | 84.68 seconds |
| Started | Oct 02 08:34:23 PM UTC 24 |
| Finished | Oct 02 08:35:50 PM UTC 24 |
| Peak memory | 1024800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771955352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.3771955352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_host_may_nack.2875950740 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1527131840 ps |
| CPU time | 7.08 seconds |
| Started | Oct 02 08:34:48 PM UTC 24 |
| Finished | Oct 02 08:34:56 PM UTC 24 |
| Peak memory | 215444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875950740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.2875950740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_host_override.3012625006 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 35834977 ps |
| CPU time | 1.04 seconds |
| Started | Oct 02 08:34:23 PM UTC 24 |
| Finished | Oct 02 08:34:26 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012625006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.3012625006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_host_perf.1458776150 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 4422511574 ps |
| CPU time | 49.16 seconds |
| Started | Oct 02 08:34:24 PM UTC 24 |
| Finished | Oct 02 08:35:14 PM UTC 24 |
| Peak memory | 586536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458776150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.1458776150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_host_perf_precise.1792602823 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 324916381 ps |
| CPU time | 8.49 seconds |
| Started | Oct 02 08:34:24 PM UTC 24 |
| Finished | Oct 02 08:34:33 PM UTC 24 |
| Peak memory | 283228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792602823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.1792602823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_host_smoke.82831238 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 3108900812 ps |
| CPU time | 71.37 seconds |
| Started | Oct 02 08:34:06 PM UTC 24 |
| Finished | Oct 02 08:35:19 PM UTC 24 |
| Peak memory | 297744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82831238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho st_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.82831238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_host_stretch_timeout.1060565385 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 5727001739 ps |
| CPU time | 10.81 seconds |
| Started | Oct 02 08:34:24 PM UTC 24 |
| Finished | Oct 02 08:34:36 PM UTC 24 |
| Peak memory | 232352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060565385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.1060565385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_bad_addr.716866554 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 2670634814 ps |
| CPU time | 10.1 seconds |
| Started | Oct 02 08:34:34 PM UTC 24 |
| Finished | Oct 02 08:34:45 PM UTC 24 |
| Peak memory | 232504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=716866554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.716866554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_acq.1194392928 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 270963761 ps |
| CPU time | 2.51 seconds |
| Started | Oct 02 08:34:31 PM UTC 24 |
| Finished | Oct 02 08:34:34 PM UTC 24 |
| Peak memory | 217308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194392 928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_acq.1194392928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_acq.3835737015 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 948493987 ps |
| CPU time | 4.96 seconds |
| Started | Oct 02 08:34:48 PM UTC 24 |
| Finished | Oct 02 08:34:54 PM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835737 015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_watermar ks_acq.3835737015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_tx.2013094586 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 92139686 ps |
| CPU time | 1.2 seconds |
| Started | Oct 02 08:34:48 PM UTC 24 |
| Finished | Oct 02 08:34:50 PM UTC 24 |
| Peak memory | 214780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013094 586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_watermark s_tx.2013094586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_hrst.1245902306 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 722915141 ps |
| CPU time | 2.56 seconds |
| Started | Oct 02 08:34:35 PM UTC 24 |
| Finished | Oct 02 08:34:39 PM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245902 306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_hrst.1245902306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_intr_smoke.590412306 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 620676585 ps |
| CPU time | 7.5 seconds |
| Started | Oct 02 08:34:27 PM UTC 24 |
| Finished | Oct 02 08:34:36 PM UTC 24 |
| Peak memory | 227804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590412 306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_smoke.590412306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_intr_stress_wr.167752534 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 5737418191 ps |
| CPU time | 17.3 seconds |
| Started | Oct 02 08:34:27 PM UTC 24 |
| Finished | Oct 02 08:34:46 PM UTC 24 |
| Peak memory | 215376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=167752534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_stress _wr.167752534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull.1049036644 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 2211540304 ps |
| CPU time | 3.53 seconds |
| Started | Oct 02 08:34:49 PM UTC 24 |
| Finished | Oct 02 08:34:54 PM UTC 24 |
| Peak memory | 225624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049036 644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_acqfull.1049036644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull_addr.3227845839 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 911236179 ps |
| CPU time | 3.33 seconds |
| Started | Oct 02 08:34:49 PM UTC 24 |
| Finished | Oct 02 08:34:53 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227845 839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_acqfull_ad dr.3227845839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_nack_txstretch.4201622326 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 528724946 ps |
| CPU time | 2.24 seconds |
| Started | Oct 02 08:34:49 PM UTC 24 |
| Finished | Oct 02 08:34:52 PM UTC 24 |
| Peak memory | 232028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201622 326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_txstretch.4201622326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_perf.3763204236 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 858512404 ps |
| CPU time | 7.77 seconds |
| Started | Oct 02 08:34:34 PM UTC 24 |
| Finished | Oct 02 08:34:43 PM UTC 24 |
| Peak memory | 232168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763204 236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_perf.3763204236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_smbus_maxlen.2665722372 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2641174320 ps |
| CPU time | 3.06 seconds |
| Started | Oct 02 08:34:49 PM UTC 24 |
| Finished | Oct 02 08:34:53 PM UTC 24 |
| Peak memory | 215296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665722 372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smbus_maxlen.2665722372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_smoke.3997041614 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 5164055758 ps |
| CPU time | 17.27 seconds |
| Started | Oct 02 08:34:24 PM UTC 24 |
| Finished | Oct 02 08:34:43 PM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997041614 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smoke.3997041614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_stress_all.1465983975 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 64331559845 ps |
| CPU time | 209.54 seconds |
| Started | Oct 02 08:34:34 PM UTC 24 |
| Finished | Oct 02 08:38:07 PM UTC 24 |
| Peak memory | 2038636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146598 3975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_all.1465983975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_stress_rd.3593601536 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 6738178984 ps |
| CPU time | 36.73 seconds |
| Started | Oct 02 08:34:24 PM UTC 24 |
| Finished | Oct 02 08:35:02 PM UTC 24 |
| Peak memory | 248904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593601536 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_rd.3593601536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_stress_wr.3843882570 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 9029411729 ps |
| CPU time | 20.69 seconds |
| Started | Oct 02 08:34:24 PM UTC 24 |
| Finished | Oct 02 08:34:46 PM UTC 24 |
| Peak memory | 215584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843882570 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_wr.3843882570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_stretch.367484051 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 7149887531 ps |
| CPU time | 4.65 seconds |
| Started | Oct 02 08:34:24 PM UTC 24 |
| Finished | Oct 02 08:34:30 PM UTC 24 |
| Peak memory | 242712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367484051 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stretch.367484051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_timeout.3309871822 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 1172867448 ps |
| CPU time | 10.76 seconds |
| Started | Oct 02 08:34:28 PM UTC 24 |
| Finished | Oct 02 08:34:39 PM UTC 24 |
| Peak memory | 229664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309871 822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_timeout.3309871822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/13.i2c_target_tx_stretch_ctrl.2912397718 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 58819527 ps |
| CPU time | 1.68 seconds |
| Started | Oct 02 08:34:49 PM UTC 24 |
| Finished | Oct 02 08:34:52 PM UTC 24 |
| Peak memory | 214864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912397 718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.2912397718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/13.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_alert_test.3713496900 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 21483903 ps |
| CPU time | 0.97 seconds |
| Started | Oct 02 08:35:19 PM UTC 24 |
| Finished | Oct 02 08:35:22 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713496900 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.3713496900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_host_error_intr.2743062335 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 78494858 ps |
| CPU time | 2.3 seconds |
| Started | Oct 02 08:34:54 PM UTC 24 |
| Finished | Oct 02 08:34:57 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743062335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.2743062335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_fmt_empty.1516751553 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 936474960 ps |
| CPU time | 9.51 seconds |
| Started | Oct 02 08:34:51 PM UTC 24 |
| Finished | Oct 02 08:35:01 PM UTC 24 |
| Peak memory | 316200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516751553 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empty.1516751553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_full.2252242858 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 5522576844 ps |
| CPU time | 204.49 seconds |
| Started | Oct 02 08:34:52 PM UTC 24 |
| Finished | Oct 02 08:38:19 PM UTC 24 |
| Peak memory | 678752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252242858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.2252242858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_overflow.481040819 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 6986447563 ps |
| CPU time | 73.11 seconds |
| Started | Oct 02 08:34:50 PM UTC 24 |
| Finished | Oct 02 08:36:04 PM UTC 24 |
| Peak memory | 701276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481040819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.481040819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_fmt.3946055197 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 242113539 ps |
| CPU time | 1.75 seconds |
| Started | Oct 02 08:34:51 PM UTC 24 |
| Finished | Oct 02 08:34:53 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946055197 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fmt.3946055197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_rx.3313413121 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 1893011459 ps |
| CPU time | 14.21 seconds |
| Started | Oct 02 08:34:52 PM UTC 24 |
| Finished | Oct 02 08:35:07 PM UTC 24 |
| Peak memory | 215248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313413121 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.3313413121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_watermark.744017648 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 4059771707 ps |
| CPU time | 242.43 seconds |
| Started | Oct 02 08:34:50 PM UTC 24 |
| Finished | Oct 02 08:38:55 PM UTC 24 |
| Peak memory | 1120996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744017648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.744017648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_host_may_nack.1646905925 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 634503447 ps |
| CPU time | 3.4 seconds |
| Started | Oct 02 08:35:13 PM UTC 24 |
| Finished | Oct 02 08:35:18 PM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646905925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.1646905925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_host_override.1832403136 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 34996630 ps |
| CPU time | 1.07 seconds |
| Started | Oct 02 08:34:49 PM UTC 24 |
| Finished | Oct 02 08:34:51 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832403136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1832403136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_host_perf.610472184 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 19099861047 ps |
| CPU time | 150.87 seconds |
| Started | Oct 02 08:34:53 PM UTC 24 |
| Finished | Oct 02 08:37:26 PM UTC 24 |
| Peak memory | 676644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610472184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.610472184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_host_perf_precise.1109226615 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 182579478 ps |
| CPU time | 3.5 seconds |
| Started | Oct 02 08:34:53 PM UTC 24 |
| Finished | Oct 02 08:34:58 PM UTC 24 |
| Peak memory | 240292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109226615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.1109226615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_host_smoke.3463508690 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 9239782740 ps |
| CPU time | 44.92 seconds |
| Started | Oct 02 08:34:49 PM UTC 24 |
| Finished | Oct 02 08:35:36 PM UTC 24 |
| Peak memory | 383960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463508690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3463508690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_host_stretch_timeout.3460987567 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 3131069957 ps |
| CPU time | 14.35 seconds |
| Started | Oct 02 08:34:54 PM UTC 24 |
| Finished | Oct 02 08:35:10 PM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460987567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.3460987567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_bad_addr.1766471385 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 3614699925 ps |
| CPU time | 6.16 seconds |
| Started | Oct 02 08:35:11 PM UTC 24 |
| Finished | Oct 02 08:35:18 PM UTC 24 |
| Peak memory | 231836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1766471385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_ad dr.1766471385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_acq.4119525934 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 409446269 ps |
| CPU time | 2.88 seconds |
| Started | Oct 02 08:35:09 PM UTC 24 |
| Finished | Oct 02 08:35:13 PM UTC 24 |
| Peak memory | 219428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119525 934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_acq.4119525934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_tx.2255990254 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1778621388 ps |
| CPU time | 2.65 seconds |
| Started | Oct 02 08:35:10 PM UTC 24 |
| Finished | Oct 02 08:35:14 PM UTC 24 |
| Peak memory | 217508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255990 254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_tx.2255990254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_acq.3846198698 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 326626575 ps |
| CPU time | 3.24 seconds |
| Started | Oct 02 08:35:15 PM UTC 24 |
| Finished | Oct 02 08:35:19 PM UTC 24 |
| Peak memory | 215380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846198 698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_watermar ks_acq.3846198698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_tx.2502113030 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 352036427 ps |
| CPU time | 1.53 seconds |
| Started | Oct 02 08:35:16 PM UTC 24 |
| Finished | Oct 02 08:35:18 PM UTC 24 |
| Peak memory | 215020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502113 030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_watermark s_tx.2502113030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_hrst.3138262784 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 856104308 ps |
| CPU time | 2.96 seconds |
| Started | Oct 02 08:35:12 PM UTC 24 |
| Finished | Oct 02 08:35:16 PM UTC 24 |
| Peak memory | 225492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138262 784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_hrst.3138262784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_intr_smoke.4153214606 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 9043475067 ps |
| CPU time | 7.87 seconds |
| Started | Oct 02 08:34:59 PM UTC 24 |
| Finished | Oct 02 08:35:08 PM UTC 24 |
| Peak memory | 225760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415321 4606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_smoke.4153214606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_intr_stress_wr.1297481561 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 5923716578 ps |
| CPU time | 7.43 seconds |
| Started | Oct 02 08:35:02 PM UTC 24 |
| Finished | Oct 02 08:35:10 PM UTC 24 |
| Peak memory | 369640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1297481561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_stres s_wr.1297481561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull.2710098084 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 2076223467 ps |
| CPU time | 3.49 seconds |
| Started | Oct 02 08:35:19 PM UTC 24 |
| Finished | Oct 02 08:35:24 PM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710098 084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_acqfull.2710098084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull_addr.685728179 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 2463632665 ps |
| CPU time | 3.72 seconds |
| Started | Oct 02 08:35:19 PM UTC 24 |
| Finished | Oct 02 08:35:24 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6857281 79 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_acqfull_addr.685728179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_nack_txstretch.1696803811 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 536229327 ps |
| CPU time | 2.14 seconds |
| Started | Oct 02 08:35:19 PM UTC 24 |
| Finished | Oct 02 08:35:22 PM UTC 24 |
| Peak memory | 232320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696803 811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_txstretch.1696803811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_perf.2900962314 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 516239022 ps |
| CPU time | 5.81 seconds |
| Started | Oct 02 08:35:11 PM UTC 24 |
| Finished | Oct 02 08:35:18 PM UTC 24 |
| Peak memory | 231644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900962 314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_perf.2900962314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_smbus_maxlen.2830906457 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 380267592 ps |
| CPU time | 3.42 seconds |
| Started | Oct 02 08:35:18 PM UTC 24 |
| Finished | Oct 02 08:35:23 PM UTC 24 |
| Peak memory | 215004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830906 457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smbus_maxlen.2830906457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_smoke.214002995 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 1696869347 ps |
| CPU time | 15.31 seconds |
| Started | Oct 02 08:34:54 PM UTC 24 |
| Finished | Oct 02 08:35:11 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214002995 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smoke.214002995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_stress_all.1349729423 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 56802984643 ps |
| CPU time | 137.42 seconds |
| Started | Oct 02 08:35:11 PM UTC 24 |
| Finished | Oct 02 08:37:31 PM UTC 24 |
| Peak memory | 1141548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134972 9423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_all.1349729423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_stress_rd.288833926 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 1259556425 ps |
| CPU time | 31.64 seconds |
| Started | Oct 02 08:34:56 PM UTC 24 |
| Finished | Oct 02 08:35:29 PM UTC 24 |
| Peak memory | 225632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288833926 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_rd.288833926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_stress_wr.1419965712 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 18458848176 ps |
| CPU time | 16.01 seconds |
| Started | Oct 02 08:34:55 PM UTC 24 |
| Finished | Oct 02 08:35:13 PM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419965712 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_wr.1419965712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_stretch.2576299877 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 701501775 ps |
| CPU time | 29.85 seconds |
| Started | Oct 02 08:34:59 PM UTC 24 |
| Finished | Oct 02 08:35:30 PM UTC 24 |
| Peak memory | 324452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576299877 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stretch.2576299877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_timeout.3234901536 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 5829021395 ps |
| CPU time | 10.57 seconds |
| Started | Oct 02 08:35:04 PM UTC 24 |
| Finished | Oct 02 08:35:15 PM UTC 24 |
| Peak memory | 231908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234901 536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_timeout.3234901536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/14.i2c_target_tx_stretch_ctrl.2803561391 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 2065102021 ps |
| CPU time | 22.39 seconds |
| Started | Oct 02 08:35:17 PM UTC 24 |
| Finished | Oct 02 08:35:41 PM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803561 391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.2803561391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/14.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_alert_test.2553075992 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 15421238 ps |
| CPU time | 0.91 seconds |
| Started | Oct 02 08:35:57 PM UTC 24 |
| Finished | Oct 02 08:35:59 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553075992 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.2553075992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_fmt_empty.1455696353 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 458773629 ps |
| CPU time | 27.1 seconds |
| Started | Oct 02 08:35:22 PM UTC 24 |
| Finished | Oct 02 08:35:51 PM UTC 24 |
| Peak memory | 291676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455696353 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empty.1455696353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_full.2695267630 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 9928232642 ps |
| CPU time | 69.56 seconds |
| Started | Oct 02 08:35:24 PM UTC 24 |
| Finished | Oct 02 08:36:35 PM UTC 24 |
| Peak memory | 666404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695267630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.2695267630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_overflow.1760156540 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 2121567995 ps |
| CPU time | 68.14 seconds |
| Started | Oct 02 08:35:20 PM UTC 24 |
| Finished | Oct 02 08:36:30 PM UTC 24 |
| Peak memory | 756456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760156540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.1760156540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_fmt.2055894706 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 89533487 ps |
| CPU time | 1.19 seconds |
| Started | Oct 02 08:35:22 PM UTC 24 |
| Finished | Oct 02 08:35:25 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055894706 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fmt.2055894706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_rx.1814836322 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 453717378 ps |
| CPU time | 4.63 seconds |
| Started | Oct 02 08:35:23 PM UTC 24 |
| Finished | Oct 02 08:35:29 PM UTC 24 |
| Peak memory | 234204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814836322 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.1814836322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_watermark.3347836793 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 3214311939 ps |
| CPU time | 74.35 seconds |
| Started | Oct 02 08:35:20 PM UTC 24 |
| Finished | Oct 02 08:36:37 PM UTC 24 |
| Peak memory | 940984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347836793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.3347836793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_host_may_nack.1708624777 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 504958477 ps |
| CPU time | 27.62 seconds |
| Started | Oct 02 08:35:51 PM UTC 24 |
| Finished | Oct 02 08:36:20 PM UTC 24 |
| Peak memory | 215184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708624777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1708624777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_host_override.1706955682 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 180432782 ps |
| CPU time | 0.86 seconds |
| Started | Oct 02 08:35:19 PM UTC 24 |
| Finished | Oct 02 08:35:21 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706955682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1706955682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_host_perf.2617074419 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 647577572 ps |
| CPU time | 5.51 seconds |
| Started | Oct 02 08:35:25 PM UTC 24 |
| Finished | Oct 02 08:35:31 PM UTC 24 |
| Peak memory | 240480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617074419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.2617074419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_host_perf_precise.3040947682 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 606917331 ps |
| CPU time | 7.47 seconds |
| Started | Oct 02 08:35:25 PM UTC 24 |
| Finished | Oct 02 08:35:33 PM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040947682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.3040947682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_host_smoke.1192470213 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 2738306782 ps |
| CPU time | 25.96 seconds |
| Started | Oct 02 08:35:19 PM UTC 24 |
| Finished | Oct 02 08:35:47 PM UTC 24 |
| Peak memory | 308052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192470213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1192470213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_host_stretch_timeout.4085988224 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 714958484 ps |
| CPU time | 29.66 seconds |
| Started | Oct 02 08:35:26 PM UTC 24 |
| Finished | Oct 02 08:35:57 PM UTC 24 |
| Peak memory | 225504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085988224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.4085988224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_bad_addr.1603029695 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1271091271 ps |
| CPU time | 3.65 seconds |
| Started | Oct 02 08:35:50 PM UTC 24 |
| Finished | Oct 02 08:35:55 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1603029695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_bad_ad dr.1603029695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_acq.93903919 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 401494382 ps |
| CPU time | 1.87 seconds |
| Started | Oct 02 08:35:42 PM UTC 24 |
| Finished | Oct 02 08:35:45 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9390391 9 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_acq.93903919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_tx.3785404701 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 252500961 ps |
| CPU time | 3.08 seconds |
| Started | Oct 02 08:35:46 PM UTC 24 |
| Finished | Oct 02 08:35:50 PM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785404 701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_tx.3785404701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_acq.2083842792 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 1388117473 ps |
| CPU time | 3.93 seconds |
| Started | Oct 02 08:35:51 PM UTC 24 |
| Finished | Oct 02 08:35:56 PM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083842 792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_watermar ks_acq.2083842792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_tx.3499218986 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 362689611 ps |
| CPU time | 1.44 seconds |
| Started | Oct 02 08:35:53 PM UTC 24 |
| Finished | Oct 02 08:35:55 PM UTC 24 |
| Peak memory | 214960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499218 986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_watermark s_tx.3499218986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_intr_smoke.1624462305 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 934480874 ps |
| CPU time | 4.99 seconds |
| Started | Oct 02 08:35:34 PM UTC 24 |
| Finished | Oct 02 08:35:41 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162446 2305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_smoke.1624462305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_intr_stress_wr.3718559463 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 14608273206 ps |
| CPU time | 29.26 seconds |
| Started | Oct 02 08:35:36 PM UTC 24 |
| Finished | Oct 02 08:36:07 PM UTC 24 |
| Peak memory | 539496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3718559463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_stres s_wr.3718559463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull.1333028189 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 562108224 ps |
| CPU time | 4.38 seconds |
| Started | Oct 02 08:35:56 PM UTC 24 |
| Finished | Oct 02 08:36:01 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333028 189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_acqfull.1333028189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull_addr.3963773150 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 2319986631 ps |
| CPU time | 4.32 seconds |
| Started | Oct 02 08:35:56 PM UTC 24 |
| Finished | Oct 02 08:36:01 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963773 150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_acqfull_ad dr.3963773150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_nack_txstretch.94624282 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 131168438 ps |
| CPU time | 2.39 seconds |
| Started | Oct 02 08:35:56 PM UTC 24 |
| Finished | Oct 02 08:35:59 PM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9462428 2 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_txstretch.94624282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_perf.3575689361 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 5807323852 ps |
| CPU time | 6.78 seconds |
| Started | Oct 02 08:35:46 PM UTC 24 |
| Finished | Oct 02 08:35:54 PM UTC 24 |
| Peak memory | 231968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575689 361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_perf.3575689361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_smbus_maxlen.1873825133 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 1952140784 ps |
| CPU time | 3.34 seconds |
| Started | Oct 02 08:35:55 PM UTC 24 |
| Finished | Oct 02 08:35:59 PM UTC 24 |
| Peak memory | 215096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873825 133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smbus_maxlen.1873825133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_smoke.1900361746 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 11428249862 ps |
| CPU time | 18.84 seconds |
| Started | Oct 02 08:35:30 PM UTC 24 |
| Finished | Oct 02 08:35:50 PM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900361746 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smoke.1900361746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_stress_all.303215993 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 76373620145 ps |
| CPU time | 69.94 seconds |
| Started | Oct 02 08:35:48 PM UTC 24 |
| Finished | Oct 02 08:37:00 PM UTC 24 |
| Peak memory | 592872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303215 993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_all.303215993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_stress_rd.761809181 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 792181158 ps |
| CPU time | 7.75 seconds |
| Started | Oct 02 08:35:32 PM UTC 24 |
| Finished | Oct 02 08:35:41 PM UTC 24 |
| Peak memory | 215312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761809181 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_rd.761809181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_stress_wr.4190632111 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 37880753457 ps |
| CPU time | 140.21 seconds |
| Started | Oct 02 08:35:31 PM UTC 24 |
| Finished | Oct 02 08:37:54 PM UTC 24 |
| Peak memory | 2347936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190632111 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_wr.4190632111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_stretch.2549753472 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1069876785 ps |
| CPU time | 17.02 seconds |
| Started | Oct 02 08:35:33 PM UTC 24 |
| Finished | Oct 02 08:35:52 PM UTC 24 |
| Peak memory | 418728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549753472 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stretch.2549753472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_timeout.1319713076 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 2595258433 ps |
| CPU time | 12.14 seconds |
| Started | Oct 02 08:35:42 PM UTC 24 |
| Finished | Oct 02 08:35:55 PM UTC 24 |
| Peak memory | 232308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319713 076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_timeout.1319713076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/15.i2c_target_tx_stretch_ctrl.2875129149 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 294348740 ps |
| CPU time | 5.23 seconds |
| Started | Oct 02 08:35:55 PM UTC 24 |
| Finished | Oct 02 08:36:01 PM UTC 24 |
| Peak memory | 215444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875129 149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.2875129149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/15.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_alert_test.3658919622 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 16991884 ps |
| CPU time | 0.95 seconds |
| Started | Oct 02 08:36:39 PM UTC 24 |
| Finished | Oct 02 08:36:41 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658919622 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.3658919622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_fmt_empty.3624768680 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 3205067452 ps |
| CPU time | 6.92 seconds |
| Started | Oct 02 08:36:02 PM UTC 24 |
| Finished | Oct 02 08:36:09 PM UTC 24 |
| Peak memory | 281380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624768680 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empty.3624768680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_full.3292205475 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 2404232731 ps |
| CPU time | 123.56 seconds |
| Started | Oct 02 08:36:03 PM UTC 24 |
| Finished | Oct 02 08:38:08 PM UTC 24 |
| Peak memory | 314164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292205475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.3292205475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_overflow.3112656715 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1739877692 ps |
| CPU time | 51.78 seconds |
| Started | Oct 02 08:36:00 PM UTC 24 |
| Finished | Oct 02 08:36:54 PM UTC 24 |
| Peak memory | 617256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112656715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.3112656715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_fmt.914781012 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 146973567 ps |
| CPU time | 1.84 seconds |
| Started | Oct 02 08:36:01 PM UTC 24 |
| Finished | Oct 02 08:36:04 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914781012 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fmt.914781012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_rx.717969703 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 146634413 ps |
| CPU time | 10.7 seconds |
| Started | Oct 02 08:36:03 PM UTC 24 |
| Finished | Oct 02 08:36:14 PM UTC 24 |
| Peak memory | 238248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717969703 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.717969703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_watermark.1624678296 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 13162912243 ps |
| CPU time | 70.01 seconds |
| Started | Oct 02 08:36:00 PM UTC 24 |
| Finished | Oct 02 08:37:12 PM UTC 24 |
| Peak memory | 1051492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624678296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.1624678296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_host_override.1821673783 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 28064155 ps |
| CPU time | 0.97 seconds |
| Started | Oct 02 08:36:00 PM UTC 24 |
| Finished | Oct 02 08:36:02 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821673783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.1821673783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_host_perf.2216409352 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 26620617231 ps |
| CPU time | 455.57 seconds |
| Started | Oct 02 08:36:05 PM UTC 24 |
| Finished | Oct 02 08:43:46 PM UTC 24 |
| Peak memory | 1706720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216409352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.2216409352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_host_perf_precise.190316537 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 23156641857 ps |
| CPU time | 683.63 seconds |
| Started | Oct 02 08:36:05 PM UTC 24 |
| Finished | Oct 02 08:47:37 PM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190316537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.190316537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_host_smoke.4147126872 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 4785884461 ps |
| CPU time | 72.53 seconds |
| Started | Oct 02 08:35:57 PM UTC 24 |
| Finished | Oct 02 08:37:11 PM UTC 24 |
| Peak memory | 428756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147126872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.4147126872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_host_stretch_timeout.1483567652 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 1453120112 ps |
| CPU time | 8.63 seconds |
| Started | Oct 02 08:36:08 PM UTC 24 |
| Finished | Oct 02 08:36:18 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483567652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.1483567652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_bad_addr.2751466853 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1860492986 ps |
| CPU time | 7.17 seconds |
| Started | Oct 02 08:36:28 PM UTC 24 |
| Finished | Oct 02 08:36:36 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2751466853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_ad dr.2751466853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_acq.3480089937 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 359470620 ps |
| CPU time | 1.88 seconds |
| Started | Oct 02 08:36:21 PM UTC 24 |
| Finished | Oct 02 08:36:24 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480089 937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_acq.3480089937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_tx.304016900 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 443105776 ps |
| CPU time | 1.5 seconds |
| Started | Oct 02 08:36:24 PM UTC 24 |
| Finished | Oct 02 08:36:27 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040169 00 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_tx.304016900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_acq.4105509378 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 213581156 ps |
| CPU time | 2.81 seconds |
| Started | Oct 02 08:36:34 PM UTC 24 |
| Finished | Oct 02 08:36:38 PM UTC 24 |
| Peak memory | 215036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105509 378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_watermar ks_acq.4105509378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_tx.4104744248 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 122653374 ps |
| CPU time | 1.65 seconds |
| Started | Oct 02 08:36:35 PM UTC 24 |
| Finished | Oct 02 08:36:38 PM UTC 24 |
| Peak memory | 215020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104744 248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_watermark s_tx.4104744248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_intr_smoke.3100089211 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 870782267 ps |
| CPU time | 4.45 seconds |
| Started | Oct 02 08:36:21 PM UTC 24 |
| Finished | Oct 02 08:36:26 PM UTC 24 |
| Peak memory | 231736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310008 9211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_smoke.3100089211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_intr_stress_wr.293311676 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 29857932564 ps |
| CPU time | 92.73 seconds |
| Started | Oct 02 08:36:21 PM UTC 24 |
| Finished | Oct 02 08:37:56 PM UTC 24 |
| Peak memory | 1682356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=293311676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_stress _wr.293311676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull.3412031700 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2396712777 ps |
| CPU time | 5.04 seconds |
| Started | Oct 02 08:36:36 PM UTC 24 |
| Finished | Oct 02 08:36:42 PM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412031 700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_acqfull.3412031700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull_addr.619957086 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 2208986274 ps |
| CPU time | 4.01 seconds |
| Started | Oct 02 08:36:38 PM UTC 24 |
| Finished | Oct 02 08:36:43 PM UTC 24 |
| Peak memory | 215468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6199570 86 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_acqfull_addr.619957086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_nack_txstretch.594237694 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 1172089163 ps |
| CPU time | 2.09 seconds |
| Started | Oct 02 08:36:38 PM UTC 24 |
| Finished | Oct 02 08:36:41 PM UTC 24 |
| Peak memory | 232352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5942376 94 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_txstretch.594237694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_perf.425594908 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 865012809 ps |
| CPU time | 9.75 seconds |
| Started | Oct 02 08:36:24 PM UTC 24 |
| Finished | Oct 02 08:36:35 PM UTC 24 |
| Peak memory | 232496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255949 08 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_perf.425594908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_smbus_maxlen.2051918359 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 629979558 ps |
| CPU time | 4.01 seconds |
| Started | Oct 02 08:36:36 PM UTC 24 |
| Finished | Oct 02 08:36:41 PM UTC 24 |
| Peak memory | 215100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051918 359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smbus_maxlen.2051918359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_smoke.600827449 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 1366828498 ps |
| CPU time | 49.95 seconds |
| Started | Oct 02 08:36:14 PM UTC 24 |
| Finished | Oct 02 08:37:05 PM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600827449 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smoke.600827449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_stress_all.3156393840 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 11359743288 ps |
| CPU time | 57.44 seconds |
| Started | Oct 02 08:36:26 PM UTC 24 |
| Finished | Oct 02 08:37:25 PM UTC 24 |
| Peak memory | 256888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315639 3840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_all.3156393840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_stress_rd.4000573441 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 962243942 ps |
| CPU time | 17.34 seconds |
| Started | Oct 02 08:36:14 PM UTC 24 |
| Finished | Oct 02 08:36:33 PM UTC 24 |
| Peak memory | 229796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000573441 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_rd.4000573441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_stress_wr.1542626739 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 46499980055 ps |
| CPU time | 178.77 seconds |
| Started | Oct 02 08:36:14 PM UTC 24 |
| Finished | Oct 02 08:39:16 PM UTC 24 |
| Peak memory | 2597860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542626739 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_wr.1542626739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_stretch.2417321944 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 230998853 ps |
| CPU time | 1.99 seconds |
| Started | Oct 02 08:36:21 PM UTC 24 |
| Finished | Oct 02 08:36:24 PM UTC 24 |
| Peak memory | 214804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417321944 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stretch.2417321944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_timeout.2206990134 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 1346948771 ps |
| CPU time | 11.12 seconds |
| Started | Oct 02 08:36:21 PM UTC 24 |
| Finished | Oct 02 08:36:33 PM UTC 24 |
| Peak memory | 232340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206990 134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_timeout.2206990134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/16.i2c_target_tx_stretch_ctrl.2528177301 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 342250932 ps |
| CPU time | 7.77 seconds |
| Started | Oct 02 08:36:36 PM UTC 24 |
| Finished | Oct 02 08:36:45 PM UTC 24 |
| Peak memory | 215380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528177 301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.2528177301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/16.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_alert_test.3164700462 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 16495129 ps |
| CPU time | 1.05 seconds |
| Started | Oct 02 08:37:32 PM UTC 24 |
| Finished | Oct 02 08:37:34 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164700462 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.3164700462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_host_error_intr.1570282811 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 281495760 ps |
| CPU time | 5.04 seconds |
| Started | Oct 02 08:36:55 PM UTC 24 |
| Finished | Oct 02 08:37:01 PM UTC 24 |
| Peak memory | 242620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570282811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.1570282811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_fmt_empty.3168188529 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 769363943 ps |
| CPU time | 21.42 seconds |
| Started | Oct 02 08:36:42 PM UTC 24 |
| Finished | Oct 02 08:37:05 PM UTC 24 |
| Peak memory | 285388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168188529 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empty.3168188529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_full.1852535278 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 2759466188 ps |
| CPU time | 84.54 seconds |
| Started | Oct 02 08:36:43 PM UTC 24 |
| Finished | Oct 02 08:38:10 PM UTC 24 |
| Peak memory | 627548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852535278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.1852535278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_overflow.2772870999 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 1851955712 ps |
| CPU time | 58.89 seconds |
| Started | Oct 02 08:36:42 PM UTC 24 |
| Finished | Oct 02 08:37:43 PM UTC 24 |
| Peak memory | 623600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772870999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2772870999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_rx.81346880 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 199231434 ps |
| CPU time | 10.35 seconds |
| Started | Oct 02 08:36:43 PM UTC 24 |
| Finished | Oct 02 08:36:55 PM UTC 24 |
| Peak memory | 215248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81346880 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.81346880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_watermark.1745671155 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 10894650187 ps |
| CPU time | 59.15 seconds |
| Started | Oct 02 08:36:42 PM UTC 24 |
| Finished | Oct 02 08:37:43 PM UTC 24 |
| Peak memory | 852712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745671155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.1745671155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_host_may_nack.3231258210 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1934506582 ps |
| CPU time | 8.91 seconds |
| Started | Oct 02 08:37:25 PM UTC 24 |
| Finished | Oct 02 08:37:35 PM UTC 24 |
| Peak memory | 215184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231258210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.3231258210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_host_override.1780260537 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 27335911 ps |
| CPU time | 1.03 seconds |
| Started | Oct 02 08:36:39 PM UTC 24 |
| Finished | Oct 02 08:36:41 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780260537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1780260537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_host_perf.104818732 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 3298082474 ps |
| CPU time | 21.27 seconds |
| Started | Oct 02 08:36:45 PM UTC 24 |
| Finished | Oct 02 08:37:08 PM UTC 24 |
| Peak memory | 414628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104818732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.104818732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_host_perf_precise.1999244515 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 2220881241 ps |
| CPU time | 120.69 seconds |
| Started | Oct 02 08:36:46 PM UTC 24 |
| Finished | Oct 02 08:38:50 PM UTC 24 |
| Peak memory | 416540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999244515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.1999244515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_host_smoke.1011608639 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 2379176847 ps |
| CPU time | 78.71 seconds |
| Started | Oct 02 08:36:39 PM UTC 24 |
| Finished | Oct 02 08:37:59 PM UTC 24 |
| Peak memory | 387948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011608639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.1011608639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_host_stretch_timeout.3782860 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2519294998 ps |
| CPU time | 23.83 seconds |
| Started | Oct 02 08:36:52 PM UTC 24 |
| Finished | Oct 02 08:37:17 PM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_hos t_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.3782860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_bad_addr.4081575231 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 705993284 ps |
| CPU time | 6.86 seconds |
| Started | Oct 02 08:37:22 PM UTC 24 |
| Finished | Oct 02 08:37:30 PM UTC 24 |
| Peak memory | 229664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=4081575231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_ad dr.4081575231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_acq.3418997928 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 207487227 ps |
| CPU time | 1.65 seconds |
| Started | Oct 02 08:37:18 PM UTC 24 |
| Finished | Oct 02 08:37:20 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418997 928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_acq.3418997928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_tx.2442707956 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 439065134 ps |
| CPU time | 1.82 seconds |
| Started | Oct 02 08:37:18 PM UTC 24 |
| Finished | Oct 02 08:37:20 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442707 956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_tx.2442707956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_acq.862468953 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 1050016284 ps |
| CPU time | 3.76 seconds |
| Started | Oct 02 08:37:27 PM UTC 24 |
| Finished | Oct 02 08:37:32 PM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8624689 53 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_watermark s_acq.862468953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_tx.3865898801 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 274638596 ps |
| CPU time | 1.28 seconds |
| Started | Oct 02 08:37:27 PM UTC 24 |
| Finished | Oct 02 08:37:30 PM UTC 24 |
| Peak memory | 214720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865898 801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_watermark s_tx.3865898801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_intr_smoke.3166902622 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 1650682440 ps |
| CPU time | 14.24 seconds |
| Started | Oct 02 08:37:06 PM UTC 24 |
| Finished | Oct 02 08:37:22 PM UTC 24 |
| Peak memory | 231636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316690 2622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_smoke.3166902622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_intr_stress_wr.2366933398 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 22887366636 ps |
| CPU time | 34.16 seconds |
| Started | Oct 02 08:37:09 PM UTC 24 |
| Finished | Oct 02 08:37:45 PM UTC 24 |
| Peak memory | 650212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2366933398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_stres s_wr.2366933398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull.1734754774 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 502697357 ps |
| CPU time | 4.73 seconds |
| Started | Oct 02 08:37:31 PM UTC 24 |
| Finished | Oct 02 08:37:36 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734754 774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_acqfull.1734754774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull_addr.2262839872 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 810117268 ps |
| CPU time | 3.7 seconds |
| Started | Oct 02 08:37:32 PM UTC 24 |
| Finished | Oct 02 08:37:36 PM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262839 872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_acqfull_ad dr.2262839872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_perf.1077333893 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 743069231 ps |
| CPU time | 6.65 seconds |
| Started | Oct 02 08:37:21 PM UTC 24 |
| Finished | Oct 02 08:37:28 PM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077333 893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_perf.1077333893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_smbus_maxlen.3988942382 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 979601073 ps |
| CPU time | 4.21 seconds |
| Started | Oct 02 08:37:30 PM UTC 24 |
| Finished | Oct 02 08:37:36 PM UTC 24 |
| Peak memory | 215160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988942 382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smbus_maxlen.3988942382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_stress_all.4170391333 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 13781454117 ps |
| CPU time | 67.08 seconds |
| Started | Oct 02 08:37:22 PM UTC 24 |
| Finished | Oct 02 08:38:31 PM UTC 24 |
| Peak memory | 420640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417039 1333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_all.4170391333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_stress_rd.1530801943 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 1416366999 ps |
| CPU time | 68.95 seconds |
| Started | Oct 02 08:37:02 PM UTC 24 |
| Finished | Oct 02 08:38:13 PM UTC 24 |
| Peak memory | 227600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530801943 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_rd.1530801943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_stress_wr.3632011791 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 41450424835 ps |
| CPU time | 421.17 seconds |
| Started | Oct 02 08:37:02 PM UTC 24 |
| Finished | Oct 02 08:44:09 PM UTC 24 |
| Peak memory | 5409564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632011791 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_wr.3632011791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_stretch.580370414 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3366906293 ps |
| CPU time | 13.53 seconds |
| Started | Oct 02 08:37:06 PM UTC 24 |
| Finished | Oct 02 08:37:21 PM UTC 24 |
| Peak memory | 379748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580370414 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stretch.580370414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_timeout.4092683675 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 17383682926 ps |
| CPU time | 9.88 seconds |
| Started | Oct 02 08:37:12 PM UTC 24 |
| Finished | Oct 02 08:37:23 PM UTC 24 |
| Peak memory | 232300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092683 675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_timeout.4092683675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/17.i2c_target_tx_stretch_ctrl.3911071314 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 122714689 ps |
| CPU time | 4.49 seconds |
| Started | Oct 02 08:37:29 PM UTC 24 |
| Finished | Oct 02 08:37:35 PM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911071 314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.3911071314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_alert_test.2890129721 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 18227068 ps |
| CPU time | 1.02 seconds |
| Started | Oct 02 08:38:14 PM UTC 24 |
| Finished | Oct 02 08:38:17 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890129721 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.2890129721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_host_error_intr.743631023 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 193932486 ps |
| CPU time | 4.93 seconds |
| Started | Oct 02 08:37:44 PM UTC 24 |
| Finished | Oct 02 08:37:50 PM UTC 24 |
| Peak memory | 231980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743631023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.743631023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_fmt_empty.2255371825 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 435336855 ps |
| CPU time | 9.96 seconds |
| Started | Oct 02 08:37:36 PM UTC 24 |
| Finished | Oct 02 08:37:47 PM UTC 24 |
| Peak memory | 299748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255371825 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empty.2255371825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_full.272565784 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 2842707431 ps |
| CPU time | 81.53 seconds |
| Started | Oct 02 08:37:38 PM UTC 24 |
| Finished | Oct 02 08:39:01 PM UTC 24 |
| Peak memory | 531236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272565784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.272565784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_overflow.3685118508 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 10463608427 ps |
| CPU time | 41.87 seconds |
| Started | Oct 02 08:37:36 PM UTC 24 |
| Finished | Oct 02 08:38:19 PM UTC 24 |
| Peak memory | 556012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685118508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.3685118508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_fmt.30479331 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 85537815 ps |
| CPU time | 1.42 seconds |
| Started | Oct 02 08:37:36 PM UTC 24 |
| Finished | Oct 02 08:37:39 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30479331 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fmt.30479331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_rx.3619279382 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 724280141 ps |
| CPU time | 13.02 seconds |
| Started | Oct 02 08:37:36 PM UTC 24 |
| Finished | Oct 02 08:37:51 PM UTC 24 |
| Peak memory | 248528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619279382 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.3619279382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_watermark.3686113533 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 17822457103 ps |
| CPU time | 111.3 seconds |
| Started | Oct 02 08:37:35 PM UTC 24 |
| Finished | Oct 02 08:39:29 PM UTC 24 |
| Peak memory | 1354528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686113533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3686113533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_host_may_nack.2809288883 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 775626913 ps |
| CPU time | 9.33 seconds |
| Started | Oct 02 08:38:07 PM UTC 24 |
| Finished | Oct 02 08:38:18 PM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809288883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.2809288883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_host_override.706911069 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 28780854 ps |
| CPU time | 1.14 seconds |
| Started | Oct 02 08:37:34 PM UTC 24 |
| Finished | Oct 02 08:37:36 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706911069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.706911069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_host_perf.3926927617 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 12997920907 ps |
| CPU time | 56.12 seconds |
| Started | Oct 02 08:37:38 PM UTC 24 |
| Finished | Oct 02 08:38:35 PM UTC 24 |
| Peak memory | 695076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926927617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.3926927617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_host_perf_precise.2657061674 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 2441923386 ps |
| CPU time | 29.16 seconds |
| Started | Oct 02 08:37:38 PM UTC 24 |
| Finished | Oct 02 08:38:08 PM UTC 24 |
| Peak memory | 237916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657061674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.2657061674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_host_smoke.562159033 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 5289302379 ps |
| CPU time | 59.41 seconds |
| Started | Oct 02 08:37:33 PM UTC 24 |
| Finished | Oct 02 08:38:34 PM UTC 24 |
| Peak memory | 357348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562159033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.562159033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_host_stress_all.3339974375 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 130675492040 ps |
| CPU time | 296.63 seconds |
| Started | Oct 02 08:37:44 PM UTC 24 |
| Finished | Oct 02 08:42:45 PM UTC 24 |
| Peak memory | 2388712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339974375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.3339974375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_host_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_host_stretch_timeout.882291881 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 5253692839 ps |
| CPU time | 14.63 seconds |
| Started | Oct 02 08:37:40 PM UTC 24 |
| Finished | Oct 02 08:37:56 PM UTC 24 |
| Peak memory | 229616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882291881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.882291881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_bad_addr.1837265606 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 4721207236 ps |
| CPU time | 6.03 seconds |
| Started | Oct 02 08:38:05 PM UTC 24 |
| Finished | Oct 02 08:38:12 PM UTC 24 |
| Peak memory | 229716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1837265606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_bad_ad dr.1837265606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_acq.4190431124 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 295861969 ps |
| CPU time | 1.82 seconds |
| Started | Oct 02 08:38:01 PM UTC 24 |
| Finished | Oct 02 08:38:04 PM UTC 24 |
| Peak memory | 214800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190431 124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_acq.4190431124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_tx.3612538509 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 1581978761 ps |
| CPU time | 1.69 seconds |
| Started | Oct 02 08:38:04 PM UTC 24 |
| Finished | Oct 02 08:38:07 PM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612538 509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_tx.3612538509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_acq.3249587961 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 403089953 ps |
| CPU time | 4.86 seconds |
| Started | Oct 02 08:38:08 PM UTC 24 |
| Finished | Oct 02 08:38:14 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249587 961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_watermar ks_acq.3249587961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_tx.2412607980 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 222130051 ps |
| CPU time | 1.26 seconds |
| Started | Oct 02 08:38:09 PM UTC 24 |
| Finished | Oct 02 08:38:12 PM UTC 24 |
| Peak memory | 214960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412607 980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_watermark s_tx.2412607980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_intr_smoke.284279634 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 1083250333 ps |
| CPU time | 9.32 seconds |
| Started | Oct 02 08:37:54 PM UTC 24 |
| Finished | Oct 02 08:38:05 PM UTC 24 |
| Peak memory | 232224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284279 634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_smoke.284279634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull_addr.3492003497 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 660826149 ps |
| CPU time | 5.31 seconds |
| Started | Oct 02 08:38:13 PM UTC 24 |
| Finished | Oct 02 08:38:19 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492003 497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_acqfull_ad dr.3492003497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_perf.3468720757 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 922232038 ps |
| CPU time | 8.88 seconds |
| Started | Oct 02 08:38:04 PM UTC 24 |
| Finished | Oct 02 08:38:14 PM UTC 24 |
| Peak memory | 242532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468720 757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_perf.3468720757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_smbus_maxlen.2811405903 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 492512976 ps |
| CPU time | 3.67 seconds |
| Started | Oct 02 08:38:11 PM UTC 24 |
| Finished | Oct 02 08:38:15 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811405 903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smbus_maxlen.2811405903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_smoke.3708349873 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 984727400 ps |
| CPU time | 15.67 seconds |
| Started | Oct 02 08:37:46 PM UTC 24 |
| Finished | Oct 02 08:38:03 PM UTC 24 |
| Peak memory | 225548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708349873 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smoke.3708349873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_stress_all.2227388339 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 19533137635 ps |
| CPU time | 180.91 seconds |
| Started | Oct 02 08:38:05 PM UTC 24 |
| Finished | Oct 02 08:41:09 PM UTC 24 |
| Peak memory | 2894708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222738 8339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_all.2227388339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_stress_rd.557824310 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 9546275464 ps |
| CPU time | 10.62 seconds |
| Started | Oct 02 08:37:51 PM UTC 24 |
| Finished | Oct 02 08:38:03 PM UTC 24 |
| Peak memory | 229732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557824310 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_rd.557824310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_stress_wr.3082684390 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 48238931048 ps |
| CPU time | 279.26 seconds |
| Started | Oct 02 08:37:48 PM UTC 24 |
| Finished | Oct 02 08:42:31 PM UTC 24 |
| Peak memory | 3748632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082684390 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_wr.3082684390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_stretch.1951054702 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1159990980 ps |
| CPU time | 7.96 seconds |
| Started | Oct 02 08:37:51 PM UTC 24 |
| Finished | Oct 02 08:38:00 PM UTC 24 |
| Peak memory | 234280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951054702 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stretch.1951054702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_timeout.3540414072 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 1535941298 ps |
| CPU time | 12 seconds |
| Started | Oct 02 08:37:57 PM UTC 24 |
| Finished | Oct 02 08:38:10 PM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540414 072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_timeout.3540414072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/18.i2c_target_tx_stretch_ctrl.3322301595 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 124532127 ps |
| CPU time | 3.24 seconds |
| Started | Oct 02 08:38:11 PM UTC 24 |
| Finished | Oct 02 08:38:15 PM UTC 24 |
| Peak memory | 214500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322301 595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.3322301595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_alert_test.2701789261 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 17652133 ps |
| CPU time | 0.9 seconds |
| Started | Oct 02 08:38:54 PM UTC 24 |
| Finished | Oct 02 08:38:56 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701789261 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2701789261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_host_error_intr.2553666237 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 151676931 ps |
| CPU time | 3.12 seconds |
| Started | Oct 02 08:38:21 PM UTC 24 |
| Finished | Oct 02 08:38:26 PM UTC 24 |
| Peak memory | 214628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553666237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.2553666237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_fmt_empty.111396715 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 428687955 ps |
| CPU time | 13.04 seconds |
| Started | Oct 02 08:38:17 PM UTC 24 |
| Finished | Oct 02 08:38:31 PM UTC 24 |
| Peak memory | 312084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111396715 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empty.111396715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_full.2176174214 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2763878379 ps |
| CPU time | 85.91 seconds |
| Started | Oct 02 08:38:18 PM UTC 24 |
| Finished | Oct 02 08:39:46 PM UTC 24 |
| Peak memory | 490292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176174214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2176174214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_overflow.3901660946 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 1860248376 ps |
| CPU time | 47.77 seconds |
| Started | Oct 02 08:38:16 PM UTC 24 |
| Finished | Oct 02 08:39:06 PM UTC 24 |
| Peak memory | 641712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901660946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.3901660946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_fmt.2781553422 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 99241693 ps |
| CPU time | 1.57 seconds |
| Started | Oct 02 08:38:16 PM UTC 24 |
| Finished | Oct 02 08:38:19 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781553422 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fmt.2781553422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_rx.1803593256 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 263473188 ps |
| CPU time | 4.77 seconds |
| Started | Oct 02 08:38:18 PM UTC 24 |
| Finished | Oct 02 08:38:23 PM UTC 24 |
| Peak memory | 215268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803593256 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.1803593256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_watermark.3534483948 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 42716193059 ps |
| CPU time | 356.01 seconds |
| Started | Oct 02 08:38:16 PM UTC 24 |
| Finished | Oct 02 08:44:17 PM UTC 24 |
| Peak memory | 1522416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534483948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3534483948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_host_may_nack.232821409 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 3636277227 ps |
| CPU time | 5.18 seconds |
| Started | Oct 02 08:38:50 PM UTC 24 |
| Finished | Oct 02 08:38:56 PM UTC 24 |
| Peak memory | 215308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232821409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.232821409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_host_override.2860255468 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 65422942 ps |
| CPU time | 1.07 seconds |
| Started | Oct 02 08:38:15 PM UTC 24 |
| Finished | Oct 02 08:38:17 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860255468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.2860255468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_host_perf.1348351871 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 6619820198 ps |
| CPU time | 26.76 seconds |
| Started | Oct 02 08:38:19 PM UTC 24 |
| Finished | Oct 02 08:38:47 PM UTC 24 |
| Peak memory | 291748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348351871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.1348351871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_host_perf_precise.3336310387 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 6173383631 ps |
| CPU time | 236.83 seconds |
| Started | Oct 02 08:38:20 PM UTC 24 |
| Finished | Oct 02 08:42:21 PM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336310387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.3336310387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_host_smoke.825616093 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 8310451133 ps |
| CPU time | 32.44 seconds |
| Started | Oct 02 08:38:15 PM UTC 24 |
| Finished | Oct 02 08:38:49 PM UTC 24 |
| Peak memory | 459556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825616093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.825616093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_host_stretch_timeout.1342386440 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 934324359 ps |
| CPU time | 24.61 seconds |
| Started | Oct 02 08:38:20 PM UTC 24 |
| Finished | Oct 02 08:38:47 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342386440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.1342386440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_bad_addr.1417947285 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 2045627906 ps |
| CPU time | 8.96 seconds |
| Started | Oct 02 08:38:47 PM UTC 24 |
| Finished | Oct 02 08:38:57 PM UTC 24 |
| Peak memory | 229596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1417947285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_ad dr.1417947285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_acq.10765907 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 152641783 ps |
| CPU time | 1.77 seconds |
| Started | Oct 02 08:38:39 PM UTC 24 |
| Finished | Oct 02 08:38:42 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076590 7 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_acq.10765907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_tx.3906783796 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 176255198 ps |
| CPU time | 1.87 seconds |
| Started | Oct 02 08:38:43 PM UTC 24 |
| Finished | Oct 02 08:38:46 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906783 796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_tx.3906783796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_acq.620478118 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 3881360616 ps |
| CPU time | 4.33 seconds |
| Started | Oct 02 08:38:51 PM UTC 24 |
| Finished | Oct 02 08:38:56 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6204781 18 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_watermark s_acq.620478118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_tx.3450889253 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 1094032697 ps |
| CPU time | 1.42 seconds |
| Started | Oct 02 08:38:51 PM UTC 24 |
| Finished | Oct 02 08:38:53 PM UTC 24 |
| Peak memory | 214780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450889 253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_watermark s_tx.3450889253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_hrst.3700260125 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 1151058352 ps |
| CPU time | 3.82 seconds |
| Started | Oct 02 08:38:48 PM UTC 24 |
| Finished | Oct 02 08:38:53 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700260 125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_hrst.3700260125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_intr_smoke.1130792889 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 1201854912 ps |
| CPU time | 10.51 seconds |
| Started | Oct 02 08:38:32 PM UTC 24 |
| Finished | Oct 02 08:38:43 PM UTC 24 |
| Peak memory | 232388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113079 2889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_smoke.1130792889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_intr_stress_wr.272010250 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 15338353454 ps |
| CPU time | 27.29 seconds |
| Started | Oct 02 08:38:32 PM UTC 24 |
| Finished | Oct 02 08:39:00 PM UTC 24 |
| Peak memory | 666472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=272010250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_stress _wr.272010250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull.3648193653 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 1152009195 ps |
| CPU time | 3.13 seconds |
| Started | Oct 02 08:38:53 PM UTC 24 |
| Finished | Oct 02 08:38:57 PM UTC 24 |
| Peak memory | 225504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648193 653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_acqfull.3648193653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull_addr.3083833164 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 530599729 ps |
| CPU time | 4.24 seconds |
| Started | Oct 02 08:38:54 PM UTC 24 |
| Finished | Oct 02 08:38:59 PM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083833 164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_acqfull_ad dr.3083833164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_nack_txstretch.1001140661 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 254675761 ps |
| CPU time | 1.76 seconds |
| Started | Oct 02 08:38:54 PM UTC 24 |
| Finished | Oct 02 08:38:57 PM UTC 24 |
| Peak memory | 231628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001140 661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_txstretch.1001140661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_perf.2281428318 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 789831169 ps |
| CPU time | 4.74 seconds |
| Started | Oct 02 08:38:44 PM UTC 24 |
| Finished | Oct 02 08:38:50 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281428 318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_perf.2281428318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_smbus_maxlen.4247227983 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 1648460776 ps |
| CPU time | 4.14 seconds |
| Started | Oct 02 08:38:52 PM UTC 24 |
| Finished | Oct 02 08:38:57 PM UTC 24 |
| Peak memory | 214996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247227 983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smbus_maxlen.4247227983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_smoke.1653679627 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 867090665 ps |
| CPU time | 26.61 seconds |
| Started | Oct 02 08:38:24 PM UTC 24 |
| Finished | Oct 02 08:38:52 PM UTC 24 |
| Peak memory | 225508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653679627 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smoke.1653679627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_stress_all.515476787 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 20896904393 ps |
| CPU time | 39.34 seconds |
| Started | Oct 02 08:38:46 PM UTC 24 |
| Finished | Oct 02 08:39:27 PM UTC 24 |
| Peak memory | 283632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515476 787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_all.515476787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_stress_rd.1678006030 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 4990102514 ps |
| CPU time | 27.2 seconds |
| Started | Oct 02 08:38:26 PM UTC 24 |
| Finished | Oct 02 08:38:55 PM UTC 24 |
| Peak memory | 248804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678006030 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_rd.1678006030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_stress_wr.2015883499 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 39418659328 ps |
| CPU time | 75.18 seconds |
| Started | Oct 02 08:38:24 PM UTC 24 |
| Finished | Oct 02 08:39:41 PM UTC 24 |
| Peak memory | 1260520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015883499 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_wr.2015883499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_stretch.4268773700 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 4369971149 ps |
| CPU time | 56.91 seconds |
| Started | Oct 02 08:38:27 PM UTC 24 |
| Finished | Oct 02 08:39:26 PM UTC 24 |
| Peak memory | 545628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268773700 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stretch.4268773700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_timeout.3247050128 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 4566804707 ps |
| CPU time | 11.42 seconds |
| Started | Oct 02 08:38:35 PM UTC 24 |
| Finished | Oct 02 08:38:47 PM UTC 24 |
| Peak memory | 232476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247050 128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_timeout.3247050128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/19.i2c_target_tx_stretch_ctrl.2487575106 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 204222335 ps |
| CPU time | 5.15 seconds |
| Started | Oct 02 08:38:52 PM UTC 24 |
| Finished | Oct 02 08:38:58 PM UTC 24 |
| Peak memory | 215448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487575 106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.2487575106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_alert_test.3504555158 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 20364170 ps |
| CPU time | 1.04 seconds |
| Started | Oct 02 08:23:04 PM UTC 24 |
| Finished | Oct 02 08:23:06 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504555158 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.3504555158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_error_intr.1781283797 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 111594163 ps |
| CPU time | 2.83 seconds |
| Started | Oct 02 08:22:06 PM UTC 24 |
| Finished | Oct 02 08:22:09 PM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781283797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1781283797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_fmt_empty.1017338295 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1882847985 ps |
| CPU time | 33.59 seconds |
| Started | Oct 02 08:21:44 PM UTC 24 |
| Finished | Oct 02 08:22:19 PM UTC 24 |
| Peak memory | 326352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017338295 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty.1017338295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_full.799196740 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 22634326009 ps |
| CPU time | 185.9 seconds |
| Started | Oct 02 08:21:46 PM UTC 24 |
| Finished | Oct 02 08:24:55 PM UTC 24 |
| Peak memory | 539460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799196740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.799196740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_overflow.812882014 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 14475544395 ps |
| CPU time | 72.12 seconds |
| Started | Oct 02 08:21:42 PM UTC 24 |
| Finished | Oct 02 08:22:56 PM UTC 24 |
| Peak memory | 729968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812882014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.812882014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_fmt.1342323438 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 411960484 ps |
| CPU time | 1.68 seconds |
| Started | Oct 02 08:21:42 PM UTC 24 |
| Finished | Oct 02 08:21:44 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342323438 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt.1342323438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_rx.1938270010 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 224583087 ps |
| CPU time | 16.46 seconds |
| Started | Oct 02 08:21:46 PM UTC 24 |
| Finished | Oct 02 08:22:04 PM UTC 24 |
| Peak memory | 258884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938270010 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.1938270010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_watermark.2352151692 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 2957267660 ps |
| CPU time | 169.14 seconds |
| Started | Oct 02 08:21:42 PM UTC 24 |
| Finished | Oct 02 08:24:34 PM UTC 24 |
| Peak memory | 940768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352151692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.2352151692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_may_nack.2010407564 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1225791847 ps |
| CPU time | 11.88 seconds |
| Started | Oct 02 08:22:53 PM UTC 24 |
| Finished | Oct 02 08:23:06 PM UTC 24 |
| Peak memory | 215248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010407564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.2010407564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_override.283531392 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 87265259 ps |
| CPU time | 1.14 seconds |
| Started | Oct 02 08:21:40 PM UTC 24 |
| Finished | Oct 02 08:21:43 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283531392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.283531392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_perf.3179686356 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 49061173200 ps |
| CPU time | 272.96 seconds |
| Started | Oct 02 08:21:49 PM UTC 24 |
| Finished | Oct 02 08:26:26 PM UTC 24 |
| Peak memory | 1641180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179686356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.3179686356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_perf_precise.4200497597 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 779854688 ps |
| CPU time | 19.76 seconds |
| Started | Oct 02 08:21:49 PM UTC 24 |
| Finished | Oct 02 08:22:10 PM UTC 24 |
| Peak memory | 215180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200497597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.4200497597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_smoke.2836654921 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1275665037 ps |
| CPU time | 33.29 seconds |
| Started | Oct 02 08:21:38 PM UTC 24 |
| Finished | Oct 02 08:22:13 PM UTC 24 |
| Peak memory | 314208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836654921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.2836654921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_host_stretch_timeout.2280037116 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1923385020 ps |
| CPU time | 23.15 seconds |
| Started | Oct 02 08:22:05 PM UTC 24 |
| Finished | Oct 02 08:22:29 PM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280037116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.2280037116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_sec_cm.3500818632 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 164304176 ps |
| CPU time | 1.36 seconds |
| Started | Oct 02 08:23:04 PM UTC 24 |
| Finished | Oct 02 08:23:07 PM UTC 24 |
| Peak memory | 244448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500818632 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.3500818632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_bad_addr.1754113450 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 5887579989 ps |
| CPU time | 11.94 seconds |
| Started | Oct 02 08:22:33 PM UTC 24 |
| Finished | Oct 02 08:22:46 PM UTC 24 |
| Peak memory | 229656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1754113450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.1754113450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_acq.3418367922 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 807998074 ps |
| CPU time | 2.2 seconds |
| Started | Oct 02 08:22:28 PM UTC 24 |
| Finished | Oct 02 08:22:32 PM UTC 24 |
| Peak memory | 215116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418367 922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_acq.3418367922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_tx.26081129 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 461246034 ps |
| CPU time | 1.33 seconds |
| Started | Oct 02 08:22:29 PM UTC 24 |
| Finished | Oct 02 08:22:32 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608112 9 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_tx.26081129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_acq.3834707162 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 458882068 ps |
| CPU time | 4.65 seconds |
| Started | Oct 02 08:22:54 PM UTC 24 |
| Finished | Oct 02 08:23:00 PM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834707 162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_watermark s_acq.3834707162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_tx.4209726761 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 128319423 ps |
| CPU time | 1.7 seconds |
| Started | Oct 02 08:22:56 PM UTC 24 |
| Finished | Oct 02 08:22:59 PM UTC 24 |
| Peak memory | 214784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209726 761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_watermarks _tx.4209726761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_intr_smoke.916017890 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 2754018793 ps |
| CPU time | 6.82 seconds |
| Started | Oct 02 08:22:20 PM UTC 24 |
| Finished | Oct 02 08:22:28 PM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916017 890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_smoke.916017890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_intr_stress_wr.36159571 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 20493784192 ps |
| CPU time | 180.39 seconds |
| Started | Oct 02 08:22:21 PM UTC 24 |
| Finished | Oct 02 08:25:25 PM UTC 24 |
| Peak memory | 1799020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=36159571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.36159571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull.2399513549 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2054100875 ps |
| CPU time | 4.43 seconds |
| Started | Oct 02 08:23:04 PM UTC 24 |
| Finished | Oct 02 08:23:10 PM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399513 549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_acqfull.2399513549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull_addr.350716524 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1576486222 ps |
| CPU time | 3.45 seconds |
| Started | Oct 02 08:23:04 PM UTC 24 |
| Finished | Oct 02 08:23:09 PM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507165 24 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.350716524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_nack_txstretch.4080271757 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 490200577 ps |
| CPU time | 1.59 seconds |
| Started | Oct 02 08:23:04 PM UTC 24 |
| Finished | Oct 02 08:23:07 PM UTC 24 |
| Peak memory | 231508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080271 757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_txstretch.4080271757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_perf.912710887 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1833140922 ps |
| CPU time | 10.27 seconds |
| Started | Oct 02 08:22:30 PM UTC 24 |
| Finished | Oct 02 08:22:41 PM UTC 24 |
| Peak memory | 242592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9127108 87 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_perf.912710887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_smbus_maxlen.3361341754 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 756583005 ps |
| CPU time | 3.56 seconds |
| Started | Oct 02 08:23:04 PM UTC 24 |
| Finished | Oct 02 08:23:09 PM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361341 754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smbus_maxlen.3361341754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_smoke.1142271052 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 829327498 ps |
| CPU time | 8.39 seconds |
| Started | Oct 02 08:22:11 PM UTC 24 |
| Finished | Oct 02 08:22:20 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142271052 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smoke.1142271052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_stress_rd.708725884 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 819572473 ps |
| CPU time | 9.92 seconds |
| Started | Oct 02 08:22:12 PM UTC 24 |
| Finished | Oct 02 08:22:23 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708725884 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_rd.708725884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_stress_wr.1015272703 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 15356704633 ps |
| CPU time | 36.22 seconds |
| Started | Oct 02 08:22:11 PM UTC 24 |
| Finished | Oct 02 08:22:48 PM UTC 24 |
| Peak memory | 215376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015272703 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_wr.1015272703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_stretch.3456328318 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 273374830 ps |
| CPU time | 4.31 seconds |
| Started | Oct 02 08:22:14 PM UTC 24 |
| Finished | Oct 02 08:22:19 PM UTC 24 |
| Peak memory | 228140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456328318 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stretch.3456328318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_timeout.2289770139 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3382313322 ps |
| CPU time | 11.01 seconds |
| Started | Oct 02 08:22:21 PM UTC 24 |
| Finished | Oct 02 08:22:34 PM UTC 24 |
| Peak memory | 242720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289770 139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_timeout.2289770139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/2.i2c_target_tx_stretch_ctrl.3264227273 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 209449384 ps |
| CPU time | 5.35 seconds |
| Started | Oct 02 08:22:56 PM UTC 24 |
| Finished | Oct 02 08:23:03 PM UTC 24 |
| Peak memory | 215248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264227 273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.3264227273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_alert_test.2100391025 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 40156351 ps |
| CPU time | 0.98 seconds |
| Started | Oct 02 08:39:25 PM UTC 24 |
| Finished | Oct 02 08:39:27 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100391025 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.2100391025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_host_error_intr.614786863 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 384906794 ps |
| CPU time | 1.89 seconds |
| Started | Oct 02 08:38:59 PM UTC 24 |
| Finished | Oct 02 08:39:02 PM UTC 24 |
| Peak memory | 224660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614786863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.614786863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_fmt_empty.92219219 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 7823448562 ps |
| CPU time | 9.59 seconds |
| Started | Oct 02 08:38:57 PM UTC 24 |
| Finished | Oct 02 08:39:07 PM UTC 24 |
| Peak memory | 289568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92219219 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empty.92219219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_full.3560248065 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 3301718511 ps |
| CPU time | 104.83 seconds |
| Started | Oct 02 08:38:58 PM UTC 24 |
| Finished | Oct 02 08:40:45 PM UTC 24 |
| Peak memory | 578528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560248065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.3560248065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_overflow.3116328178 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 2630909609 ps |
| CPU time | 171.81 seconds |
| Started | Oct 02 08:38:57 PM UTC 24 |
| Finished | Oct 02 08:41:51 PM UTC 24 |
| Peak memory | 852712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116328178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3116328178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_fmt.3727966284 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 115826106 ps |
| CPU time | 1.78 seconds |
| Started | Oct 02 08:38:57 PM UTC 24 |
| Finished | Oct 02 08:38:59 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727966284 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fmt.3727966284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_rx.1845102166 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 1194220788 ps |
| CPU time | 14.16 seconds |
| Started | Oct 02 08:38:58 PM UTC 24 |
| Finished | Oct 02 08:39:13 PM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845102166 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.1845102166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_watermark.775072377 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 15886591008 ps |
| CPU time | 96.01 seconds |
| Started | Oct 02 08:38:57 PM UTC 24 |
| Finished | Oct 02 08:40:35 PM UTC 24 |
| Peak memory | 1192752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775072377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.775072377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_host_override.3770431727 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 26909267 ps |
| CPU time | 1.1 seconds |
| Started | Oct 02 08:38:55 PM UTC 24 |
| Finished | Oct 02 08:38:57 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770431727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.3770431727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_host_perf.4052522746 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 5354629059 ps |
| CPU time | 23.08 seconds |
| Started | Oct 02 08:38:58 PM UTC 24 |
| Finished | Oct 02 08:39:22 PM UTC 24 |
| Peak memory | 240316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052522746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.4052522746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_host_perf_precise.2390780733 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 824637667 ps |
| CPU time | 5.03 seconds |
| Started | Oct 02 08:38:58 PM UTC 24 |
| Finished | Oct 02 08:39:04 PM UTC 24 |
| Peak memory | 246632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390780733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.2390780733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_host_smoke.824800335 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 1249656148 ps |
| CPU time | 63.06 seconds |
| Started | Oct 02 08:38:55 PM UTC 24 |
| Finished | Oct 02 08:40:00 PM UTC 24 |
| Peak memory | 357092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824800335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.824800335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_host_stretch_timeout.447337612 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 906728718 ps |
| CPU time | 37.08 seconds |
| Started | Oct 02 08:38:58 PM UTC 24 |
| Finished | Oct 02 08:39:36 PM UTC 24 |
| Peak memory | 225656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447337612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.447337612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_bad_addr.2121500108 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 1022574129 ps |
| CPU time | 8.26 seconds |
| Started | Oct 02 08:39:17 PM UTC 24 |
| Finished | Oct 02 08:39:26 PM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2121500108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_bad_ad dr.2121500108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_acq.3101482856 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 393803289 ps |
| CPU time | 2.18 seconds |
| Started | Oct 02 08:39:16 PM UTC 24 |
| Finished | Oct 02 08:39:19 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101482 856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_acq.3101482856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_tx.3575031964 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 539421379 ps |
| CPU time | 1.47 seconds |
| Started | Oct 02 08:39:16 PM UTC 24 |
| Finished | Oct 02 08:39:18 PM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575031 964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_tx.3575031964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_acq.2905084391 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 467259666 ps |
| CPU time | 4.59 seconds |
| Started | Oct 02 08:39:18 PM UTC 24 |
| Finished | Oct 02 08:39:24 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905084 391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_watermar ks_acq.2905084391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_tx.3641134374 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 1473182550 ps |
| CPU time | 1.38 seconds |
| Started | Oct 02 08:39:19 PM UTC 24 |
| Finished | Oct 02 08:39:22 PM UTC 24 |
| Peak memory | 214780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641134 374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_watermark s_tx.3641134374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_intr_smoke.3750585470 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 5194786561 ps |
| CPU time | 10.89 seconds |
| Started | Oct 02 08:39:04 PM UTC 24 |
| Finished | Oct 02 08:39:16 PM UTC 24 |
| Peak memory | 232280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375058 5470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_smoke.3750585470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_intr_stress_wr.2485607194 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 11767674277 ps |
| CPU time | 91.41 seconds |
| Started | Oct 02 08:39:05 PM UTC 24 |
| Finished | Oct 02 08:40:38 PM UTC 24 |
| Peak memory | 1280924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2485607194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_stres s_wr.2485607194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull.2344893583 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 555770369 ps |
| CPU time | 4.21 seconds |
| Started | Oct 02 08:39:23 PM UTC 24 |
| Finished | Oct 02 08:39:28 PM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344893 583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_acqfull.2344893583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull_addr.3948173291 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 941552160 ps |
| CPU time | 3.65 seconds |
| Started | Oct 02 08:39:24 PM UTC 24 |
| Finished | Oct 02 08:39:28 PM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948173 291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_acqfull_ad dr.3948173291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_nack_txstretch.3977775825 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 1657231158 ps |
| CPU time | 2.33 seconds |
| Started | Oct 02 08:39:24 PM UTC 24 |
| Finished | Oct 02 08:39:27 PM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977775 825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_txstretch.3977775825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_perf.2467831011 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 1918307332 ps |
| CPU time | 4.79 seconds |
| Started | Oct 02 08:39:17 PM UTC 24 |
| Finished | Oct 02 08:39:23 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467831 011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_perf.2467831011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_smbus_maxlen.1818509477 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 2376290804 ps |
| CPU time | 4.05 seconds |
| Started | Oct 02 08:39:22 PM UTC 24 |
| Finished | Oct 02 08:39:27 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818509 477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smbus_maxlen.1818509477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_smoke.194066170 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 6246343472 ps |
| CPU time | 14.6 seconds |
| Started | Oct 02 08:39:00 PM UTC 24 |
| Finished | Oct 02 08:39:16 PM UTC 24 |
| Peak memory | 225888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194066170 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smoke.194066170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_stress_all.2728322597 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 49345210044 ps |
| CPU time | 443.72 seconds |
| Started | Oct 02 08:39:17 PM UTC 24 |
| Finished | Oct 02 08:46:46 PM UTC 24 |
| Peak memory | 2972580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272832 2597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_all.2728322597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_stress_rd.3470773030 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 4583047554 ps |
| CPU time | 22.82 seconds |
| Started | Oct 02 08:39:01 PM UTC 24 |
| Finished | Oct 02 08:39:26 PM UTC 24 |
| Peak memory | 232360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470773030 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_rd.3470773030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_stress_wr.871613422 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 16264414251 ps |
| CPU time | 14.55 seconds |
| Started | Oct 02 08:39:01 PM UTC 24 |
| Finished | Oct 02 08:39:17 PM UTC 24 |
| Peak memory | 215524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871613422 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_wr.871613422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_stretch.2039651222 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 1156672668 ps |
| CPU time | 8.88 seconds |
| Started | Oct 02 08:39:03 PM UTC 24 |
| Finished | Oct 02 08:39:12 PM UTC 24 |
| Peak memory | 250912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039651222 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stretch.2039651222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_timeout.338634396 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 2507543637 ps |
| CPU time | 9.38 seconds |
| Started | Oct 02 08:39:07 PM UTC 24 |
| Finished | Oct 02 08:39:17 PM UTC 24 |
| Peak memory | 225540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386343 96 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_timeout.338634396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/20.i2c_target_tx_stretch_ctrl.1661373247 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 138723314 ps |
| CPU time | 3.33 seconds |
| Started | Oct 02 08:39:19 PM UTC 24 |
| Finished | Oct 02 08:39:24 PM UTC 24 |
| Peak memory | 215444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661373 247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.1661373247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/20.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_alert_test.2561670433 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 22904342 ps |
| CPU time | 1.01 seconds |
| Started | Oct 02 08:40:01 PM UTC 24 |
| Finished | Oct 02 08:40:03 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561670433 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2561670433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_host_error_intr.1423504389 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 1467638291 ps |
| CPU time | 5.15 seconds |
| Started | Oct 02 08:39:30 PM UTC 24 |
| Finished | Oct 02 08:39:36 PM UTC 24 |
| Peak memory | 225792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423504389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.1423504389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_fmt_empty.2848157832 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 313341499 ps |
| CPU time | 7.92 seconds |
| Started | Oct 02 08:39:27 PM UTC 24 |
| Finished | Oct 02 08:39:36 PM UTC 24 |
| Peak memory | 269212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848157832 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empty.2848157832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_full.2989961783 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 2017664398 ps |
| CPU time | 70.68 seconds |
| Started | Oct 02 08:39:29 PM UTC 24 |
| Finished | Oct 02 08:40:41 PM UTC 24 |
| Peak memory | 641768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989961783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.2989961783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_overflow.1765100078 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 4128733934 ps |
| CPU time | 63.8 seconds |
| Started | Oct 02 08:39:27 PM UTC 24 |
| Finished | Oct 02 08:40:33 PM UTC 24 |
| Peak memory | 660456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765100078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.1765100078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_fmt.4141700880 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 1388255949 ps |
| CPU time | 1.28 seconds |
| Started | Oct 02 08:39:27 PM UTC 24 |
| Finished | Oct 02 08:39:29 PM UTC 24 |
| Peak memory | 214964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141700880 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fmt.4141700880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_rx.1033786038 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 606540546 ps |
| CPU time | 3.67 seconds |
| Started | Oct 02 08:39:27 PM UTC 24 |
| Finished | Oct 02 08:39:32 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033786038 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.1033786038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_watermark.1057253397 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 10301628762 ps |
| CPU time | 57.93 seconds |
| Started | Oct 02 08:39:26 PM UTC 24 |
| Finished | Oct 02 08:40:26 PM UTC 24 |
| Peak memory | 910184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057253397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.1057253397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_host_may_nack.4089334659 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 442421356 ps |
| CPU time | 19.51 seconds |
| Started | Oct 02 08:39:54 PM UTC 24 |
| Finished | Oct 02 08:40:15 PM UTC 24 |
| Peak memory | 215168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089334659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.4089334659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_host_override.2341235767 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 37336219 ps |
| CPU time | 1 seconds |
| Started | Oct 02 08:39:26 PM UTC 24 |
| Finished | Oct 02 08:39:28 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341235767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.2341235767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_host_perf.1348667618 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 51406217182 ps |
| CPU time | 767.07 seconds |
| Started | Oct 02 08:39:29 PM UTC 24 |
| Finished | Oct 02 08:52:25 PM UTC 24 |
| Peak memory | 1303328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348667618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.1348667618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_host_perf_precise.3266235660 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 2614724009 ps |
| CPU time | 23.74 seconds |
| Started | Oct 02 08:39:29 PM UTC 24 |
| Finished | Oct 02 08:39:54 PM UTC 24 |
| Peak memory | 486248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266235660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.3266235660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_host_smoke.488767934 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 1466799504 ps |
| CPU time | 77.27 seconds |
| Started | Oct 02 08:39:25 PM UTC 24 |
| Finished | Oct 02 08:40:44 PM UTC 24 |
| Peak memory | 291536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488767934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.488767934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_host_stretch_timeout.714544869 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 3915415121 ps |
| CPU time | 54.7 seconds |
| Started | Oct 02 08:39:29 PM UTC 24 |
| Finished | Oct 02 08:40:25 PM UTC 24 |
| Peak memory | 227760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714544869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.714544869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_bad_addr.1282500986 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 6574737779 ps |
| CPU time | 6.11 seconds |
| Started | Oct 02 08:39:47 PM UTC 24 |
| Finished | Oct 02 08:39:54 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1282500986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_bad_ad dr.1282500986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_acq.2387384046 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 203590388 ps |
| CPU time | 1.39 seconds |
| Started | Oct 02 08:39:45 PM UTC 24 |
| Finished | Oct 02 08:39:48 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387384 046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_acq.2387384046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_tx.3909252749 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 187107328 ps |
| CPU time | 2.15 seconds |
| Started | Oct 02 08:39:45 PM UTC 24 |
| Finished | Oct 02 08:39:48 PM UTC 24 |
| Peak memory | 215308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909252 749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_tx.3909252749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_acq.4212720016 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 467000084 ps |
| CPU time | 4.05 seconds |
| Started | Oct 02 08:39:54 PM UTC 24 |
| Finished | Oct 02 08:39:59 PM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212720 016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_watermar ks_acq.4212720016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_tx.1757582832 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 459783808 ps |
| CPU time | 2.05 seconds |
| Started | Oct 02 08:39:54 PM UTC 24 |
| Finished | Oct 02 08:39:58 PM UTC 24 |
| Peak memory | 215228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757582 832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_watermark s_tx.1757582832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_intr_smoke.1415248974 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 877782364 ps |
| CPU time | 6.46 seconds |
| Started | Oct 02 08:39:37 PM UTC 24 |
| Finished | Oct 02 08:39:45 PM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141524 8974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_smoke.1415248974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_intr_stress_wr.1403790824 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 22847880580 ps |
| CPU time | 80.53 seconds |
| Started | Oct 02 08:39:39 PM UTC 24 |
| Finished | Oct 02 08:41:02 PM UTC 24 |
| Peak memory | 1198948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1403790824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_stres s_wr.1403790824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull.3671595690 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 5140704598 ps |
| CPU time | 3.42 seconds |
| Started | Oct 02 08:39:56 PM UTC 24 |
| Finished | Oct 02 08:40:00 PM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671595 690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_acqfull.3671595690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull_addr.3022581626 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 535289539 ps |
| CPU time | 3.42 seconds |
| Started | Oct 02 08:40:01 PM UTC 24 |
| Finished | Oct 02 08:40:06 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022581 626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_acqfull_ad dr.3022581626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_nack_txstretch.2318923463 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 570048226 ps |
| CPU time | 2.49 seconds |
| Started | Oct 02 08:40:01 PM UTC 24 |
| Finished | Oct 02 08:40:05 PM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318923 463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_txstretch.2318923463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_perf.1672949864 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 9311103269 ps |
| CPU time | 6.99 seconds |
| Started | Oct 02 08:39:46 PM UTC 24 |
| Finished | Oct 02 08:39:54 PM UTC 24 |
| Peak memory | 231836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672949 864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_perf.1672949864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_smbus_maxlen.1768916837 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 1767585237 ps |
| CPU time | 3.44 seconds |
| Started | Oct 02 08:39:56 PM UTC 24 |
| Finished | Oct 02 08:40:00 PM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768916 837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smbus_maxlen.1768916837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_smoke.3328052003 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 3516283095 ps |
| CPU time | 12.33 seconds |
| Started | Oct 02 08:39:30 PM UTC 24 |
| Finished | Oct 02 08:39:43 PM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328052003 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smoke.3328052003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_stress_all.4184009787 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 87963478612 ps |
| CPU time | 110.16 seconds |
| Started | Oct 02 08:39:47 PM UTC 24 |
| Finished | Oct 02 08:41:39 PM UTC 24 |
| Peak memory | 1022824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418400 9787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_all.4184009787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_stress_rd.3434390660 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 305455607 ps |
| CPU time | 5.65 seconds |
| Started | Oct 02 08:39:37 PM UTC 24 |
| Finished | Oct 02 08:39:44 PM UTC 24 |
| Peak memory | 215524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434390660 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_rd.3434390660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_stress_wr.647656070 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 23385045576 ps |
| CPU time | 112.64 seconds |
| Started | Oct 02 08:39:33 PM UTC 24 |
| Finished | Oct 02 08:41:28 PM UTC 24 |
| Peak memory | 944928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647656070 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_wr.647656070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_stretch.1545116620 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 344740556 ps |
| CPU time | 1.87 seconds |
| Started | Oct 02 08:39:37 PM UTC 24 |
| Finished | Oct 02 08:39:40 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545116620 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stretch.1545116620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_timeout.6774160 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 4999226312 ps |
| CPU time | 11.42 seconds |
| Started | Oct 02 08:39:40 PM UTC 24 |
| Finished | Oct 02 08:39:53 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6774160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_timeout.6774160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/21.i2c_target_tx_stretch_ctrl.3591783075 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 228531735 ps |
| CPU time | 6.7 seconds |
| Started | Oct 02 08:39:56 PM UTC 24 |
| Finished | Oct 02 08:40:03 PM UTC 24 |
| Peak memory | 215316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591783 075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.3591783075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/21.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_alert_test.1122611308 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 43407573 ps |
| CPU time | 1 seconds |
| Started | Oct 02 08:40:47 PM UTC 24 |
| Finished | Oct 02 08:40:49 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122611308 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1122611308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_fmt_empty.2473928015 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 461052607 ps |
| CPU time | 14.49 seconds |
| Started | Oct 02 08:40:05 PM UTC 24 |
| Finished | Oct 02 08:40:20 PM UTC 24 |
| Peak memory | 314148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473928015 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empty.2473928015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_full.1718413051 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 15534981360 ps |
| CPU time | 105.85 seconds |
| Started | Oct 02 08:40:06 PM UTC 24 |
| Finished | Oct 02 08:41:54 PM UTC 24 |
| Peak memory | 391952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718413051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.1718413051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_overflow.1303623638 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 3472669770 ps |
| CPU time | 59.11 seconds |
| Started | Oct 02 08:40:02 PM UTC 24 |
| Finished | Oct 02 08:41:04 PM UTC 24 |
| Peak memory | 641768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303623638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.1303623638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_fmt.3305447007 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 1664914417 ps |
| CPU time | 1.63 seconds |
| Started | Oct 02 08:40:05 PM UTC 24 |
| Finished | Oct 02 08:40:07 PM UTC 24 |
| Peak memory | 214884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305447007 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fmt.3305447007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_rx.3552777722 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 1095400261 ps |
| CPU time | 6.33 seconds |
| Started | Oct 02 08:40:05 PM UTC 24 |
| Finished | Oct 02 08:40:12 PM UTC 24 |
| Peak memory | 258668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552777722 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.3552777722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_watermark.3059063990 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 2963983729 ps |
| CPU time | 74.8 seconds |
| Started | Oct 02 08:40:01 PM UTC 24 |
| Finished | Oct 02 08:41:18 PM UTC 24 |
| Peak memory | 949224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059063990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.3059063990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_host_may_nack.1775767467 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 767311922 ps |
| CPU time | 6.68 seconds |
| Started | Oct 02 08:40:39 PM UTC 24 |
| Finished | Oct 02 08:40:47 PM UTC 24 |
| Peak memory | 215240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775767467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.1775767467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_host_override.3165748355 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 89037424 ps |
| CPU time | 0.95 seconds |
| Started | Oct 02 08:40:01 PM UTC 24 |
| Finished | Oct 02 08:40:03 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165748355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.3165748355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_host_perf.2552428469 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 5533554137 ps |
| CPU time | 50.02 seconds |
| Started | Oct 02 08:40:07 PM UTC 24 |
| Finished | Oct 02 08:40:58 PM UTC 24 |
| Peak memory | 555724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552428469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.2552428469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_host_perf_precise.1775039971 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 72633207 ps |
| CPU time | 2.27 seconds |
| Started | Oct 02 08:40:14 PM UTC 24 |
| Finished | Oct 02 08:40:17 PM UTC 24 |
| Peak memory | 231644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775039971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.1775039971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_host_smoke.1024134206 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 5017622620 ps |
| CPU time | 56.35 seconds |
| Started | Oct 02 08:40:01 PM UTC 24 |
| Finished | Oct 02 08:40:59 PM UTC 24 |
| Peak memory | 314340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024134206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.1024134206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_host_stress_all.2483609856 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 53523414885 ps |
| CPU time | 2793.1 seconds |
| Started | Oct 02 08:40:16 PM UTC 24 |
| Finished | Oct 02 09:27:20 PM UTC 24 |
| Peak memory | 4072268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483609856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.2483609856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_host_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_host_stretch_timeout.3801173514 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 404648214 ps |
| CPU time | 24.75 seconds |
| Started | Oct 02 08:40:14 PM UTC 24 |
| Finished | Oct 02 08:40:40 PM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801173514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.3801173514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_bad_addr.2127928243 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1058823393 ps |
| CPU time | 8.28 seconds |
| Started | Oct 02 08:40:38 PM UTC 24 |
| Finished | Oct 02 08:40:47 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2127928243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_ad dr.2127928243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_acq.2812016481 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 249638350 ps |
| CPU time | 1.96 seconds |
| Started | Oct 02 08:40:36 PM UTC 24 |
| Finished | Oct 02 08:40:39 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812016 481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_acq.2812016481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_tx.2710087618 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 194172047 ps |
| CPU time | 1.53 seconds |
| Started | Oct 02 08:40:37 PM UTC 24 |
| Finished | Oct 02 08:40:39 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710087 618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_tx.2710087618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_acq.720248029 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 1728954359 ps |
| CPU time | 4.43 seconds |
| Started | Oct 02 08:40:41 PM UTC 24 |
| Finished | Oct 02 08:40:46 PM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7202480 29 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_watermark s_acq.720248029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_tx.286642503 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 100751755 ps |
| CPU time | 1.58 seconds |
| Started | Oct 02 08:40:41 PM UTC 24 |
| Finished | Oct 02 08:40:43 PM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866425 03 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_watermarks _tx.286642503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_intr_smoke.3562813721 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 779939991 ps |
| CPU time | 7.98 seconds |
| Started | Oct 02 08:40:27 PM UTC 24 |
| Finished | Oct 02 08:40:36 PM UTC 24 |
| Peak memory | 232220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356281 3721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_smoke.3562813721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_intr_stress_wr.3526472581 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 12484103148 ps |
| CPU time | 33.12 seconds |
| Started | Oct 02 08:40:27 PM UTC 24 |
| Finished | Oct 02 08:41:02 PM UTC 24 |
| Peak memory | 727840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3526472581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_stres s_wr.3526472581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull.4216245337 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 673804574 ps |
| CPU time | 4.12 seconds |
| Started | Oct 02 08:40:44 PM UTC 24 |
| Finished | Oct 02 08:40:49 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216245 337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_acqfull.4216245337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_nack_txstretch.524866174 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 167396526 ps |
| CPU time | 2.91 seconds |
| Started | Oct 02 08:40:46 PM UTC 24 |
| Finished | Oct 02 08:40:50 PM UTC 24 |
| Peak memory | 232356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5248661 74 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_txstretch.524866174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_perf.2721692158 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 2557416636 ps |
| CPU time | 8.65 seconds |
| Started | Oct 02 08:40:37 PM UTC 24 |
| Finished | Oct 02 08:40:47 PM UTC 24 |
| Peak memory | 229660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721692 158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_perf.2721692158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_smbus_maxlen.3764190106 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 463083691 ps |
| CPU time | 4.08 seconds |
| Started | Oct 02 08:40:43 PM UTC 24 |
| Finished | Oct 02 08:40:48 PM UTC 24 |
| Peak memory | 215096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764190 106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smbus_maxlen.3764190106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_smoke.998725394 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 773075771 ps |
| CPU time | 31.46 seconds |
| Started | Oct 02 08:40:18 PM UTC 24 |
| Finished | Oct 02 08:40:51 PM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998725394 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smoke.998725394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_stress_all.1295937621 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 24540724345 ps |
| CPU time | 53.38 seconds |
| Started | Oct 02 08:40:38 PM UTC 24 |
| Finished | Oct 02 08:41:33 PM UTC 24 |
| Peak memory | 310060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129593 7621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_all.1295937621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_stress_rd.3299961739 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1138917764 ps |
| CPU time | 14.52 seconds |
| Started | Oct 02 08:40:21 PM UTC 24 |
| Finished | Oct 02 08:40:37 PM UTC 24 |
| Peak memory | 215236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299961739 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_rd.3299961739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_stress_wr.2602523974 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 47159469770 ps |
| CPU time | 37.49 seconds |
| Started | Oct 02 08:40:19 PM UTC 24 |
| Finished | Oct 02 08:40:58 PM UTC 24 |
| Peak memory | 641884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602523974 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_wr.2602523974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_stretch.562422270 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 376411239 ps |
| CPU time | 1.78 seconds |
| Started | Oct 02 08:40:22 PM UTC 24 |
| Finished | Oct 02 08:40:25 PM UTC 24 |
| Peak memory | 214804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562422270 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stretch.562422270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_timeout.428460255 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3345425534 ps |
| CPU time | 9.38 seconds |
| Started | Oct 02 08:40:27 PM UTC 24 |
| Finished | Oct 02 08:40:37 PM UTC 24 |
| Peak memory | 225768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284602 55 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_timeout.428460255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/22.i2c_target_tx_stretch_ctrl.1321464493 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 435300533 ps |
| CPU time | 5.79 seconds |
| Started | Oct 02 08:40:42 PM UTC 24 |
| Finished | Oct 02 08:40:48 PM UTC 24 |
| Peak memory | 215448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321464 493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.1321464493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/22.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_alert_test.4140606465 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 31358309 ps |
| CPU time | 0.99 seconds |
| Started | Oct 02 08:41:19 PM UTC 24 |
| Finished | Oct 02 08:41:21 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140606465 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.4140606465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_host_error_intr.3537636644 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 231727243 ps |
| CPU time | 2.15 seconds |
| Started | Oct 02 08:40:53 PM UTC 24 |
| Finished | Oct 02 08:40:56 PM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537636644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.3537636644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_fmt_empty.852536142 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 384435734 ps |
| CPU time | 18.38 seconds |
| Started | Oct 02 08:40:50 PM UTC 24 |
| Finished | Oct 02 08:41:09 PM UTC 24 |
| Peak memory | 281304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852536142 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empty.852536142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_full.1176370331 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 2862270658 ps |
| CPU time | 192.17 seconds |
| Started | Oct 02 08:40:51 PM UTC 24 |
| Finished | Oct 02 08:44:06 PM UTC 24 |
| Peak memory | 764776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176370331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1176370331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_overflow.3012078689 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 2575601137 ps |
| CPU time | 43.93 seconds |
| Started | Oct 02 08:40:48 PM UTC 24 |
| Finished | Oct 02 08:41:34 PM UTC 24 |
| Peak memory | 541560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012078689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.3012078689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_fmt.3130331618 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 390966437 ps |
| CPU time | 1.49 seconds |
| Started | Oct 02 08:40:50 PM UTC 24 |
| Finished | Oct 02 08:40:52 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130331618 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fmt.3130331618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_rx.338114231 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 325121843 ps |
| CPU time | 6.51 seconds |
| Started | Oct 02 08:40:50 PM UTC 24 |
| Finished | Oct 02 08:40:57 PM UTC 24 |
| Peak memory | 244652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338114231 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.338114231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_watermark.2700564023 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 22748444581 ps |
| CPU time | 143.32 seconds |
| Started | Oct 02 08:40:48 PM UTC 24 |
| Finished | Oct 02 08:43:14 PM UTC 24 |
| Peak memory | 912180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700564023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.2700564023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_host_may_nack.2400237108 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 590960579 ps |
| CPU time | 10.62 seconds |
| Started | Oct 02 08:41:12 PM UTC 24 |
| Finished | Oct 02 08:41:24 PM UTC 24 |
| Peak memory | 215312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400237108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.2400237108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_host_override.1137248613 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 54476793 ps |
| CPU time | 0.97 seconds |
| Started | Oct 02 08:40:48 PM UTC 24 |
| Finished | Oct 02 08:40:50 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137248613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1137248613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_host_perf.2424283808 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 7245123649 ps |
| CPU time | 10.49 seconds |
| Started | Oct 02 08:40:51 PM UTC 24 |
| Finished | Oct 02 08:41:02 PM UTC 24 |
| Peak memory | 242452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424283808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.2424283808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_host_perf_precise.989152330 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 1242043037 ps |
| CPU time | 6.94 seconds |
| Started | Oct 02 08:40:51 PM UTC 24 |
| Finished | Oct 02 08:40:59 PM UTC 24 |
| Peak memory | 215176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989152330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.989152330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_host_smoke.3637847982 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 7963038002 ps |
| CPU time | 101.03 seconds |
| Started | Oct 02 08:40:47 PM UTC 24 |
| Finished | Oct 02 08:42:30 PM UTC 24 |
| Peak memory | 349020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637847982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3637847982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_host_stress_all.2157108102 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 6285732093 ps |
| CPU time | 316.19 seconds |
| Started | Oct 02 08:40:57 PM UTC 24 |
| Finished | Oct 02 08:46:18 PM UTC 24 |
| Peak memory | 1004332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157108102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.2157108102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_host_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_host_stretch_timeout.2094804395 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 4015568430 ps |
| CPU time | 24.88 seconds |
| Started | Oct 02 08:40:52 PM UTC 24 |
| Finished | Oct 02 08:41:18 PM UTC 24 |
| Peak memory | 242664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094804395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.2094804395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_bad_addr.242534778 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 745459432 ps |
| CPU time | 5.91 seconds |
| Started | Oct 02 08:41:08 PM UTC 24 |
| Finished | Oct 02 08:41:16 PM UTC 24 |
| Peak memory | 225632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=242534778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.242534778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_acq.490478766 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 409451047 ps |
| CPU time | 1.51 seconds |
| Started | Oct 02 08:41:04 PM UTC 24 |
| Finished | Oct 02 08:41:06 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4904787 66 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_acq.490478766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_tx.2345706367 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 422499122 ps |
| CPU time | 1.76 seconds |
| Started | Oct 02 08:41:05 PM UTC 24 |
| Finished | Oct 02 08:41:08 PM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345706 367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_tx.2345706367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_acq.1327732911 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 520571717 ps |
| CPU time | 3.48 seconds |
| Started | Oct 02 08:41:14 PM UTC 24 |
| Finished | Oct 02 08:41:19 PM UTC 24 |
| Peak memory | 215036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327732 911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_watermar ks_acq.1327732911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_tx.1548566654 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 1911123675 ps |
| CPU time | 1.7 seconds |
| Started | Oct 02 08:41:15 PM UTC 24 |
| Finished | Oct 02 08:41:18 PM UTC 24 |
| Peak memory | 214708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548566 654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_watermark s_tx.1548566654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_hrst.3215813185 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 362999853 ps |
| CPU time | 3.58 seconds |
| Started | Oct 02 08:41:10 PM UTC 24 |
| Finished | Oct 02 08:41:14 PM UTC 24 |
| Peak memory | 225508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215813 185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_hrst.3215813185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_intr_smoke.1672930923 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 4921925444 ps |
| CPU time | 8.89 seconds |
| Started | Oct 02 08:41:01 PM UTC 24 |
| Finished | Oct 02 08:41:11 PM UTC 24 |
| Peak memory | 232300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167293 0923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_smoke.1672930923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_intr_stress_wr.2636360988 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 14626522923 ps |
| CPU time | 34.33 seconds |
| Started | Oct 02 08:41:03 PM UTC 24 |
| Finished | Oct 02 08:41:38 PM UTC 24 |
| Peak memory | 928540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2636360988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_stres s_wr.2636360988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull.3095222942 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 2261395045 ps |
| CPU time | 3.74 seconds |
| Started | Oct 02 08:41:17 PM UTC 24 |
| Finished | Oct 02 08:41:22 PM UTC 24 |
| Peak memory | 225648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095222 942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_acqfull.3095222942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull_addr.2101362885 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 831644491 ps |
| CPU time | 3.3 seconds |
| Started | Oct 02 08:41:19 PM UTC 24 |
| Finished | Oct 02 08:41:24 PM UTC 24 |
| Peak memory | 215188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101362 885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_acqfull_ad dr.2101362885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_perf.1346633382 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 1836348397 ps |
| CPU time | 7.84 seconds |
| Started | Oct 02 08:41:07 PM UTC 24 |
| Finished | Oct 02 08:41:17 PM UTC 24 |
| Peak memory | 229596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346633 382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_perf.1346633382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_smbus_maxlen.792503837 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 2382526392 ps |
| CPU time | 3.05 seconds |
| Started | Oct 02 08:41:16 PM UTC 24 |
| Finished | Oct 02 08:41:20 PM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7925038 37 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smbus_maxlen.792503837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_smoke.4290427970 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2823701293 ps |
| CPU time | 27.37 seconds |
| Started | Oct 02 08:40:58 PM UTC 24 |
| Finished | Oct 02 08:41:27 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290427970 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smoke.4290427970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_stress_all.2737691554 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 23553547995 ps |
| CPU time | 358.86 seconds |
| Started | Oct 02 08:41:07 PM UTC 24 |
| Finished | Oct 02 08:47:12 PM UTC 24 |
| Peak memory | 4420644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273769 1554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_all.2737691554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_stress_rd.3476606301 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 508389475 ps |
| CPU time | 20.38 seconds |
| Started | Oct 02 08:41:00 PM UTC 24 |
| Finished | Oct 02 08:41:21 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476606301 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_rd.3476606301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_stress_wr.2421920646 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 26283960132 ps |
| CPU time | 36.93 seconds |
| Started | Oct 02 08:40:59 PM UTC 24 |
| Finished | Oct 02 08:41:38 PM UTC 24 |
| Peak memory | 504804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421920646 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_wr.2421920646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_stretch.1028066760 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 4236194386 ps |
| CPU time | 23.18 seconds |
| Started | Oct 02 08:41:00 PM UTC 24 |
| Finished | Oct 02 08:41:24 PM UTC 24 |
| Peak memory | 881500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028066760 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stretch.1028066760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_timeout.236015165 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 1256749500 ps |
| CPU time | 8.72 seconds |
| Started | Oct 02 08:41:03 PM UTC 24 |
| Finished | Oct 02 08:41:13 PM UTC 24 |
| Peak memory | 232300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360151 65 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_timeout.236015165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/23.i2c_target_tx_stretch_ctrl.58819404 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 80342722 ps |
| CPU time | 2.4 seconds |
| Started | Oct 02 08:41:15 PM UTC 24 |
| Finished | Oct 02 08:41:19 PM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5881940 4 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.58819404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/23.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_alert_test.529471847 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 14908308 ps |
| CPU time | 1.02 seconds |
| Started | Oct 02 08:41:55 PM UTC 24 |
| Finished | Oct 02 08:41:57 PM UTC 24 |
| Peak memory | 214256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529471847 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.529471847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_host_error_intr.1472757726 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 69588369 ps |
| CPU time | 2.73 seconds |
| Started | Oct 02 08:41:26 PM UTC 24 |
| Finished | Oct 02 08:41:31 PM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472757726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.1472757726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_fmt_empty.1849903271 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 478292864 ps |
| CPU time | 12.48 seconds |
| Started | Oct 02 08:41:23 PM UTC 24 |
| Finished | Oct 02 08:41:37 PM UTC 24 |
| Peak memory | 311892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849903271 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empty.1849903271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_full.1463165704 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 11508320035 ps |
| CPU time | 82.75 seconds |
| Started | Oct 02 08:41:24 PM UTC 24 |
| Finished | Oct 02 08:42:49 PM UTC 24 |
| Peak memory | 451428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463165704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.1463165704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_overflow.1238957311 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 7299117313 ps |
| CPU time | 51.23 seconds |
| Started | Oct 02 08:41:22 PM UTC 24 |
| Finished | Oct 02 08:42:15 PM UTC 24 |
| Peak memory | 590836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238957311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.1238957311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_fmt.2136493722 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 454757647 ps |
| CPU time | 1.92 seconds |
| Started | Oct 02 08:41:23 PM UTC 24 |
| Finished | Oct 02 08:41:26 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136493722 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fmt.2136493722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_rx.889405710 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 161020341 ps |
| CPU time | 4.36 seconds |
| Started | Oct 02 08:41:23 PM UTC 24 |
| Finished | Oct 02 08:41:29 PM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889405710 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.889405710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_watermark.3529502425 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 28038463949 ps |
| CPU time | 180.99 seconds |
| Started | Oct 02 08:41:22 PM UTC 24 |
| Finished | Oct 02 08:44:26 PM UTC 24 |
| Peak memory | 938720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529502425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.3529502425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_host_may_nack.2474441047 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1265774281 ps |
| CPU time | 4.83 seconds |
| Started | Oct 02 08:41:48 PM UTC 24 |
| Finished | Oct 02 08:41:54 PM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474441047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.2474441047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_host_mode_toggle.266790477 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 355247634 ps |
| CPU time | 4.29 seconds |
| Started | Oct 02 08:41:48 PM UTC 24 |
| Finished | Oct 02 08:41:53 PM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266790477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.266790477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_host_mode_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_host_override.1749592474 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 44539940 ps |
| CPU time | 1.03 seconds |
| Started | Oct 02 08:41:20 PM UTC 24 |
| Finished | Oct 02 08:41:22 PM UTC 24 |
| Peak memory | 214080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749592474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1749592474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_host_perf.1288800828 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 2616561568 ps |
| CPU time | 149.17 seconds |
| Started | Oct 02 08:41:24 PM UTC 24 |
| Finished | Oct 02 08:43:56 PM UTC 24 |
| Peak memory | 822176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288800828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.1288800828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_host_perf_precise.183880087 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 2355178979 ps |
| CPU time | 89.58 seconds |
| Started | Oct 02 08:41:25 PM UTC 24 |
| Finished | Oct 02 08:42:57 PM UTC 24 |
| Peak memory | 235888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183880087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.183880087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_host_smoke.967338789 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 1784388056 ps |
| CPU time | 83.84 seconds |
| Started | Oct 02 08:41:20 PM UTC 24 |
| Finished | Oct 02 08:42:45 PM UTC 24 |
| Peak memory | 357116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967338789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.967338789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_host_stretch_timeout.3485706349 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 773747251 ps |
| CPU time | 20.09 seconds |
| Started | Oct 02 08:41:25 PM UTC 24 |
| Finished | Oct 02 08:41:47 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485706349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3485706349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_bad_addr.2778479451 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 540332308 ps |
| CPU time | 6.19 seconds |
| Started | Oct 02 08:41:46 PM UTC 24 |
| Finished | Oct 02 08:41:53 PM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2778479451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_ad dr.2778479451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_acq.5875539 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 584645050 ps |
| CPU time | 2.39 seconds |
| Started | Oct 02 08:41:40 PM UTC 24 |
| Finished | Oct 02 08:41:44 PM UTC 24 |
| Peak memory | 219432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5875539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_acq.5875539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_tx.3216088368 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 451077098 ps |
| CPU time | 1.52 seconds |
| Started | Oct 02 08:41:43 PM UTC 24 |
| Finished | Oct 02 08:41:46 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216088 368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_tx.3216088368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_acq.1181621772 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 492479990 ps |
| CPU time | 4.33 seconds |
| Started | Oct 02 08:41:50 PM UTC 24 |
| Finished | Oct 02 08:41:55 PM UTC 24 |
| Peak memory | 215308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181621 772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_watermar ks_acq.1181621772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_tx.2747758999 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 145745528 ps |
| CPU time | 2.25 seconds |
| Started | Oct 02 08:41:52 PM UTC 24 |
| Finished | Oct 02 08:41:55 PM UTC 24 |
| Peak memory | 215304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747758 999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_watermark s_tx.2747758999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_intr_smoke.1477991110 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 4511567433 ps |
| CPU time | 7.75 seconds |
| Started | Oct 02 08:41:35 PM UTC 24 |
| Finished | Oct 02 08:41:44 PM UTC 24 |
| Peak memory | 242716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147799 1110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_smoke.1477991110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_intr_stress_wr.1631319227 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 30839634332 ps |
| CPU time | 95.2 seconds |
| Started | Oct 02 08:41:37 PM UTC 24 |
| Finished | Oct 02 08:43:14 PM UTC 24 |
| Peak memory | 1735524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1631319227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_stres s_wr.1631319227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull.148104538 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 531271313 ps |
| CPU time | 5.61 seconds |
| Started | Oct 02 08:41:55 PM UTC 24 |
| Finished | Oct 02 08:42:01 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481045 38 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_acqfull.148104538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull_addr.2551730819 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 584259505 ps |
| CPU time | 5.24 seconds |
| Started | Oct 02 08:41:55 PM UTC 24 |
| Finished | Oct 02 08:42:01 PM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551730 819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_acqfull_ad dr.2551730819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_perf.804047850 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 711732156 ps |
| CPU time | 5.53 seconds |
| Started | Oct 02 08:41:45 PM UTC 24 |
| Finished | Oct 02 08:41:51 PM UTC 24 |
| Peak memory | 227608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8040478 50 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_perf.804047850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_smbus_maxlen.1158732830 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 481090992 ps |
| CPU time | 4.13 seconds |
| Started | Oct 02 08:41:54 PM UTC 24 |
| Finished | Oct 02 08:42:00 PM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158732 830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smbus_maxlen.1158732830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_smoke.760419483 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 4422227456 ps |
| CPU time | 19.56 seconds |
| Started | Oct 02 08:41:29 PM UTC 24 |
| Finished | Oct 02 08:41:50 PM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760419483 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smoke.760419483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_stress_all.130869391 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 77304430894 ps |
| CPU time | 282.26 seconds |
| Started | Oct 02 08:41:45 PM UTC 24 |
| Finished | Oct 02 08:46:30 PM UTC 24 |
| Peak memory | 2427752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130869 391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_all.130869391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_stress_rd.2936282725 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 1216291204 ps |
| CPU time | 26.77 seconds |
| Started | Oct 02 08:41:32 PM UTC 24 |
| Finished | Oct 02 08:42:00 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936282725 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_rd.2936282725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_stress_wr.1555472594 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 57840184217 ps |
| CPU time | 1338.41 seconds |
| Started | Oct 02 08:41:30 PM UTC 24 |
| Finished | Oct 02 09:04:01 PM UTC 24 |
| Peak memory | 9657320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555472594 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_wr.1555472594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_stretch.2521115798 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 6404744137 ps |
| CPU time | 18.13 seconds |
| Started | Oct 02 08:41:34 PM UTC 24 |
| Finished | Oct 02 08:41:53 PM UTC 24 |
| Peak memory | 570220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521115798 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stretch.2521115798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_timeout.3632188258 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1188275379 ps |
| CPU time | 7.57 seconds |
| Started | Oct 02 08:41:38 PM UTC 24 |
| Finished | Oct 02 08:41:47 PM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632188 258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_timeout.3632188258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/24.i2c_target_tx_stretch_ctrl.3194612845 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 288285873 ps |
| CPU time | 7.51 seconds |
| Started | Oct 02 08:41:52 PM UTC 24 |
| Finished | Oct 02 08:42:01 PM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194612 845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.3194612845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/24.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_alert_test.2381653270 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 16408324 ps |
| CPU time | 0.91 seconds |
| Started | Oct 02 08:42:50 PM UTC 24 |
| Finished | Oct 02 08:42:52 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381653270 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.2381653270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_fmt_empty.3964981605 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 285066960 ps |
| CPU time | 17.81 seconds |
| Started | Oct 02 08:42:00 PM UTC 24 |
| Finished | Oct 02 08:42:19 PM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964981605 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empty.3964981605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_full.4270630521 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 3777506007 ps |
| CPU time | 132.8 seconds |
| Started | Oct 02 08:42:01 PM UTC 24 |
| Finished | Oct 02 08:44:17 PM UTC 24 |
| Peak memory | 666328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270630521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.4270630521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_overflow.683626851 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 2232106626 ps |
| CPU time | 148.25 seconds |
| Started | Oct 02 08:41:59 PM UTC 24 |
| Finished | Oct 02 08:44:30 PM UTC 24 |
| Peak memory | 746284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683626851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.683626851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_fmt.3282629831 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 137275104 ps |
| CPU time | 1.94 seconds |
| Started | Oct 02 08:41:59 PM UTC 24 |
| Finished | Oct 02 08:42:02 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282629831 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fmt.3282629831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_rx.1302309248 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 182915828 ps |
| CPU time | 8.1 seconds |
| Started | Oct 02 08:42:01 PM UTC 24 |
| Finished | Oct 02 08:42:11 PM UTC 24 |
| Peak memory | 250660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302309248 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.1302309248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_watermark.1579790700 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 20763267048 ps |
| CPU time | 127.39 seconds |
| Started | Oct 02 08:41:58 PM UTC 24 |
| Finished | Oct 02 08:44:08 PM UTC 24 |
| Peak memory | 1493704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579790700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.1579790700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_host_may_nack.1233487385 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 407343728 ps |
| CPU time | 6.52 seconds |
| Started | Oct 02 08:42:42 PM UTC 24 |
| Finished | Oct 02 08:42:50 PM UTC 24 |
| Peak memory | 215312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233487385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.1233487385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_host_override.1253506573 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 21797214 ps |
| CPU time | 1.03 seconds |
| Started | Oct 02 08:41:56 PM UTC 24 |
| Finished | Oct 02 08:41:58 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253506573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.1253506573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_host_perf.3534703660 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 24130817514 ps |
| CPU time | 877.84 seconds |
| Started | Oct 02 08:42:01 PM UTC 24 |
| Finished | Oct 02 08:56:51 PM UTC 24 |
| Peak memory | 248596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534703660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.3534703660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_host_perf_precise.12694971 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 853574101 ps |
| CPU time | 18.11 seconds |
| Started | Oct 02 08:42:03 PM UTC 24 |
| Finished | Oct 02 08:42:22 PM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12694971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho st_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.12694971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_host_smoke.2912823801 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 1929303920 ps |
| CPU time | 44.02 seconds |
| Started | Oct 02 08:41:56 PM UTC 24 |
| Finished | Oct 02 08:42:41 PM UTC 24 |
| Peak memory | 402116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912823801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.2912823801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_host_stretch_timeout.4205935746 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 2741664108 ps |
| CPU time | 39.78 seconds |
| Started | Oct 02 08:42:03 PM UTC 24 |
| Finished | Oct 02 08:42:44 PM UTC 24 |
| Peak memory | 225640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205935746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.4205935746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_bad_addr.43583823 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 1356758385 ps |
| CPU time | 7.37 seconds |
| Started | Oct 02 08:42:36 PM UTC 24 |
| Finished | Oct 02 08:42:44 PM UTC 24 |
| Peak memory | 229860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=43583823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.43583823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_acq.306150566 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 333425910 ps |
| CPU time | 1.58 seconds |
| Started | Oct 02 08:42:32 PM UTC 24 |
| Finished | Oct 02 08:42:34 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061505 66 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_acq.306150566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_tx.1099024228 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 251343013 ps |
| CPU time | 2.7 seconds |
| Started | Oct 02 08:42:33 PM UTC 24 |
| Finished | Oct 02 08:42:37 PM UTC 24 |
| Peak memory | 217308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099024 228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_tx.1099024228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_acq.3881488494 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 936195354 ps |
| CPU time | 2.18 seconds |
| Started | Oct 02 08:42:45 PM UTC 24 |
| Finished | Oct 02 08:42:49 PM UTC 24 |
| Peak memory | 215036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881488 494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_watermar ks_acq.3881488494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_tx.3018556163 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 177090991 ps |
| CPU time | 2.33 seconds |
| Started | Oct 02 08:42:45 PM UTC 24 |
| Finished | Oct 02 08:42:49 PM UTC 24 |
| Peak memory | 215240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018556 163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_watermark s_tx.3018556163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_intr_smoke.2213211147 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 1067549348 ps |
| CPU time | 8.76 seconds |
| Started | Oct 02 08:42:22 PM UTC 24 |
| Finished | Oct 02 08:42:32 PM UTC 24 |
| Peak memory | 242432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221321 1147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_smoke.2213211147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_intr_stress_wr.2708285217 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 17427553015 ps |
| CPU time | 348.95 seconds |
| Started | Oct 02 08:42:28 PM UTC 24 |
| Finished | Oct 02 08:48:22 PM UTC 24 |
| Peak memory | 4252516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2708285217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_stres s_wr.2708285217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull.922502358 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 488123295 ps |
| CPU time | 3.36 seconds |
| Started | Oct 02 08:42:46 PM UTC 24 |
| Finished | Oct 02 08:42:50 PM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9225023 58 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_acqfull.922502358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull_addr.3642400369 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 585177548 ps |
| CPU time | 3.85 seconds |
| Started | Oct 02 08:42:47 PM UTC 24 |
| Finished | Oct 02 08:42:52 PM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642400 369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_acqfull_ad dr.3642400369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_nack_txstretch.3401402620 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 138175978 ps |
| CPU time | 2.78 seconds |
| Started | Oct 02 08:42:49 PM UTC 24 |
| Finished | Oct 02 08:42:53 PM UTC 24 |
| Peak memory | 232084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401402 620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_txstretch.3401402620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_perf.3247544310 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 1232142561 ps |
| CPU time | 7.73 seconds |
| Started | Oct 02 08:42:35 PM UTC 24 |
| Finished | Oct 02 08:42:44 PM UTC 24 |
| Peak memory | 231784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247544 310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_perf.3247544310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_smbus_maxlen.2639033021 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 481751121 ps |
| CPU time | 4.52 seconds |
| Started | Oct 02 08:42:46 PM UTC 24 |
| Finished | Oct 02 08:42:51 PM UTC 24 |
| Peak memory | 214992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639033 021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smbus_maxlen.2639033021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_smoke.219407371 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 1017324463 ps |
| CPU time | 15.89 seconds |
| Started | Oct 02 08:42:14 PM UTC 24 |
| Finished | Oct 02 08:42:31 PM UTC 24 |
| Peak memory | 225504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219407371 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smoke.219407371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_stress_all.1116500534 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 38305879326 ps |
| CPU time | 747.83 seconds |
| Started | Oct 02 08:42:36 PM UTC 24 |
| Finished | Oct 02 08:55:12 PM UTC 24 |
| Peak memory | 6030184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111650 0534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_all.1116500534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_stress_rd.3420897981 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 255019969 ps |
| CPU time | 13.36 seconds |
| Started | Oct 02 08:42:20 PM UTC 24 |
| Finished | Oct 02 08:42:35 PM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420897981 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_rd.3420897981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_stress_wr.1377456150 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 9811149440 ps |
| CPU time | 28.47 seconds |
| Started | Oct 02 08:42:15 PM UTC 24 |
| Finished | Oct 02 08:42:45 PM UTC 24 |
| Peak memory | 215376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377456150 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_wr.1377456150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_stretch.2008490264 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 468485247 ps |
| CPU time | 5.07 seconds |
| Started | Oct 02 08:42:21 PM UTC 24 |
| Finished | Oct 02 08:42:27 PM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008490264 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stretch.2008490264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_timeout.4258462498 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 4332721239 ps |
| CPU time | 7.47 seconds |
| Started | Oct 02 08:42:32 PM UTC 24 |
| Finished | Oct 02 08:42:40 PM UTC 24 |
| Peak memory | 242664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258462 498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_timeout.4258462498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/25.i2c_target_tx_stretch_ctrl.2989155530 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 118017357 ps |
| CPU time | 2.74 seconds |
| Started | Oct 02 08:42:46 PM UTC 24 |
| Finished | Oct 02 08:42:49 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989155 530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.2989155530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/25.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_alert_test.2787883464 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 34087073 ps |
| CPU time | 0.92 seconds |
| Started | Oct 02 08:43:47 PM UTC 24 |
| Finished | Oct 02 08:43:49 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787883464 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.2787883464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_host_error_intr.4147882237 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 184991953 ps |
| CPU time | 4.51 seconds |
| Started | Oct 02 08:42:58 PM UTC 24 |
| Finished | Oct 02 08:43:04 PM UTC 24 |
| Peak memory | 242580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147882237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.4147882237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_fmt_empty.230260792 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 1622136705 ps |
| CPU time | 10.68 seconds |
| Started | Oct 02 08:42:53 PM UTC 24 |
| Finished | Oct 02 08:43:05 PM UTC 24 |
| Peak memory | 308064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230260792 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empty.230260792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_full.735749376 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 7367861432 ps |
| CPU time | 208.02 seconds |
| Started | Oct 02 08:42:53 PM UTC 24 |
| Finished | Oct 02 08:46:24 PM UTC 24 |
| Peak memory | 566036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735749376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.735749376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_overflow.3659817579 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 1356977356 ps |
| CPU time | 75.41 seconds |
| Started | Oct 02 08:42:51 PM UTC 24 |
| Finished | Oct 02 08:44:09 PM UTC 24 |
| Peak memory | 428772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659817579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.3659817579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_fmt.4134862328 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 278517198 ps |
| CPU time | 1.45 seconds |
| Started | Oct 02 08:42:51 PM UTC 24 |
| Finished | Oct 02 08:42:54 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134862328 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fmt.4134862328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_rx.1393693256 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 878947898 ps |
| CPU time | 17.3 seconds |
| Started | Oct 02 08:42:53 PM UTC 24 |
| Finished | Oct 02 08:43:12 PM UTC 24 |
| Peak memory | 258712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393693256 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.1393693256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_watermark.665401809 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 13988848585 ps |
| CPU time | 233.36 seconds |
| Started | Oct 02 08:42:50 PM UTC 24 |
| Finished | Oct 02 08:46:47 PM UTC 24 |
| Peak memory | 1076068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665401809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.665401809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_host_may_nack.720161246 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 3972586440 ps |
| CPU time | 23.47 seconds |
| Started | Oct 02 08:43:36 PM UTC 24 |
| Finished | Oct 02 08:44:00 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720161246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.720161246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_host_override.930028510 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 29082905 ps |
| CPU time | 0.91 seconds |
| Started | Oct 02 08:42:50 PM UTC 24 |
| Finished | Oct 02 08:42:52 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930028510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.930028510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_host_perf.1444569564 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 676786340 ps |
| CPU time | 4.4 seconds |
| Started | Oct 02 08:42:53 PM UTC 24 |
| Finished | Oct 02 08:42:59 PM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444569564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.1444569564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_host_perf_precise.2268215 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 6595371899 ps |
| CPU time | 34.87 seconds |
| Started | Oct 02 08:42:54 PM UTC 24 |
| Finished | Oct 02 08:43:31 PM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_hos t_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.2268215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_host_smoke.3841914864 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 1075442202 ps |
| CPU time | 46.42 seconds |
| Started | Oct 02 08:42:50 PM UTC 24 |
| Finished | Oct 02 08:43:38 PM UTC 24 |
| Peak memory | 295708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841914864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.3841914864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_host_stretch_timeout.575273297 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 814915781 ps |
| CPU time | 21.31 seconds |
| Started | Oct 02 08:42:55 PM UTC 24 |
| Finished | Oct 02 08:43:18 PM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575273297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.575273297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_bad_addr.3820291310 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 5630454268 ps |
| CPU time | 7.99 seconds |
| Started | Oct 02 08:43:28 PM UTC 24 |
| Finished | Oct 02 08:43:38 PM UTC 24 |
| Peak memory | 231708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3820291310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_bad_ad dr.3820291310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_acq.3912872 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 145665304 ps |
| CPU time | 1.67 seconds |
| Started | Oct 02 08:43:22 PM UTC 24 |
| Finished | Oct 02 08:43:25 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_acq.3912872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_tx.3797045924 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 417501133 ps |
| CPU time | 1.88 seconds |
| Started | Oct 02 08:43:25 PM UTC 24 |
| Finished | Oct 02 08:43:28 PM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797045 924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_tx.3797045924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_acq.1461939695 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 1039623632 ps |
| CPU time | 2.77 seconds |
| Started | Oct 02 08:43:37 PM UTC 24 |
| Finished | Oct 02 08:43:41 PM UTC 24 |
| Peak memory | 215236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461939 695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_watermar ks_acq.1461939695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_tx.1475158203 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 89569067 ps |
| CPU time | 1.6 seconds |
| Started | Oct 02 08:43:39 PM UTC 24 |
| Finished | Oct 02 08:43:42 PM UTC 24 |
| Peak memory | 215020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475158 203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_watermark s_tx.1475158203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_intr_smoke.1186958333 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 827492507 ps |
| CPU time | 5.33 seconds |
| Started | Oct 02 08:43:15 PM UTC 24 |
| Finished | Oct 02 08:43:21 PM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118695 8333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_smoke.1186958333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_intr_stress_wr.2812113612 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 21861936341 ps |
| CPU time | 317.19 seconds |
| Started | Oct 02 08:43:15 PM UTC 24 |
| Finished | Oct 02 08:48:36 PM UTC 24 |
| Peak memory | 3677164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2812113612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_stres s_wr.2812113612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull.4167322353 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 660381906 ps |
| CPU time | 5.07 seconds |
| Started | Oct 02 08:43:42 PM UTC 24 |
| Finished | Oct 02 08:43:48 PM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167322 353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_acqfull.4167322353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull_addr.4207012910 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 366272006 ps |
| CPU time | 3.02 seconds |
| Started | Oct 02 08:43:46 PM UTC 24 |
| Finished | Oct 02 08:43:50 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207012 910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_acqfull_ad dr.4207012910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_nack_txstretch.996077208 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 142658176 ps |
| CPU time | 1.9 seconds |
| Started | Oct 02 08:43:47 PM UTC 24 |
| Finished | Oct 02 08:43:50 PM UTC 24 |
| Peak memory | 231628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9960772 08 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_txstretch.996077208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_perf.1459764618 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 4692322681 ps |
| CPU time | 8.5 seconds |
| Started | Oct 02 08:43:25 PM UTC 24 |
| Finished | Oct 02 08:43:35 PM UTC 24 |
| Peak memory | 234544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459764 618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_perf.1459764618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_smbus_maxlen.3025870202 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 622564109 ps |
| CPU time | 4.47 seconds |
| Started | Oct 02 08:43:41 PM UTC 24 |
| Finished | Oct 02 08:43:47 PM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025870 202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smbus_maxlen.3025870202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_smoke.4247049431 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 487237371 ps |
| CPU time | 14.44 seconds |
| Started | Oct 02 08:43:05 PM UTC 24 |
| Finished | Oct 02 08:43:21 PM UTC 24 |
| Peak memory | 225624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247049431 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smoke.4247049431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_stress_all.2046802300 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 27477873330 ps |
| CPU time | 313.46 seconds |
| Started | Oct 02 08:43:26 PM UTC 24 |
| Finished | Oct 02 08:48:44 PM UTC 24 |
| Peak memory | 4033372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204680 2300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_all.2046802300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_stress_rd.2912470771 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 835891974 ps |
| CPU time | 12.82 seconds |
| Started | Oct 02 08:43:12 PM UTC 24 |
| Finished | Oct 02 08:43:26 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912470771 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_rd.2912470771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_stress_wr.847103183 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 35785616614 ps |
| CPU time | 257.16 seconds |
| Started | Oct 02 08:43:05 PM UTC 24 |
| Finished | Oct 02 08:47:26 PM UTC 24 |
| Peak memory | 3574552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847103183 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_wr.847103183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_stretch.1121996137 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 3175654253 ps |
| CPU time | 171.52 seconds |
| Started | Oct 02 08:43:13 PM UTC 24 |
| Finished | Oct 02 08:46:07 PM UTC 24 |
| Peak memory | 959336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121996137 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stretch.1121996137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_timeout.2133514589 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 1026779271 ps |
| CPU time | 7.56 seconds |
| Started | Oct 02 08:43:19 PM UTC 24 |
| Finished | Oct 02 08:43:28 PM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133514 589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_timeout.2133514589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/26.i2c_target_tx_stretch_ctrl.77465387 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 1287509586 ps |
| CPU time | 20.13 seconds |
| Started | Oct 02 08:43:39 PM UTC 24 |
| Finished | Oct 02 08:44:00 PM UTC 24 |
| Peak memory | 217496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7746538 7 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.77465387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/26.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_alert_test.737929362 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 15580193 ps |
| CPU time | 0.9 seconds |
| Started | Oct 02 08:44:43 PM UTC 24 |
| Finished | Oct 02 08:44:45 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737929362 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.737929362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_host_error_intr.1437452288 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 70797441 ps |
| CPU time | 1.95 seconds |
| Started | Oct 02 08:44:10 PM UTC 24 |
| Finished | Oct 02 08:44:12 PM UTC 24 |
| Peak memory | 224604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437452288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.1437452288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_fmt_empty.833712173 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 3755075628 ps |
| CPU time | 14.35 seconds |
| Started | Oct 02 08:43:57 PM UTC 24 |
| Finished | Oct 02 08:44:12 PM UTC 24 |
| Peak memory | 261036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833712173 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empty.833712173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_full.464207219 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 2500686693 ps |
| CPU time | 64.87 seconds |
| Started | Oct 02 08:44:01 PM UTC 24 |
| Finished | Oct 02 08:45:08 PM UTC 24 |
| Peak memory | 512792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464207219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.464207219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_overflow.1737874499 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 10504695587 ps |
| CPU time | 70.67 seconds |
| Started | Oct 02 08:43:52 PM UTC 24 |
| Finished | Oct 02 08:45:04 PM UTC 24 |
| Peak memory | 832280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737874499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.1737874499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_fmt.2210535459 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 283777529 ps |
| CPU time | 1.36 seconds |
| Started | Oct 02 08:43:54 PM UTC 24 |
| Finished | Oct 02 08:43:56 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210535459 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fmt.2210535459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_rx.957213712 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1011267866 ps |
| CPU time | 16.16 seconds |
| Started | Oct 02 08:43:57 PM UTC 24 |
| Finished | Oct 02 08:44:14 PM UTC 24 |
| Peak memory | 215248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957213712 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.957213712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_watermark.942380173 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 85093106587 ps |
| CPU time | 238.56 seconds |
| Started | Oct 02 08:43:51 PM UTC 24 |
| Finished | Oct 02 08:47:53 PM UTC 24 |
| Peak memory | 1303328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942380173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.942380173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_host_may_nack.2628250514 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 329605805 ps |
| CPU time | 9.76 seconds |
| Started | Oct 02 08:44:34 PM UTC 24 |
| Finished | Oct 02 08:44:45 PM UTC 24 |
| Peak memory | 215156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628250514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2628250514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_host_override.4052447710 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 31981036 ps |
| CPU time | 0.9 seconds |
| Started | Oct 02 08:43:51 PM UTC 24 |
| Finished | Oct 02 08:43:53 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052447710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.4052447710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_host_perf.3469577093 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 3133834101 ps |
| CPU time | 65.74 seconds |
| Started | Oct 02 08:44:01 PM UTC 24 |
| Finished | Oct 02 08:45:08 PM UTC 24 |
| Peak memory | 701144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469577093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.3469577093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_host_perf_precise.2028888406 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 5852488490 ps |
| CPU time | 201.15 seconds |
| Started | Oct 02 08:44:07 PM UTC 24 |
| Finished | Oct 02 08:47:32 PM UTC 24 |
| Peak memory | 1548968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028888406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.2028888406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_host_smoke.2793830072 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 2780287956 ps |
| CPU time | 34.55 seconds |
| Started | Oct 02 08:43:50 PM UTC 24 |
| Finished | Oct 02 08:44:25 PM UTC 24 |
| Peak memory | 340700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793830072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.2793830072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_host_stretch_timeout.2085607104 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 1028751791 ps |
| CPU time | 23.3 seconds |
| Started | Oct 02 08:44:08 PM UTC 24 |
| Finished | Oct 02 08:44:33 PM UTC 24 |
| Peak memory | 225508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085607104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.2085607104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_bad_addr.2438235415 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 2228909044 ps |
| CPU time | 8.74 seconds |
| Started | Oct 02 08:44:31 PM UTC 24 |
| Finished | Oct 02 08:44:41 PM UTC 24 |
| Peak memory | 225768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2438235415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_ad dr.2438235415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_acq.395971338 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 768881359 ps |
| CPU time | 2.53 seconds |
| Started | Oct 02 08:44:26 PM UTC 24 |
| Finished | Oct 02 08:44:30 PM UTC 24 |
| Peak memory | 215268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959713 38 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_acq.395971338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_tx.349881226 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 188076377 ps |
| CPU time | 2.15 seconds |
| Started | Oct 02 08:44:28 PM UTC 24 |
| Finished | Oct 02 08:44:31 PM UTC 24 |
| Peak memory | 215120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498812 26 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_tx.349881226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_acq.3377401571 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 388573084 ps |
| CPU time | 3.91 seconds |
| Started | Oct 02 08:44:36 PM UTC 24 |
| Finished | Oct 02 08:44:41 PM UTC 24 |
| Peak memory | 215236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377401 571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_watermar ks_acq.3377401571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_tx.214449628 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 132021520 ps |
| CPU time | 1.85 seconds |
| Started | Oct 02 08:44:36 PM UTC 24 |
| Finished | Oct 02 08:44:39 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144496 28 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_watermarks _tx.214449628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_hrst.2367206631 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 1139543139 ps |
| CPU time | 3.18 seconds |
| Started | Oct 02 08:44:31 PM UTC 24 |
| Finished | Oct 02 08:44:35 PM UTC 24 |
| Peak memory | 232372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367206 631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_hrst.2367206631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_intr_smoke.2467321647 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 4135834609 ps |
| CPU time | 8.78 seconds |
| Started | Oct 02 08:44:18 PM UTC 24 |
| Finished | Oct 02 08:44:28 PM UTC 24 |
| Peak memory | 229976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246732 1647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_smoke.2467321647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_intr_stress_wr.1531287625 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 1585553482 ps |
| CPU time | 3.95 seconds |
| Started | Oct 02 08:44:22 PM UTC 24 |
| Finished | Oct 02 08:44:27 PM UTC 24 |
| Peak memory | 215584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1531287625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_stres s_wr.1531287625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull.2372309851 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 1043339868 ps |
| CPU time | 5.51 seconds |
| Started | Oct 02 08:44:41 PM UTC 24 |
| Finished | Oct 02 08:44:48 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372309 851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_acqfull.2372309851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull_addr.1219981696 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5620731920 ps |
| CPU time | 5.13 seconds |
| Started | Oct 02 08:44:41 PM UTC 24 |
| Finished | Oct 02 08:44:47 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219981 696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_acqfull_ad dr.1219981696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_nack_txstretch.996651436 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 319435052 ps |
| CPU time | 1.82 seconds |
| Started | Oct 02 08:44:42 PM UTC 24 |
| Finished | Oct 02 08:44:45 PM UTC 24 |
| Peak memory | 231568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9966514 36 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_txstretch.996651436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_perf.830254212 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 872424758 ps |
| CPU time | 9.85 seconds |
| Started | Oct 02 08:44:29 PM UTC 24 |
| Finished | Oct 02 08:44:40 PM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8302542 12 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_perf.830254212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_smbus_maxlen.690151323 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 1882058324 ps |
| CPU time | 3.28 seconds |
| Started | Oct 02 08:44:38 PM UTC 24 |
| Finished | Oct 02 08:44:43 PM UTC 24 |
| Peak memory | 215096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6901513 23 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smbus_maxlen.690151323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_smoke.540144853 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 923990493 ps |
| CPU time | 28.01 seconds |
| Started | Oct 02 08:44:14 PM UTC 24 |
| Finished | Oct 02 08:44:43 PM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540144853 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smoke.540144853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_stress_all.3441492702 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 18389701739 ps |
| CPU time | 95.77 seconds |
| Started | Oct 02 08:44:30 PM UTC 24 |
| Finished | Oct 02 08:46:08 PM UTC 24 |
| Peak memory | 1346424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344149 2702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_all.3441492702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_stress_rd.2282983108 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 2700410240 ps |
| CPU time | 25.22 seconds |
| Started | Oct 02 08:44:15 PM UTC 24 |
| Finished | Oct 02 08:44:41 PM UTC 24 |
| Peak memory | 248752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282983108 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_rd.2282983108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_stress_wr.2785292439 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 15979606169 ps |
| CPU time | 6.07 seconds |
| Started | Oct 02 08:44:14 PM UTC 24 |
| Finished | Oct 02 08:44:21 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785292439 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_wr.2785292439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_stretch.922455175 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 3262635339 ps |
| CPU time | 138.43 seconds |
| Started | Oct 02 08:44:17 PM UTC 24 |
| Finished | Oct 02 08:46:38 PM UTC 24 |
| Peak memory | 879596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922455175 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stretch.922455175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_timeout.1208610677 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 1302943337 ps |
| CPU time | 10.62 seconds |
| Started | Oct 02 08:44:26 PM UTC 24 |
| Finished | Oct 02 08:44:38 PM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208610 677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_timeout.1208610677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/27.i2c_target_tx_stretch_ctrl.4189687366 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 214661286 ps |
| CPU time | 5.32 seconds |
| Started | Oct 02 08:44:36 PM UTC 24 |
| Finished | Oct 02 08:44:43 PM UTC 24 |
| Peak memory | 215444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189687 366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.4189687366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/27.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_alert_test.1077066414 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 34445660 ps |
| CPU time | 1.07 seconds |
| Started | Oct 02 08:45:37 PM UTC 24 |
| Finished | Oct 02 08:45:39 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077066414 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.1077066414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_host_error_intr.1996821408 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 973610476 ps |
| CPU time | 4.94 seconds |
| Started | Oct 02 08:44:53 PM UTC 24 |
| Finished | Oct 02 08:44:59 PM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996821408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.1996821408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_fmt_empty.3088600136 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 321824994 ps |
| CPU time | 18.87 seconds |
| Started | Oct 02 08:44:50 PM UTC 24 |
| Finished | Oct 02 08:45:10 PM UTC 24 |
| Peak memory | 275348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088600136 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empty.3088600136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_full.1843621553 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 3274045836 ps |
| CPU time | 150.24 seconds |
| Started | Oct 02 08:44:50 PM UTC 24 |
| Finished | Oct 02 08:47:23 PM UTC 24 |
| Peak memory | 336884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843621553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.1843621553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_overflow.2480701625 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 4530387992 ps |
| CPU time | 75.16 seconds |
| Started | Oct 02 08:44:44 PM UTC 24 |
| Finished | Oct 02 08:46:02 PM UTC 24 |
| Peak memory | 791536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480701625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.2480701625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_fmt.3775443381 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 1485440392 ps |
| CPU time | 1.95 seconds |
| Started | Oct 02 08:44:50 PM UTC 24 |
| Finished | Oct 02 08:44:53 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775443381 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fmt.3775443381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_rx.263064940 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 133586627 ps |
| CPU time | 5.53 seconds |
| Started | Oct 02 08:44:50 PM UTC 24 |
| Finished | Oct 02 08:44:57 PM UTC 24 |
| Peak memory | 236464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263064940 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.263064940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_watermark.1212063270 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 11884079599 ps |
| CPU time | 78.67 seconds |
| Started | Oct 02 08:44:44 PM UTC 24 |
| Finished | Oct 02 08:46:05 PM UTC 24 |
| Peak memory | 975720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212063270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.1212063270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_host_may_nack.2717893135 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 504110025 ps |
| CPU time | 24.69 seconds |
| Started | Oct 02 08:45:30 PM UTC 24 |
| Finished | Oct 02 08:45:56 PM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717893135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.2717893135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_host_override.1760024719 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 343738655 ps |
| CPU time | 0.98 seconds |
| Started | Oct 02 08:44:44 PM UTC 24 |
| Finished | Oct 02 08:44:46 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760024719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1760024719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_host_perf.4016111565 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 8200344348 ps |
| CPU time | 47.47 seconds |
| Started | Oct 02 08:44:50 PM UTC 24 |
| Finished | Oct 02 08:45:39 PM UTC 24 |
| Peak memory | 233440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016111565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.4016111565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_host_perf_precise.627993896 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 630511322 ps |
| CPU time | 4.15 seconds |
| Started | Oct 02 08:44:50 PM UTC 24 |
| Finished | Oct 02 08:44:56 PM UTC 24 |
| Peak memory | 214960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627993896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.627993896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_host_smoke.1961213877 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 2255099695 ps |
| CPU time | 25.58 seconds |
| Started | Oct 02 08:44:43 PM UTC 24 |
| Finished | Oct 02 08:45:10 PM UTC 24 |
| Peak memory | 375704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961213877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1961213877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_host_stretch_timeout.3200949861 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 1482230221 ps |
| CPU time | 41.1 seconds |
| Started | Oct 02 08:44:50 PM UTC 24 |
| Finished | Oct 02 08:45:33 PM UTC 24 |
| Peak memory | 225504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200949861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.3200949861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_bad_addr.2841259045 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 2810967523 ps |
| CPU time | 9.72 seconds |
| Started | Oct 02 08:45:25 PM UTC 24 |
| Finished | Oct 02 08:45:36 PM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2841259045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_bad_ad dr.2841259045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_acq.1207327216 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 219984648 ps |
| CPU time | 1.77 seconds |
| Started | Oct 02 08:45:18 PM UTC 24 |
| Finished | Oct 02 08:45:21 PM UTC 24 |
| Peak memory | 213984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207327 216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_acq.1207327216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_tx.4199112403 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 192073832 ps |
| CPU time | 1.96 seconds |
| Started | Oct 02 08:45:20 PM UTC 24 |
| Finished | Oct 02 08:45:23 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199112 403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_tx.4199112403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_acq.2334399883 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 1046533242 ps |
| CPU time | 3.47 seconds |
| Started | Oct 02 08:45:31 PM UTC 24 |
| Finished | Oct 02 08:45:36 PM UTC 24 |
| Peak memory | 215236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334399 883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_watermar ks_acq.2334399883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_tx.4092076615 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 77445061 ps |
| CPU time | 1.38 seconds |
| Started | Oct 02 08:45:32 PM UTC 24 |
| Finished | Oct 02 08:45:35 PM UTC 24 |
| Peak memory | 214780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092076 615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_watermark s_tx.4092076615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_hrst.612589455 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 563207470 ps |
| CPU time | 2.87 seconds |
| Started | Oct 02 08:45:25 PM UTC 24 |
| Finished | Oct 02 08:45:29 PM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6125894 55 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_hrst.612589455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_intr_smoke.848619425 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 2839597556 ps |
| CPU time | 9.88 seconds |
| Started | Oct 02 08:45:09 PM UTC 24 |
| Finished | Oct 02 08:45:20 PM UTC 24 |
| Peak memory | 242668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848619 425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_smoke.848619425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_intr_stress_wr.3963733323 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 22856687525 ps |
| CPU time | 185.47 seconds |
| Started | Oct 02 08:45:11 PM UTC 24 |
| Finished | Oct 02 08:48:19 PM UTC 24 |
| Peak memory | 2759524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3963733323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_stres s_wr.3963733323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull.4069342371 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 1850320652 ps |
| CPU time | 4.73 seconds |
| Started | Oct 02 08:45:35 PM UTC 24 |
| Finished | Oct 02 08:45:41 PM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069342 371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_acqfull.4069342371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull_addr.149350106 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 753860711 ps |
| CPU time | 3.53 seconds |
| Started | Oct 02 08:45:37 PM UTC 24 |
| Finished | Oct 02 08:45:41 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493501 06 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_acqfull_addr.149350106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_nack_txstretch.2138080396 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 141664707 ps |
| CPU time | 2.11 seconds |
| Started | Oct 02 08:45:37 PM UTC 24 |
| Finished | Oct 02 08:45:40 PM UTC 24 |
| Peak memory | 232292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138080 396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_txstretch.2138080396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_perf.1800639698 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 782867483 ps |
| CPU time | 7.75 seconds |
| Started | Oct 02 08:45:21 PM UTC 24 |
| Finished | Oct 02 08:45:30 PM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800639 698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_perf.1800639698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_smbus_maxlen.1888149962 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 2009397982 ps |
| CPU time | 5.23 seconds |
| Started | Oct 02 08:45:34 PM UTC 24 |
| Finished | Oct 02 08:45:41 PM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888149 962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smbus_maxlen.1888149962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_smoke.2851718818 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 1300944564 ps |
| CPU time | 22.11 seconds |
| Started | Oct 02 08:44:58 PM UTC 24 |
| Finished | Oct 02 08:45:21 PM UTC 24 |
| Peak memory | 225512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851718818 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smoke.2851718818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_stress_all.3783729994 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 11524157800 ps |
| CPU time | 107.24 seconds |
| Started | Oct 02 08:45:22 PM UTC 24 |
| Finished | Oct 02 08:47:11 PM UTC 24 |
| Peak memory | 990056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378372 9994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_all.3783729994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_stress_rd.2339604315 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 1493346165 ps |
| CPU time | 25.02 seconds |
| Started | Oct 02 08:45:05 PM UTC 24 |
| Finished | Oct 02 08:45:31 PM UTC 24 |
| Peak memory | 244440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339604315 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_rd.2339604315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_stress_wr.3190452208 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 37522424790 ps |
| CPU time | 72.32 seconds |
| Started | Oct 02 08:45:01 PM UTC 24 |
| Finished | Oct 02 08:46:15 PM UTC 24 |
| Peak memory | 1203044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190452208 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_wr.3190452208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_timeout.1342556113 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 6584275484 ps |
| CPU time | 11.2 seconds |
| Started | Oct 02 08:45:11 PM UTC 24 |
| Finished | Oct 02 08:45:23 PM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342556 113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_timeout.1342556113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/28.i2c_target_tx_stretch_ctrl.756426257 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 227435491 ps |
| CPU time | 5.97 seconds |
| Started | Oct 02 08:45:34 PM UTC 24 |
| Finished | Oct 02 08:45:41 PM UTC 24 |
| Peak memory | 215448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7564262 57 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.756426257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_alert_test.3938889945 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 18571422 ps |
| CPU time | 1.08 seconds |
| Started | Oct 02 08:46:28 PM UTC 24 |
| Finished | Oct 02 08:46:31 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938889945 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3938889945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_fmt_empty.178875373 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 1755952182 ps |
| CPU time | 9.87 seconds |
| Started | Oct 02 08:45:42 PM UTC 24 |
| Finished | Oct 02 08:45:53 PM UTC 24 |
| Peak memory | 303836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178875373 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empty.178875373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_full.1883025934 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 20968136769 ps |
| CPU time | 46.25 seconds |
| Started | Oct 02 08:45:43 PM UTC 24 |
| Finished | Oct 02 08:46:31 PM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883025934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.1883025934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_overflow.3946239469 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 1690969965 ps |
| CPU time | 114.17 seconds |
| Started | Oct 02 08:45:42 PM UTC 24 |
| Finished | Oct 02 08:47:38 PM UTC 24 |
| Peak memory | 557864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946239469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.3946239469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_fmt.3361146479 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 435705901 ps |
| CPU time | 1.7 seconds |
| Started | Oct 02 08:45:42 PM UTC 24 |
| Finished | Oct 02 08:45:45 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361146479 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fmt.3361146479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_rx.3125824899 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 259213146 ps |
| CPU time | 8.41 seconds |
| Started | Oct 02 08:45:42 PM UTC 24 |
| Finished | Oct 02 08:45:52 PM UTC 24 |
| Peak memory | 258924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125824899 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.3125824899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_watermark.1034530329 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 3144506689 ps |
| CPU time | 191.29 seconds |
| Started | Oct 02 08:45:41 PM UTC 24 |
| Finished | Oct 02 08:48:56 PM UTC 24 |
| Peak memory | 951020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034530329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1034530329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_may_nack.1208926865 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3073604711 ps |
| CPU time | 7.24 seconds |
| Started | Oct 02 08:46:22 PM UTC 24 |
| Finished | Oct 02 08:46:31 PM UTC 24 |
| Peak memory | 215512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208926865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.1208926865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_override.3458161878 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 33292422 ps |
| CPU time | 1.03 seconds |
| Started | Oct 02 08:45:41 PM UTC 24 |
| Finished | Oct 02 08:45:43 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458161878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3458161878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_perf.2718013880 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 30653365840 ps |
| CPU time | 176.59 seconds |
| Started | Oct 02 08:45:52 PM UTC 24 |
| Finished | Oct 02 08:48:52 PM UTC 24 |
| Peak memory | 225504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718013880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.2718013880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_perf_precise.1760834252 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 687793231 ps |
| CPU time | 10.56 seconds |
| Started | Oct 02 08:45:59 PM UTC 24 |
| Finished | Oct 02 08:46:10 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760834252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.1760834252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_smoke.548318544 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2365992998 ps |
| CPU time | 26.68 seconds |
| Started | Oct 02 08:45:40 PM UTC 24 |
| Finished | Oct 02 08:46:08 PM UTC 24 |
| Peak memory | 314328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548318544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.548318544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_stress_all.3748265964 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 17935259009 ps |
| CPU time | 920.72 seconds |
| Started | Oct 02 08:46:00 PM UTC 24 |
| Finished | Oct 02 09:01:30 PM UTC 24 |
| Peak memory | 3390240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748265964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.3748265964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_host_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_host_stretch_timeout.3142937649 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 3467344264 ps |
| CPU time | 25.69 seconds |
| Started | Oct 02 08:45:59 PM UTC 24 |
| Finished | Oct 02 08:46:26 PM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142937649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.3142937649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_bad_addr.729992076 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 3044660360 ps |
| CPU time | 5.67 seconds |
| Started | Oct 02 08:46:19 PM UTC 24 |
| Finished | Oct 02 08:46:26 PM UTC 24 |
| Peak memory | 225672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=729992076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.729992076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_acq.4246536780 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 205029043 ps |
| CPU time | 1.84 seconds |
| Started | Oct 02 08:46:16 PM UTC 24 |
| Finished | Oct 02 08:46:19 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246536 780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_acq.4246536780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_tx.2355141526 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 567865470 ps |
| CPU time | 1.85 seconds |
| Started | Oct 02 08:46:16 PM UTC 24 |
| Finished | Oct 02 08:46:19 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355141 526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_tx.2355141526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_acq.178981672 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 362625837 ps |
| CPU time | 2.51 seconds |
| Started | Oct 02 08:46:22 PM UTC 24 |
| Finished | Oct 02 08:46:26 PM UTC 24 |
| Peak memory | 215232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789816 72 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_watermark s_acq.178981672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_tx.616894035 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 516682058 ps |
| CPU time | 1.86 seconds |
| Started | Oct 02 08:46:23 PM UTC 24 |
| Finished | Oct 02 08:46:27 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6168940 35 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_watermarks _tx.616894035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_hrst.2151230373 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 1167226985 ps |
| CPU time | 2.63 seconds |
| Started | Oct 02 08:46:19 PM UTC 24 |
| Finished | Oct 02 08:46:23 PM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151230 373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_hrst.2151230373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_intr_smoke.334611043 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 3359990780 ps |
| CPU time | 13.34 seconds |
| Started | Oct 02 08:46:08 PM UTC 24 |
| Finished | Oct 02 08:46:23 PM UTC 24 |
| Peak memory | 248812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334611 043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_smoke.334611043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_intr_stress_wr.2230314147 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 14949631532 ps |
| CPU time | 17.03 seconds |
| Started | Oct 02 08:46:08 PM UTC 24 |
| Finished | Oct 02 08:46:27 PM UTC 24 |
| Peak memory | 510820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2230314147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_stres s_wr.2230314147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull.3970794234 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 3456042266 ps |
| CPU time | 3.03 seconds |
| Started | Oct 02 08:46:27 PM UTC 24 |
| Finished | Oct 02 08:46:31 PM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970794 234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_acqfull.3970794234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull_addr.2609853978 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 1972752544 ps |
| CPU time | 3.06 seconds |
| Started | Oct 02 08:46:27 PM UTC 24 |
| Finished | Oct 02 08:46:31 PM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609853 978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_acqfull_ad dr.2609853978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_perf.349258547 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 466458032 ps |
| CPU time | 4.73 seconds |
| Started | Oct 02 08:46:16 PM UTC 24 |
| Finished | Oct 02 08:46:22 PM UTC 24 |
| Peak memory | 232284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492585 47 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_perf.349258547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_smbus_maxlen.2636192595 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 2380076106 ps |
| CPU time | 3.63 seconds |
| Started | Oct 02 08:46:26 PM UTC 24 |
| Finished | Oct 02 08:46:31 PM UTC 24 |
| Peak memory | 215156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636192 595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smbus_maxlen.2636192595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_smoke.346900718 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 846860928 ps |
| CPU time | 13.64 seconds |
| Started | Oct 02 08:46:00 PM UTC 24 |
| Finished | Oct 02 08:46:15 PM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346900718 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smoke.346900718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_stress_all.2731050581 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 46273429527 ps |
| CPU time | 92.86 seconds |
| Started | Oct 02 08:46:19 PM UTC 24 |
| Finished | Oct 02 08:47:54 PM UTC 24 |
| Peak memory | 1072052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273105 0581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_all.2731050581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_stress_rd.2421762797 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 2853581501 ps |
| CPU time | 76 seconds |
| Started | Oct 02 08:46:03 PM UTC 24 |
| Finished | Oct 02 08:47:21 PM UTC 24 |
| Peak memory | 229732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421762797 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_rd.2421762797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_stress_wr.2961105442 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 24380330270 ps |
| CPU time | 33.36 seconds |
| Started | Oct 02 08:46:03 PM UTC 24 |
| Finished | Oct 02 08:46:38 PM UTC 24 |
| Peak memory | 592744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961105442 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_wr.2961105442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_stretch.1999067868 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 4674990266 ps |
| CPU time | 19.76 seconds |
| Started | Oct 02 08:46:06 PM UTC 24 |
| Finished | Oct 02 08:46:27 PM UTC 24 |
| Peak memory | 369712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999067868 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stretch.1999067868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_timeout.4023535091 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 2672916254 ps |
| CPU time | 11.34 seconds |
| Started | Oct 02 08:46:08 PM UTC 24 |
| Finished | Oct 02 08:46:21 PM UTC 24 |
| Peak memory | 225616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023535 091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_timeout.4023535091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/29.i2c_target_tx_stretch_ctrl.1513463311 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 841639542 ps |
| CPU time | 14.66 seconds |
| Started | Oct 02 08:46:25 PM UTC 24 |
| Finished | Oct 02 08:46:41 PM UTC 24 |
| Peak memory | 215248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513463 311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.1513463311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/29.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_alert_test.2216041869 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 17152708 ps |
| CPU time | 0.91 seconds |
| Started | Oct 02 08:24:56 PM UTC 24 |
| Finished | Oct 02 08:24:57 PM UTC 24 |
| Peak memory | 214256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216041869 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.2216041869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_error_intr.3911264437 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 371902403 ps |
| CPU time | 2.29 seconds |
| Started | Oct 02 08:23:17 PM UTC 24 |
| Finished | Oct 02 08:23:20 PM UTC 24 |
| Peak memory | 227836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911264437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3911264437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_fmt_empty.3620901134 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 789453665 ps |
| CPU time | 14.45 seconds |
| Started | Oct 02 08:23:10 PM UTC 24 |
| Finished | Oct 02 08:23:25 PM UTC 24 |
| Peak memory | 250592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620901134 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty.3620901134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_full.4078195329 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 2343162168 ps |
| CPU time | 143.27 seconds |
| Started | Oct 02 08:23:11 PM UTC 24 |
| Finished | Oct 02 08:25:37 PM UTC 24 |
| Peak memory | 527208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078195329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.4078195329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_overflow.1071868577 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2840214316 ps |
| CPU time | 37.7 seconds |
| Started | Oct 02 08:23:08 PM UTC 24 |
| Finished | Oct 02 08:23:47 PM UTC 24 |
| Peak memory | 428840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071868577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.1071868577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_fmt.21993750 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 416602955 ps |
| CPU time | 1.98 seconds |
| Started | Oct 02 08:23:10 PM UTC 24 |
| Finished | Oct 02 08:23:13 PM UTC 24 |
| Peak memory | 214968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21993750 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt.21993750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_watermark.4112581293 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 22137791479 ps |
| CPU time | 167.44 seconds |
| Started | Oct 02 08:23:08 PM UTC 24 |
| Finished | Oct 02 08:25:58 PM UTC 24 |
| Peak memory | 1569708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112581293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.4112581293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_override.3876369623 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 33706383 ps |
| CPU time | 1.04 seconds |
| Started | Oct 02 08:23:07 PM UTC 24 |
| Finished | Oct 02 08:23:09 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876369623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3876369623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_perf.2200634496 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7515410717 ps |
| CPU time | 115.74 seconds |
| Started | Oct 02 08:23:14 PM UTC 24 |
| Finished | Oct 02 08:25:12 PM UTC 24 |
| Peak memory | 602868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200634496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.2200634496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_perf_precise.2377218486 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 438897728 ps |
| CPU time | 3.36 seconds |
| Started | Oct 02 08:23:16 PM UTC 24 |
| Finished | Oct 02 08:23:20 PM UTC 24 |
| Peak memory | 242320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377218486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.2377218486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_smoke.123078400 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1607615923 ps |
| CPU time | 38.04 seconds |
| Started | Oct 02 08:23:07 PM UTC 24 |
| Finished | Oct 02 08:23:47 PM UTC 24 |
| Peak memory | 340636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123078400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.123078400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_host_stretch_timeout.1323683292 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 615378443 ps |
| CPU time | 12.23 seconds |
| Started | Oct 02 08:23:17 PM UTC 24 |
| Finished | Oct 02 08:23:31 PM UTC 24 |
| Peak memory | 225632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323683292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.1323683292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_sec_cm.406918418 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 141181308 ps |
| CPU time | 1.27 seconds |
| Started | Oct 02 08:24:56 PM UTC 24 |
| Finished | Oct 02 08:24:58 PM UTC 24 |
| Peak memory | 244512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406918418 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.406918418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_bad_addr.1053822108 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1142213001 ps |
| CPU time | 8.98 seconds |
| Started | Oct 02 08:24:05 PM UTC 24 |
| Finished | Oct 02 08:24:15 PM UTC 24 |
| Peak memory | 232344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1053822108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.1053822108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_acq.838323611 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 284554804 ps |
| CPU time | 1.6 seconds |
| Started | Oct 02 08:24:01 PM UTC 24 |
| Finished | Oct 02 08:24:04 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8383236 11 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_acq.838323611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_tx.946077862 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 239211950 ps |
| CPU time | 2.74 seconds |
| Started | Oct 02 08:24:01 PM UTC 24 |
| Finished | Oct 02 08:24:05 PM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9460778 62 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_tx.946077862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_acq.2715300583 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 670029600 ps |
| CPU time | 2.71 seconds |
| Started | Oct 02 08:24:36 PM UTC 24 |
| Finished | Oct 02 08:24:40 PM UTC 24 |
| Peak memory | 215300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715300 583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_watermark s_acq.2715300583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_tx.2041528927 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 786770264 ps |
| CPU time | 1.67 seconds |
| Started | Oct 02 08:24:38 PM UTC 24 |
| Finished | Oct 02 08:24:41 PM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041528 927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_watermarks _tx.2041528927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_intr_smoke.1668715850 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4028851139 ps |
| CPU time | 10.98 seconds |
| Started | Oct 02 08:23:48 PM UTC 24 |
| Finished | Oct 02 08:24:00 PM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166871 5850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_smoke.1668715850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_intr_stress_wr.2165631268 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 17488027164 ps |
| CPU time | 197.14 seconds |
| Started | Oct 02 08:23:48 PM UTC 24 |
| Finished | Oct 02 08:27:08 PM UTC 24 |
| Peak memory | 2702180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2165631268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_stress _wr.2165631268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull.143284675 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1069209818 ps |
| CPU time | 5.68 seconds |
| Started | Oct 02 08:24:48 PM UTC 24 |
| Finished | Oct 02 08:24:55 PM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432846 75 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_acqfull.143284675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull_addr.231658982 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 515290922 ps |
| CPU time | 3.16 seconds |
| Started | Oct 02 08:24:51 PM UTC 24 |
| Finished | Oct 02 08:24:56 PM UTC 24 |
| Peak memory | 215524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316589 82 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.231658982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_nack_txstretch.4137314162 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 275627271 ps |
| CPU time | 2.13 seconds |
| Started | Oct 02 08:24:51 PM UTC 24 |
| Finished | Oct 02 08:24:55 PM UTC 24 |
| Peak memory | 232096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137314 162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_txstretch.4137314162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_perf.2551832434 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 380030622 ps |
| CPU time | 5.68 seconds |
| Started | Oct 02 08:24:04 PM UTC 24 |
| Finished | Oct 02 08:24:11 PM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551832 434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_perf.2551832434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_smbus_maxlen.919742279 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 2230239571 ps |
| CPU time | 5.36 seconds |
| Started | Oct 02 08:24:41 PM UTC 24 |
| Finished | Oct 02 08:24:48 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9197422 79 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smbus_maxlen.919742279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_smoke.2256256044 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 884023557 ps |
| CPU time | 16.92 seconds |
| Started | Oct 02 08:23:21 PM UTC 24 |
| Finished | Oct 02 08:23:39 PM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256256044 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smoke.2256256044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_stress_all.1138808639 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 50107598362 ps |
| CPU time | 848.42 seconds |
| Started | Oct 02 08:24:05 PM UTC 24 |
| Finished | Oct 02 08:38:23 PM UTC 24 |
| Peak memory | 10056736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113880 8639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_all.1138808639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_stress_rd.427307903 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1055433265 ps |
| CPU time | 24.72 seconds |
| Started | Oct 02 08:23:32 PM UTC 24 |
| Finished | Oct 02 08:23:57 PM UTC 24 |
| Peak memory | 234284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427307903 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_rd.427307903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_stress_wr.1672747186 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 49859429025 ps |
| CPU time | 311.21 seconds |
| Started | Oct 02 08:23:26 PM UTC 24 |
| Finished | Oct 02 08:28:42 PM UTC 24 |
| Peak memory | 3513116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672747186 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_wr.1672747186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_stretch.3528969430 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2225796654 ps |
| CPU time | 9.3 seconds |
| Started | Oct 02 08:23:41 PM UTC 24 |
| Finished | Oct 02 08:23:51 PM UTC 24 |
| Peak memory | 451496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528969430 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stretch.3528969430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_timeout.22074008 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1398366625 ps |
| CPU time | 11.61 seconds |
| Started | Oct 02 08:23:52 PM UTC 24 |
| Finished | Oct 02 08:24:05 PM UTC 24 |
| Peak memory | 229660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207400 8 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_timeout.22074008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/3.i2c_target_tx_stretch_ctrl.63579306 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 828812324 ps |
| CPU time | 16.17 seconds |
| Started | Oct 02 08:24:40 PM UTC 24 |
| Finished | Oct 02 08:24:58 PM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6357930 6 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.63579306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_alert_test.3557289581 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 55411143 ps |
| CPU time | 0.99 seconds |
| Started | Oct 02 08:47:01 PM UTC 24 |
| Finished | Oct 02 08:47:03 PM UTC 24 |
| Peak memory | 214256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557289581 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.3557289581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_fmt_empty.981776899 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 450023517 ps |
| CPU time | 27.6 seconds |
| Started | Oct 02 08:46:31 PM UTC 24 |
| Finished | Oct 02 08:47:00 PM UTC 24 |
| Peak memory | 301724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981776899 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empty.981776899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_full.2500278411 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 3700769433 ps |
| CPU time | 131.55 seconds |
| Started | Oct 02 08:46:32 PM UTC 24 |
| Finished | Oct 02 08:48:46 PM UTC 24 |
| Peak memory | 885724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500278411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.2500278411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_overflow.624886884 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 4591233416 ps |
| CPU time | 68.04 seconds |
| Started | Oct 02 08:46:31 PM UTC 24 |
| Finished | Oct 02 08:47:41 PM UTC 24 |
| Peak memory | 650044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624886884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.624886884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_fmt.898517735 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 199440939 ps |
| CPU time | 2.07 seconds |
| Started | Oct 02 08:46:31 PM UTC 24 |
| Finished | Oct 02 08:46:35 PM UTC 24 |
| Peak memory | 215044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898517735 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fmt.898517735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_rx.211533248 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 847265024 ps |
| CPU time | 6.26 seconds |
| Started | Oct 02 08:46:31 PM UTC 24 |
| Finished | Oct 02 08:46:39 PM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211533248 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.211533248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_watermark.744679244 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 4164385271 ps |
| CPU time | 118 seconds |
| Started | Oct 02 08:46:29 PM UTC 24 |
| Finished | Oct 02 08:48:30 PM UTC 24 |
| Peak memory | 1151692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744679244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.744679244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_may_nack.1226310233 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 526584834 ps |
| CPU time | 7.57 seconds |
| Started | Oct 02 08:46:52 PM UTC 24 |
| Finished | Oct 02 08:47:01 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226310233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.1226310233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_override.4098974797 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 45028850 ps |
| CPU time | 1.01 seconds |
| Started | Oct 02 08:46:28 PM UTC 24 |
| Finished | Oct 02 08:46:31 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098974797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.4098974797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_perf.3059663300 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 5252409266 ps |
| CPU time | 43.06 seconds |
| Started | Oct 02 08:46:33 PM UTC 24 |
| Finished | Oct 02 08:47:17 PM UTC 24 |
| Peak memory | 285540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059663300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3059663300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_perf_precise.776083733 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 402190804 ps |
| CPU time | 21.11 seconds |
| Started | Oct 02 08:46:33 PM UTC 24 |
| Finished | Oct 02 08:46:55 PM UTC 24 |
| Peak memory | 264864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776083733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.776083733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_smoke.1719258054 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 4590822586 ps |
| CPU time | 18.42 seconds |
| Started | Oct 02 08:46:28 PM UTC 24 |
| Finished | Oct 02 08:46:48 PM UTC 24 |
| Peak memory | 314264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719258054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1719258054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_host_stretch_timeout.1626754521 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 1434627923 ps |
| CPU time | 16.4 seconds |
| Started | Oct 02 08:46:33 PM UTC 24 |
| Finished | Oct 02 08:46:50 PM UTC 24 |
| Peak memory | 231636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626754521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.1626754521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_bad_addr.1839852384 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 818753995 ps |
| CPU time | 7.2 seconds |
| Started | Oct 02 08:46:51 PM UTC 24 |
| Finished | Oct 02 08:46:59 PM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1839852384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_bad_ad dr.1839852384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_acq.3713637230 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 177263171 ps |
| CPU time | 1.44 seconds |
| Started | Oct 02 08:46:48 PM UTC 24 |
| Finished | Oct 02 08:46:50 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713637 230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_acq.3713637230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_tx.2711346405 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 222319183 ps |
| CPU time | 1.2 seconds |
| Started | Oct 02 08:46:49 PM UTC 24 |
| Finished | Oct 02 08:46:51 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711346 405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_tx.2711346405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_acq.3609720005 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 1637355665 ps |
| CPU time | 4.12 seconds |
| Started | Oct 02 08:46:56 PM UTC 24 |
| Finished | Oct 02 08:47:01 PM UTC 24 |
| Peak memory | 215316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609720 005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_watermar ks_acq.3609720005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_tx.4233816125 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 1290524718 ps |
| CPU time | 1.88 seconds |
| Started | Oct 02 08:46:57 PM UTC 24 |
| Finished | Oct 02 08:46:59 PM UTC 24 |
| Peak memory | 214960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233816 125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_watermark s_tx.4233816125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_intr_smoke.4040850347 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 8838957197 ps |
| CPU time | 7.86 seconds |
| Started | Oct 02 08:46:41 PM UTC 24 |
| Finished | Oct 02 08:46:50 PM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404085 0347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_smoke.4040850347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_intr_stress_wr.4289621952 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 22330124406 ps |
| CPU time | 24.1 seconds |
| Started | Oct 02 08:46:47 PM UTC 24 |
| Finished | Oct 02 08:47:12 PM UTC 24 |
| Peak memory | 465896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4289621952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_stres s_wr.4289621952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull.2644793046 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 471608994 ps |
| CPU time | 3.48 seconds |
| Started | Oct 02 08:46:58 PM UTC 24 |
| Finished | Oct 02 08:47:02 PM UTC 24 |
| Peak memory | 225232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644793 046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_acqfull.2644793046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull_addr.1576663029 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 1257962205 ps |
| CPU time | 3.15 seconds |
| Started | Oct 02 08:47:00 PM UTC 24 |
| Finished | Oct 02 08:47:04 PM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576663 029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_acqfull_ad dr.1576663029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_perf.2897710698 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 441956622 ps |
| CPU time | 3.54 seconds |
| Started | Oct 02 08:46:51 PM UTC 24 |
| Finished | Oct 02 08:46:56 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897710 698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_perf.2897710698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_smbus_maxlen.2322185588 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 1808374828 ps |
| CPU time | 3.66 seconds |
| Started | Oct 02 08:46:57 PM UTC 24 |
| Finished | Oct 02 08:47:01 PM UTC 24 |
| Peak memory | 215132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322185 588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smbus_maxlen.2322185588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_smoke.1065964356 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 829547170 ps |
| CPU time | 12.94 seconds |
| Started | Oct 02 08:46:37 PM UTC 24 |
| Finished | Oct 02 08:46:51 PM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065964356 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smoke.1065964356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_stress_all.2167647732 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 55280296420 ps |
| CPU time | 1154.82 seconds |
| Started | Oct 02 08:46:51 PM UTC 24 |
| Finished | Oct 02 09:06:18 PM UTC 24 |
| Peak memory | 8735512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216764 7732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_all.2167647732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_stress_rd.1701342627 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 1101801425 ps |
| CPU time | 7.88 seconds |
| Started | Oct 02 08:46:38 PM UTC 24 |
| Finished | Oct 02 08:46:47 PM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701342627 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_rd.1701342627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_stress_wr.17554074 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 15695713380 ps |
| CPU time | 6.4 seconds |
| Started | Oct 02 08:46:38 PM UTC 24 |
| Finished | Oct 02 08:46:46 PM UTC 24 |
| Peak memory | 215580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17554074 -assert nopostpro c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_wr.17554074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_timeout.3026931427 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 1154470988 ps |
| CPU time | 9.72 seconds |
| Started | Oct 02 08:46:47 PM UTC 24 |
| Finished | Oct 02 08:46:57 PM UTC 24 |
| Peak memory | 231700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026931 427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_timeout.3026931427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/30.i2c_target_tx_stretch_ctrl.2966220714 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 125837581 ps |
| CPU time | 4.72 seconds |
| Started | Oct 02 08:46:57 PM UTC 24 |
| Finished | Oct 02 08:47:02 PM UTC 24 |
| Peak memory | 215316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966220 714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.2966220714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/30.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_alert_test.2025829310 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 34046935 ps |
| CPU time | 0.98 seconds |
| Started | Oct 02 08:47:39 PM UTC 24 |
| Finished | Oct 02 08:47:41 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025829310 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2025829310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_fmt_empty.3897188633 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 563390366 ps |
| CPU time | 14.77 seconds |
| Started | Oct 02 08:47:04 PM UTC 24 |
| Finished | Oct 02 08:47:19 PM UTC 24 |
| Peak memory | 273124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897188633 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empty.3897188633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_full.1184198008 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 6448312514 ps |
| CPU time | 187.03 seconds |
| Started | Oct 02 08:47:05 PM UTC 24 |
| Finished | Oct 02 08:50:15 PM UTC 24 |
| Peak memory | 535328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184198008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.1184198008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_overflow.3010662750 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 3002899365 ps |
| CPU time | 195.66 seconds |
| Started | Oct 02 08:47:03 PM UTC 24 |
| Finished | Oct 02 08:50:22 PM UTC 24 |
| Peak memory | 873328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010662750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.3010662750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_fmt.3149012451 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 961185608 ps |
| CPU time | 1.61 seconds |
| Started | Oct 02 08:47:04 PM UTC 24 |
| Finished | Oct 02 08:47:06 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149012451 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fmt.3149012451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_rx.2838094659 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 1304891263 ps |
| CPU time | 4.75 seconds |
| Started | Oct 02 08:47:04 PM UTC 24 |
| Finished | Oct 02 08:47:09 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838094659 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.2838094659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_watermark.1356462659 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 11587112956 ps |
| CPU time | 165.39 seconds |
| Started | Oct 02 08:47:02 PM UTC 24 |
| Finished | Oct 02 08:49:51 PM UTC 24 |
| Peak memory | 936736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356462659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.1356462659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_override.126559973 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 43845835 ps |
| CPU time | 1.08 seconds |
| Started | Oct 02 08:47:02 PM UTC 24 |
| Finished | Oct 02 08:47:04 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126559973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.126559973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_perf.946221018 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 5179325862 ps |
| CPU time | 120.03 seconds |
| Started | Oct 02 08:47:05 PM UTC 24 |
| Finished | Oct 02 08:49:07 PM UTC 24 |
| Peak memory | 865124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946221018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.946221018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_perf_precise.2626669657 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 228620276 ps |
| CPU time | 2.52 seconds |
| Started | Oct 02 08:47:07 PM UTC 24 |
| Finished | Oct 02 08:47:11 PM UTC 24 |
| Peak memory | 229472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626669657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.2626669657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_smoke.2367829805 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 4149814720 ps |
| CPU time | 61.7 seconds |
| Started | Oct 02 08:47:01 PM UTC 24 |
| Finished | Oct 02 08:48:05 PM UTC 24 |
| Peak memory | 314148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367829805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.2367829805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_host_stretch_timeout.4115592346 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 1251184552 ps |
| CPU time | 17.79 seconds |
| Started | Oct 02 08:47:10 PM UTC 24 |
| Finished | Oct 02 08:47:29 PM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115592346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.4115592346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_bad_addr.2897485893 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 7343899148 ps |
| CPU time | 6.81 seconds |
| Started | Oct 02 08:47:29 PM UTC 24 |
| Finished | Oct 02 08:47:38 PM UTC 24 |
| Peak memory | 231764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2897485893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_ad dr.2897485893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_acq.2624701948 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 619834013 ps |
| CPU time | 1.78 seconds |
| Started | Oct 02 08:47:25 PM UTC 24 |
| Finished | Oct 02 08:47:28 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624701 948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_acq.2624701948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_tx.2109586709 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 689546886 ps |
| CPU time | 1.9 seconds |
| Started | Oct 02 08:47:27 PM UTC 24 |
| Finished | Oct 02 08:47:30 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109586 709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_tx.2109586709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_acq.286908584 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 870885433 ps |
| CPU time | 3.3 seconds |
| Started | Oct 02 08:47:33 PM UTC 24 |
| Finished | Oct 02 08:47:37 PM UTC 24 |
| Peak memory | 214620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869085 84 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_watermark s_acq.286908584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_tx.2215016939 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 83874062 ps |
| CPU time | 1.47 seconds |
| Started | Oct 02 08:47:33 PM UTC 24 |
| Finished | Oct 02 08:47:36 PM UTC 24 |
| Peak memory | 214780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215016 939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_watermark s_tx.2215016939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_hrst.3044599848 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 1062928275 ps |
| CPU time | 3.07 seconds |
| Started | Oct 02 08:47:30 PM UTC 24 |
| Finished | Oct 02 08:47:34 PM UTC 24 |
| Peak memory | 225640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044599 848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_hrst.3044599848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_intr_smoke.2861319854 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 10597370948 ps |
| CPU time | 4.99 seconds |
| Started | Oct 02 08:47:18 PM UTC 24 |
| Finished | Oct 02 08:47:24 PM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286131 9854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_smoke.2861319854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_intr_stress_wr.480131695 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 2468844588 ps |
| CPU time | 9.54 seconds |
| Started | Oct 02 08:47:21 PM UTC 24 |
| Finished | Oct 02 08:47:31 PM UTC 24 |
| Peak memory | 215372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=480131695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_stress _wr.480131695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull.720804152 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2123089422 ps |
| CPU time | 3.4 seconds |
| Started | Oct 02 08:47:36 PM UTC 24 |
| Finished | Oct 02 08:47:41 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7208041 52 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_acqfull.720804152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull_addr.171958101 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 8458289298 ps |
| CPU time | 4.32 seconds |
| Started | Oct 02 08:47:36 PM UTC 24 |
| Finished | Oct 02 08:47:42 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719581 01 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_acqfull_addr.171958101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_nack_txstretch.3165747037 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 580267566 ps |
| CPU time | 2.68 seconds |
| Started | Oct 02 08:47:37 PM UTC 24 |
| Finished | Oct 02 08:47:41 PM UTC 24 |
| Peak memory | 232028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165747 037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_txstretch.3165747037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_perf.183787885 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 456613875 ps |
| CPU time | 5.72 seconds |
| Started | Oct 02 08:47:28 PM UTC 24 |
| Finished | Oct 02 08:47:36 PM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837878 85 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_perf.183787885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_smbus_maxlen.3717760342 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 1544953552 ps |
| CPU time | 3.67 seconds |
| Started | Oct 02 08:47:35 PM UTC 24 |
| Finished | Oct 02 08:47:40 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717760 342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smbus_maxlen.3717760342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_smoke.53067988 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 2286296212 ps |
| CPU time | 16.57 seconds |
| Started | Oct 02 08:47:12 PM UTC 24 |
| Finished | Oct 02 08:47:30 PM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53067988 -assert nopostpro c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smoke.53067988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_stress_all.523257265 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 58506364095 ps |
| CPU time | 116.97 seconds |
| Started | Oct 02 08:47:28 PM UTC 24 |
| Finished | Oct 02 08:49:28 PM UTC 24 |
| Peak memory | 887736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523257 265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_all.523257265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_stress_rd.2502764358 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 4673089195 ps |
| CPU time | 54.29 seconds |
| Started | Oct 02 08:47:14 PM UTC 24 |
| Finished | Oct 02 08:48:10 PM UTC 24 |
| Peak memory | 232288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502764358 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_rd.2502764358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_stress_wr.19342649 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 58177149411 ps |
| CPU time | 223.32 seconds |
| Started | Oct 02 08:47:12 PM UTC 24 |
| Finished | Oct 02 08:50:59 PM UTC 24 |
| Peak memory | 2429856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19342649 -assert nopostpro c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_wr.19342649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_stretch.694440245 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 1368510228 ps |
| CPU time | 12.07 seconds |
| Started | Oct 02 08:47:16 PM UTC 24 |
| Finished | Oct 02 08:47:29 PM UTC 24 |
| Peak memory | 277464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694440245 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stretch.694440245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_timeout.4025752181 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 5854159623 ps |
| CPU time | 9.9 seconds |
| Started | Oct 02 08:47:22 PM UTC 24 |
| Finished | Oct 02 08:47:33 PM UTC 24 |
| Peak memory | 232428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025752 181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_timeout.4025752181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/31.i2c_target_tx_stretch_ctrl.1602594563 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 118805932 ps |
| CPU time | 3.01 seconds |
| Started | Oct 02 08:47:34 PM UTC 24 |
| Finished | Oct 02 08:47:38 PM UTC 24 |
| Peak memory | 215316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602594 563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.1602594563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/31.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_alert_test.703738942 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 18316090 ps |
| CPU time | 1 seconds |
| Started | Oct 02 08:48:15 PM UTC 24 |
| Finished | Oct 02 08:48:17 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703738942 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.703738942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_error_intr.1100260620 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 345903386 ps |
| CPU time | 1.4 seconds |
| Started | Oct 02 08:47:42 PM UTC 24 |
| Finished | Oct 02 08:47:45 PM UTC 24 |
| Peak memory | 224604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100260620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1100260620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_fmt_empty.3873923904 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 330504213 ps |
| CPU time | 5.22 seconds |
| Started | Oct 02 08:47:41 PM UTC 24 |
| Finished | Oct 02 08:47:47 PM UTC 24 |
| Peak memory | 244436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873923904 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empty.3873923904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_full.2988745375 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 2294159617 ps |
| CPU time | 67.67 seconds |
| Started | Oct 02 08:47:42 PM UTC 24 |
| Finished | Oct 02 08:48:52 PM UTC 24 |
| Peak memory | 623316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988745375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2988745375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_overflow.3038625769 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 1797686336 ps |
| CPU time | 57.71 seconds |
| Started | Oct 02 08:47:40 PM UTC 24 |
| Finished | Oct 02 08:48:39 PM UTC 24 |
| Peak memory | 603060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038625769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.3038625769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_fmt.2912983228 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 107535349 ps |
| CPU time | 1.78 seconds |
| Started | Oct 02 08:47:41 PM UTC 24 |
| Finished | Oct 02 08:47:44 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912983228 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fmt.2912983228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_rx.253235013 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 464502605 ps |
| CPU time | 11.14 seconds |
| Started | Oct 02 08:47:42 PM UTC 24 |
| Finished | Oct 02 08:47:55 PM UTC 24 |
| Peak memory | 236156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253235013 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.253235013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_watermark.4206095364 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 3401313868 ps |
| CPU time | 194.9 seconds |
| Started | Oct 02 08:47:39 PM UTC 24 |
| Finished | Oct 02 08:50:57 PM UTC 24 |
| Peak memory | 1008564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206095364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.4206095364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_may_nack.3099431611 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 1618552821 ps |
| CPU time | 8.46 seconds |
| Started | Oct 02 08:48:06 PM UTC 24 |
| Finished | Oct 02 08:48:16 PM UTC 24 |
| Peak memory | 215240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099431611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.3099431611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_mode_toggle.2486455425 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 267066739 ps |
| CPU time | 1.87 seconds |
| Started | Oct 02 08:48:06 PM UTC 24 |
| Finished | Oct 02 08:48:09 PM UTC 24 |
| Peak memory | 224836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486455425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.2486455425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_host_mode_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_override.3229243917 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 30391234 ps |
| CPU time | 1.09 seconds |
| Started | Oct 02 08:47:39 PM UTC 24 |
| Finished | Oct 02 08:47:41 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229243917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3229243917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_perf.3591262866 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 3569176693 ps |
| CPU time | 21.12 seconds |
| Started | Oct 02 08:47:42 PM UTC 24 |
| Finished | Oct 02 08:48:05 PM UTC 24 |
| Peak memory | 269100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591262866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.3591262866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_perf_precise.3685316890 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 24341350194 ps |
| CPU time | 303.94 seconds |
| Started | Oct 02 08:47:42 PM UTC 24 |
| Finished | Oct 02 08:52:51 PM UTC 24 |
| Peak memory | 215316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685316890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.3685316890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_smoke.1934043585 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 1686072156 ps |
| CPU time | 94.26 seconds |
| Started | Oct 02 08:47:39 PM UTC 24 |
| Finished | Oct 02 08:49:15 PM UTC 24 |
| Peak memory | 373452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934043585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.1934043585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_host_stretch_timeout.3116871765 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 957630118 ps |
| CPU time | 26.2 seconds |
| Started | Oct 02 08:47:42 PM UTC 24 |
| Finished | Oct 02 08:48:10 PM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116871765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.3116871765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_bad_addr.3175779437 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 1234325137 ps |
| CPU time | 9.64 seconds |
| Started | Oct 02 08:48:03 PM UTC 24 |
| Finished | Oct 02 08:48:13 PM UTC 24 |
| Peak memory | 232120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3175779437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_bad_ad dr.3175779437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_acq.4275296297 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 561375707 ps |
| CPU time | 2.09 seconds |
| Started | Oct 02 08:47:59 PM UTC 24 |
| Finished | Oct 02 08:48:02 PM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275296 297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_acq.4275296297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_tx.1307849189 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 112772575 ps |
| CPU time | 1.62 seconds |
| Started | Oct 02 08:47:59 PM UTC 24 |
| Finished | Oct 02 08:48:02 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307849 189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_tx.1307849189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_acq.1821951119 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 757294248 ps |
| CPU time | 4.06 seconds |
| Started | Oct 02 08:48:08 PM UTC 24 |
| Finished | Oct 02 08:48:13 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821951 119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_watermar ks_acq.1821951119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_tx.46213440 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 166501379 ps |
| CPU time | 2.18 seconds |
| Started | Oct 02 08:48:09 PM UTC 24 |
| Finished | Oct 02 08:48:12 PM UTC 24 |
| Peak memory | 215308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4621344 0 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.46213440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_intr_smoke.3364793816 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 3074121307 ps |
| CPU time | 7.35 seconds |
| Started | Oct 02 08:47:50 PM UTC 24 |
| Finished | Oct 02 08:47:58 PM UTC 24 |
| Peak memory | 232496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336479 3816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_smoke.3364793816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_intr_stress_wr.3945829534 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 4844113332 ps |
| CPU time | 12.1 seconds |
| Started | Oct 02 08:47:54 PM UTC 24 |
| Finished | Oct 02 08:48:07 PM UTC 24 |
| Peak memory | 394008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3945829534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_stres s_wr.3945829534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull.1257807223 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 2170064676 ps |
| CPU time | 5.62 seconds |
| Started | Oct 02 08:48:11 PM UTC 24 |
| Finished | Oct 02 08:48:18 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257807 223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_acqfull.1257807223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull_addr.373351835 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 1600383231 ps |
| CPU time | 4.35 seconds |
| Started | Oct 02 08:48:12 PM UTC 24 |
| Finished | Oct 02 08:48:17 PM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733518 35 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_acqfull_addr.373351835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_nack_txstretch.2402427853 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 2165210970 ps |
| CPU time | 2.46 seconds |
| Started | Oct 02 08:48:14 PM UTC 24 |
| Finished | Oct 02 08:48:17 PM UTC 24 |
| Peak memory | 232220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402427 853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_txstretch.2402427853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_perf.1378518540 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 613291119 ps |
| CPU time | 7.91 seconds |
| Started | Oct 02 08:48:01 PM UTC 24 |
| Finished | Oct 02 08:48:10 PM UTC 24 |
| Peak memory | 229604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378518 540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_perf.1378518540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_smbus_maxlen.647998129 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 3012254815 ps |
| CPU time | 4.18 seconds |
| Started | Oct 02 08:48:11 PM UTC 24 |
| Finished | Oct 02 08:48:17 PM UTC 24 |
| Peak memory | 215164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6479981 29 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smbus_maxlen.647998129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_smoke.960876476 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 980554301 ps |
| CPU time | 12.09 seconds |
| Started | Oct 02 08:47:45 PM UTC 24 |
| Finished | Oct 02 08:47:58 PM UTC 24 |
| Peak memory | 217440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960876476 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smoke.960876476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_stress_all.4128974989 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 12412719279 ps |
| CPU time | 69.78 seconds |
| Started | Oct 02 08:48:01 PM UTC 24 |
| Finished | Oct 02 08:49:12 PM UTC 24 |
| Peak memory | 588552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412897 4989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_all.4128974989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_stress_rd.3633583716 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 3269091050 ps |
| CPU time | 71.13 seconds |
| Started | Oct 02 08:47:47 PM UTC 24 |
| Finished | Oct 02 08:49:00 PM UTC 24 |
| Peak memory | 229864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633583716 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_rd.3633583716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.1022882961 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 69498795229 ps |
| CPU time | 91.9 seconds |
| Started | Oct 02 08:47:46 PM UTC 24 |
| Finished | Oct 02 08:49:20 PM UTC 24 |
| Peak memory | 1045340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022882961 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_wr.1022882961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_stretch.2478911062 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 476814606 ps |
| CPU time | 10.65 seconds |
| Started | Oct 02 08:47:48 PM UTC 24 |
| Finished | Oct 02 08:48:00 PM UTC 24 |
| Peak memory | 242396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478911062 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stretch.2478911062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_timeout.1674730019 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 1359352900 ps |
| CPU time | 14.59 seconds |
| Started | Oct 02 08:47:54 PM UTC 24 |
| Finished | Oct 02 08:48:10 PM UTC 24 |
| Peak memory | 242484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674730 019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_timeout.1674730019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/32.i2c_target_tx_stretch_ctrl.2095386505 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 104793879 ps |
| CPU time | 2.29 seconds |
| Started | Oct 02 08:48:10 PM UTC 24 |
| Finished | Oct 02 08:48:13 PM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095386 505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.2095386505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/32.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_alert_test.617885052 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 48059784 ps |
| CPU time | 0.98 seconds |
| Started | Oct 02 08:48:57 PM UTC 24 |
| Finished | Oct 02 08:48:59 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617885052 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.617885052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_error_intr.3522351417 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 302039937 ps |
| CPU time | 6.78 seconds |
| Started | Oct 02 08:48:23 PM UTC 24 |
| Finished | Oct 02 08:48:31 PM UTC 24 |
| Peak memory | 265144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522351417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.3522351417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_fmt_empty.453738529 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 1253206576 ps |
| CPU time | 20.62 seconds |
| Started | Oct 02 08:48:18 PM UTC 24 |
| Finished | Oct 02 08:48:40 PM UTC 24 |
| Peak memory | 281316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453738529 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empty.453738529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_full.1120968901 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 3307862961 ps |
| CPU time | 122.92 seconds |
| Started | Oct 02 08:48:18 PM UTC 24 |
| Finished | Oct 02 08:50:24 PM UTC 24 |
| Peak memory | 582416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120968901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.1120968901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_overflow.2143924292 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 14357089213 ps |
| CPU time | 132.53 seconds |
| Started | Oct 02 08:48:17 PM UTC 24 |
| Finished | Oct 02 08:50:32 PM UTC 24 |
| Peak memory | 653568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143924292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2143924292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_fmt.3930227593 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 99542751 ps |
| CPU time | 2.02 seconds |
| Started | Oct 02 08:48:17 PM UTC 24 |
| Finished | Oct 02 08:48:20 PM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930227593 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fmt.3930227593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_rx.2229765267 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 1651965938 ps |
| CPU time | 9.2 seconds |
| Started | Oct 02 08:48:18 PM UTC 24 |
| Finished | Oct 02 08:48:29 PM UTC 24 |
| Peak memory | 260768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229765267 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.2229765267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_watermark.3340304195 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 5072860362 ps |
| CPU time | 130.54 seconds |
| Started | Oct 02 08:48:16 PM UTC 24 |
| Finished | Oct 02 08:50:29 PM UTC 24 |
| Peak memory | 1543092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340304195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.3340304195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_may_nack.3740504147 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2788812835 ps |
| CPU time | 10.74 seconds |
| Started | Oct 02 08:48:49 PM UTC 24 |
| Finished | Oct 02 08:49:02 PM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740504147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.3740504147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_override.1630475820 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 49655935 ps |
| CPU time | 1.03 seconds |
| Started | Oct 02 08:48:15 PM UTC 24 |
| Finished | Oct 02 08:48:17 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630475820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.1630475820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_perf.798810450 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 3003331305 ps |
| CPU time | 27.02 seconds |
| Started | Oct 02 08:48:19 PM UTC 24 |
| Finished | Oct 02 08:48:48 PM UTC 24 |
| Peak memory | 281308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798810450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.798810450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_perf_precise.2365598066 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 73965251 ps |
| CPU time | 3.87 seconds |
| Started | Oct 02 08:48:21 PM UTC 24 |
| Finished | Oct 02 08:48:25 PM UTC 24 |
| Peak memory | 215248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365598066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.2365598066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_smoke.838650685 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 2487950830 ps |
| CPU time | 23.26 seconds |
| Started | Oct 02 08:48:15 PM UTC 24 |
| Finished | Oct 02 08:48:39 PM UTC 24 |
| Peak memory | 349032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838650685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.838650685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_stress_all.985809861 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 80817074461 ps |
| CPU time | 827.57 seconds |
| Started | Oct 02 08:48:26 PM UTC 24 |
| Finished | Oct 02 09:02:23 PM UTC 24 |
| Peak memory | 1921820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985809861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.985809861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_host_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_host_stretch_timeout.2296430697 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 2211190408 ps |
| CPU time | 14.02 seconds |
| Started | Oct 02 08:48:21 PM UTC 24 |
| Finished | Oct 02 08:48:36 PM UTC 24 |
| Peak memory | 225640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296430697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.2296430697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_bad_addr.4158003364 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 2390703110 ps |
| CPU time | 12.78 seconds |
| Started | Oct 02 08:48:48 PM UTC 24 |
| Finished | Oct 02 08:49:02 PM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=4158003364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_ad dr.4158003364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_tx.7011850 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 5483222714 ps |
| CPU time | 3 seconds |
| Started | Oct 02 08:48:46 PM UTC 24 |
| Finished | Oct 02 08:48:50 PM UTC 24 |
| Peak memory | 226096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7011850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_tx.7011850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_acq.1743030977 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 1048667201 ps |
| CPU time | 4.99 seconds |
| Started | Oct 02 08:48:50 PM UTC 24 |
| Finished | Oct 02 08:48:56 PM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743030 977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_watermar ks_acq.1743030977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_tx.3528895993 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 234049148 ps |
| CPU time | 2.02 seconds |
| Started | Oct 02 08:48:51 PM UTC 24 |
| Finished | Oct 02 08:48:54 PM UTC 24 |
| Peak memory | 215240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528895 993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_watermark s_tx.3528895993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_intr_smoke.3057691414 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 5321007801 ps |
| CPU time | 8.84 seconds |
| Started | Oct 02 08:48:37 PM UTC 24 |
| Finished | Oct 02 08:48:47 PM UTC 24 |
| Peak memory | 231760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305769 1414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_smoke.3057691414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_intr_stress_wr.2407196071 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 22266627054 ps |
| CPU time | 197.07 seconds |
| Started | Oct 02 08:48:40 PM UTC 24 |
| Finished | Oct 02 08:52:00 PM UTC 24 |
| Peak memory | 3298280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2407196071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_stres s_wr.2407196071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull.1717814310 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 913058964 ps |
| CPU time | 3.65 seconds |
| Started | Oct 02 08:48:54 PM UTC 24 |
| Finished | Oct 02 08:48:59 PM UTC 24 |
| Peak memory | 225484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717814 310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_acqfull.1717814310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull_addr.3467673564 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 516218393 ps |
| CPU time | 4.59 seconds |
| Started | Oct 02 08:48:56 PM UTC 24 |
| Finished | Oct 02 08:49:02 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467673 564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_acqfull_ad dr.3467673564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_perf.3651612558 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 2827307951 ps |
| CPU time | 6.85 seconds |
| Started | Oct 02 08:48:47 PM UTC 24 |
| Finished | Oct 02 08:48:55 PM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651612 558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_perf.3651612558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_smbus_maxlen.3014331881 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 1734908670 ps |
| CPU time | 4.14 seconds |
| Started | Oct 02 08:48:53 PM UTC 24 |
| Finished | Oct 02 08:48:58 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014331 881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smbus_maxlen.3014331881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_smoke.1753266263 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 12103945049 ps |
| CPU time | 35.56 seconds |
| Started | Oct 02 08:48:29 PM UTC 24 |
| Finished | Oct 02 08:49:06 PM UTC 24 |
| Peak memory | 225620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753266263 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smoke.1753266263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_stress_all.3441982536 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 4056269488 ps |
| CPU time | 25.86 seconds |
| Started | Oct 02 08:48:48 PM UTC 24 |
| Finished | Oct 02 08:49:15 PM UTC 24 |
| Peak memory | 275428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344198 2536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_all.3441982536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_stress_rd.4255329678 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 761565723 ps |
| CPU time | 17.92 seconds |
| Started | Oct 02 08:48:31 PM UTC 24 |
| Finished | Oct 02 08:48:50 PM UTC 24 |
| Peak memory | 227600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255329678 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_rd.4255329678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_stress_wr.4194744770 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 63519347728 ps |
| CPU time | 512.27 seconds |
| Started | Oct 02 08:48:31 PM UTC 24 |
| Finished | Oct 02 08:57:09 PM UTC 24 |
| Peak memory | 5481376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194744770 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_wr.4194744770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_stretch.1804908608 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 4635521820 ps |
| CPU time | 71.26 seconds |
| Started | Oct 02 08:48:36 PM UTC 24 |
| Finished | Oct 02 08:49:49 PM UTC 24 |
| Peak memory | 936868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804908608 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stretch.1804908608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_timeout.584482664 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 1911099111 ps |
| CPU time | 11.64 seconds |
| Started | Oct 02 08:48:40 PM UTC 24 |
| Finished | Oct 02 08:48:53 PM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5844826 64 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_timeout.584482664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/33.i2c_target_tx_stretch_ctrl.4230491484 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 526409428 ps |
| CPU time | 11.1 seconds |
| Started | Oct 02 08:48:53 PM UTC 24 |
| Finished | Oct 02 08:49:05 PM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230491 484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.4230491484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/33.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_alert_test.38746641 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 16276809 ps |
| CPU time | 1.08 seconds |
| Started | Oct 02 08:49:33 PM UTC 24 |
| Finished | Oct 02 08:49:35 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38746641 -assert nopostproc +UVM_TESTNAME=i2c_base _test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.38746641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_fmt_empty.3116042441 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 1451613813 ps |
| CPU time | 28.73 seconds |
| Started | Oct 02 08:49:00 PM UTC 24 |
| Finished | Oct 02 08:49:31 PM UTC 24 |
| Peak memory | 312152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116042441 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empty.3116042441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_full.2293519257 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 4881575698 ps |
| CPU time | 97.76 seconds |
| Started | Oct 02 08:49:02 PM UTC 24 |
| Finished | Oct 02 08:50:41 PM UTC 24 |
| Peak memory | 314208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293519257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.2293519257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_overflow.3180376810 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 9336231973 ps |
| CPU time | 114.83 seconds |
| Started | Oct 02 08:49:00 PM UTC 24 |
| Finished | Oct 02 08:50:58 PM UTC 24 |
| Peak memory | 602792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180376810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3180376810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_fmt.3552835241 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 415293674 ps |
| CPU time | 1.75 seconds |
| Started | Oct 02 08:49:00 PM UTC 24 |
| Finished | Oct 02 08:49:03 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552835241 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fmt.3552835241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_rx.1441673205 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 200606058 ps |
| CPU time | 11.29 seconds |
| Started | Oct 02 08:49:02 PM UTC 24 |
| Finished | Oct 02 08:49:14 PM UTC 24 |
| Peak memory | 215240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441673205 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.1441673205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_watermark.1734396671 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 2941986266 ps |
| CPU time | 74.03 seconds |
| Started | Oct 02 08:48:59 PM UTC 24 |
| Finished | Oct 02 08:50:15 PM UTC 24 |
| Peak memory | 967540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734396671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.1734396671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_may_nack.2397944052 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 2294909248 ps |
| CPU time | 25 seconds |
| Started | Oct 02 08:49:23 PM UTC 24 |
| Finished | Oct 02 08:49:50 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397944052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.2397944052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_override.608843948 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 57715267 ps |
| CPU time | 1.13 seconds |
| Started | Oct 02 08:48:58 PM UTC 24 |
| Finished | Oct 02 08:49:00 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608843948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.608843948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_perf.3101995997 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 6894670952 ps |
| CPU time | 24.91 seconds |
| Started | Oct 02 08:49:03 PM UTC 24 |
| Finished | Oct 02 08:49:29 PM UTC 24 |
| Peak memory | 248544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101995997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.3101995997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_perf_precise.3970727479 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 875592833 ps |
| CPU time | 2.17 seconds |
| Started | Oct 02 08:49:03 PM UTC 24 |
| Finished | Oct 02 08:49:06 PM UTC 24 |
| Peak memory | 215184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970727479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.3970727479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_smoke.1687419046 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 5482064542 ps |
| CPU time | 72.13 seconds |
| Started | Oct 02 08:48:57 PM UTC 24 |
| Finished | Oct 02 08:50:11 PM UTC 24 |
| Peak memory | 330520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687419046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.1687419046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_host_stretch_timeout.3627024256 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 5161053472 ps |
| CPU time | 15.18 seconds |
| Started | Oct 02 08:49:03 PM UTC 24 |
| Finished | Oct 02 08:49:19 PM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627024256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3627024256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_bad_addr.747946130 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 4712454715 ps |
| CPU time | 11.13 seconds |
| Started | Oct 02 08:49:21 PM UTC 24 |
| Finished | Oct 02 08:49:33 PM UTC 24 |
| Peak memory | 225836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=747946130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.747946130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_acq.817668618 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 534571788 ps |
| CPU time | 1.98 seconds |
| Started | Oct 02 08:49:16 PM UTC 24 |
| Finished | Oct 02 08:49:19 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8176686 18 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_acq.817668618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_tx.2447200524 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 401265905 ps |
| CPU time | 1.6 seconds |
| Started | Oct 02 08:49:20 PM UTC 24 |
| Finished | Oct 02 08:49:23 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447200 524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_tx.2447200524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_acq.3716018747 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 587132254 ps |
| CPU time | 4.59 seconds |
| Started | Oct 02 08:49:29 PM UTC 24 |
| Finished | Oct 02 08:49:34 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716018 747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_watermar ks_acq.3716018747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_tx.3543029537 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 176526789 ps |
| CPU time | 2.39 seconds |
| Started | Oct 02 08:49:29 PM UTC 24 |
| Finished | Oct 02 08:49:32 PM UTC 24 |
| Peak memory | 215108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543029 537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_watermark s_tx.3543029537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_intr_smoke.2932916297 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 3277453210 ps |
| CPU time | 11.25 seconds |
| Started | Oct 02 08:49:08 PM UTC 24 |
| Finished | Oct 02 08:49:21 PM UTC 24 |
| Peak memory | 232492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293291 6297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_smoke.2932916297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_intr_stress_wr.3157897571 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 20717865567 ps |
| CPU time | 68.97 seconds |
| Started | Oct 02 08:49:14 PM UTC 24 |
| Finished | Oct 02 08:50:25 PM UTC 24 |
| Peak memory | 1125280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3157897571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_stres s_wr.3157897571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull.701382464 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 610717565 ps |
| CPU time | 3.8 seconds |
| Started | Oct 02 08:49:32 PM UTC 24 |
| Finished | Oct 02 08:49:37 PM UTC 24 |
| Peak memory | 225628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7013824 64 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_acqfull.701382464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull_addr.3868946677 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 2174964907 ps |
| CPU time | 4.82 seconds |
| Started | Oct 02 08:49:32 PM UTC 24 |
| Finished | Oct 02 08:49:38 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868946 677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_acqfull_ad dr.3868946677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_nack_txstretch.275341453 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 567315127 ps |
| CPU time | 2.22 seconds |
| Started | Oct 02 08:49:32 PM UTC 24 |
| Finished | Oct 02 08:49:35 PM UTC 24 |
| Peak memory | 232216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753414 53 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_txstretch.275341453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_perf.53918980 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 1973310307 ps |
| CPU time | 10.41 seconds |
| Started | Oct 02 08:49:20 PM UTC 24 |
| Finished | Oct 02 08:49:31 PM UTC 24 |
| Peak memory | 232424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5391898 0 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_perf.53918980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_smbus_maxlen.619449971 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 432733397 ps |
| CPU time | 3.52 seconds |
| Started | Oct 02 08:49:30 PM UTC 24 |
| Finished | Oct 02 08:49:34 PM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6194499 71 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smbus_maxlen.619449971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_smoke.2340935428 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 2268245641 ps |
| CPU time | 37.01 seconds |
| Started | Oct 02 08:49:06 PM UTC 24 |
| Finished | Oct 02 08:49:44 PM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340935428 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smoke.2340935428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_stress_all.2504649370 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 23772181715 ps |
| CPU time | 212.88 seconds |
| Started | Oct 02 08:49:20 PM UTC 24 |
| Finished | Oct 02 08:52:56 PM UTC 24 |
| Peak memory | 2298672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250464 9370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_all.2504649370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_stress_rd.3105093563 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 539759070 ps |
| CPU time | 22.09 seconds |
| Started | Oct 02 08:49:07 PM UTC 24 |
| Finished | Oct 02 08:49:31 PM UTC 24 |
| Peak memory | 225640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105093563 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_rd.3105093563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_stress_wr.2278542953 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 34909143301 ps |
| CPU time | 143.77 seconds |
| Started | Oct 02 08:49:07 PM UTC 24 |
| Finished | Oct 02 08:51:34 PM UTC 24 |
| Peak memory | 2036708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278542953 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_wr.2278542953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_stretch.999423862 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 4412259739 ps |
| CPU time | 10.14 seconds |
| Started | Oct 02 08:49:08 PM UTC 24 |
| Finished | Oct 02 08:49:20 PM UTC 24 |
| Peak memory | 246700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999423862 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stretch.999423862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_timeout.1678063699 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 4424070101 ps |
| CPU time | 11.46 seconds |
| Started | Oct 02 08:49:15 PM UTC 24 |
| Finished | Oct 02 08:49:27 PM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678063 699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_timeout.1678063699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/34.i2c_target_tx_stretch_ctrl.4089225210 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 883081888 ps |
| CPU time | 12.76 seconds |
| Started | Oct 02 08:49:29 PM UTC 24 |
| Finished | Oct 02 08:49:43 PM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089225 210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.4089225210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/34.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_alert_test.1791020620 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 16951604 ps |
| CPU time | 0.99 seconds |
| Started | Oct 02 08:50:19 PM UTC 24 |
| Finished | Oct 02 08:50:21 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791020620 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.1791020620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_fmt_empty.2591255717 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 1765505727 ps |
| CPU time | 12.74 seconds |
| Started | Oct 02 08:49:45 PM UTC 24 |
| Finished | Oct 02 08:49:59 PM UTC 24 |
| Peak memory | 316128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591255717 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empty.2591255717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_full.1992680032 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 5124599699 ps |
| CPU time | 64.45 seconds |
| Started | Oct 02 08:49:45 PM UTC 24 |
| Finished | Oct 02 08:50:51 PM UTC 24 |
| Peak memory | 349024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992680032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1992680032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_overflow.2197684272 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 2488296723 ps |
| CPU time | 74.92 seconds |
| Started | Oct 02 08:49:35 PM UTC 24 |
| Finished | Oct 02 08:50:52 PM UTC 24 |
| Peak memory | 500716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197684272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2197684272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_fmt.1369410828 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 107489547 ps |
| CPU time | 1.79 seconds |
| Started | Oct 02 08:49:45 PM UTC 24 |
| Finished | Oct 02 08:49:47 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369410828 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fmt.1369410828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_rx.2921075452 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 769889588 ps |
| CPU time | 10.76 seconds |
| Started | Oct 02 08:49:45 PM UTC 24 |
| Finished | Oct 02 08:49:57 PM UTC 24 |
| Peak memory | 254816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921075452 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx.2921075452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_watermark.2637402336 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 13296009789 ps |
| CPU time | 93.77 seconds |
| Started | Oct 02 08:49:35 PM UTC 24 |
| Finished | Oct 02 08:51:11 PM UTC 24 |
| Peak memory | 1372900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637402336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.2637402336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_may_nack.351561827 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 5724604072 ps |
| CPU time | 15.49 seconds |
| Started | Oct 02 08:50:15 PM UTC 24 |
| Finished | Oct 02 08:50:32 PM UTC 24 |
| Peak memory | 215380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351561827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.351561827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_mode_toggle.1470623381 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 119462079 ps |
| CPU time | 5.34 seconds |
| Started | Oct 02 08:50:15 PM UTC 24 |
| Finished | Oct 02 08:50:21 PM UTC 24 |
| Peak memory | 231904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470623381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.1470623381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_host_mode_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_override.2045087974 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 28220914 ps |
| CPU time | 1.03 seconds |
| Started | Oct 02 08:49:34 PM UTC 24 |
| Finished | Oct 02 08:49:36 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045087974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2045087974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_perf.3903962535 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 48508882299 ps |
| CPU time | 268.77 seconds |
| Started | Oct 02 08:49:45 PM UTC 24 |
| Finished | Oct 02 08:54:18 PM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903962535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.3903962535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_perf_precise.965355741 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 24323166587 ps |
| CPU time | 242.85 seconds |
| Started | Oct 02 08:49:45 PM UTC 24 |
| Finished | Oct 02 08:53:51 PM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965355741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.965355741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_smoke.1209008603 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 7107676886 ps |
| CPU time | 35.27 seconds |
| Started | Oct 02 08:49:33 PM UTC 24 |
| Finished | Oct 02 08:50:10 PM UTC 24 |
| Peak memory | 379728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209008603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.1209008603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_stress_all.1828710872 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 72870612804 ps |
| CPU time | 284.63 seconds |
| Started | Oct 02 08:49:48 PM UTC 24 |
| Finished | Oct 02 08:54:37 PM UTC 24 |
| Peak memory | 553716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828710872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.1828710872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_host_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_host_stretch_timeout.3026058628 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 656295907 ps |
| CPU time | 12.27 seconds |
| Started | Oct 02 08:49:45 PM UTC 24 |
| Finished | Oct 02 08:49:58 PM UTC 24 |
| Peak memory | 225676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026058628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.3026058628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_bad_addr.256610806 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 1045546697 ps |
| CPU time | 9.96 seconds |
| Started | Oct 02 08:50:07 PM UTC 24 |
| Finished | Oct 02 08:50:18 PM UTC 24 |
| Peak memory | 232064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=256610806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.256610806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_acq.3829599424 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 379710954 ps |
| CPU time | 2.51 seconds |
| Started | Oct 02 08:49:59 PM UTC 24 |
| Finished | Oct 02 08:50:03 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829599 424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_acq.3829599424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_tx.656972380 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 1081750185 ps |
| CPU time | 3.59 seconds |
| Started | Oct 02 08:50:02 PM UTC 24 |
| Finished | Oct 02 08:50:07 PM UTC 24 |
| Peak memory | 217384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6569723 80 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_tx.656972380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_acq.3773308189 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 2153977291 ps |
| CPU time | 4.55 seconds |
| Started | Oct 02 08:50:15 PM UTC 24 |
| Finished | Oct 02 08:50:21 PM UTC 24 |
| Peak memory | 215524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773308 189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_watermar ks_acq.3773308189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_tx.2430612960 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 1241876856 ps |
| CPU time | 2.12 seconds |
| Started | Oct 02 08:50:15 PM UTC 24 |
| Finished | Oct 02 08:50:18 PM UTC 24 |
| Peak memory | 215112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430612 960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_watermark s_tx.2430612960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_intr_smoke.361107231 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 1350236372 ps |
| CPU time | 6.13 seconds |
| Started | Oct 02 08:49:58 PM UTC 24 |
| Finished | Oct 02 08:50:05 PM UTC 24 |
| Peak memory | 227816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361107 231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_smoke.361107231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_intr_stress_wr.1049827042 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 15846810511 ps |
| CPU time | 98.02 seconds |
| Started | Oct 02 08:49:58 PM UTC 24 |
| Finished | Oct 02 08:51:38 PM UTC 24 |
| Peak memory | 2364192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1049827042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_stres s_wr.1049827042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull.3940797219 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 1089053249 ps |
| CPU time | 4.09 seconds |
| Started | Oct 02 08:50:15 PM UTC 24 |
| Finished | Oct 02 08:50:20 PM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940797 219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_acqfull.3940797219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull_addr.1678127385 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 494612761 ps |
| CPU time | 4.31 seconds |
| Started | Oct 02 08:50:16 PM UTC 24 |
| Finished | Oct 02 08:50:22 PM UTC 24 |
| Peak memory | 215336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678127 385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_acqfull_ad dr.1678127385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_perf.3067754001 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 632074257 ps |
| CPU time | 6.7 seconds |
| Started | Oct 02 08:50:03 PM UTC 24 |
| Finished | Oct 02 08:50:11 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067754 001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_perf.3067754001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_smbus_maxlen.2534556342 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 489284045 ps |
| CPU time | 3.53 seconds |
| Started | Oct 02 08:50:15 PM UTC 24 |
| Finished | Oct 02 08:50:20 PM UTC 24 |
| Peak memory | 215060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534556 342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smbus_maxlen.2534556342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_smoke.1757716355 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 1471590837 ps |
| CPU time | 15.71 seconds |
| Started | Oct 02 08:49:50 PM UTC 24 |
| Finished | Oct 02 08:50:07 PM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757716355 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smoke.1757716355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_stress_all.841587477 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 41791130882 ps |
| CPU time | 427.78 seconds |
| Started | Oct 02 08:50:05 PM UTC 24 |
| Finished | Oct 02 08:57:18 PM UTC 24 |
| Peak memory | 3771372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841587 477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_all.841587477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_stress_rd.3999132219 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 2847138700 ps |
| CPU time | 27.45 seconds |
| Started | Oct 02 08:49:51 PM UTC 24 |
| Finished | Oct 02 08:50:19 PM UTC 24 |
| Peak memory | 232296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999132219 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_rd.3999132219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_stress_wr.1168920490 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 7655889789 ps |
| CPU time | 18.51 seconds |
| Started | Oct 02 08:49:50 PM UTC 24 |
| Finished | Oct 02 08:50:10 PM UTC 24 |
| Peak memory | 215104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168920490 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_wr.1168920490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_stretch.2786023457 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 3007917850 ps |
| CPU time | 4.49 seconds |
| Started | Oct 02 08:49:52 PM UTC 24 |
| Finished | Oct 02 08:49:57 PM UTC 24 |
| Peak memory | 267112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786023457 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stretch.2786023457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_timeout.3277916702 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 1285501809 ps |
| CPU time | 11.8 seconds |
| Started | Oct 02 08:49:58 PM UTC 24 |
| Finished | Oct 02 08:50:11 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277916 702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_timeout.3277916702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/35.i2c_target_tx_stretch_ctrl.2730829813 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 407143211 ps |
| CPU time | 9.09 seconds |
| Started | Oct 02 08:50:15 PM UTC 24 |
| Finished | Oct 02 08:50:25 PM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730829 813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.2730829813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/35.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_alert_test.392384529 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 44201903 ps |
| CPU time | 0.95 seconds |
| Started | Oct 02 08:50:49 PM UTC 24 |
| Finished | Oct 02 08:50:51 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392384529 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.392384529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_fmt_empty.283615563 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 635124789 ps |
| CPU time | 14.76 seconds |
| Started | Oct 02 08:50:21 PM UTC 24 |
| Finished | Oct 02 08:50:37 PM UTC 24 |
| Peak memory | 326376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283615563 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empty.283615563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_full.3446226673 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 25287695494 ps |
| CPU time | 70.39 seconds |
| Started | Oct 02 08:50:22 PM UTC 24 |
| Finished | Oct 02 08:51:34 PM UTC 24 |
| Peak memory | 539616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446226673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.3446226673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_overflow.438323352 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 2255121694 ps |
| CPU time | 64.87 seconds |
| Started | Oct 02 08:50:21 PM UTC 24 |
| Finished | Oct 02 08:51:27 PM UTC 24 |
| Peak memory | 773088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438323352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.438323352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_fmt.1608614141 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 135414833 ps |
| CPU time | 2.01 seconds |
| Started | Oct 02 08:50:21 PM UTC 24 |
| Finished | Oct 02 08:50:24 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608614141 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fmt.1608614141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_rx.631488678 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 164695894 ps |
| CPU time | 10.13 seconds |
| Started | Oct 02 08:50:21 PM UTC 24 |
| Finished | Oct 02 08:50:32 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631488678 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.631488678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_watermark.508222629 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 11945441853 ps |
| CPU time | 170.32 seconds |
| Started | Oct 02 08:50:20 PM UTC 24 |
| Finished | Oct 02 08:53:13 PM UTC 24 |
| Peak memory | 944940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508222629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.508222629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_may_nack.3979576855 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 2091332467 ps |
| CPU time | 8.57 seconds |
| Started | Oct 02 08:50:42 PM UTC 24 |
| Finished | Oct 02 08:50:51 PM UTC 24 |
| Peak memory | 215160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979576855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.3979576855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_override.1207265749 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 18930645 ps |
| CPU time | 0.95 seconds |
| Started | Oct 02 08:50:20 PM UTC 24 |
| Finished | Oct 02 08:50:22 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207265749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.1207265749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_perf.13323822 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 13141514970 ps |
| CPU time | 46.31 seconds |
| Started | Oct 02 08:50:22 PM UTC 24 |
| Finished | Oct 02 08:51:10 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13323822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho st_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.13323822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_perf_precise.2874106028 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 24389407699 ps |
| CPU time | 148.46 seconds |
| Started | Oct 02 08:50:22 PM UTC 24 |
| Finished | Oct 02 08:52:53 PM UTC 24 |
| Peak memory | 215188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874106028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.2874106028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_smoke.1727147672 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 4475817462 ps |
| CPU time | 59.77 seconds |
| Started | Oct 02 08:50:20 PM UTC 24 |
| Finished | Oct 02 08:51:21 PM UTC 24 |
| Peak memory | 334700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727147672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.1727147672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_host_stretch_timeout.992096876 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 3441758385 ps |
| CPU time | 12.9 seconds |
| Started | Oct 02 08:50:24 PM UTC 24 |
| Finished | Oct 02 08:50:38 PM UTC 24 |
| Peak memory | 242608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992096876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.992096876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_bad_addr.3047069761 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 867130740 ps |
| CPU time | 8.33 seconds |
| Started | Oct 02 08:50:39 PM UTC 24 |
| Finished | Oct 02 08:50:49 PM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3047069761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_bad_ad dr.3047069761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_acq.3013012621 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 243240675 ps |
| CPU time | 1.31 seconds |
| Started | Oct 02 08:50:36 PM UTC 24 |
| Finished | Oct 02 08:50:38 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013012 621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_acq.3013012621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_tx.1891785015 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 895427057 ps |
| CPU time | 3.02 seconds |
| Started | Oct 02 08:50:37 PM UTC 24 |
| Finished | Oct 02 08:50:41 PM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891785 015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_tx.1891785015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_acq.1174540466 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 1578485098 ps |
| CPU time | 4.15 seconds |
| Started | Oct 02 08:50:43 PM UTC 24 |
| Finished | Oct 02 08:50:48 PM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174540 466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_watermar ks_acq.1174540466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_tx.2535289200 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 129367742 ps |
| CPU time | 2.1 seconds |
| Started | Oct 02 08:50:45 PM UTC 24 |
| Finished | Oct 02 08:50:48 PM UTC 24 |
| Peak memory | 215176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535289 200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_watermark s_tx.2535289200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_hrst.1360338826 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 595772646 ps |
| CPU time | 4.23 seconds |
| Started | Oct 02 08:50:39 PM UTC 24 |
| Finished | Oct 02 08:50:45 PM UTC 24 |
| Peak memory | 217432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360338 826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_hrst.1360338826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_intr_smoke.3013520795 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 9294013407 ps |
| CPU time | 9.75 seconds |
| Started | Oct 02 08:50:36 PM UTC 24 |
| Finished | Oct 02 08:50:47 PM UTC 24 |
| Peak memory | 229728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301352 0795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_smoke.3013520795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_intr_stress_wr.3521217548 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 19486104040 ps |
| CPU time | 46.44 seconds |
| Started | Oct 02 08:50:36 PM UTC 24 |
| Finished | Oct 02 08:51:24 PM UTC 24 |
| Peak memory | 822312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3521217548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_stres s_wr.3521217548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull.3595906854 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 1804329852 ps |
| CPU time | 4.29 seconds |
| Started | Oct 02 08:50:47 PM UTC 24 |
| Finished | Oct 02 08:50:53 PM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595906 854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_acqfull.3595906854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull_addr.1312709403 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 9684245104 ps |
| CPU time | 3.88 seconds |
| Started | Oct 02 08:50:47 PM UTC 24 |
| Finished | Oct 02 08:50:52 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312709 403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_acqfull_ad dr.1312709403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_perf.3445727446 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 1895196583 ps |
| CPU time | 5.66 seconds |
| Started | Oct 02 08:50:38 PM UTC 24 |
| Finished | Oct 02 08:50:45 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445727 446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_perf.3445727446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_smbus_maxlen.3100650921 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 464150390 ps |
| CPU time | 4.24 seconds |
| Started | Oct 02 08:50:46 PM UTC 24 |
| Finished | Oct 02 08:50:51 PM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100650 921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smbus_maxlen.3100650921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_smoke.1629497743 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 1760813293 ps |
| CPU time | 11.58 seconds |
| Started | Oct 02 08:50:26 PM UTC 24 |
| Finished | Oct 02 08:50:39 PM UTC 24 |
| Peak memory | 225488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629497743 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smoke.1629497743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_stress_all.2014190442 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 28488084958 ps |
| CPU time | 282.78 seconds |
| Started | Oct 02 08:50:38 PM UTC 24 |
| Finished | Oct 02 08:55:25 PM UTC 24 |
| Peak memory | 2831208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201419 0442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_all.2014190442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_stress_rd.1899342989 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 1037759308 ps |
| CPU time | 53.92 seconds |
| Started | Oct 02 08:50:36 PM UTC 24 |
| Finished | Oct 02 08:51:31 PM UTC 24 |
| Peak memory | 225640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899342989 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_rd.1899342989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_stress_wr.679062292 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 9369899360 ps |
| CPU time | 8.91 seconds |
| Started | Oct 02 08:50:26 PM UTC 24 |
| Finished | Oct 02 08:50:36 PM UTC 24 |
| Peak memory | 215036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679062292 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_wr.679062292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_stretch.2699509632 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 4245569777 ps |
| CPU time | 21.69 seconds |
| Started | Oct 02 08:50:36 PM UTC 24 |
| Finished | Oct 02 08:50:59 PM UTC 24 |
| Peak memory | 477976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699509632 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stretch.2699509632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_timeout.4096271507 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 1329099647 ps |
| CPU time | 8.92 seconds |
| Started | Oct 02 08:50:36 PM UTC 24 |
| Finished | Oct 02 08:50:46 PM UTC 24 |
| Peak memory | 248544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096271 507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_timeout.4096271507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/36.i2c_target_tx_stretch_ctrl.534119847 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 86256651 ps |
| CPU time | 2.59 seconds |
| Started | Oct 02 08:50:46 PM UTC 24 |
| Finished | Oct 02 08:50:49 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5341198 47 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.534119847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/36.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_alert_test.1488819934 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 25966639 ps |
| CPU time | 0.92 seconds |
| Started | Oct 02 08:51:22 PM UTC 24 |
| Finished | Oct 02 08:51:24 PM UTC 24 |
| Peak memory | 214020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488819934 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.1488819934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_fmt_empty.3998337925 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 676291171 ps |
| CPU time | 10.63 seconds |
| Started | Oct 02 08:50:53 PM UTC 24 |
| Finished | Oct 02 08:51:05 PM UTC 24 |
| Peak memory | 291604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998337925 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empty.3998337925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_full.2667325986 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 5902649407 ps |
| CPU time | 60.48 seconds |
| Started | Oct 02 08:50:53 PM UTC 24 |
| Finished | Oct 02 08:51:55 PM UTC 24 |
| Peak memory | 449328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667325986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.2667325986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_overflow.3530688397 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 8895957546 ps |
| CPU time | 87.68 seconds |
| Started | Oct 02 08:50:53 PM UTC 24 |
| Finished | Oct 02 08:52:23 PM UTC 24 |
| Peak memory | 850732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530688397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.3530688397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_fmt.1255312119 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 222241810 ps |
| CPU time | 1.68 seconds |
| Started | Oct 02 08:50:53 PM UTC 24 |
| Finished | Oct 02 08:50:56 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255312119 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fmt.1255312119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_rx.3142958584 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 1642395120 ps |
| CPU time | 9.25 seconds |
| Started | Oct 02 08:50:53 PM UTC 24 |
| Finished | Oct 02 08:51:03 PM UTC 24 |
| Peak memory | 236240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142958584 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.3142958584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_watermark.3381107779 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 4513511655 ps |
| CPU time | 281.42 seconds |
| Started | Oct 02 08:50:52 PM UTC 24 |
| Finished | Oct 02 08:55:37 PM UTC 24 |
| Peak memory | 1366960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381107779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.3381107779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_may_nack.4190612210 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 2136681906 ps |
| CPU time | 9.92 seconds |
| Started | Oct 02 08:51:13 PM UTC 24 |
| Finished | Oct 02 08:51:24 PM UTC 24 |
| Peak memory | 215240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190612210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.4190612210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_override.1083718110 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 113697945 ps |
| CPU time | 0.97 seconds |
| Started | Oct 02 08:50:50 PM UTC 24 |
| Finished | Oct 02 08:50:53 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083718110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.1083718110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_perf.212767232 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 2896469488 ps |
| CPU time | 31.55 seconds |
| Started | Oct 02 08:50:54 PM UTC 24 |
| Finished | Oct 02 08:51:27 PM UTC 24 |
| Peak memory | 239900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212767232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.212767232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_perf_precise.2195840597 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 94112581 ps |
| CPU time | 1.61 seconds |
| Started | Oct 02 08:50:54 PM UTC 24 |
| Finished | Oct 02 08:50:57 PM UTC 24 |
| Peak memory | 214852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195840597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.2195840597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_smoke.420011273 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 898392729 ps |
| CPU time | 47.82 seconds |
| Started | Oct 02 08:50:50 PM UTC 24 |
| Finished | Oct 02 08:51:40 PM UTC 24 |
| Peak memory | 293532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420011273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.420011273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_stress_all.1178268031 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 14954368165 ps |
| CPU time | 1124.33 seconds |
| Started | Oct 02 08:50:57 PM UTC 24 |
| Finished | Oct 02 09:09:54 PM UTC 24 |
| Peak memory | 2050940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178268031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.1178268031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_host_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_host_stretch_timeout.4034792819 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 577041463 ps |
| CPU time | 12.04 seconds |
| Started | Oct 02 08:50:54 PM UTC 24 |
| Finished | Oct 02 08:51:08 PM UTC 24 |
| Peak memory | 231988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034792819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.4034792819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_bad_addr.3619531035 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 1192534632 ps |
| CPU time | 9.45 seconds |
| Started | Oct 02 08:51:11 PM UTC 24 |
| Finished | Oct 02 08:51:22 PM UTC 24 |
| Peak memory | 225628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3619531035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_ad dr.3619531035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_acq.3556077250 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 298584313 ps |
| CPU time | 3.1 seconds |
| Started | Oct 02 08:51:08 PM UTC 24 |
| Finished | Oct 02 08:51:12 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556077 250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_acq.3556077250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_tx.2347582064 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 146797421 ps |
| CPU time | 1.83 seconds |
| Started | Oct 02 08:51:08 PM UTC 24 |
| Finished | Oct 02 08:51:11 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347582 064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_tx.2347582064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_acq.2555036464 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 1023166787 ps |
| CPU time | 4.04 seconds |
| Started | Oct 02 08:51:17 PM UTC 24 |
| Finished | Oct 02 08:51:22 PM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555036 464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_watermar ks_acq.2555036464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_tx.2370602271 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 440045096 ps |
| CPU time | 1.98 seconds |
| Started | Oct 02 08:51:17 PM UTC 24 |
| Finished | Oct 02 08:51:20 PM UTC 24 |
| Peak memory | 214780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370602 271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_watermark s_tx.2370602271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_hrst.3239694188 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 550179382 ps |
| CPU time | 4.35 seconds |
| Started | Oct 02 08:51:11 PM UTC 24 |
| Finished | Oct 02 08:51:17 PM UTC 24 |
| Peak memory | 229848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239694 188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_hrst.3239694188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_intr_smoke.453501543 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 1479612236 ps |
| CPU time | 7.14 seconds |
| Started | Oct 02 08:51:00 PM UTC 24 |
| Finished | Oct 02 08:51:08 PM UTC 24 |
| Peak memory | 225640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453501 543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_smoke.453501543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_intr_stress_wr.1567336161 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 4177033456 ps |
| CPU time | 7.76 seconds |
| Started | Oct 02 08:51:07 PM UTC 24 |
| Finished | Oct 02 08:51:16 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1567336161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_stres s_wr.1567336161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull.3648083095 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 437068566 ps |
| CPU time | 4.74 seconds |
| Started | Oct 02 08:51:21 PM UTC 24 |
| Finished | Oct 02 08:51:27 PM UTC 24 |
| Peak memory | 225580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648083 095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_acqfull.3648083095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull_addr.1397656998 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 545989124 ps |
| CPU time | 4.09 seconds |
| Started | Oct 02 08:51:21 PM UTC 24 |
| Finished | Oct 02 08:51:26 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397656 998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_acqfull_ad dr.1397656998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_perf.397782310 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 1156686108 ps |
| CPU time | 5.83 seconds |
| Started | Oct 02 08:51:09 PM UTC 24 |
| Finished | Oct 02 08:51:16 PM UTC 24 |
| Peak memory | 231720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977823 10 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_perf.397782310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_smbus_maxlen.388680036 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 517215040 ps |
| CPU time | 2.79 seconds |
| Started | Oct 02 08:51:21 PM UTC 24 |
| Finished | Oct 02 08:51:25 PM UTC 24 |
| Peak memory | 215100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886800 36 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smbus_maxlen.388680036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_smoke.3001194309 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2381596746 ps |
| CPU time | 23.09 seconds |
| Started | Oct 02 08:50:57 PM UTC 24 |
| Finished | Oct 02 08:51:22 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001194309 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smoke.3001194309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_stress_all.1950896884 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 85087845630 ps |
| CPU time | 244.48 seconds |
| Started | Oct 02 08:51:11 PM UTC 24 |
| Finished | Oct 02 08:55:19 PM UTC 24 |
| Peak memory | 1801080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195089 6884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_all.1950896884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_stress_rd.1582928867 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 3791961850 ps |
| CPU time | 37.34 seconds |
| Started | Oct 02 08:51:00 PM UTC 24 |
| Finished | Oct 02 08:51:38 PM UTC 24 |
| Peak memory | 225884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582928867 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_rd.1582928867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_stress_wr.2059004565 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 12188648370 ps |
| CPU time | 23.13 seconds |
| Started | Oct 02 08:50:59 PM UTC 24 |
| Finished | Oct 02 08:51:23 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059004565 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_wr.2059004565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_stretch.1544897414 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 1843364341 ps |
| CPU time | 34.18 seconds |
| Started | Oct 02 08:51:00 PM UTC 24 |
| Finished | Oct 02 08:51:35 PM UTC 24 |
| Peak memory | 613292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544897414 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stretch.1544897414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_timeout.1787513420 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 5373054259 ps |
| CPU time | 11.23 seconds |
| Started | Oct 02 08:51:08 PM UTC 24 |
| Finished | Oct 02 08:51:20 PM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787513 420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_timeout.1787513420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/37.i2c_target_tx_stretch_ctrl.3738492902 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 246636850 ps |
| CPU time | 7.29 seconds |
| Started | Oct 02 08:51:18 PM UTC 24 |
| Finished | Oct 02 08:51:26 PM UTC 24 |
| Peak memory | 215444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738492 902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.3738492902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/37.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_alert_test.464047612 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 18443990 ps |
| CPU time | 0.97 seconds |
| Started | Oct 02 08:51:52 PM UTC 24 |
| Finished | Oct 02 08:51:54 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464047612 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.464047612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_error_intr.3749661713 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 248816117 ps |
| CPU time | 1.85 seconds |
| Started | Oct 02 08:51:38 PM UTC 24 |
| Finished | Oct 02 08:51:41 PM UTC 24 |
| Peak memory | 224740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749661713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3749661713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_fmt_empty.3121689076 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 1658010333 ps |
| CPU time | 18.68 seconds |
| Started | Oct 02 08:51:38 PM UTC 24 |
| Finished | Oct 02 08:51:58 PM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121689076 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empty.3121689076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_full.3950207195 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 3606837346 ps |
| CPU time | 116.23 seconds |
| Started | Oct 02 08:51:38 PM UTC 24 |
| Finished | Oct 02 08:53:36 PM UTC 24 |
| Peak memory | 592660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950207195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.3950207195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_overflow.2034308399 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 2374682374 ps |
| CPU time | 84.76 seconds |
| Started | Oct 02 08:51:33 PM UTC 24 |
| Finished | Oct 02 08:53:00 PM UTC 24 |
| Peak memory | 817896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034308399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2034308399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_fmt.1649225406 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 472636929 ps |
| CPU time | 1.52 seconds |
| Started | Oct 02 08:51:38 PM UTC 24 |
| Finished | Oct 02 08:51:40 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649225406 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fmt.1649225406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_rx.2152864081 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 247417028 ps |
| CPU time | 4.61 seconds |
| Started | Oct 02 08:51:38 PM UTC 24 |
| Finished | Oct 02 08:51:43 PM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152864081 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.2152864081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_watermark.3897952468 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 10438779363 ps |
| CPU time | 61.98 seconds |
| Started | Oct 02 08:51:33 PM UTC 24 |
| Finished | Oct 02 08:52:37 PM UTC 24 |
| Peak memory | 852712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897952468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.3897952468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_may_nack.1707699632 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 612900115 ps |
| CPU time | 7.02 seconds |
| Started | Oct 02 08:51:44 PM UTC 24 |
| Finished | Oct 02 08:51:52 PM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707699632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.1707699632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_mode_toggle.4280529062 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 300277635 ps |
| CPU time | 2.38 seconds |
| Started | Oct 02 08:51:44 PM UTC 24 |
| Finished | Oct 02 08:51:48 PM UTC 24 |
| Peak memory | 231656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280529062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.4280529062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_host_mode_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_override.3351906422 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 21557516 ps |
| CPU time | 0.94 seconds |
| Started | Oct 02 08:51:33 PM UTC 24 |
| Finished | Oct 02 08:51:35 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351906422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3351906422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_perf.3014092582 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 18299821647 ps |
| CPU time | 437.65 seconds |
| Started | Oct 02 08:51:38 PM UTC 24 |
| Finished | Oct 02 08:59:01 PM UTC 24 |
| Peak memory | 887592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014092582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.3014092582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_perf_precise.2167115871 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 358246668 ps |
| CPU time | 2.35 seconds |
| Started | Oct 02 08:51:38 PM UTC 24 |
| Finished | Oct 02 08:51:41 PM UTC 24 |
| Peak memory | 235652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167115871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.2167115871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_smoke.1234902186 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 6700803628 ps |
| CPU time | 33.89 seconds |
| Started | Oct 02 08:51:22 PM UTC 24 |
| Finished | Oct 02 08:51:58 PM UTC 24 |
| Peak memory | 412508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234902186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1234902186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_host_stretch_timeout.2248753387 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 1105742336 ps |
| CPU time | 25.1 seconds |
| Started | Oct 02 08:51:38 PM UTC 24 |
| Finished | Oct 02 08:52:04 PM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248753387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.2248753387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_bad_addr.3790196561 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 1597024655 ps |
| CPU time | 6.07 seconds |
| Started | Oct 02 08:51:42 PM UTC 24 |
| Finished | Oct 02 08:51:49 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3790196561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_bad_ad dr.3790196561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_acq.622171000 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 326748922 ps |
| CPU time | 1.75 seconds |
| Started | Oct 02 08:51:40 PM UTC 24 |
| Finished | Oct 02 08:51:42 PM UTC 24 |
| Peak memory | 214808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6221710 00 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_acq.622171000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_tx.1318736488 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 154264692 ps |
| CPU time | 1.85 seconds |
| Started | Oct 02 08:51:41 PM UTC 24 |
| Finished | Oct 02 08:51:44 PM UTC 24 |
| Peak memory | 214748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318736 488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_tx.1318736488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_acq.2362959657 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 612509199 ps |
| CPU time | 5.11 seconds |
| Started | Oct 02 08:51:44 PM UTC 24 |
| Finished | Oct 02 08:51:50 PM UTC 24 |
| Peak memory | 215308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362959 657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_watermar ks_acq.2362959657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_tx.122769989 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 380835888 ps |
| CPU time | 2.51 seconds |
| Started | Oct 02 08:51:48 PM UTC 24 |
| Finished | Oct 02 08:51:52 PM UTC 24 |
| Peak memory | 215112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227699 89 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_watermarks _tx.122769989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_hrst.3420254714 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 297892693 ps |
| CPU time | 3.96 seconds |
| Started | Oct 02 08:51:43 PM UTC 24 |
| Finished | Oct 02 08:51:48 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420254 714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_hrst.3420254714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_intr_smoke.3193115697 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 6942181651 ps |
| CPU time | 11.31 seconds |
| Started | Oct 02 08:51:38 PM UTC 24 |
| Finished | Oct 02 08:51:51 PM UTC 24 |
| Peak memory | 242596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319311 5697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_smoke.3193115697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_intr_stress_wr.1058172555 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 11950078732 ps |
| CPU time | 182.7 seconds |
| Started | Oct 02 08:51:38 PM UTC 24 |
| Finished | Oct 02 08:54:44 PM UTC 24 |
| Peak memory | 2931560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1058172555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_stres s_wr.1058172555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull.3748800345 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 549204605 ps |
| CPU time | 5.23 seconds |
| Started | Oct 02 08:51:50 PM UTC 24 |
| Finished | Oct 02 08:51:56 PM UTC 24 |
| Peak memory | 225552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748800 345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_acqfull.3748800345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull_addr.2342824455 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 2038858873 ps |
| CPU time | 4.35 seconds |
| Started | Oct 02 08:51:51 PM UTC 24 |
| Finished | Oct 02 08:51:56 PM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342824 455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_acqfull_ad dr.2342824455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_nack_txstretch.2938285769 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 581788770 ps |
| CPU time | 1.6 seconds |
| Started | Oct 02 08:51:51 PM UTC 24 |
| Finished | Oct 02 08:51:53 PM UTC 24 |
| Peak memory | 231688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938285 769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_txstretch.2938285769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_perf.1451513401 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 615825333 ps |
| CPU time | 7.87 seconds |
| Started | Oct 02 08:51:41 PM UTC 24 |
| Finished | Oct 02 08:51:50 PM UTC 24 |
| Peak memory | 232216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451513 401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_perf.1451513401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_smbus_maxlen.3472189299 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 2284671503 ps |
| CPU time | 5.04 seconds |
| Started | Oct 02 08:51:48 PM UTC 24 |
| Finished | Oct 02 08:51:55 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472189 299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smbus_maxlen.3472189299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_smoke.514547870 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 978402838 ps |
| CPU time | 13.01 seconds |
| Started | Oct 02 08:51:38 PM UTC 24 |
| Finished | Oct 02 08:51:52 PM UTC 24 |
| Peak memory | 217440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514547870 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smoke.514547870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_stress_rd.1832487541 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 1850686085 ps |
| CPU time | 12.17 seconds |
| Started | Oct 02 08:51:38 PM UTC 24 |
| Finished | Oct 02 08:51:51 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832487541 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_rd.1832487541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_stress_wr.2153210471 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 78386824799 ps |
| CPU time | 110.06 seconds |
| Started | Oct 02 08:51:38 PM UTC 24 |
| Finished | Oct 02 08:53:30 PM UTC 24 |
| Peak memory | 910168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153210471 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_wr.2153210471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_stretch.1028786380 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 3905414441 ps |
| CPU time | 34.85 seconds |
| Started | Oct 02 08:51:38 PM UTC 24 |
| Finished | Oct 02 08:52:14 PM UTC 24 |
| Peak memory | 412524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028786380 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stretch.1028786380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_timeout.356564031 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 5948669400 ps |
| CPU time | 10.76 seconds |
| Started | Oct 02 08:51:38 PM UTC 24 |
| Finished | Oct 02 08:51:50 PM UTC 24 |
| Peak memory | 242484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565640 31 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_timeout.356564031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/38.i2c_target_tx_stretch_ctrl.741897749 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 151486035 ps |
| CPU time | 2.8 seconds |
| Started | Oct 02 08:51:48 PM UTC 24 |
| Finished | Oct 02 08:51:52 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7418977 49 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.741897749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_alert_test.2908812348 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 52381623 ps |
| CPU time | 1.01 seconds |
| Started | Oct 02 08:52:20 PM UTC 24 |
| Finished | Oct 02 08:52:22 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908812348 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.2908812348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_fmt_empty.1471282550 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 304439080 ps |
| CPU time | 3.48 seconds |
| Started | Oct 02 08:51:53 PM UTC 24 |
| Finished | Oct 02 08:51:58 PM UTC 24 |
| Peak memory | 240532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471282550 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empty.1471282550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_full.290989893 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 8865453255 ps |
| CPU time | 164.56 seconds |
| Started | Oct 02 08:51:54 PM UTC 24 |
| Finished | Oct 02 08:54:42 PM UTC 24 |
| Peak memory | 574296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290989893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.290989893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_overflow.144968768 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 2656634221 ps |
| CPU time | 96.64 seconds |
| Started | Oct 02 08:51:53 PM UTC 24 |
| Finished | Oct 02 08:53:32 PM UTC 24 |
| Peak memory | 873384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144968768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.144968768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_fmt.581292097 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 714893004 ps |
| CPU time | 1.93 seconds |
| Started | Oct 02 08:51:53 PM UTC 24 |
| Finished | Oct 02 08:51:56 PM UTC 24 |
| Peak memory | 214808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581292097 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fmt.581292097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_rx.2893070257 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 916474140 ps |
| CPU time | 5.46 seconds |
| Started | Oct 02 08:51:54 PM UTC 24 |
| Finished | Oct 02 08:52:01 PM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893070257 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.2893070257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_watermark.2098584701 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 15610653918 ps |
| CPU time | 229.41 seconds |
| Started | Oct 02 08:51:53 PM UTC 24 |
| Finished | Oct 02 08:55:46 PM UTC 24 |
| Peak memory | 1213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098584701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.2098584701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_host_may_nack.2850268260 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 3061880309 ps |
| CPU time | 22.61 seconds |
| Started | Oct 02 08:52:13 PM UTC 24 |
| Finished | Oct 02 08:52:37 PM UTC 24 |
| Peak memory | 215304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850268260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.2850268260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_host_override.1509459249 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 18977808 ps |
| CPU time | 1.14 seconds |
| Started | Oct 02 08:51:53 PM UTC 24 |
| Finished | Oct 02 08:51:55 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509459249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.1509459249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_host_perf.3427459537 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 25529888645 ps |
| CPU time | 348.51 seconds |
| Started | Oct 02 08:51:56 PM UTC 24 |
| Finished | Oct 02 08:57:49 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427459537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.3427459537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_host_perf_precise.2775048995 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 6400801417 ps |
| CPU time | 7.84 seconds |
| Started | Oct 02 08:51:56 PM UTC 24 |
| Finished | Oct 02 08:52:05 PM UTC 24 |
| Peak memory | 215236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775048995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.2775048995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_host_smoke.918469537 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 1511900090 ps |
| CPU time | 27.14 seconds |
| Started | Oct 02 08:51:52 PM UTC 24 |
| Finished | Oct 02 08:52:20 PM UTC 24 |
| Peak memory | 391912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918469537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.918469537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_host_stress_all.795574095 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 48289113428 ps |
| CPU time | 412.27 seconds |
| Started | Oct 02 08:51:57 PM UTC 24 |
| Finished | Oct 02 08:58:55 PM UTC 24 |
| Peak memory | 2227012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795574095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.795574095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_host_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_host_stretch_timeout.2755990829 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 628793301 ps |
| CPU time | 16.1 seconds |
| Started | Oct 02 08:51:56 PM UTC 24 |
| Finished | Oct 02 08:52:13 PM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755990829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.2755990829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_bad_addr.2045116307 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 502436422 ps |
| CPU time | 5.93 seconds |
| Started | Oct 02 08:52:10 PM UTC 24 |
| Finished | Oct 02 08:52:17 PM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2045116307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_ad dr.2045116307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_acq.3629604911 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 435892671 ps |
| CPU time | 2.55 seconds |
| Started | Oct 02 08:52:06 PM UTC 24 |
| Finished | Oct 02 08:52:09 PM UTC 24 |
| Peak memory | 215524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629604 911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_acq.3629604911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_tx.832396069 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 313893114 ps |
| CPU time | 1.88 seconds |
| Started | Oct 02 08:52:06 PM UTC 24 |
| Finished | Oct 02 08:52:09 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8323960 69 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_tx.832396069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_acq.747646021 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 2082152104 ps |
| CPU time | 4.08 seconds |
| Started | Oct 02 08:52:14 PM UTC 24 |
| Finished | Oct 02 08:52:19 PM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7476460 21 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_watermark s_acq.747646021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_tx.3635726104 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 646087511 ps |
| CPU time | 2.52 seconds |
| Started | Oct 02 08:52:15 PM UTC 24 |
| Finished | Oct 02 08:52:19 PM UTC 24 |
| Peak memory | 215240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635726 104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_watermark s_tx.3635726104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_intr_smoke.3660573363 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 2069640509 ps |
| CPU time | 10.52 seconds |
| Started | Oct 02 08:52:00 PM UTC 24 |
| Finished | Oct 02 08:52:12 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366057 3363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_smoke.3660573363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_intr_stress_wr.3114006123 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 21474012475 ps |
| CPU time | 58.91 seconds |
| Started | Oct 02 08:52:01 PM UTC 24 |
| Finished | Oct 02 08:53:02 PM UTC 24 |
| Peak memory | 971756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3114006123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_stres s_wr.3114006123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull.3921641354 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 2025940405 ps |
| CPU time | 5.19 seconds |
| Started | Oct 02 08:52:18 PM UTC 24 |
| Finished | Oct 02 08:52:24 PM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921641 354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_acqfull.3921641354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull_addr.3067768233 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 1203009955 ps |
| CPU time | 3.84 seconds |
| Started | Oct 02 08:52:19 PM UTC 24 |
| Finished | Oct 02 08:52:24 PM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067768 233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_acqfull_ad dr.3067768233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_nack_txstretch.3314827812 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 217475668 ps |
| CPU time | 2.72 seconds |
| Started | Oct 02 08:52:20 PM UTC 24 |
| Finished | Oct 02 08:52:24 PM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314827 812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_txstretch.3314827812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_perf.516240334 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 8671184816 ps |
| CPU time | 10.41 seconds |
| Started | Oct 02 08:52:09 PM UTC 24 |
| Finished | Oct 02 08:52:20 PM UTC 24 |
| Peak memory | 225824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5162403 34 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_perf.516240334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_smbus_maxlen.1059235800 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 1100001597 ps |
| CPU time | 4.43 seconds |
| Started | Oct 02 08:52:18 PM UTC 24 |
| Finished | Oct 02 08:52:23 PM UTC 24 |
| Peak memory | 215012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059235 800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smbus_maxlen.1059235800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_smoke.1387738107 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 431662711 ps |
| CPU time | 16.66 seconds |
| Started | Oct 02 08:51:57 PM UTC 24 |
| Finished | Oct 02 08:52:15 PM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387738107 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smoke.1387738107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_stress_all.1844959720 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 65712703786 ps |
| CPU time | 1887.49 seconds |
| Started | Oct 02 08:52:10 PM UTC 24 |
| Finished | Oct 02 09:23:56 PM UTC 24 |
| Peak memory | 11838440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184495 9720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_all.1844959720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_stress_rd.3328734223 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 1089885586 ps |
| CPU time | 25.77 seconds |
| Started | Oct 02 08:51:58 PM UTC 24 |
| Finished | Oct 02 08:52:25 PM UTC 24 |
| Peak memory | 242528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328734223 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_rd.3328734223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_stress_wr.3812420070 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 7208324043 ps |
| CPU time | 8.95 seconds |
| Started | Oct 02 08:51:58 PM UTC 24 |
| Finished | Oct 02 08:52:08 PM UTC 24 |
| Peak memory | 215172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812420070 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_wr.3812420070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_stretch.2844964194 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 4214243026 ps |
| CPU time | 39.84 seconds |
| Started | Oct 02 08:51:59 PM UTC 24 |
| Finished | Oct 02 08:52:41 PM UTC 24 |
| Peak memory | 652140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844964194 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stretch.2844964194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_timeout.1522935832 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 1354380792 ps |
| CPU time | 8.33 seconds |
| Started | Oct 02 08:52:01 PM UTC 24 |
| Finished | Oct 02 08:52:11 PM UTC 24 |
| Peak memory | 232296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522935 832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_timeout.1522935832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/39.i2c_target_tx_stretch_ctrl.4262574574 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 131313571 ps |
| CPU time | 4.74 seconds |
| Started | Oct 02 08:52:17 PM UTC 24 |
| Finished | Oct 02 08:52:22 PM UTC 24 |
| Peak memory | 215316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262574 574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.4262574574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/39.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_alert_test.3013451796 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 37378241 ps |
| CPU time | 0.98 seconds |
| Started | Oct 02 08:26:28 PM UTC 24 |
| Finished | Oct 02 08:26:31 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013451796 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.3013451796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_fmt_empty.1277598612 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1023708246 ps |
| CPU time | 15.12 seconds |
| Started | Oct 02 08:25:00 PM UTC 24 |
| Finished | Oct 02 08:25:16 PM UTC 24 |
| Peak memory | 240284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277598612 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty.1277598612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_full.194159888 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 7956428488 ps |
| CPU time | 144.07 seconds |
| Started | Oct 02 08:25:06 PM UTC 24 |
| Finished | Oct 02 08:27:34 PM UTC 24 |
| Peak memory | 420760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194159888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.194159888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_overflow.3920151323 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2371684993 ps |
| CPU time | 69.98 seconds |
| Started | Oct 02 08:24:59 PM UTC 24 |
| Finished | Oct 02 08:26:11 PM UTC 24 |
| Peak memory | 772836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920151323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.3920151323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_fmt.2464629885 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 979172859 ps |
| CPU time | 1.73 seconds |
| Started | Oct 02 08:24:59 PM UTC 24 |
| Finished | Oct 02 08:25:02 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464629885 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt.2464629885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_rx.532571759 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 823473582 ps |
| CPU time | 11.83 seconds |
| Started | Oct 02 08:25:02 PM UTC 24 |
| Finished | Oct 02 08:25:15 PM UTC 24 |
| Peak memory | 215248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532571759 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.532571759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_watermark.3141705269 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 17354929358 ps |
| CPU time | 86.85 seconds |
| Started | Oct 02 08:24:58 PM UTC 24 |
| Finished | Oct 02 08:26:27 PM UTC 24 |
| Peak memory | 1248240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141705269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.3141705269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_may_nack.2818972393 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 283103079 ps |
| CPU time | 6.29 seconds |
| Started | Oct 02 08:26:17 PM UTC 24 |
| Finished | Oct 02 08:26:24 PM UTC 24 |
| Peak memory | 215312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818972393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.2818972393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_override.1978974371 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 43609666 ps |
| CPU time | 0.96 seconds |
| Started | Oct 02 08:24:57 PM UTC 24 |
| Finished | Oct 02 08:24:59 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978974371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.1978974371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_perf.2252659013 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 12285381296 ps |
| CPU time | 63.63 seconds |
| Started | Oct 02 08:25:08 PM UTC 24 |
| Finished | Oct 02 08:26:14 PM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252659013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.2252659013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_perf_precise.3885451428 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 101247516 ps |
| CPU time | 1.58 seconds |
| Started | Oct 02 08:25:13 PM UTC 24 |
| Finished | Oct 02 08:25:16 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885451428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.3885451428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_smoke.3611520758 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 8761029714 ps |
| CPU time | 78.93 seconds |
| Started | Oct 02 08:24:56 PM UTC 24 |
| Finished | Oct 02 08:26:17 PM UTC 24 |
| Peak memory | 291604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611520758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.3611520758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_host_stretch_timeout.1668077617 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2767515287 ps |
| CPU time | 41.89 seconds |
| Started | Oct 02 08:25:16 PM UTC 24 |
| Finished | Oct 02 08:26:00 PM UTC 24 |
| Peak memory | 225504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668077617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.1668077617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_sec_cm.4042606707 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 416441222 ps |
| CPU time | 1.17 seconds |
| Started | Oct 02 08:26:27 PM UTC 24 |
| Finished | Oct 02 08:26:29 PM UTC 24 |
| Peak memory | 244508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042606707 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.4042606707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_bad_addr.861054845 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 14269453632 ps |
| CPU time | 6.73 seconds |
| Started | Oct 02 08:26:10 PM UTC 24 |
| Finished | Oct 02 08:26:18 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=861054845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.861054845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_acq.1021706876 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 126795590 ps |
| CPU time | 1.64 seconds |
| Started | Oct 02 08:26:03 PM UTC 24 |
| Finished | Oct 02 08:26:06 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021706 876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_acq.1021706876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_tx.4231233588 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 283127188 ps |
| CPU time | 2.22 seconds |
| Started | Oct 02 08:26:05 PM UTC 24 |
| Finished | Oct 02 08:26:09 PM UTC 24 |
| Peak memory | 225276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231233 588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_tx.4231233588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_acq.3779993386 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3210185984 ps |
| CPU time | 3.06 seconds |
| Started | Oct 02 08:26:18 PM UTC 24 |
| Finished | Oct 02 08:26:22 PM UTC 24 |
| Peak memory | 215444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779993 386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_watermark s_acq.3779993386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_tx.2308291882 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 376041636 ps |
| CPU time | 1.64 seconds |
| Started | Oct 02 08:26:19 PM UTC 24 |
| Finished | Oct 02 08:26:22 PM UTC 24 |
| Peak memory | 214784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308291 882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_watermarks _tx.2308291882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_intr_smoke.2310950401 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 4013282583 ps |
| CPU time | 8.48 seconds |
| Started | Oct 02 08:25:56 PM UTC 24 |
| Finished | Oct 02 08:26:06 PM UTC 24 |
| Peak memory | 231704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231095 0401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_smoke.2310950401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_intr_stress_wr.3267476381 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 21915690042 ps |
| CPU time | 306.08 seconds |
| Started | Oct 02 08:25:59 PM UTC 24 |
| Finished | Oct 02 08:31:09 PM UTC 24 |
| Peak memory | 5276516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3267476381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_stress _wr.3267476381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull.2025115069 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 560826852 ps |
| CPU time | 4.81 seconds |
| Started | Oct 02 08:26:25 PM UTC 24 |
| Finished | Oct 02 08:26:31 PM UTC 24 |
| Peak memory | 225704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025115 069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_acqfull.2025115069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull_addr.2252873223 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1068673487 ps |
| CPU time | 3.53 seconds |
| Started | Oct 02 08:26:25 PM UTC 24 |
| Finished | Oct 02 08:26:29 PM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252873 223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.2252873223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_nack_txstretch.1033419616 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 312718094 ps |
| CPU time | 2.37 seconds |
| Started | Oct 02 08:26:25 PM UTC 24 |
| Finished | Oct 02 08:26:28 PM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033419 616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_txstretch.1033419616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_perf.1791437085 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 2839154446 ps |
| CPU time | 7.69 seconds |
| Started | Oct 02 08:26:07 PM UTC 24 |
| Finished | Oct 02 08:26:15 PM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791437 085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_perf.1791437085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_smbus_maxlen.3775079984 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 2155653066 ps |
| CPU time | 3.49 seconds |
| Started | Oct 02 08:26:22 PM UTC 24 |
| Finished | Oct 02 08:26:27 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775079 984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smbus_maxlen.3775079984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_smoke.1472422864 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 854622930 ps |
| CPU time | 35.03 seconds |
| Started | Oct 02 08:25:26 PM UTC 24 |
| Finished | Oct 02 08:26:03 PM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472422864 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smoke.1472422864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_stress_all.440079897 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 16486801282 ps |
| CPU time | 149.42 seconds |
| Started | Oct 02 08:26:07 PM UTC 24 |
| Finished | Oct 02 08:28:39 PM UTC 24 |
| Peak memory | 1653544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440079 897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_all.440079897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_stress_rd.2521794824 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1708405115 ps |
| CPU time | 85.96 seconds |
| Started | Oct 02 08:25:38 PM UTC 24 |
| Finished | Oct 02 08:27:06 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521794824 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_rd.2521794824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_stress_wr.1700081164 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 35781899739 ps |
| CPU time | 58.94 seconds |
| Started | Oct 02 08:25:34 PM UTC 24 |
| Finished | Oct 02 08:26:34 PM UTC 24 |
| Peak memory | 1088360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700081164 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_wr.1700081164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_stretch.3758580800 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 2365460826 ps |
| CPU time | 10.95 seconds |
| Started | Oct 02 08:25:43 PM UTC 24 |
| Finished | Oct 02 08:25:55 PM UTC 24 |
| Peak memory | 322608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758580800 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stretch.3758580800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_timeout.1131541297 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1248389790 ps |
| CPU time | 12.57 seconds |
| Started | Oct 02 08:26:00 PM UTC 24 |
| Finished | Oct 02 08:26:14 PM UTC 24 |
| Peak memory | 232240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131541 297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_timeout.1131541297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/4.i2c_target_tx_stretch_ctrl.1801316654 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 197502902 ps |
| CPU time | 4.32 seconds |
| Started | Oct 02 08:26:21 PM UTC 24 |
| Finished | Oct 02 08:26:27 PM UTC 24 |
| Peak memory | 215248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801316 654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.1801316654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/4.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_alert_test.3448168298 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 21337236 ps |
| CPU time | 0.91 seconds |
| Started | Oct 02 08:52:57 PM UTC 24 |
| Finished | Oct 02 08:52:59 PM UTC 24 |
| Peak memory | 214784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448168298 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.3448168298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_host_error_intr.1163689208 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 653552606 ps |
| CPU time | 5.23 seconds |
| Started | Oct 02 08:52:26 PM UTC 24 |
| Finished | Oct 02 08:52:32 PM UTC 24 |
| Peak memory | 248628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163689208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.1163689208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_fmt_empty.744134496 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 595022412 ps |
| CPU time | 9.46 seconds |
| Started | Oct 02 08:52:25 PM UTC 24 |
| Finished | Oct 02 08:52:35 PM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744134496 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empty.744134496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_full.1743683013 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 5939031241 ps |
| CPU time | 187.82 seconds |
| Started | Oct 02 08:52:25 PM UTC 24 |
| Finished | Oct 02 08:55:36 PM UTC 24 |
| Peak memory | 521000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743683013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.1743683013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_overflow.1123810589 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 6837972270 ps |
| CPU time | 56.82 seconds |
| Started | Oct 02 08:52:23 PM UTC 24 |
| Finished | Oct 02 08:53:22 PM UTC 24 |
| Peak memory | 617196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123810589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1123810589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_fmt.109969909 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 256923542 ps |
| CPU time | 1.19 seconds |
| Started | Oct 02 08:52:23 PM UTC 24 |
| Finished | Oct 02 08:52:26 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109969909 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fmt.109969909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_rx.1238778849 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 758183407 ps |
| CPU time | 6.36 seconds |
| Started | Oct 02 08:52:25 PM UTC 24 |
| Finished | Oct 02 08:52:32 PM UTC 24 |
| Peak memory | 215268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238778849 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.1238778849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_watermark.111414942 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 4616443187 ps |
| CPU time | 99.52 seconds |
| Started | Oct 02 08:52:23 PM UTC 24 |
| Finished | Oct 02 08:54:05 PM UTC 24 |
| Peak memory | 1227756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111414942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.111414942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_host_may_nack.3152809645 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 2656151590 ps |
| CPU time | 6.74 seconds |
| Started | Oct 02 08:52:52 PM UTC 24 |
| Finished | Oct 02 08:52:59 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152809645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.3152809645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_host_override.1468547224 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 54661492 ps |
| CPU time | 1.08 seconds |
| Started | Oct 02 08:52:21 PM UTC 24 |
| Finished | Oct 02 08:52:23 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468547224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.1468547224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_host_perf.1912165130 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 2715168081 ps |
| CPU time | 92.29 seconds |
| Started | Oct 02 08:52:25 PM UTC 24 |
| Finished | Oct 02 08:53:59 PM UTC 24 |
| Peak memory | 854752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912165130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.1912165130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_host_perf_precise.300478763 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 74979542 ps |
| CPU time | 2.43 seconds |
| Started | Oct 02 08:52:26 PM UTC 24 |
| Finished | Oct 02 08:52:30 PM UTC 24 |
| Peak memory | 215376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300478763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.300478763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_host_smoke.1036511869 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 3024834794 ps |
| CPU time | 34.95 seconds |
| Started | Oct 02 08:52:21 PM UTC 24 |
| Finished | Oct 02 08:52:58 PM UTC 24 |
| Peak memory | 385824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036511869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.1036511869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_host_stretch_timeout.4284198235 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 1857806623 ps |
| CPU time | 18.72 seconds |
| Started | Oct 02 08:52:26 PM UTC 24 |
| Finished | Oct 02 08:52:46 PM UTC 24 |
| Peak memory | 225508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284198235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.4284198235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_bad_addr.1952413281 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 790825381 ps |
| CPU time | 6.52 seconds |
| Started | Oct 02 08:52:48 PM UTC 24 |
| Finished | Oct 02 08:52:56 PM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1952413281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_ad dr.1952413281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_acq.1446695532 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 192926679 ps |
| CPU time | 1.78 seconds |
| Started | Oct 02 08:52:45 PM UTC 24 |
| Finished | Oct 02 08:52:48 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446695 532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_acq.1446695532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_tx.1902428686 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 661369960 ps |
| CPU time | 2.09 seconds |
| Started | Oct 02 08:52:45 PM UTC 24 |
| Finished | Oct 02 08:52:48 PM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902428 686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_tx.1902428686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_acq.293813991 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 1257018557 ps |
| CPU time | 2.97 seconds |
| Started | Oct 02 08:52:53 PM UTC 24 |
| Finished | Oct 02 08:52:57 PM UTC 24 |
| Peak memory | 215020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938139 91 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_watermark s_acq.293813991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_tx.2095087004 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 78258609 ps |
| CPU time | 1.59 seconds |
| Started | Oct 02 08:52:53 PM UTC 24 |
| Finished | Oct 02 08:52:55 PM UTC 24 |
| Peak memory | 214780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095087 004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_watermark s_tx.2095087004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_intr_smoke.2111353995 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 767340195 ps |
| CPU time | 7.03 seconds |
| Started | Oct 02 08:52:37 PM UTC 24 |
| Finished | Oct 02 08:52:45 PM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211135 3995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_smoke.2111353995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_intr_stress_wr.289946988 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 6644228096 ps |
| CPU time | 47.73 seconds |
| Started | Oct 02 08:52:38 PM UTC 24 |
| Finished | Oct 02 08:53:27 PM UTC 24 |
| Peak memory | 1291036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=289946988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_stress _wr.289946988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull.3560031739 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 4442371791 ps |
| CPU time | 3.07 seconds |
| Started | Oct 02 08:52:56 PM UTC 24 |
| Finished | Oct 02 08:53:00 PM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560031 739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_acqfull.3560031739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull_addr.1644319494 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 1077546607 ps |
| CPU time | 4.48 seconds |
| Started | Oct 02 08:52:56 PM UTC 24 |
| Finished | Oct 02 08:53:02 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644319 494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_acqfull_ad dr.1644319494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_perf.713539323 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 2667117636 ps |
| CPU time | 6.63 seconds |
| Started | Oct 02 08:52:46 PM UTC 24 |
| Finished | Oct 02 08:52:54 PM UTC 24 |
| Peak memory | 225768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7135393 23 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_perf.713539323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_smbus_maxlen.2733539035 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 441620405 ps |
| CPU time | 2.85 seconds |
| Started | Oct 02 08:52:55 PM UTC 24 |
| Finished | Oct 02 08:52:59 PM UTC 24 |
| Peak memory | 215004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733539 035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smbus_maxlen.2733539035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_smoke.797784474 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 1194150052 ps |
| CPU time | 24.09 seconds |
| Started | Oct 02 08:52:30 PM UTC 24 |
| Finished | Oct 02 08:52:56 PM UTC 24 |
| Peak memory | 225768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797784474 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smoke.797784474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_stress_all.1254085525 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 49730312604 ps |
| CPU time | 157.35 seconds |
| Started | Oct 02 08:52:47 PM UTC 24 |
| Finished | Oct 02 08:55:27 PM UTC 24 |
| Peak memory | 1444664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125408 5525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_all.1254085525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_stress_rd.606954270 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 34944282092 ps |
| CPU time | 40.39 seconds |
| Started | Oct 02 08:52:33 PM UTC 24 |
| Finished | Oct 02 08:53:15 PM UTC 24 |
| Peak memory | 248860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606954270 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_rd.606954270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_stress_wr.738066994 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 65485298061 ps |
| CPU time | 1372.44 seconds |
| Started | Oct 02 08:52:31 PM UTC 24 |
| Finished | Oct 02 09:15:38 PM UTC 24 |
| Peak memory | 11903772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738066994 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_wr.738066994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_stretch.3620723961 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 1900374659 ps |
| CPU time | 9.71 seconds |
| Started | Oct 02 08:52:33 PM UTC 24 |
| Finished | Oct 02 08:52:44 PM UTC 24 |
| Peak memory | 303964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620723961 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stretch.3620723961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_timeout.2128609976 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 991952502 ps |
| CPU time | 9.34 seconds |
| Started | Oct 02 08:52:38 PM UTC 24 |
| Finished | Oct 02 08:52:48 PM UTC 24 |
| Peak memory | 231844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128609 976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_timeout.2128609976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/40.i2c_target_tx_stretch_ctrl.2107909150 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 248951444 ps |
| CPU time | 6.03 seconds |
| Started | Oct 02 08:52:54 PM UTC 24 |
| Finished | Oct 02 08:53:01 PM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107909 150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.2107909150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/40.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_alert_test.2903446716 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 16954588 ps |
| CPU time | 1.04 seconds |
| Started | Oct 02 08:53:31 PM UTC 24 |
| Finished | Oct 02 08:53:34 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903446716 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.2903446716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_host_error_intr.3690308232 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 140180513 ps |
| CPU time | 2.46 seconds |
| Started | Oct 02 08:53:03 PM UTC 24 |
| Finished | Oct 02 08:53:07 PM UTC 24 |
| Peak memory | 225720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690308232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3690308232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_fmt_empty.855019756 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 115769972 ps |
| CPU time | 7.27 seconds |
| Started | Oct 02 08:53:01 PM UTC 24 |
| Finished | Oct 02 08:53:09 PM UTC 24 |
| Peak memory | 226144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855019756 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empty.855019756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_full.2506076239 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 3383377006 ps |
| CPU time | 144.09 seconds |
| Started | Oct 02 08:53:01 PM UTC 24 |
| Finished | Oct 02 08:55:28 PM UTC 24 |
| Peak memory | 635664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506076239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2506076239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_overflow.1663705470 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 9578526825 ps |
| CPU time | 186.86 seconds |
| Started | Oct 02 08:53:00 PM UTC 24 |
| Finished | Oct 02 08:56:09 PM UTC 24 |
| Peak memory | 824116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663705470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1663705470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_fmt.4167604324 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 682299546 ps |
| CPU time | 1.8 seconds |
| Started | Oct 02 08:53:01 PM UTC 24 |
| Finished | Oct 02 08:53:04 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167604324 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fmt.4167604324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_rx.3814248013 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 124320450 ps |
| CPU time | 10.6 seconds |
| Started | Oct 02 08:53:01 PM UTC 24 |
| Finished | Oct 02 08:53:13 PM UTC 24 |
| Peak memory | 236192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814248013 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.3814248013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_watermark.830641207 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 20072727604 ps |
| CPU time | 132.6 seconds |
| Started | Oct 02 08:53:00 PM UTC 24 |
| Finished | Oct 02 08:55:14 PM UTC 24 |
| Peak memory | 1577696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830641207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.830641207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_host_may_nack.1830238109 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 565203039 ps |
| CPU time | 12.03 seconds |
| Started | Oct 02 08:53:23 PM UTC 24 |
| Finished | Oct 02 08:53:36 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830238109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.1830238109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_host_override.707184021 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 36134746 ps |
| CPU time | 0.93 seconds |
| Started | Oct 02 08:52:59 PM UTC 24 |
| Finished | Oct 02 08:53:00 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707184021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.707184021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_host_perf.1330818904 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 3785444634 ps |
| CPU time | 6.9 seconds |
| Started | Oct 02 08:53:02 PM UTC 24 |
| Finished | Oct 02 08:53:10 PM UTC 24 |
| Peak memory | 215308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330818904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.1330818904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_host_perf_precise.926256858 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 101706047 ps |
| CPU time | 2.04 seconds |
| Started | Oct 02 08:53:02 PM UTC 24 |
| Finished | Oct 02 08:53:05 PM UTC 24 |
| Peak memory | 237860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926256858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.926256858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_host_smoke.443099854 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 6364551975 ps |
| CPU time | 35.14 seconds |
| Started | Oct 02 08:52:57 PM UTC 24 |
| Finished | Oct 02 08:53:34 PM UTC 24 |
| Peak memory | 357156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443099854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.443099854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_host_stress_all.1199517147 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 15910922898 ps |
| CPU time | 550.33 seconds |
| Started | Oct 02 08:53:04 PM UTC 24 |
| Finished | Oct 02 09:02:21 PM UTC 24 |
| Peak memory | 2560796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199517147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.1199517147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_host_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_host_stretch_timeout.1772158631 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 642923546 ps |
| CPU time | 11.94 seconds |
| Started | Oct 02 08:53:02 PM UTC 24 |
| Finished | Oct 02 08:53:15 PM UTC 24 |
| Peak memory | 231792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772158631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.1772158631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_bad_addr.1204659872 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 4555521794 ps |
| CPU time | 4.08 seconds |
| Started | Oct 02 08:53:19 PM UTC 24 |
| Finished | Oct 02 08:53:25 PM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1204659872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_ad dr.1204659872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_acq.2130346668 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 200357483 ps |
| CPU time | 2.23 seconds |
| Started | Oct 02 08:53:16 PM UTC 24 |
| Finished | Oct 02 08:53:19 PM UTC 24 |
| Peak memory | 215524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130346 668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_acq.2130346668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_tx.2204407758 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 455170304 ps |
| CPU time | 1.6 seconds |
| Started | Oct 02 08:53:16 PM UTC 24 |
| Finished | Oct 02 08:53:19 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204407 758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_tx.2204407758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_acq.3747836874 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 594162957 ps |
| CPU time | 3.3 seconds |
| Started | Oct 02 08:53:24 PM UTC 24 |
| Finished | Oct 02 08:53:28 PM UTC 24 |
| Peak memory | 215236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747836 874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_watermar ks_acq.3747836874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_tx.931043918 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 512376904 ps |
| CPU time | 1.96 seconds |
| Started | Oct 02 08:53:25 PM UTC 24 |
| Finished | Oct 02 08:53:28 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9310439 18 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_watermarks _tx.931043918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_intr_smoke.4094800906 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 9412238990 ps |
| CPU time | 8.33 seconds |
| Started | Oct 02 08:53:10 PM UTC 24 |
| Finished | Oct 02 08:53:19 PM UTC 24 |
| Peak memory | 232272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409480 0906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_smoke.4094800906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_intr_stress_wr.976164792 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 21626130746 ps |
| CPU time | 164.11 seconds |
| Started | Oct 02 08:53:11 PM UTC 24 |
| Finished | Oct 02 08:55:57 PM UTC 24 |
| Peak memory | 1946604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=976164792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_stress _wr.976164792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull.2093975372 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 2058496783 ps |
| CPU time | 4.14 seconds |
| Started | Oct 02 08:53:29 PM UTC 24 |
| Finished | Oct 02 08:53:34 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093975 372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_acqfull.2093975372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull_addr.139985705 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 545963308 ps |
| CPU time | 3.64 seconds |
| Started | Oct 02 08:53:29 PM UTC 24 |
| Finished | Oct 02 08:53:34 PM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399857 05 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_acqfull_addr.139985705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_nack_txstretch.4099317316 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 135403129 ps |
| CPU time | 2.08 seconds |
| Started | Oct 02 08:53:29 PM UTC 24 |
| Finished | Oct 02 08:53:32 PM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099317 316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_txstretch.4099317316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_perf.1093994067 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 799026692 ps |
| CPU time | 9.51 seconds |
| Started | Oct 02 08:53:17 PM UTC 24 |
| Finished | Oct 02 08:53:28 PM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093994 067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_perf.1093994067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_smbus_maxlen.3576597764 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 1788621108 ps |
| CPU time | 2.91 seconds |
| Started | Oct 02 08:53:28 PM UTC 24 |
| Finished | Oct 02 08:53:32 PM UTC 24 |
| Peak memory | 215228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576597 764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smbus_maxlen.3576597764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_smoke.329795610 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 1474257402 ps |
| CPU time | 54.5 seconds |
| Started | Oct 02 08:53:06 PM UTC 24 |
| Finished | Oct 02 08:54:02 PM UTC 24 |
| Peak memory | 225772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329795610 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smoke.329795610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_stress_all.4278758587 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 14035570286 ps |
| CPU time | 152.34 seconds |
| Started | Oct 02 08:53:19 PM UTC 24 |
| Finished | Oct 02 08:55:54 PM UTC 24 |
| Peak memory | 1377124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427875 8587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_all.4278758587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_stress_rd.469801027 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 2129583304 ps |
| CPU time | 34.55 seconds |
| Started | Oct 02 08:53:08 PM UTC 24 |
| Finished | Oct 02 08:53:44 PM UTC 24 |
| Peak memory | 258936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469801027 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_rd.469801027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_stress_wr.2002015139 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 13616588489 ps |
| CPU time | 11.22 seconds |
| Started | Oct 02 08:53:07 PM UTC 24 |
| Finished | Oct 02 08:53:19 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002015139 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_wr.2002015139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_stretch.1266369269 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 3140204276 ps |
| CPU time | 21.85 seconds |
| Started | Oct 02 08:53:08 PM UTC 24 |
| Finished | Oct 02 08:53:31 PM UTC 24 |
| Peak memory | 359252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266369269 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stretch.1266369269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_timeout.2147568525 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 2257293538 ps |
| CPU time | 9.08 seconds |
| Started | Oct 02 08:53:13 PM UTC 24 |
| Finished | Oct 02 08:53:23 PM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147568 525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_timeout.2147568525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/41.i2c_target_tx_stretch_ctrl.3711081304 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 1735238246 ps |
| CPU time | 20.58 seconds |
| Started | Oct 02 08:53:27 PM UTC 24 |
| Finished | Oct 02 08:53:49 PM UTC 24 |
| Peak memory | 215248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711081 304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.3711081304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/41.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_alert_test.2777256758 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 40058532 ps |
| CPU time | 1.09 seconds |
| Started | Oct 02 08:54:08 PM UTC 24 |
| Finished | Oct 02 08:54:10 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777256758 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.2777256758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_fmt_empty.3550437708 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 230343646 ps |
| CPU time | 6.24 seconds |
| Started | Oct 02 08:53:35 PM UTC 24 |
| Finished | Oct 02 08:53:43 PM UTC 24 |
| Peak memory | 258776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550437708 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empty.3550437708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_full.1374180498 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 2111425880 ps |
| CPU time | 51.25 seconds |
| Started | Oct 02 08:53:36 PM UTC 24 |
| Finished | Oct 02 08:54:29 PM UTC 24 |
| Peak memory | 369436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374180498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.1374180498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_overflow.207749847 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 1378445120 ps |
| CPU time | 33.41 seconds |
| Started | Oct 02 08:53:34 PM UTC 24 |
| Finished | Oct 02 08:54:09 PM UTC 24 |
| Peak memory | 426660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207749847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.207749847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_fmt.95122769 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 101218755 ps |
| CPU time | 1.68 seconds |
| Started | Oct 02 08:53:35 PM UTC 24 |
| Finished | Oct 02 08:53:38 PM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95122769 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fmt.95122769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_rx.492450304 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 144935607 ps |
| CPU time | 4.73 seconds |
| Started | Oct 02 08:53:35 PM UTC 24 |
| Finished | Oct 02 08:53:41 PM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492450304 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.492450304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.1934883818 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 11268454213 ps |
| CPU time | 135.42 seconds |
| Started | Oct 02 08:53:33 PM UTC 24 |
| Finished | Oct 02 08:55:52 PM UTC 24 |
| Peak memory | 1657704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934883818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.1934883818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_host_may_nack.3155723118 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 683628195 ps |
| CPU time | 12.48 seconds |
| Started | Oct 02 08:54:02 PM UTC 24 |
| Finished | Oct 02 08:54:16 PM UTC 24 |
| Peak memory | 215240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155723118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.3155723118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_host_mode_toggle.3815131315 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 127301263 ps |
| CPU time | 2.88 seconds |
| Started | Oct 02 08:54:00 PM UTC 24 |
| Finished | Oct 02 08:54:04 PM UTC 24 |
| Peak memory | 225508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815131315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.3815131315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_host_mode_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_host_override.510806971 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 44216930 ps |
| CPU time | 1.04 seconds |
| Started | Oct 02 08:53:33 PM UTC 24 |
| Finished | Oct 02 08:53:36 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510806971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.510806971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_host_perf.3766954562 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 29277808726 ps |
| CPU time | 879.22 seconds |
| Started | Oct 02 08:53:37 PM UTC 24 |
| Finished | Oct 02 09:08:27 PM UTC 24 |
| Peak memory | 2769784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766954562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.3766954562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_host_perf_precise.2700151500 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 142072772 ps |
| CPU time | 2.13 seconds |
| Started | Oct 02 08:53:37 PM UTC 24 |
| Finished | Oct 02 08:53:41 PM UTC 24 |
| Peak memory | 225380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700151500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.2700151500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_host_smoke.120294324 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 4481015688 ps |
| CPU time | 16.7 seconds |
| Started | Oct 02 08:53:32 PM UTC 24 |
| Finished | Oct 02 08:53:50 PM UTC 24 |
| Peak memory | 312164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120294324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.120294324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_host_stretch_timeout.3390939175 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 247572790 ps |
| CPU time | 13.61 seconds |
| Started | Oct 02 08:53:38 PM UTC 24 |
| Finished | Oct 02 08:53:53 PM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390939175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.3390939175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_bad_addr.1375305237 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 4128784107 ps |
| CPU time | 7.45 seconds |
| Started | Oct 02 08:53:59 PM UTC 24 |
| Finished | Oct 02 08:54:08 PM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1375305237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_ad dr.1375305237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_acq.43686331 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 212877881 ps |
| CPU time | 2.1 seconds |
| Started | Oct 02 08:53:53 PM UTC 24 |
| Finished | Oct 02 08:53:56 PM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4368633 1 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_acq.43686331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_tx.759019142 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 281471318 ps |
| CPU time | 3.01 seconds |
| Started | Oct 02 08:53:54 PM UTC 24 |
| Finished | Oct 02 08:53:59 PM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7590191 42 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_tx.759019142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_acq.1278701299 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 687253366 ps |
| CPU time | 2.89 seconds |
| Started | Oct 02 08:54:02 PM UTC 24 |
| Finished | Oct 02 08:54:06 PM UTC 24 |
| Peak memory | 215296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278701 299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_watermar ks_acq.1278701299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_tx.727273522 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 182457689 ps |
| CPU time | 1.17 seconds |
| Started | Oct 02 08:54:04 PM UTC 24 |
| Finished | Oct 02 08:54:06 PM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7272735 22 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_watermarks _tx.727273522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_intr_smoke.1075440309 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 20023801865 ps |
| CPU time | 6.94 seconds |
| Started | Oct 02 08:53:50 PM UTC 24 |
| Finished | Oct 02 08:53:58 PM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107544 0309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_smoke.1075440309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_intr_stress_wr.187276820 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 8354740966 ps |
| CPU time | 9.48 seconds |
| Started | Oct 02 08:53:50 PM UTC 24 |
| Finished | Oct 02 08:54:01 PM UTC 24 |
| Peak memory | 215380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=187276820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_stress _wr.187276820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull.1590090890 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 1969537036 ps |
| CPU time | 4.27 seconds |
| Started | Oct 02 08:54:05 PM UTC 24 |
| Finished | Oct 02 08:54:11 PM UTC 24 |
| Peak memory | 225508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590090 890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_acqfull.1590090890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull_addr.3633478031 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 837443109 ps |
| CPU time | 3.53 seconds |
| Started | Oct 02 08:54:07 PM UTC 24 |
| Finished | Oct 02 08:54:11 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633478 031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_acqfull_ad dr.3633478031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_perf.861363854 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 606107699 ps |
| CPU time | 6.5 seconds |
| Started | Oct 02 08:53:55 PM UTC 24 |
| Finished | Oct 02 08:54:03 PM UTC 24 |
| Peak memory | 231860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8613638 54 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_perf.861363854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_smbus_maxlen.3784613524 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 888395340 ps |
| CPU time | 4.84 seconds |
| Started | Oct 02 08:54:05 PM UTC 24 |
| Finished | Oct 02 08:54:11 PM UTC 24 |
| Peak memory | 215060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784613 524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smbus_maxlen.3784613524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_smoke.1217646684 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1761063778 ps |
| CPU time | 25.12 seconds |
| Started | Oct 02 08:53:43 PM UTC 24 |
| Finished | Oct 02 08:54:09 PM UTC 24 |
| Peak memory | 225832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217646684 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smoke.1217646684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.3018559188 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 31728049040 ps |
| CPU time | 323.36 seconds |
| Started | Oct 02 08:53:58 PM UTC 24 |
| Finished | Oct 02 08:59:25 PM UTC 24 |
| Peak memory | 4021084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301855 9188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_all.3018559188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_stress_rd.4210346084 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 4115511089 ps |
| CPU time | 18.99 seconds |
| Started | Oct 02 08:53:44 PM UTC 24 |
| Finished | Oct 02 08:54:04 PM UTC 24 |
| Peak memory | 232224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210346084 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_rd.4210346084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.2057446630 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 26717698022 ps |
| CPU time | 129.27 seconds |
| Started | Oct 02 08:53:44 PM UTC 24 |
| Finished | Oct 02 08:55:55 PM UTC 24 |
| Peak memory | 1764200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057446630 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_wr.2057446630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_stretch.430997422 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 904483790 ps |
| CPU time | 6.59 seconds |
| Started | Oct 02 08:53:45 PM UTC 24 |
| Finished | Oct 02 08:53:52 PM UTC 24 |
| Peak memory | 285544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430997422 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stretch.430997422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_timeout.1987984091 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 1316420986 ps |
| CPU time | 11.72 seconds |
| Started | Oct 02 08:53:51 PM UTC 24 |
| Finished | Oct 02 08:54:04 PM UTC 24 |
| Peak memory | 232244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987984 091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_timeout.1987984091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/42.i2c_target_tx_stretch_ctrl.1161933013 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 119920580 ps |
| CPU time | 3.24 seconds |
| Started | Oct 02 08:54:05 PM UTC 24 |
| Finished | Oct 02 08:54:10 PM UTC 24 |
| Peak memory | 215448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161933 013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.1161933013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_alert_test.3085925136 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 17372264 ps |
| CPU time | 0.97 seconds |
| Started | Oct 02 08:54:46 PM UTC 24 |
| Finished | Oct 02 08:54:48 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085925136 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.3085925136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_host_error_intr.1541078548 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 279980951 ps |
| CPU time | 2.8 seconds |
| Started | Oct 02 08:54:17 PM UTC 24 |
| Finished | Oct 02 08:54:21 PM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541078548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1541078548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_fmt_empty.3551612916 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 259283477 ps |
| CPU time | 7.15 seconds |
| Started | Oct 02 08:54:11 PM UTC 24 |
| Finished | Oct 02 08:54:19 PM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551612916 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empty.3551612916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_full.2705309516 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 7552667634 ps |
| CPU time | 248.03 seconds |
| Started | Oct 02 08:54:12 PM UTC 24 |
| Finished | Oct 02 08:58:24 PM UTC 24 |
| Peak memory | 629608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705309516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.2705309516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_overflow.3092667715 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 1647515506 ps |
| CPU time | 42.87 seconds |
| Started | Oct 02 08:54:11 PM UTC 24 |
| Finished | Oct 02 08:54:55 PM UTC 24 |
| Peak memory | 555952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092667715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.3092667715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_fmt.2539045463 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 126694540 ps |
| CPU time | 1.22 seconds |
| Started | Oct 02 08:54:11 PM UTC 24 |
| Finished | Oct 02 08:54:13 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539045463 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fmt.2539045463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_rx.3919008293 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 182699429 ps |
| CPU time | 6.95 seconds |
| Started | Oct 02 08:54:12 PM UTC 24 |
| Finished | Oct 02 08:54:20 PM UTC 24 |
| Peak memory | 248744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919008293 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.3919008293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.3756016515 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 3022337315 ps |
| CPU time | 69.36 seconds |
| Started | Oct 02 08:54:10 PM UTC 24 |
| Finished | Oct 02 08:55:21 PM UTC 24 |
| Peak memory | 928572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756016515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.3756016515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_host_may_nack.1921269417 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 2270231388 ps |
| CPU time | 8.86 seconds |
| Started | Oct 02 08:54:40 PM UTC 24 |
| Finished | Oct 02 08:54:50 PM UTC 24 |
| Peak memory | 215248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921269417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.1921269417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_host_override.3633208671 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 143561313 ps |
| CPU time | 0.86 seconds |
| Started | Oct 02 08:54:10 PM UTC 24 |
| Finished | Oct 02 08:54:12 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633208671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.3633208671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_host_perf.1892857431 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 12739576003 ps |
| CPU time | 440.52 seconds |
| Started | Oct 02 08:54:12 PM UTC 24 |
| Finished | Oct 02 09:01:38 PM UTC 24 |
| Peak memory | 3101384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892857431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.1892857431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_host_perf_precise.2293362679 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 439322819 ps |
| CPU time | 12.92 seconds |
| Started | Oct 02 08:54:12 PM UTC 24 |
| Finished | Oct 02 08:54:26 PM UTC 24 |
| Peak memory | 215380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293362679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.2293362679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_host_smoke.396695964 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 6895754041 ps |
| CPU time | 24.35 seconds |
| Started | Oct 02 08:54:09 PM UTC 24 |
| Finished | Oct 02 08:54:35 PM UTC 24 |
| Peak memory | 373556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396695964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.396695964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_host_stretch_timeout.1437791529 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 9075856056 ps |
| CPU time | 29.36 seconds |
| Started | Oct 02 08:54:15 PM UTC 24 |
| Finished | Oct 02 08:54:45 PM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437791529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.1437791529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_bad_addr.3043374240 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 739103423 ps |
| CPU time | 5.92 seconds |
| Started | Oct 02 08:54:38 PM UTC 24 |
| Finished | Oct 02 08:54:45 PM UTC 24 |
| Peak memory | 227804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3043374240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_bad_ad dr.3043374240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_acq.1269817318 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 527663104 ps |
| CPU time | 1.41 seconds |
| Started | Oct 02 08:54:35 PM UTC 24 |
| Finished | Oct 02 08:54:37 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269817 318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_acq.1269817318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_tx.405481024 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 681701209 ps |
| CPU time | 2.23 seconds |
| Started | Oct 02 08:54:36 PM UTC 24 |
| Finished | Oct 02 08:54:39 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054810 24 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_tx.405481024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_acq.3986514233 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 1360971815 ps |
| CPU time | 3.99 seconds |
| Started | Oct 02 08:54:41 PM UTC 24 |
| Finished | Oct 02 08:54:46 PM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986514 233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_watermar ks_acq.3986514233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_tx.2710643818 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 140564082 ps |
| CPU time | 1.59 seconds |
| Started | Oct 02 08:54:41 PM UTC 24 |
| Finished | Oct 02 08:54:44 PM UTC 24 |
| Peak memory | 215020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710643 818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_watermark s_tx.2710643818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_hrst.2418743155 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 602291999 ps |
| CPU time | 3.78 seconds |
| Started | Oct 02 08:54:38 PM UTC 24 |
| Finished | Oct 02 08:54:43 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418743 155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_hrst.2418743155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_intr_smoke.3648853408 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 1284593148 ps |
| CPU time | 11.73 seconds |
| Started | Oct 02 08:54:22 PM UTC 24 |
| Finished | Oct 02 08:54:35 PM UTC 24 |
| Peak memory | 229732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364885 3408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_smoke.3648853408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_intr_stress_wr.1892617748 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 21948618535 ps |
| CPU time | 51.03 seconds |
| Started | Oct 02 08:54:26 PM UTC 24 |
| Finished | Oct 02 08:55:19 PM UTC 24 |
| Peak memory | 1073948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1892617748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_stres s_wr.1892617748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull.3046762718 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 604398450 ps |
| CPU time | 4.75 seconds |
| Started | Oct 02 08:54:44 PM UTC 24 |
| Finished | Oct 02 08:54:50 PM UTC 24 |
| Peak memory | 225296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046762 718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_acqfull.3046762718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull_addr.380811992 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 1957609394 ps |
| CPU time | 4.64 seconds |
| Started | Oct 02 08:54:45 PM UTC 24 |
| Finished | Oct 02 08:54:50 PM UTC 24 |
| Peak memory | 215192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808119 92 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_acqfull_addr.380811992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_perf.2413877354 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 2597417526 ps |
| CPU time | 5.92 seconds |
| Started | Oct 02 08:54:36 PM UTC 24 |
| Finished | Oct 02 08:54:43 PM UTC 24 |
| Peak memory | 229728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413877 354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_perf.2413877354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_smbus_maxlen.309627700 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 579781151 ps |
| CPU time | 3.52 seconds |
| Started | Oct 02 08:54:44 PM UTC 24 |
| Finished | Oct 02 08:54:48 PM UTC 24 |
| Peak memory | 215096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096277 00 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smbus_maxlen.309627700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_smoke.1572213139 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 3373351086 ps |
| CPU time | 14.76 seconds |
| Started | Oct 02 08:54:20 PM UTC 24 |
| Finished | Oct 02 08:54:36 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572213139 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smoke.1572213139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.731217745 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 49079824730 ps |
| CPU time | 131.33 seconds |
| Started | Oct 02 08:54:37 PM UTC 24 |
| Finished | Oct 02 08:56:50 PM UTC 24 |
| Peak memory | 1280796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731217 745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_all.731217745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_stress_rd.2250702040 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 6006338203 ps |
| CPU time | 27.7 seconds |
| Started | Oct 02 08:54:21 PM UTC 24 |
| Finished | Oct 02 08:54:50 PM UTC 24 |
| Peak memory | 244724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250702040 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_rd.2250702040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.1280319266 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 10395589589 ps |
| CPU time | 14.42 seconds |
| Started | Oct 02 08:54:21 PM UTC 24 |
| Finished | Oct 02 08:54:37 PM UTC 24 |
| Peak memory | 215592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280319266 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_wr.1280319266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_stretch.922209180 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 886661358 ps |
| CPU time | 2.46 seconds |
| Started | Oct 02 08:54:22 PM UTC 24 |
| Finished | Oct 02 08:54:26 PM UTC 24 |
| Peak memory | 215436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922209180 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stretch.922209180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_timeout.374271337 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 4864183597 ps |
| CPU time | 11.97 seconds |
| Started | Oct 02 08:54:27 PM UTC 24 |
| Finished | Oct 02 08:54:40 PM UTC 24 |
| Peak memory | 232500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742713 37 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_timeout.374271337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/43.i2c_target_tx_stretch_ctrl.149535736 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 638969361 ps |
| CPU time | 10.95 seconds |
| Started | Oct 02 08:54:42 PM UTC 24 |
| Finished | Oct 02 08:54:54 PM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495357 36 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.149535736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_alert_test.477768608 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 15246283 ps |
| CPU time | 1 seconds |
| Started | Oct 02 08:55:28 PM UTC 24 |
| Finished | Oct 02 08:55:30 PM UTC 24 |
| Peak memory | 214256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477768608 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.477768608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_fmt_empty.1281306319 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 671631280 ps |
| CPU time | 9.98 seconds |
| Started | Oct 02 08:54:50 PM UTC 24 |
| Finished | Oct 02 08:55:02 PM UTC 24 |
| Peak memory | 287600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281306319 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empty.1281306319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.1922410773 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 2934379321 ps |
| CPU time | 165.11 seconds |
| Started | Oct 02 08:54:51 PM UTC 24 |
| Finished | Oct 02 08:57:39 PM UTC 24 |
| Peak memory | 429032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922410773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.1922410773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.2779213098 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 1374428092 ps |
| CPU time | 92.29 seconds |
| Started | Oct 02 08:54:49 PM UTC 24 |
| Finished | Oct 02 08:56:24 PM UTC 24 |
| Peak memory | 555948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779213098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2779213098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_fmt.223677050 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 132883606 ps |
| CPU time | 2.09 seconds |
| Started | Oct 02 08:54:49 PM UTC 24 |
| Finished | Oct 02 08:54:52 PM UTC 24 |
| Peak memory | 215120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223677050 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fmt.223677050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_rx.2145918605 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 182206024 ps |
| CPU time | 7.24 seconds |
| Started | Oct 02 08:54:51 PM UTC 24 |
| Finished | Oct 02 08:54:59 PM UTC 24 |
| Peak memory | 246496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145918605 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.2145918605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.612778888 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 3326918471 ps |
| CPU time | 202.23 seconds |
| Started | Oct 02 08:54:48 PM UTC 24 |
| Finished | Oct 02 08:58:14 PM UTC 24 |
| Peak memory | 1000156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612778888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.612778888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_host_may_nack.2830590683 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 1207017251 ps |
| CPU time | 24.14 seconds |
| Started | Oct 02 08:55:21 PM UTC 24 |
| Finished | Oct 02 08:55:46 PM UTC 24 |
| Peak memory | 215240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830590683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.2830590683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_host_override.270587920 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 18528806 ps |
| CPU time | 1.02 seconds |
| Started | Oct 02 08:54:47 PM UTC 24 |
| Finished | Oct 02 08:54:49 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270587920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.270587920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_host_perf.1166548457 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 27554666119 ps |
| CPU time | 378.78 seconds |
| Started | Oct 02 08:54:52 PM UTC 24 |
| Finished | Oct 02 09:01:16 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166548457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.1166548457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_host_perf_precise.678171465 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 285049076 ps |
| CPU time | 14.45 seconds |
| Started | Oct 02 08:54:52 PM UTC 24 |
| Finished | Oct 02 08:55:07 PM UTC 24 |
| Peak memory | 267112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678171465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.678171465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_host_smoke.2733165615 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 3489616492 ps |
| CPU time | 37.41 seconds |
| Started | Oct 02 08:54:46 PM UTC 24 |
| Finished | Oct 02 08:55:25 PM UTC 24 |
| Peak memory | 377640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733165615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2733165615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_host_stretch_timeout.3673318239 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 4284081850 ps |
| CPU time | 10.16 seconds |
| Started | Oct 02 08:54:53 PM UTC 24 |
| Finished | Oct 02 08:55:04 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673318239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.3673318239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_bad_addr.2287433799 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 765765826 ps |
| CPU time | 6.77 seconds |
| Started | Oct 02 08:55:19 PM UTC 24 |
| Finished | Oct 02 08:55:27 PM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2287433799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_bad_ad dr.2287433799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_acq.1932365321 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 710415312 ps |
| CPU time | 2.2 seconds |
| Started | Oct 02 08:55:15 PM UTC 24 |
| Finished | Oct 02 08:55:18 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932365 321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_acq.1932365321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_tx.220911830 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 651886240 ps |
| CPU time | 2.67 seconds |
| Started | Oct 02 08:55:16 PM UTC 24 |
| Finished | Oct 02 08:55:20 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209118 30 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_tx.220911830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_acq.1459487715 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 434225403 ps |
| CPU time | 3.48 seconds |
| Started | Oct 02 08:55:22 PM UTC 24 |
| Finished | Oct 02 08:55:26 PM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459487 715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_watermar ks_acq.1459487715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_tx.3663442220 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 165795213 ps |
| CPU time | 1.65 seconds |
| Started | Oct 02 08:55:25 PM UTC 24 |
| Finished | Oct 02 08:55:28 PM UTC 24 |
| Peak memory | 215020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663442 220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_watermark s_tx.3663442220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_intr_smoke.679103999 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 1923572538 ps |
| CPU time | 6.96 seconds |
| Started | Oct 02 08:55:09 PM UTC 24 |
| Finished | Oct 02 08:55:17 PM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679103 999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_smoke.679103999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.3798206220 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 10818373703 ps |
| CPU time | 18.01 seconds |
| Started | Oct 02 08:55:10 PM UTC 24 |
| Finished | Oct 02 08:55:29 PM UTC 24 |
| Peak memory | 506724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3798206220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_stres s_wr.3798206220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull.128754396 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 1159441626 ps |
| CPU time | 5.75 seconds |
| Started | Oct 02 08:55:26 PM UTC 24 |
| Finished | Oct 02 08:55:33 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287543 96 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_acqfull.128754396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull_addr.3448112505 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 443877819 ps |
| CPU time | 3.9 seconds |
| Started | Oct 02 08:55:27 PM UTC 24 |
| Finished | Oct 02 08:55:32 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448112 505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_acqfull_ad dr.3448112505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_nack_txstretch.1900733889 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 268559018 ps |
| CPU time | 2.26 seconds |
| Started | Oct 02 08:55:28 PM UTC 24 |
| Finished | Oct 02 08:55:31 PM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900733 889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_txstretch.1900733889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_perf.157006866 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 2259532863 ps |
| CPU time | 6.17 seconds |
| Started | Oct 02 08:55:17 PM UTC 24 |
| Finished | Oct 02 08:55:24 PM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570068 66 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_perf.157006866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_smbus_maxlen.3740747202 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 2392621314 ps |
| CPU time | 3.07 seconds |
| Started | Oct 02 08:55:26 PM UTC 24 |
| Finished | Oct 02 08:55:31 PM UTC 24 |
| Peak memory | 215164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740747 202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smbus_maxlen.3740747202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_smoke.2010867578 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 2433183341 ps |
| CPU time | 9.79 seconds |
| Started | Oct 02 08:54:58 PM UTC 24 |
| Finished | Oct 02 08:55:09 PM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010867578 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smoke.2010867578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.3720627580 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 41467300758 ps |
| CPU time | 326.78 seconds |
| Started | Oct 02 08:55:18 PM UTC 24 |
| Finished | Oct 02 09:00:49 PM UTC 24 |
| Peak memory | 1852196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372062 7580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_all.3720627580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_stress_rd.3951941632 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 1876109071 ps |
| CPU time | 37.23 seconds |
| Started | Oct 02 08:55:02 PM UTC 24 |
| Finished | Oct 02 08:55:41 PM UTC 24 |
| Peak memory | 248540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951941632 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_rd.3951941632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.2822147898 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 40721632521 ps |
| CPU time | 466.76 seconds |
| Started | Oct 02 08:54:59 PM UTC 24 |
| Finished | Oct 02 09:02:51 PM UTC 24 |
| Peak memory | 5280540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822147898 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_wr.2822147898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_stretch.3841458819 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 2114905787 ps |
| CPU time | 2.3 seconds |
| Started | Oct 02 08:55:05 PM UTC 24 |
| Finished | Oct 02 08:55:09 PM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841458819 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stretch.3841458819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_timeout.127297167 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 3025342178 ps |
| CPU time | 6.95 seconds |
| Started | Oct 02 08:55:10 PM UTC 24 |
| Finished | Oct 02 08:55:18 PM UTC 24 |
| Peak memory | 231784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272971 67 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_timeout.127297167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/44.i2c_target_tx_stretch_ctrl.4153536556 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 258885246 ps |
| CPU time | 7.98 seconds |
| Started | Oct 02 08:55:26 PM UTC 24 |
| Finished | Oct 02 08:55:36 PM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153536 556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.4153536556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/44.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_alert_test.820998174 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 28306624 ps |
| CPU time | 1.02 seconds |
| Started | Oct 02 08:56:07 PM UTC 24 |
| Finished | Oct 02 08:56:09 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820998174 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.820998174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_error_intr.2442791441 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 86455524 ps |
| CPU time | 2.6 seconds |
| Started | Oct 02 08:55:36 PM UTC 24 |
| Finished | Oct 02 08:55:40 PM UTC 24 |
| Peak memory | 232332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442791441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.2442791441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_fmt_empty.1855033020 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 260772305 ps |
| CPU time | 14.65 seconds |
| Started | Oct 02 08:55:32 PM UTC 24 |
| Finished | Oct 02 08:55:48 PM UTC 24 |
| Peak memory | 246692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855033020 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empty.1855033020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.2918304776 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 6051558705 ps |
| CPU time | 175.85 seconds |
| Started | Oct 02 08:55:33 PM UTC 24 |
| Finished | Oct 02 08:58:32 PM UTC 24 |
| Peak memory | 615004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918304776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.2918304776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.4076049495 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 4277663816 ps |
| CPU time | 72.14 seconds |
| Started | Oct 02 08:55:32 PM UTC 24 |
| Finished | Oct 02 08:56:46 PM UTC 24 |
| Peak memory | 623464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076049495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.4076049495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_fmt.3134780092 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 289652884 ps |
| CPU time | 1.98 seconds |
| Started | Oct 02 08:55:32 PM UTC 24 |
| Finished | Oct 02 08:55:35 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134780092 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fmt.3134780092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_rx.1415278138 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 264905271 ps |
| CPU time | 7.62 seconds |
| Started | Oct 02 08:55:33 PM UTC 24 |
| Finished | Oct 02 08:55:42 PM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415278138 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.1415278138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.569334016 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 5155533774 ps |
| CPU time | 149.49 seconds |
| Started | Oct 02 08:55:29 PM UTC 24 |
| Finished | Oct 02 08:58:02 PM UTC 24 |
| Peak memory | 1510260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569334016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.569334016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.3302617259 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 521330344 ps |
| CPU time | 9.11 seconds |
| Started | Oct 02 08:55:59 PM UTC 24 |
| Finished | Oct 02 08:56:09 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302617259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.3302617259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_mode_toggle.2336834661 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 122062066 ps |
| CPU time | 2.84 seconds |
| Started | Oct 02 08:55:58 PM UTC 24 |
| Finished | Oct 02 08:56:02 PM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336834661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.2336834661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_host_mode_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_override.1371475506 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 25777052 ps |
| CPU time | 1.04 seconds |
| Started | Oct 02 08:55:28 PM UTC 24 |
| Finished | Oct 02 08:55:30 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371475506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.1371475506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_perf.32916231 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 6864036951 ps |
| CPU time | 101.32 seconds |
| Started | Oct 02 08:55:33 PM UTC 24 |
| Finished | Oct 02 08:57:17 PM UTC 24 |
| Peak memory | 609040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32916231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho st_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.32916231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_perf_precise.4062795665 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 6152397093 ps |
| CPU time | 300.55 seconds |
| Started | Oct 02 08:55:34 PM UTC 24 |
| Finished | Oct 02 09:00:39 PM UTC 24 |
| Peak memory | 760672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062795665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.4062795665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.2078638553 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 1897747563 ps |
| CPU time | 88.13 seconds |
| Started | Oct 02 08:55:28 PM UTC 24 |
| Finished | Oct 02 08:56:58 PM UTC 24 |
| Peak memory | 297752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078638553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.2078638553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_stress_all.3104024817 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 8093263949 ps |
| CPU time | 538.11 seconds |
| Started | Oct 02 08:55:36 PM UTC 24 |
| Finished | Oct 02 09:04:41 PM UTC 24 |
| Peak memory | 1170224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104024817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.3104024817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_host_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.3837287490 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 708505382 ps |
| CPU time | 38.43 seconds |
| Started | Oct 02 08:55:36 PM UTC 24 |
| Finished | Oct 02 08:56:16 PM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837287490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.3837287490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.1199856973 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 3146437205 ps |
| CPU time | 7.8 seconds |
| Started | Oct 02 08:55:57 PM UTC 24 |
| Finished | Oct 02 08:56:05 PM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1199856973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_bad_ad dr.1199856973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_acq.2060897400 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 198828185 ps |
| CPU time | 2.27 seconds |
| Started | Oct 02 08:55:52 PM UTC 24 |
| Finished | Oct 02 08:55:55 PM UTC 24 |
| Peak memory | 215044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060897 400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_acq.2060897400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_tx.103538417 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 498140086 ps |
| CPU time | 1.89 seconds |
| Started | Oct 02 08:55:54 PM UTC 24 |
| Finished | Oct 02 08:55:57 PM UTC 24 |
| Peak memory | 224848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035384 17 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_tx.103538417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.1872023980 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 494794927 ps |
| CPU time | 3.3 seconds |
| Started | Oct 02 08:56:01 PM UTC 24 |
| Finished | Oct 02 08:56:05 PM UTC 24 |
| Peak memory | 215300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872023 980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_watermar ks_acq.1872023980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.449986277 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 814522990 ps |
| CPU time | 2.07 seconds |
| Started | Oct 02 08:56:02 PM UTC 24 |
| Finished | Oct 02 08:56:05 PM UTC 24 |
| Peak memory | 215240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4499862 77 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_watermarks _tx.449986277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_intr_smoke.233407716 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 857586431 ps |
| CPU time | 9.14 seconds |
| Started | Oct 02 08:55:45 PM UTC 24 |
| Finished | Oct 02 08:55:55 PM UTC 24 |
| Peak memory | 232396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233407 716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_smoke.233407716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.2601964440 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 4150846198 ps |
| CPU time | 42.89 seconds |
| Started | Oct 02 08:55:47 PM UTC 24 |
| Finished | Oct 02 08:56:31 PM UTC 24 |
| Peak memory | 1133340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2601964440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_stres s_wr.2601964440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.3632165325 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 542785315 ps |
| CPU time | 3.79 seconds |
| Started | Oct 02 08:56:06 PM UTC 24 |
| Finished | Oct 02 08:56:11 PM UTC 24 |
| Peak memory | 225752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632165 325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_acqfull.3632165325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.1116199116 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 495722481 ps |
| CPU time | 4.67 seconds |
| Started | Oct 02 08:56:06 PM UTC 24 |
| Finished | Oct 02 08:56:12 PM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116199 116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_acqfull_ad dr.1116199116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_nack_txstretch.2490323191 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 131437858 ps |
| CPU time | 1.94 seconds |
| Started | Oct 02 08:56:06 PM UTC 24 |
| Finished | Oct 02 08:56:09 PM UTC 24 |
| Peak memory | 231628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490323 191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_txstretch.2490323191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_perf.317125177 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 2795628526 ps |
| CPU time | 8.16 seconds |
| Started | Oct 02 08:55:55 PM UTC 24 |
| Finished | Oct 02 08:56:05 PM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171251 77 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_perf.317125177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.3480469983 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 377112691 ps |
| CPU time | 4.24 seconds |
| Started | Oct 02 08:56:05 PM UTC 24 |
| Finished | Oct 02 08:56:10 PM UTC 24 |
| Peak memory | 215228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480469 983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smbus_maxlen.3480469983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.2625208795 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 1114724052 ps |
| CPU time | 20.78 seconds |
| Started | Oct 02 08:55:38 PM UTC 24 |
| Finished | Oct 02 08:56:00 PM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625208795 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smoke.2625208795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.3689314447 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 7127628129 ps |
| CPU time | 58.43 seconds |
| Started | Oct 02 08:55:57 PM UTC 24 |
| Finished | Oct 02 08:56:57 PM UTC 24 |
| Peak memory | 740192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368931 4447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_all.3689314447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.3681268526 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 7805013071 ps |
| CPU time | 50.26 seconds |
| Started | Oct 02 08:55:42 PM UTC 24 |
| Finished | Oct 02 08:56:34 PM UTC 24 |
| Peak memory | 242616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681268526 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_rd.3681268526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.852067798 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 44329992383 ps |
| CPU time | 252.32 seconds |
| Started | Oct 02 08:55:41 PM UTC 24 |
| Finished | Oct 02 08:59:56 PM UTC 24 |
| Peak memory | 2782056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852067798 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_wr.852067798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_stretch.393965434 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 4899285576 ps |
| CPU time | 24.29 seconds |
| Started | Oct 02 08:55:43 PM UTC 24 |
| Finished | Oct 02 08:56:08 PM UTC 24 |
| Peak memory | 324504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393965434 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stretch.393965434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.361227208 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 1320769004 ps |
| CPU time | 13.33 seconds |
| Started | Oct 02 08:55:47 PM UTC 24 |
| Finished | Oct 02 08:56:02 PM UTC 24 |
| Peak memory | 225772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612272 08 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_timeout.361227208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.127952208 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 163329722 ps |
| CPU time | 2.43 seconds |
| Started | Oct 02 08:56:02 PM UTC 24 |
| Finished | Oct 02 08:56:05 PM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279522 08 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.127952208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_alert_test.1686365452 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 22910438 ps |
| CPU time | 0.93 seconds |
| Started | Oct 02 08:56:56 PM UTC 24 |
| Finished | Oct 02 08:56:58 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686365452 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1686365452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.3209708501 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 386995878 ps |
| CPU time | 3.61 seconds |
| Started | Oct 02 08:56:17 PM UTC 24 |
| Finished | Oct 02 08:56:21 PM UTC 24 |
| Peak memory | 242680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209708501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3209708501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.835597831 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 513705773 ps |
| CPU time | 32.72 seconds |
| Started | Oct 02 08:56:11 PM UTC 24 |
| Finished | Oct 02 08:56:45 PM UTC 24 |
| Peak memory | 314136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835597831 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empty.835597831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.2304709756 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 34412397700 ps |
| CPU time | 116.57 seconds |
| Started | Oct 02 08:56:12 PM UTC 24 |
| Finished | Oct 02 08:58:11 PM UTC 24 |
| Peak memory | 748312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304709756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.2304709756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.2426547342 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 20617112620 ps |
| CPU time | 73.33 seconds |
| Started | Oct 02 08:56:11 PM UTC 24 |
| Finished | Oct 02 08:57:26 PM UTC 24 |
| Peak memory | 629672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426547342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2426547342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.1209271802 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 173943164 ps |
| CPU time | 1.46 seconds |
| Started | Oct 02 08:56:11 PM UTC 24 |
| Finished | Oct 02 08:56:13 PM UTC 24 |
| Peak memory | 214612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209271802 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fmt.1209271802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.1518225492 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 866358271 ps |
| CPU time | 7.6 seconds |
| Started | Oct 02 08:56:12 PM UTC 24 |
| Finished | Oct 02 08:56:21 PM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518225492 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.1518225492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.3200759385 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 12882534247 ps |
| CPU time | 86.47 seconds |
| Started | Oct 02 08:56:10 PM UTC 24 |
| Finished | Oct 02 08:57:38 PM UTC 24 |
| Peak memory | 1037104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200759385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.3200759385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.226910098 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 573409658 ps |
| CPU time | 12.62 seconds |
| Started | Oct 02 08:56:50 PM UTC 24 |
| Finished | Oct 02 08:57:04 PM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226910098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.226910098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_mode_toggle.836395638 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 142102695 ps |
| CPU time | 4.26 seconds |
| Started | Oct 02 08:56:50 PM UTC 24 |
| Finished | Oct 02 08:56:56 PM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836395638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.836395638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_host_mode_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_override.2711455834 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 80787600 ps |
| CPU time | 1.06 seconds |
| Started | Oct 02 08:56:10 PM UTC 24 |
| Finished | Oct 02 08:56:12 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711455834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.2711455834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_perf.1974722831 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 6693002412 ps |
| CPU time | 29.51 seconds |
| Started | Oct 02 08:56:13 PM UTC 24 |
| Finished | Oct 02 08:56:44 PM UTC 24 |
| Peak memory | 215380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974722831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.1974722831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.677218332 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 85550801 ps |
| CPU time | 3.05 seconds |
| Started | Oct 02 08:56:14 PM UTC 24 |
| Finished | Oct 02 08:56:18 PM UTC 24 |
| Peak memory | 235872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677218332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.677218332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.4268346923 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 5613903699 ps |
| CPU time | 23.27 seconds |
| Started | Oct 02 08:56:10 PM UTC 24 |
| Finished | Oct 02 08:56:34 PM UTC 24 |
| Peak memory | 297940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268346923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.4268346923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.2825727225 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 2338461642 ps |
| CPU time | 36.64 seconds |
| Started | Oct 02 08:56:14 PM UTC 24 |
| Finished | Oct 02 08:56:52 PM UTC 24 |
| Peak memory | 225560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825727225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2825727225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.387391279 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 1454317886 ps |
| CPU time | 5.67 seconds |
| Started | Oct 02 08:56:47 PM UTC 24 |
| Finished | Oct 02 08:56:55 PM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=387391279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.387391279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.3644431684 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 430009767 ps |
| CPU time | 2.33 seconds |
| Started | Oct 02 08:56:46 PM UTC 24 |
| Finished | Oct 02 08:56:49 PM UTC 24 |
| Peak memory | 217304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644431 684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_acq.3644431684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.3666615109 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 366572932 ps |
| CPU time | 2.23 seconds |
| Started | Oct 02 08:56:46 PM UTC 24 |
| Finished | Oct 02 08:56:49 PM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666615 109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_tx.3666615109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.1083046912 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 1704762280 ps |
| CPU time | 4.26 seconds |
| Started | Oct 02 08:56:50 PM UTC 24 |
| Finished | Oct 02 08:56:56 PM UTC 24 |
| Peak memory | 215528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083046 912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_watermar ks_acq.1083046912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.137238182 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 3318715574 ps |
| CPU time | 9.72 seconds |
| Started | Oct 02 08:56:34 PM UTC 24 |
| Finished | Oct 02 08:56:45 PM UTC 24 |
| Peak memory | 227812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137238 182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_smoke.137238182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.1194070586 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 22781697764 ps |
| CPU time | 432.75 seconds |
| Started | Oct 02 08:56:35 PM UTC 24 |
| Finished | Oct 02 09:03:53 PM UTC 24 |
| Peak memory | 5841696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1194070586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_stres s_wr.1194070586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.4140937901 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 2111064996 ps |
| CPU time | 5.04 seconds |
| Started | Oct 02 08:56:54 PM UTC 24 |
| Finished | Oct 02 08:57:00 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140937 901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_acqfull.4140937901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.2386896091 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 951680725 ps |
| CPU time | 2.85 seconds |
| Started | Oct 02 08:56:54 PM UTC 24 |
| Finished | Oct 02 08:56:58 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386896 091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_acqfull_ad dr.2386896091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_nack_txstretch.69422072 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 287652483 ps |
| CPU time | 2.21 seconds |
| Started | Oct 02 08:56:55 PM UTC 24 |
| Finished | Oct 02 08:56:58 PM UTC 24 |
| Peak memory | 232224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6942207 2 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_txstretch.69422072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_perf.2966559208 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 3844561681 ps |
| CPU time | 4.54 seconds |
| Started | Oct 02 08:56:47 PM UTC 24 |
| Finished | Oct 02 08:56:53 PM UTC 24 |
| Peak memory | 232284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966559 208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_perf.2966559208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.2957650349 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 1998345231 ps |
| CPU time | 4.21 seconds |
| Started | Oct 02 08:56:51 PM UTC 24 |
| Finished | Oct 02 08:56:57 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957650 349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smbus_maxlen.2957650349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.3705510513 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 1253197302 ps |
| CPU time | 22.01 seconds |
| Started | Oct 02 08:56:22 PM UTC 24 |
| Finished | Oct 02 08:56:45 PM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705510513 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smoke.3705510513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.433728928 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 14956253797 ps |
| CPU time | 165.19 seconds |
| Started | Oct 02 08:56:47 PM UTC 24 |
| Finished | Oct 02 08:59:35 PM UTC 24 |
| Peak memory | 947036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433728 928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_all.433728928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.1246939861 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 11334032074 ps |
| CPU time | 20.28 seconds |
| Started | Oct 02 08:56:25 PM UTC 24 |
| Finished | Oct 02 08:56:46 PM UTC 24 |
| Peak memory | 231848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246939861 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_rd.1246939861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.1088954841 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 29111076898 ps |
| CPU time | 195.32 seconds |
| Started | Oct 02 08:56:22 PM UTC 24 |
| Finished | Oct 02 08:59:40 PM UTC 24 |
| Peak memory | 2118428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088954841 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_wr.1088954841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.4197650847 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 1150622889 ps |
| CPU time | 9.39 seconds |
| Started | Oct 02 08:56:39 PM UTC 24 |
| Finished | Oct 02 08:56:50 PM UTC 24 |
| Peak memory | 229652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197650 847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_timeout.4197650847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.632021256 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 1272119237 ps |
| CPU time | 15.33 seconds |
| Started | Oct 02 08:56:51 PM UTC 24 |
| Finished | Oct 02 08:57:08 PM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6320212 56 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.632021256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_alert_test.578719957 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 199991260 ps |
| CPU time | 0.95 seconds |
| Started | Oct 02 08:57:35 PM UTC 24 |
| Finished | Oct 02 08:57:37 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578719957 -assert nopostproc +UVM_TESTNAME=i2c_bas e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.578719957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.2455591464 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 155413029 ps |
| CPU time | 3.33 seconds |
| Started | Oct 02 08:57:05 PM UTC 24 |
| Finished | Oct 02 08:57:09 PM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455591464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.2455591464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.2821428484 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 1038242434 ps |
| CPU time | 15.23 seconds |
| Started | Oct 02 08:56:58 PM UTC 24 |
| Finished | Oct 02 08:57:15 PM UTC 24 |
| Peak memory | 271056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821428484 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empty.2821428484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.389367335 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 3787465683 ps |
| CPU time | 43.33 seconds |
| Started | Oct 02 08:56:59 PM UTC 24 |
| Finished | Oct 02 08:57:44 PM UTC 24 |
| Peak memory | 469788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389367335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.389367335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.1473084756 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 1227560762 ps |
| CPU time | 92.99 seconds |
| Started | Oct 02 08:56:58 PM UTC 24 |
| Finished | Oct 02 08:58:33 PM UTC 24 |
| Peak memory | 516840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473084756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1473084756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.1266887518 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 1020179754 ps |
| CPU time | 1.68 seconds |
| Started | Oct 02 08:56:58 PM UTC 24 |
| Finished | Oct 02 08:57:01 PM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266887518 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fmt.1266887518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.802295392 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 445351639 ps |
| CPU time | 8.19 seconds |
| Started | Oct 02 08:56:59 PM UTC 24 |
| Finished | Oct 02 08:57:09 PM UTC 24 |
| Peak memory | 230128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802295392 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.802295392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.1015033 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 16574705329 ps |
| CPU time | 119.87 seconds |
| Started | Oct 02 08:56:57 PM UTC 24 |
| Finished | Oct 02 08:58:59 PM UTC 24 |
| Peak memory | 1276728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_hos t_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1015033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.1398864693 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 3323677733 ps |
| CPU time | 17.84 seconds |
| Started | Oct 02 08:57:27 PM UTC 24 |
| Finished | Oct 02 08:57:46 PM UTC 24 |
| Peak memory | 215304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398864693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.1398864693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_override.2149099619 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 39502816 ps |
| CPU time | 0.91 seconds |
| Started | Oct 02 08:56:57 PM UTC 24 |
| Finished | Oct 02 08:56:59 PM UTC 24 |
| Peak memory | 214088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149099619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2149099619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.721807529 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 152862629 ps |
| CPU time | 8.85 seconds |
| Started | Oct 02 08:57:01 PM UTC 24 |
| Finished | Oct 02 08:57:11 PM UTC 24 |
| Peak memory | 215248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721807529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.721807529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.423291621 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 6905753857 ps |
| CPU time | 80.67 seconds |
| Started | Oct 02 08:56:57 PM UTC 24 |
| Finished | Oct 02 08:58:19 PM UTC 24 |
| Peak memory | 363268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423291621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.423291621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.2031665942 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 12049296105 ps |
| CPU time | 25.18 seconds |
| Started | Oct 02 08:57:02 PM UTC 24 |
| Finished | Oct 02 08:57:28 PM UTC 24 |
| Peak memory | 242540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031665942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.2031665942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.1945730693 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 17804661912 ps |
| CPU time | 10.46 seconds |
| Started | Oct 02 08:57:24 PM UTC 24 |
| Finished | Oct 02 08:57:36 PM UTC 24 |
| Peak memory | 229732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1945730693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_ad dr.1945730693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.3975058649 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 218057649 ps |
| CPU time | 1.51 seconds |
| Started | Oct 02 08:57:21 PM UTC 24 |
| Finished | Oct 02 08:57:23 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975058 649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_acq.3975058649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.1819247008 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 384084186 ps |
| CPU time | 1.71 seconds |
| Started | Oct 02 08:57:21 PM UTC 24 |
| Finished | Oct 02 08:57:24 PM UTC 24 |
| Peak memory | 214788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819247 008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_tx.1819247008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.1554854812 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 558574188 ps |
| CPU time | 5.63 seconds |
| Started | Oct 02 08:57:27 PM UTC 24 |
| Finished | Oct 02 08:57:34 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554854 812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_watermar ks_acq.1554854812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.1713122414 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 271637079 ps |
| CPU time | 1.97 seconds |
| Started | Oct 02 08:57:29 PM UTC 24 |
| Finished | Oct 02 08:57:31 PM UTC 24 |
| Peak memory | 214780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713122 414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_watermark s_tx.1713122414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_hrst.2800222133 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 828335753 ps |
| CPU time | 3.47 seconds |
| Started | Oct 02 08:57:24 PM UTC 24 |
| Finished | Oct 02 08:57:29 PM UTC 24 |
| Peak memory | 227672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800222 133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_hrst.2800222133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.3308006511 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 2863867105 ps |
| CPU time | 9.08 seconds |
| Started | Oct 02 08:57:11 PM UTC 24 |
| Finished | Oct 02 08:57:22 PM UTC 24 |
| Peak memory | 232480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330800 6511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_smoke.3308006511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.288363930 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 32102098703 ps |
| CPU time | 19.88 seconds |
| Started | Oct 02 08:57:15 PM UTC 24 |
| Finished | Oct 02 08:57:37 PM UTC 24 |
| Peak memory | 525092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=288363930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_stress _wr.288363930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.2448444673 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 1770860383 ps |
| CPU time | 3.1 seconds |
| Started | Oct 02 08:57:31 PM UTC 24 |
| Finished | Oct 02 08:57:35 PM UTC 24 |
| Peak memory | 225628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448444 673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_acqfull.2448444673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.1264979001 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 8015498744 ps |
| CPU time | 4.61 seconds |
| Started | Oct 02 08:57:31 PM UTC 24 |
| Finished | Oct 02 08:57:37 PM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264979 001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_acqfull_ad dr.1264979001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.598464745 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 368699529 ps |
| CPU time | 2.57 seconds |
| Started | Oct 02 08:57:32 PM UTC 24 |
| Finished | Oct 02 08:57:36 PM UTC 24 |
| Peak memory | 232088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5984647 45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_txstretch.598464745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_perf.2891901408 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 758685050 ps |
| CPU time | 6.44 seconds |
| Started | Oct 02 08:57:23 PM UTC 24 |
| Finished | Oct 02 08:57:30 PM UTC 24 |
| Peak memory | 232376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891901 408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_perf.2891901408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.3576573011 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 3010488240 ps |
| CPU time | 4.28 seconds |
| Started | Oct 02 08:57:30 PM UTC 24 |
| Finished | Oct 02 08:57:35 PM UTC 24 |
| Peak memory | 215228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576573 011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smbus_maxlen.3576573011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.65290021 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 826158682 ps |
| CPU time | 16.76 seconds |
| Started | Oct 02 08:57:09 PM UTC 24 |
| Finished | Oct 02 08:57:27 PM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65290021 -assert nopostpro c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smoke.65290021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.3541670888 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 90649196773 ps |
| CPU time | 91.29 seconds |
| Started | Oct 02 08:57:23 PM UTC 24 |
| Finished | Oct 02 08:58:56 PM UTC 24 |
| Peak memory | 1125292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354167 0888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_all.3541670888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.3266066534 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 6387514328 ps |
| CPU time | 29.62 seconds |
| Started | Oct 02 08:57:10 PM UTC 24 |
| Finished | Oct 02 08:57:41 PM UTC 24 |
| Peak memory | 248860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266066534 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_rd.3266066534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.769954690 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 48414822677 ps |
| CPU time | 128.55 seconds |
| Started | Oct 02 08:57:10 PM UTC 24 |
| Finished | Oct 02 08:59:21 PM UTC 24 |
| Peak memory | 1805152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769954690 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_wr.769954690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.1596269879 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 1807852859 ps |
| CPU time | 8.71 seconds |
| Started | Oct 02 08:57:10 PM UTC 24 |
| Finished | Oct 02 08:57:20 PM UTC 24 |
| Peak memory | 215120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596269879 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stretch.1596269879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.662520322 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 16938746755 ps |
| CPU time | 7.99 seconds |
| Started | Oct 02 08:57:18 PM UTC 24 |
| Finished | Oct 02 08:57:27 PM UTC 24 |
| Peak memory | 232296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6625203 22 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_timeout.662520322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.4293937797 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 384119472 ps |
| CPU time | 8.77 seconds |
| Started | Oct 02 08:57:30 PM UTC 24 |
| Finished | Oct 02 08:57:40 PM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293937 797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.4293937797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_alert_test.3893297373 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 19569741 ps |
| CPU time | 0.93 seconds |
| Started | Oct 02 08:58:17 PM UTC 24 |
| Finished | Oct 02 08:58:19 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893297373 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.3893297373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.3475006828 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 212879248 ps |
| CPU time | 2.05 seconds |
| Started | Oct 02 08:57:41 PM UTC 24 |
| Finished | Oct 02 08:57:44 PM UTC 24 |
| Peak memory | 225720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475006828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.3475006828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.2094404523 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 869312339 ps |
| CPU time | 4.59 seconds |
| Started | Oct 02 08:57:38 PM UTC 24 |
| Finished | Oct 02 08:57:43 PM UTC 24 |
| Peak memory | 254876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094404523 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empty.2094404523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.1054095700 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 32149949531 ps |
| CPU time | 67.07 seconds |
| Started | Oct 02 08:57:39 PM UTC 24 |
| Finished | Oct 02 08:58:47 PM UTC 24 |
| Peak memory | 289756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054095700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.1054095700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.717911684 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 9335137999 ps |
| CPU time | 64.86 seconds |
| Started | Oct 02 08:57:36 PM UTC 24 |
| Finished | Oct 02 08:58:43 PM UTC 24 |
| Peak memory | 682780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717911684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.717911684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.3052956908 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 512397518 ps |
| CPU time | 1.38 seconds |
| Started | Oct 02 08:57:38 PM UTC 24 |
| Finished | Oct 02 08:57:40 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052956908 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fmt.3052956908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.558987966 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 300391306 ps |
| CPU time | 4.21 seconds |
| Started | Oct 02 08:57:38 PM UTC 24 |
| Finished | Oct 02 08:57:43 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558987966 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.558987966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.4196193445 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 2910254557 ps |
| CPU time | 64.64 seconds |
| Started | Oct 02 08:57:36 PM UTC 24 |
| Finished | Oct 02 08:58:43 PM UTC 24 |
| Peak memory | 928484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196193445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.4196193445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.2640897505 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 217113905 ps |
| CPU time | 8.69 seconds |
| Started | Oct 02 08:58:13 PM UTC 24 |
| Finished | Oct 02 08:58:23 PM UTC 24 |
| Peak memory | 215184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640897505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.2640897505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_override.3882256662 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 43708981 ps |
| CPU time | 1.07 seconds |
| Started | Oct 02 08:57:36 PM UTC 24 |
| Finished | Oct 02 08:57:38 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882256662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.3882256662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_perf.3369856229 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 2485833426 ps |
| CPU time | 50.45 seconds |
| Started | Oct 02 08:57:39 PM UTC 24 |
| Finished | Oct 02 08:58:31 PM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369856229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.3369856229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.281602503 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 147084298 ps |
| CPU time | 1.83 seconds |
| Started | Oct 02 08:57:40 PM UTC 24 |
| Finished | Oct 02 08:57:43 PM UTC 24 |
| Peak memory | 234888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281602503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.281602503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.870386054 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 1250456361 ps |
| CPU time | 58.21 seconds |
| Started | Oct 02 08:57:36 PM UTC 24 |
| Finished | Oct 02 08:58:36 PM UTC 24 |
| Peak memory | 314196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870386054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.870386054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.2345780123 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 823628990 ps |
| CPU time | 41.95 seconds |
| Started | Oct 02 08:57:40 PM UTC 24 |
| Finished | Oct 02 08:58:23 PM UTC 24 |
| Peak memory | 225436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345780123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.2345780123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.2096503443 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 1963878905 ps |
| CPU time | 10.51 seconds |
| Started | Oct 02 08:58:03 PM UTC 24 |
| Finished | Oct 02 08:58:15 PM UTC 24 |
| Peak memory | 232308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2096503443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_bad_ad dr.2096503443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.605011419 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 177198831 ps |
| CPU time | 1.94 seconds |
| Started | Oct 02 08:57:59 PM UTC 24 |
| Finished | Oct 02 08:58:02 PM UTC 24 |
| Peak memory | 214848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6050114 19 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_acq.605011419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.4259590095 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 960382255 ps |
| CPU time | 3.18 seconds |
| Started | Oct 02 08:58:01 PM UTC 24 |
| Finished | Oct 02 08:58:05 PM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259590 095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_tx.4259590095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.1975033972 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 9971636979 ps |
| CPU time | 3.25 seconds |
| Started | Oct 02 08:58:13 PM UTC 24 |
| Finished | Oct 02 08:58:17 PM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975033 972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_watermar ks_acq.1975033972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.2209767064 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 620742468 ps |
| CPU time | 2.35 seconds |
| Started | Oct 02 08:58:13 PM UTC 24 |
| Finished | Oct 02 08:58:17 PM UTC 24 |
| Peak memory | 215240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209767 064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_watermark s_tx.2209767064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.998131657 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 1338160009 ps |
| CPU time | 13.09 seconds |
| Started | Oct 02 08:57:46 PM UTC 24 |
| Finished | Oct 02 08:58:00 PM UTC 24 |
| Peak memory | 232364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998131 657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_smoke.998131657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.1337868468 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 5737692988 ps |
| CPU time | 67.11 seconds |
| Started | Oct 02 08:57:48 PM UTC 24 |
| Finished | Oct 02 08:58:56 PM UTC 24 |
| Peak memory | 1420060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1337868468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_stres s_wr.1337868468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.4156662124 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 595836622 ps |
| CPU time | 5.17 seconds |
| Started | Oct 02 08:58:15 PM UTC 24 |
| Finished | Oct 02 08:58:21 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156662 124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_acqfull.4156662124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.152258778 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 1923685187 ps |
| CPU time | 4.7 seconds |
| Started | Oct 02 08:58:16 PM UTC 24 |
| Finished | Oct 02 08:58:22 PM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522587 78 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_acqfull_addr.152258778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_perf.2771119914 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 2364950701 ps |
| CPU time | 9.14 seconds |
| Started | Oct 02 08:58:01 PM UTC 24 |
| Finished | Oct 02 08:58:11 PM UTC 24 |
| Peak memory | 242432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771119 914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_perf.2771119914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.3378366498 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 939713018 ps |
| CPU time | 3.57 seconds |
| Started | Oct 02 08:58:14 PM UTC 24 |
| Finished | Oct 02 08:58:18 PM UTC 24 |
| Peak memory | 215004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378366 498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smbus_maxlen.3378366498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.3317004261 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 4702853226 ps |
| CPU time | 9.56 seconds |
| Started | Oct 02 08:57:43 PM UTC 24 |
| Finished | Oct 02 08:57:54 PM UTC 24 |
| Peak memory | 225632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317004261 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smoke.3317004261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.3097226063 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 50380011586 ps |
| CPU time | 61.29 seconds |
| Started | Oct 02 08:58:02 PM UTC 24 |
| Finished | Oct 02 08:59:05 PM UTC 24 |
| Peak memory | 295996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309722 6063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_all.3097226063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.1764067631 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 1536205471 ps |
| CPU time | 26.53 seconds |
| Started | Oct 02 08:57:44 PM UTC 24 |
| Finished | Oct 02 08:58:12 PM UTC 24 |
| Peak memory | 234348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764067631 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_rd.1764067631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.1388320930 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 30287957290 ps |
| CPU time | 33.04 seconds |
| Started | Oct 02 08:57:44 PM UTC 24 |
| Finished | Oct 02 08:58:19 PM UTC 24 |
| Peak memory | 627564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388320930 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_wr.1388320930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.3811473766 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 5088407684 ps |
| CPU time | 11.09 seconds |
| Started | Oct 02 08:57:50 PM UTC 24 |
| Finished | Oct 02 08:58:02 PM UTC 24 |
| Peak memory | 229872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811473 766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_timeout.3811473766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.757844670 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 54870123 ps |
| CPU time | 1.64 seconds |
| Started | Oct 02 08:58:13 PM UTC 24 |
| Finished | Oct 02 08:58:16 PM UTC 24 |
| Peak memory | 215052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7578446 70 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.757844670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_alert_test.3955475675 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 15803975 ps |
| CPU time | 1.02 seconds |
| Started | Oct 02 08:58:48 PM UTC 24 |
| Finished | Oct 02 08:58:50 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955475675 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.3955475675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.633940034 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 227150263 ps |
| CPU time | 3.12 seconds |
| Started | Oct 02 08:58:23 PM UTC 24 |
| Finished | Oct 02 08:58:28 PM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633940034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.633940034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.563703006 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 402272400 ps |
| CPU time | 7.27 seconds |
| Started | Oct 02 08:58:20 PM UTC 24 |
| Finished | Oct 02 08:58:29 PM UTC 24 |
| Peak memory | 283492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563703006 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empty.563703006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.120256134 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 8466987984 ps |
| CPU time | 88.73 seconds |
| Started | Oct 02 08:58:22 PM UTC 24 |
| Finished | Oct 02 08:59:53 PM UTC 24 |
| Peak memory | 740316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120256134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.120256134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.1063238223 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 4040869245 ps |
| CPU time | 121.23 seconds |
| Started | Oct 02 08:58:19 PM UTC 24 |
| Finished | Oct 02 09:00:23 PM UTC 24 |
| Peak memory | 580456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063238223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1063238223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.1146276333 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 299229790 ps |
| CPU time | 1.37 seconds |
| Started | Oct 02 08:58:19 PM UTC 24 |
| Finished | Oct 02 08:58:22 PM UTC 24 |
| Peak memory | 214904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146276333 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fmt.1146276333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.2476794388 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 911147979 ps |
| CPU time | 8.82 seconds |
| Started | Oct 02 08:58:22 PM UTC 24 |
| Finished | Oct 02 08:58:32 PM UTC 24 |
| Peak memory | 246428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476794388 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.2476794388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.2060632882 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 22594297466 ps |
| CPU time | 114.53 seconds |
| Started | Oct 02 08:58:19 PM UTC 24 |
| Finished | Oct 02 09:00:16 PM UTC 24 |
| Peak memory | 1428336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060632882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.2060632882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.2977565659 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 2128820530 ps |
| CPU time | 22.19 seconds |
| Started | Oct 02 08:58:43 PM UTC 24 |
| Finished | Oct 02 08:59:07 PM UTC 24 |
| Peak memory | 215240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977565659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.2977565659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_override.2412369793 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 29158135 ps |
| CPU time | 1.1 seconds |
| Started | Oct 02 08:58:18 PM UTC 24 |
| Finished | Oct 02 08:58:20 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412369793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.2412369793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_perf.1093143735 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 4869139251 ps |
| CPU time | 51.6 seconds |
| Started | Oct 02 08:58:22 PM UTC 24 |
| Finished | Oct 02 08:59:15 PM UTC 24 |
| Peak memory | 332664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093143735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1093143735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.3755299206 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 631819444 ps |
| CPU time | 28.61 seconds |
| Started | Oct 02 08:58:22 PM UTC 24 |
| Finished | Oct 02 08:58:52 PM UTC 24 |
| Peak memory | 330292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755299206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.3755299206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.3627868979 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 7581938306 ps |
| CPU time | 40.59 seconds |
| Started | Oct 02 08:58:18 PM UTC 24 |
| Finished | Oct 02 08:59:00 PM UTC 24 |
| Peak memory | 369440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627868979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.3627868979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.2326092955 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 3511787844 ps |
| CPU time | 10.83 seconds |
| Started | Oct 02 08:58:23 PM UTC 24 |
| Finished | Oct 02 08:58:35 PM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326092955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.2326092955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.2274021956 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 798315756 ps |
| CPU time | 7.08 seconds |
| Started | Oct 02 08:58:41 PM UTC 24 |
| Finished | Oct 02 08:58:49 PM UTC 24 |
| Peak memory | 225512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2274021956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_bad_ad dr.2274021956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.2717695305 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 229172039 ps |
| CPU time | 2.55 seconds |
| Started | Oct 02 08:58:36 PM UTC 24 |
| Finished | Oct 02 08:58:40 PM UTC 24 |
| Peak memory | 215040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717695 305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_acq.2717695305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.230165491 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 221835397 ps |
| CPU time | 2.22 seconds |
| Started | Oct 02 08:58:37 PM UTC 24 |
| Finished | Oct 02 08:58:40 PM UTC 24 |
| Peak memory | 215336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301654 91 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_tx.230165491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.973400714 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 2975833252 ps |
| CPU time | 2.98 seconds |
| Started | Oct 02 08:58:43 PM UTC 24 |
| Finished | Oct 02 08:58:48 PM UTC 24 |
| Peak memory | 215096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9734007 14 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_watermark s_acq.973400714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.2957585171 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 380304919 ps |
| CPU time | 1.63 seconds |
| Started | Oct 02 08:58:44 PM UTC 24 |
| Finished | Oct 02 08:58:46 PM UTC 24 |
| Peak memory | 214960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957585 171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_watermark s_tx.2957585171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.3582174325 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 993262086 ps |
| CPU time | 7.27 seconds |
| Started | Oct 02 08:58:31 PM UTC 24 |
| Finished | Oct 02 08:58:40 PM UTC 24 |
| Peak memory | 229588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358217 4325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_smoke.3582174325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.643292154 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 11337403551 ps |
| CPU time | 7.23 seconds |
| Started | Oct 02 08:58:33 PM UTC 24 |
| Finished | Oct 02 08:58:41 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=643292154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_stress _wr.643292154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.3685854799 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 390691271 ps |
| CPU time | 3.84 seconds |
| Started | Oct 02 08:58:46 PM UTC 24 |
| Finished | Oct 02 08:58:51 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685854 799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_acqfull.3685854799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.3662310618 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 1054995431 ps |
| CPU time | 4.41 seconds |
| Started | Oct 02 08:58:47 PM UTC 24 |
| Finished | Oct 02 08:58:52 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662310 618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_acqfull_ad dr.3662310618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_perf.2801741727 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 852115265 ps |
| CPU time | 9.74 seconds |
| Started | Oct 02 08:58:38 PM UTC 24 |
| Finished | Oct 02 08:58:49 PM UTC 24 |
| Peak memory | 231844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801741 727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_perf.2801741727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.2217876250 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 786200103 ps |
| CPU time | 2.34 seconds |
| Started | Oct 02 08:58:45 PM UTC 24 |
| Finished | Oct 02 08:58:48 PM UTC 24 |
| Peak memory | 215100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217876 250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smbus_maxlen.2217876250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.577621713 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 3718432115 ps |
| CPU time | 18.14 seconds |
| Started | Oct 02 08:58:24 PM UTC 24 |
| Finished | Oct 02 08:58:43 PM UTC 24 |
| Peak memory | 225824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577621713 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smoke.577621713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.3112200829 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 11185904988 ps |
| CPU time | 52.35 seconds |
| Started | Oct 02 08:58:40 PM UTC 24 |
| Finished | Oct 02 08:59:34 PM UTC 24 |
| Peak memory | 250744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311220 0829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_all.3112200829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.490823360 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 814747304 ps |
| CPU time | 34.87 seconds |
| Started | Oct 02 08:58:28 PM UTC 24 |
| Finished | Oct 02 08:59:04 PM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490823360 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_rd.490823360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.2057443809 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 39876827604 ps |
| CPU time | 129.9 seconds |
| Started | Oct 02 08:58:25 PM UTC 24 |
| Finished | Oct 02 09:00:38 PM UTC 24 |
| Peak memory | 1825564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057443809 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_wr.2057443809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.350330479 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 2384774095 ps |
| CPU time | 11.46 seconds |
| Started | Oct 02 08:58:30 PM UTC 24 |
| Finished | Oct 02 08:58:43 PM UTC 24 |
| Peak memory | 396256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350330479 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stretch.350330479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.3512812646 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 3361323005 ps |
| CPU time | 9.92 seconds |
| Started | Oct 02 08:58:33 PM UTC 24 |
| Finished | Oct 02 08:58:44 PM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512812 646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_timeout.3512812646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_alert_test.1114625614 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 106169154 ps |
| CPU time | 1.03 seconds |
| Started | Oct 02 08:27:30 PM UTC 24 |
| Finished | Oct 02 08:27:32 PM UTC 24 |
| Peak memory | 214804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114625614 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.1114625614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_error_intr.4151578496 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 457903332 ps |
| CPU time | 3.03 seconds |
| Started | Oct 02 08:26:38 PM UTC 24 |
| Finished | Oct 02 08:26:42 PM UTC 24 |
| Peak memory | 231712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151578496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.4151578496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_fmt_empty.1416816164 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 839511160 ps |
| CPU time | 5.94 seconds |
| Started | Oct 02 08:26:31 PM UTC 24 |
| Finished | Oct 02 08:26:39 PM UTC 24 |
| Peak memory | 248680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416816164 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty.1416816164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_full.363390530 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 3317979324 ps |
| CPU time | 97.95 seconds |
| Started | Oct 02 08:26:32 PM UTC 24 |
| Finished | Oct 02 08:28:12 PM UTC 24 |
| Peak memory | 783068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363390530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.363390530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_overflow.4043261753 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2640838232 ps |
| CPU time | 35.24 seconds |
| Started | Oct 02 08:26:30 PM UTC 24 |
| Finished | Oct 02 08:27:07 PM UTC 24 |
| Peak memory | 519076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043261753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.4043261753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_fmt.1941577099 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 105208138 ps |
| CPU time | 1.46 seconds |
| Started | Oct 02 08:26:30 PM UTC 24 |
| Finished | Oct 02 08:26:33 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941577099 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt.1941577099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_rx.2059523922 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 178385471 ps |
| CPU time | 10.84 seconds |
| Started | Oct 02 08:26:32 PM UTC 24 |
| Finished | Oct 02 08:26:44 PM UTC 24 |
| Peak memory | 215264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059523922 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.2059523922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_watermark.4012752091 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 9976914110 ps |
| CPU time | 61.13 seconds |
| Started | Oct 02 08:26:29 PM UTC 24 |
| Finished | Oct 02 08:27:32 PM UTC 24 |
| Peak memory | 740124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012752091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.4012752091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_may_nack.1036132449 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 348143776 ps |
| CPU time | 8.02 seconds |
| Started | Oct 02 08:27:26 PM UTC 24 |
| Finished | Oct 02 08:27:35 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036132449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.1036132449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_mode_toggle.890169618 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 374004918 ps |
| CPU time | 2.46 seconds |
| Started | Oct 02 08:27:23 PM UTC 24 |
| Finished | Oct 02 08:27:27 PM UTC 24 |
| Peak memory | 225580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890169618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.890169618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_host_mode_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_override.810440703 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 20472926 ps |
| CPU time | 1.05 seconds |
| Started | Oct 02 08:26:28 PM UTC 24 |
| Finished | Oct 02 08:26:31 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810440703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.810440703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_perf.1798587591 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2813968099 ps |
| CPU time | 31.6 seconds |
| Started | Oct 02 08:26:34 PM UTC 24 |
| Finished | Oct 02 08:27:07 PM UTC 24 |
| Peak memory | 233892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798587591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.1798587591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_perf_precise.3418207641 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 180546388 ps |
| CPU time | 2.63 seconds |
| Started | Oct 02 08:26:34 PM UTC 24 |
| Finished | Oct 02 08:26:38 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418207641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.3418207641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_smoke.3896120023 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1457650273 ps |
| CPU time | 27.22 seconds |
| Started | Oct 02 08:26:28 PM UTC 24 |
| Finished | Oct 02 08:26:57 PM UTC 24 |
| Peak memory | 328480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896120023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3896120023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_stress_all.1428115294 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 26820935971 ps |
| CPU time | 1398.39 seconds |
| Started | Oct 02 08:26:40 PM UTC 24 |
| Finished | Oct 02 08:50:14 PM UTC 24 |
| Peak memory | 2389036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428115294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.1428115294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_host_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_host_stretch_timeout.1792891156 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3312067681 ps |
| CPU time | 47.79 seconds |
| Started | Oct 02 08:26:35 PM UTC 24 |
| Finished | Oct 02 08:27:25 PM UTC 24 |
| Peak memory | 225704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792891156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.1792891156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_bad_addr.2711260772 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 953555513 ps |
| CPU time | 8.23 seconds |
| Started | Oct 02 08:27:16 PM UTC 24 |
| Finished | Oct 02 08:27:25 PM UTC 24 |
| Peak memory | 229664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2711260772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2711260772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_acq.2704919564 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 684164485 ps |
| CPU time | 2.59 seconds |
| Started | Oct 02 08:27:12 PM UTC 24 |
| Finished | Oct 02 08:27:15 PM UTC 24 |
| Peak memory | 215316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704919 564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_acq.2704919564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_tx.60177271 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1158693008 ps |
| CPU time | 1.44 seconds |
| Started | Oct 02 08:27:13 PM UTC 24 |
| Finished | Oct 02 08:27:15 PM UTC 24 |
| Peak memory | 214912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6017727 1 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_tx.60177271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_acq.1846278750 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1505321225 ps |
| CPU time | 2.67 seconds |
| Started | Oct 02 08:27:26 PM UTC 24 |
| Finished | Oct 02 08:27:29 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846278 750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_watermark s_acq.1846278750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_tx.226771298 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 96479818 ps |
| CPU time | 2.02 seconds |
| Started | Oct 02 08:27:26 PM UTC 24 |
| Finished | Oct 02 08:27:29 PM UTC 24 |
| Peak memory | 215244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267712 98 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.226771298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_hrst.2847044018 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 242371772 ps |
| CPU time | 3.86 seconds |
| Started | Oct 02 08:27:20 PM UTC 24 |
| Finished | Oct 02 08:27:25 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847044 018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_hrst.2847044018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_intr_smoke.3518366833 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4988880735 ps |
| CPU time | 6.05 seconds |
| Started | Oct 02 08:27:07 PM UTC 24 |
| Finished | Oct 02 08:27:14 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351836 6833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_smoke.3518366833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_intr_stress_wr.3591308679 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 6910619002 ps |
| CPU time | 15.46 seconds |
| Started | Oct 02 08:27:08 PM UTC 24 |
| Finished | Oct 02 08:27:24 PM UTC 24 |
| Peak memory | 482152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3591308679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_stress _wr.3591308679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull.1864995419 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 439068843 ps |
| CPU time | 3.32 seconds |
| Started | Oct 02 08:27:27 PM UTC 24 |
| Finished | Oct 02 08:27:31 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864995 419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_acqfull.1864995419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull_addr.1700152188 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 3678303547 ps |
| CPU time | 2.94 seconds |
| Started | Oct 02 08:27:28 PM UTC 24 |
| Finished | Oct 02 08:27:32 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700152 188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.1700152188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_perf.626174107 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 565838628 ps |
| CPU time | 7.04 seconds |
| Started | Oct 02 08:27:14 PM UTC 24 |
| Finished | Oct 02 08:27:22 PM UTC 24 |
| Peak memory | 232368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6261741 07 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_perf.626174107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_smbus_maxlen.2131276311 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1819708160 ps |
| CPU time | 3.01 seconds |
| Started | Oct 02 08:27:27 PM UTC 24 |
| Finished | Oct 02 08:27:31 PM UTC 24 |
| Peak memory | 215228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131276 311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smbus_maxlen.2131276311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_smoke.3611144921 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 1093022296 ps |
| CPU time | 34.12 seconds |
| Started | Oct 02 08:26:43 PM UTC 24 |
| Finished | Oct 02 08:27:19 PM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611144921 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smoke.3611144921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_stress_all.378178701 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 4384755782 ps |
| CPU time | 39.13 seconds |
| Started | Oct 02 08:27:16 PM UTC 24 |
| Finished | Oct 02 08:27:57 PM UTC 24 |
| Peak memory | 264984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378178 701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_all.378178701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_stress_rd.1217161514 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 5240044856 ps |
| CPU time | 63.89 seconds |
| Started | Oct 02 08:26:45 PM UTC 24 |
| Finished | Oct 02 08:27:51 PM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217161514 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_rd.1217161514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_stress_wr.265938875 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 31143615972 ps |
| CPU time | 34.23 seconds |
| Started | Oct 02 08:26:44 PM UTC 24 |
| Finished | Oct 02 08:27:20 PM UTC 24 |
| Peak memory | 721824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265938875 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_wr.265938875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_stretch.2549424972 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 4809194095 ps |
| CPU time | 74.8 seconds |
| Started | Oct 02 08:26:58 PM UTC 24 |
| Finished | Oct 02 08:28:15 PM UTC 24 |
| Peak memory | 1338200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549424972 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stretch.2549424972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_timeout.4261932604 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1143310672 ps |
| CPU time | 11.57 seconds |
| Started | Oct 02 08:27:08 PM UTC 24 |
| Finished | Oct 02 08:27:20 PM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261932 604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_timeout.4261932604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/5.i2c_target_tx_stretch_ctrl.1640851338 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 131858266 ps |
| CPU time | 2.79 seconds |
| Started | Oct 02 08:27:26 PM UTC 24 |
| Finished | Oct 02 08:27:30 PM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640851 338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.1640851338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_alert_test.3422072911 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 19548536 ps |
| CPU time | 0.94 seconds |
| Started | Oct 02 08:28:34 PM UTC 24 |
| Finished | Oct 02 08:28:35 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422072911 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.3422072911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_error_intr.2707895835 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 102108525 ps |
| CPU time | 2.18 seconds |
| Started | Oct 02 08:27:39 PM UTC 24 |
| Finished | Oct 02 08:27:42 PM UTC 24 |
| Peak memory | 225516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707895835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.2707895835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_fmt_empty.1735310078 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 351459013 ps |
| CPU time | 23.15 seconds |
| Started | Oct 02 08:27:34 PM UTC 24 |
| Finished | Oct 02 08:27:58 PM UTC 24 |
| Peak memory | 289576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735310078 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty.1735310078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_full.2951665780 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 18179469120 ps |
| CPU time | 55.17 seconds |
| Started | Oct 02 08:27:35 PM UTC 24 |
| Finished | Oct 02 08:28:31 PM UTC 24 |
| Peak memory | 351208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951665780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2951665780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_overflow.4243793048 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 7034204689 ps |
| CPU time | 46.58 seconds |
| Started | Oct 02 08:27:32 PM UTC 24 |
| Finished | Oct 02 08:28:21 PM UTC 24 |
| Peak memory | 602904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243793048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.4243793048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_fmt.4184381597 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 98344739 ps |
| CPU time | 1.54 seconds |
| Started | Oct 02 08:27:34 PM UTC 24 |
| Finished | Oct 02 08:27:36 PM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184381597 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt.4184381597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_rx.1802950738 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 138763093 ps |
| CPU time | 8.15 seconds |
| Started | Oct 02 08:27:34 PM UTC 24 |
| Finished | Oct 02 08:27:43 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802950738 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.1802950738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_watermark.3432620897 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 13348202367 ps |
| CPU time | 90.31 seconds |
| Started | Oct 02 08:27:32 PM UTC 24 |
| Finished | Oct 02 08:29:05 PM UTC 24 |
| Peak memory | 1039076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432620897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.3432620897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_may_nack.2434389515 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 471382247 ps |
| CPU time | 11.52 seconds |
| Started | Oct 02 08:28:13 PM UTC 24 |
| Finished | Oct 02 08:28:25 PM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434389515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.2434389515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_mode_toggle.2417139027 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 580906038 ps |
| CPU time | 3.25 seconds |
| Started | Oct 02 08:28:10 PM UTC 24 |
| Finished | Oct 02 08:28:15 PM UTC 24 |
| Peak memory | 215192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417139027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.2417139027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_host_mode_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_override.3133907677 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 32434030 ps |
| CPU time | 0.97 seconds |
| Started | Oct 02 08:27:31 PM UTC 24 |
| Finished | Oct 02 08:27:33 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133907677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.3133907677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_perf.1301839193 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 12180829214 ps |
| CPU time | 380.53 seconds |
| Started | Oct 02 08:27:35 PM UTC 24 |
| Finished | Oct 02 08:34:00 PM UTC 24 |
| Peak memory | 2913184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301839193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.1301839193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_perf_precise.1019489810 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 71714504 ps |
| CPU time | 1.73 seconds |
| Started | Oct 02 08:27:36 PM UTC 24 |
| Finished | Oct 02 08:27:39 PM UTC 24 |
| Peak memory | 236792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019489810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.1019489810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_smoke.2026808596 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1076440011 ps |
| CPU time | 51.82 seconds |
| Started | Oct 02 08:27:30 PM UTC 24 |
| Finished | Oct 02 08:28:24 PM UTC 24 |
| Peak memory | 277148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026808596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.2026808596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_host_stretch_timeout.4207281649 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 4389576554 ps |
| CPU time | 24.37 seconds |
| Started | Oct 02 08:27:37 PM UTC 24 |
| Finished | Oct 02 08:28:03 PM UTC 24 |
| Peak memory | 231648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207281649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.4207281649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_bad_addr.1882786519 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 2708362470 ps |
| CPU time | 6.05 seconds |
| Started | Oct 02 08:28:06 PM UTC 24 |
| Finished | Oct 02 08:28:13 PM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1882786519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.1882786519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_acq.1517187567 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 609872458 ps |
| CPU time | 2.03 seconds |
| Started | Oct 02 08:28:04 PM UTC 24 |
| Finished | Oct 02 08:28:07 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517187 567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_acq.1517187567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_tx.1552743402 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 447069493 ps |
| CPU time | 2.96 seconds |
| Started | Oct 02 08:28:04 PM UTC 24 |
| Finished | Oct 02 08:28:08 PM UTC 24 |
| Peak memory | 215328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552743 402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_tx.1552743402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_acq.1171559902 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1313478190 ps |
| CPU time | 3.33 seconds |
| Started | Oct 02 08:28:15 PM UTC 24 |
| Finished | Oct 02 08:28:19 PM UTC 24 |
| Peak memory | 215236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171559 902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_watermark s_acq.1171559902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_tx.1386550242 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 334824685 ps |
| CPU time | 1.91 seconds |
| Started | Oct 02 08:28:15 PM UTC 24 |
| Finished | Oct 02 08:28:18 PM UTC 24 |
| Peak memory | 214784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386550 242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_watermarks _tx.1386550242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_intr_smoke.3558624462 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4274000666 ps |
| CPU time | 8.5 seconds |
| Started | Oct 02 08:27:53 PM UTC 24 |
| Finished | Oct 02 08:28:03 PM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355862 4462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_smoke.3558624462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_intr_stress_wr.676533545 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 9916560645 ps |
| CPU time | 45.2 seconds |
| Started | Oct 02 08:27:58 PM UTC 24 |
| Finished | Oct 02 08:28:44 PM UTC 24 |
| Peak memory | 930596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=676533545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.676533545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull.2234813943 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 2176964694 ps |
| CPU time | 3.02 seconds |
| Started | Oct 02 08:28:25 PM UTC 24 |
| Finished | Oct 02 08:28:29 PM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234813 943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_acqfull.2234813943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_perf.1687459932 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3121754921 ps |
| CPU time | 8.61 seconds |
| Started | Oct 02 08:28:04 PM UTC 24 |
| Finished | Oct 02 08:28:14 PM UTC 24 |
| Peak memory | 232320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687459 932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_perf.1687459932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_smbus_maxlen.3728321941 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 457957386 ps |
| CPU time | 3.69 seconds |
| Started | Oct 02 08:28:16 PM UTC 24 |
| Finished | Oct 02 08:28:21 PM UTC 24 |
| Peak memory | 215228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728321 941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smbus_maxlen.3728321941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_smoke.1101089238 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 8155612210 ps |
| CPU time | 17.11 seconds |
| Started | Oct 02 08:27:51 PM UTC 24 |
| Finished | Oct 02 08:28:10 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101089238 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smoke.1101089238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_stress_all.451024621 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 35237983140 ps |
| CPU time | 68.55 seconds |
| Started | Oct 02 08:28:04 PM UTC 24 |
| Finished | Oct 02 08:29:14 PM UTC 24 |
| Peak memory | 293864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451024 621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_all.451024621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_stress_rd.4072663577 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 809328977 ps |
| CPU time | 6.36 seconds |
| Started | Oct 02 08:27:51 PM UTC 24 |
| Finished | Oct 02 08:27:59 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072663577 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_rd.4072663577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_stress_wr.2149234066 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 61103163453 ps |
| CPU time | 1797.06 seconds |
| Started | Oct 02 08:27:51 PM UTC 24 |
| Finished | Oct 02 08:58:07 PM UTC 24 |
| Peak memory | 10855328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149234066 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_wr.2149234066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_stretch.489690196 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 3092686673 ps |
| CPU time | 12.17 seconds |
| Started | Oct 02 08:27:52 PM UTC 24 |
| Finished | Oct 02 08:28:05 PM UTC 24 |
| Peak memory | 377824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489690196 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stretch.489690196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_timeout.1498524666 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 2285485708 ps |
| CPU time | 9.11 seconds |
| Started | Oct 02 08:27:59 PM UTC 24 |
| Finished | Oct 02 08:28:09 PM UTC 24 |
| Peak memory | 232272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498524 666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_timeout.1498524666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/6.i2c_target_tx_stretch_ctrl.2285900544 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 539722916 ps |
| CPU time | 11.18 seconds |
| Started | Oct 02 08:28:16 PM UTC 24 |
| Finished | Oct 02 08:28:28 PM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285900 544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.2285900544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_alert_test.3714613244 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 34997381 ps |
| CPU time | 0.95 seconds |
| Started | Oct 02 08:29:05 PM UTC 24 |
| Finished | Oct 02 08:29:07 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714613244 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.3714613244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_fmt_empty.1921849991 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1440787418 ps |
| CPU time | 23.23 seconds |
| Started | Oct 02 08:28:34 PM UTC 24 |
| Finished | Oct 02 08:28:58 PM UTC 24 |
| Peak memory | 293672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921849991 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty.1921849991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_full.3338119889 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 4730804362 ps |
| CPU time | 112.63 seconds |
| Started | Oct 02 08:28:35 PM UTC 24 |
| Finished | Oct 02 08:30:30 PM UTC 24 |
| Peak memory | 340760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338119889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.3338119889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_overflow.959853321 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1520295774 ps |
| CPU time | 49.84 seconds |
| Started | Oct 02 08:28:34 PM UTC 24 |
| Finished | Oct 02 08:29:25 PM UTC 24 |
| Peak memory | 559952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959853321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.959853321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_fmt.3212769159 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 65207909 ps |
| CPU time | 1.28 seconds |
| Started | Oct 02 08:28:34 PM UTC 24 |
| Finished | Oct 02 08:28:36 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212769159 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt.3212769159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_rx.558088845 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 736697636 ps |
| CPU time | 12.77 seconds |
| Started | Oct 02 08:28:35 PM UTC 24 |
| Finished | Oct 02 08:28:49 PM UTC 24 |
| Peak memory | 215196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558088845 -assert nopostproc +UVM_TESTNAME=i2c_b ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.558088845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_watermark.2726466053 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 11243791233 ps |
| CPU time | 54.76 seconds |
| Started | Oct 02 08:28:34 PM UTC 24 |
| Finished | Oct 02 08:29:30 PM UTC 24 |
| Peak memory | 787256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726466053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.2726466053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_host_may_nack.1378746925 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2578586473 ps |
| CPU time | 28.37 seconds |
| Started | Oct 02 08:29:00 PM UTC 24 |
| Finished | Oct 02 08:29:29 PM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378746925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.1378746925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_host_override.1115953218 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 16800130 ps |
| CPU time | 0.88 seconds |
| Started | Oct 02 08:28:34 PM UTC 24 |
| Finished | Oct 02 08:28:36 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115953218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.1115953218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_host_perf.799731528 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 25681616679 ps |
| CPU time | 1008.8 seconds |
| Started | Oct 02 08:28:35 PM UTC 24 |
| Finished | Oct 02 08:45:36 PM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799731528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.799731528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_host_perf_precise.197394570 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 461942133 ps |
| CPU time | 7.23 seconds |
| Started | Oct 02 08:28:35 PM UTC 24 |
| Finished | Oct 02 08:28:44 PM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197394570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.197394570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_host_smoke.1823839149 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1261757453 ps |
| CPU time | 72.16 seconds |
| Started | Oct 02 08:28:34 PM UTC 24 |
| Finished | Oct 02 08:29:48 PM UTC 24 |
| Peak memory | 287388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823839149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.1823839149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_host_stretch_timeout.2404349508 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1075535165 ps |
| CPU time | 26.58 seconds |
| Started | Oct 02 08:28:36 PM UTC 24 |
| Finished | Oct 02 08:29:04 PM UTC 24 |
| Peak memory | 225568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404349508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.2404349508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_bad_addr.1214136754 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 549909842 ps |
| CPU time | 4.67 seconds |
| Started | Oct 02 08:28:53 PM UTC 24 |
| Finished | Oct 02 08:28:59 PM UTC 24 |
| Peak memory | 229648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1214136754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.1214136754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_acq.3271996045 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 297824804 ps |
| CPU time | 3.21 seconds |
| Started | Oct 02 08:28:46 PM UTC 24 |
| Finished | Oct 02 08:28:50 PM UTC 24 |
| Peak memory | 221476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271996 045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_acq.3271996045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_tx.4264545827 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 167430749 ps |
| CPU time | 1.19 seconds |
| Started | Oct 02 08:28:50 PM UTC 24 |
| Finished | Oct 02 08:28:52 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264545 827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_tx.4264545827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_acq.2776927110 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 584852970 ps |
| CPU time | 5.59 seconds |
| Started | Oct 02 08:29:00 PM UTC 24 |
| Finished | Oct 02 08:29:07 PM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776927 110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_watermark s_acq.2776927110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_tx.2766394565 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 152330364 ps |
| CPU time | 2.21 seconds |
| Started | Oct 02 08:29:01 PM UTC 24 |
| Finished | Oct 02 08:29:04 PM UTC 24 |
| Peak memory | 215308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766394 565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_watermarks _tx.2766394565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_hrst.1330599536 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 277711016 ps |
| CPU time | 3.29 seconds |
| Started | Oct 02 08:28:58 PM UTC 24 |
| Finished | Oct 02 08:29:02 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330599 536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_hrst.1330599536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_hrst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_intr_smoke.1406886956 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 8019325223 ps |
| CPU time | 12.77 seconds |
| Started | Oct 02 08:28:43 PM UTC 24 |
| Finished | Oct 02 08:28:57 PM UTC 24 |
| Peak memory | 229672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140688 6956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_smoke.1406886956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_intr_stress_wr.1176244147 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 15064016109 ps |
| CPU time | 94.34 seconds |
| Started | Oct 02 08:28:44 PM UTC 24 |
| Finished | Oct 02 08:30:20 PM UTC 24 |
| Peak memory | 1872664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1176244147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_stress _wr.1176244147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull.132144556 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 527305701 ps |
| CPU time | 5.39 seconds |
| Started | Oct 02 08:29:03 PM UTC 24 |
| Finished | Oct 02 08:29:10 PM UTC 24 |
| Peak memory | 225588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321445 56 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_acqfull.132144556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull_addr.609373267 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 568385379 ps |
| CPU time | 4.35 seconds |
| Started | Oct 02 08:29:05 PM UTC 24 |
| Finished | Oct 02 08:29:11 PM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6093732 67 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.609373267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_nack_txstretch.2371392514 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 1781426270 ps |
| CPU time | 2.42 seconds |
| Started | Oct 02 08:29:05 PM UTC 24 |
| Finished | Oct 02 08:29:09 PM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371392 514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_txstretch.2371392514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_perf.857220109 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 3594087684 ps |
| CPU time | 8.71 seconds |
| Started | Oct 02 08:28:51 PM UTC 24 |
| Finished | Oct 02 08:29:01 PM UTC 24 |
| Peak memory | 227684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8572201 09 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_perf.857220109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_smbus_maxlen.3548042576 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 1772011053 ps |
| CPU time | 4.43 seconds |
| Started | Oct 02 08:29:03 PM UTC 24 |
| Finished | Oct 02 08:29:09 PM UTC 24 |
| Peak memory | 215200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548042 576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smbus_maxlen.3548042576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_smoke.3606819489 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1870706437 ps |
| CPU time | 18.46 seconds |
| Started | Oct 02 08:28:38 PM UTC 24 |
| Finished | Oct 02 08:28:57 PM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606819489 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smoke.3606819489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_stress_all.1797041382 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 93087806325 ps |
| CPU time | 82.93 seconds |
| Started | Oct 02 08:28:51 PM UTC 24 |
| Finished | Oct 02 08:30:16 PM UTC 24 |
| Peak memory | 707640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179704 1382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_all.1797041382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_stress_rd.824079606 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 3764354672 ps |
| CPU time | 43.6 seconds |
| Started | Oct 02 08:28:40 PM UTC 24 |
| Finished | Oct 02 08:29:25 PM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824079606 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_rd.824079606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_stress_wr.3022363440 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 11419547762 ps |
| CPU time | 16.04 seconds |
| Started | Oct 02 08:28:40 PM UTC 24 |
| Finished | Oct 02 08:28:57 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022363440 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_wr.3022363440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_stretch.1830822115 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 3075592499 ps |
| CPU time | 14.5 seconds |
| Started | Oct 02 08:28:42 PM UTC 24 |
| Finished | Oct 02 08:28:57 PM UTC 24 |
| Peak memory | 240104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830822115 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stretch.1830822115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_timeout.3433184590 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 5760554036 ps |
| CPU time | 14.91 seconds |
| Started | Oct 02 08:28:44 PM UTC 24 |
| Finished | Oct 02 08:29:00 PM UTC 24 |
| Peak memory | 232268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433184 590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_timeout.3433184590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/7.i2c_target_tx_stretch_ctrl.2715788900 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 392909893 ps |
| CPU time | 12.21 seconds |
| Started | Oct 02 08:29:02 PM UTC 24 |
| Finished | Oct 02 08:29:15 PM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715788 900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.2715788900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_alert_test.2590713021 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 22023876 ps |
| CPU time | 0.98 seconds |
| Started | Oct 02 08:30:17 PM UTC 24 |
| Finished | Oct 02 08:30:19 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590713021 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.2590713021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_fmt_empty.1329595887 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 110332418 ps |
| CPU time | 5.5 seconds |
| Started | Oct 02 08:29:12 PM UTC 24 |
| Finished | Oct 02 08:29:19 PM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329595887 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty.1329595887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_full.2123023522 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2989724829 ps |
| CPU time | 171.14 seconds |
| Started | Oct 02 08:29:14 PM UTC 24 |
| Finished | Oct 02 08:32:08 PM UTC 24 |
| Peak memory | 594736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123023522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2123023522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_overflow.1377366038 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 10263003092 ps |
| CPU time | 199.35 seconds |
| Started | Oct 02 08:29:10 PM UTC 24 |
| Finished | Oct 02 08:32:32 PM UTC 24 |
| Peak memory | 842604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377366038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.1377366038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_fmt.3293619811 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 116487553 ps |
| CPU time | 1.66 seconds |
| Started | Oct 02 08:29:11 PM UTC 24 |
| Finished | Oct 02 08:29:13 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293619811 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt.3293619811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_rx.1351186727 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1033615084 ps |
| CPU time | 12.42 seconds |
| Started | Oct 02 08:29:12 PM UTC 24 |
| Finished | Oct 02 08:29:26 PM UTC 24 |
| Peak memory | 238364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351186727 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.1351186727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_watermark.3339351673 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 13136486481 ps |
| CPU time | 141.7 seconds |
| Started | Oct 02 08:29:10 PM UTC 24 |
| Finished | Oct 02 08:31:34 PM UTC 24 |
| Peak memory | 1590184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339351673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3339351673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_may_nack.20919144 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2727254268 ps |
| CPU time | 4.85 seconds |
| Started | Oct 02 08:30:06 PM UTC 24 |
| Finished | Oct 02 08:30:12 PM UTC 24 |
| Peak memory | 215296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20919144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho st_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.20919144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_mode_toggle.2543719084 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 284789931 ps |
| CPU time | 3.37 seconds |
| Started | Oct 02 08:30:02 PM UTC 24 |
| Finished | Oct 02 08:30:07 PM UTC 24 |
| Peak memory | 225704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543719084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.2543719084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_host_mode_toggle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_override.649863349 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 146991588 ps |
| CPU time | 1.05 seconds |
| Started | Oct 02 08:29:09 PM UTC 24 |
| Finished | Oct 02 08:29:11 PM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649863349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.649863349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_perf_precise.2498166530 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 5967246918 ps |
| CPU time | 53.27 seconds |
| Started | Oct 02 08:29:16 PM UTC 24 |
| Finished | Oct 02 08:30:11 PM UTC 24 |
| Peak memory | 215444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498166530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.2498166530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_smoke.1938533349 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 1541761685 ps |
| CPU time | 31.11 seconds |
| Started | Oct 02 08:29:07 PM UTC 24 |
| Finished | Oct 02 08:29:40 PM UTC 24 |
| Peak memory | 301916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938533349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.1938533349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_host_stretch_timeout.3144875 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2921820631 ps |
| CPU time | 16.7 seconds |
| Started | Oct 02 08:29:19 PM UTC 24 |
| Finished | Oct 02 08:29:37 PM UTC 24 |
| Peak memory | 231996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_hos t_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.3144875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_bad_addr.1605126006 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3753438310 ps |
| CPU time | 7.68 seconds |
| Started | Oct 02 08:29:53 PM UTC 24 |
| Finished | Oct 02 08:30:02 PM UTC 24 |
| Peak memory | 229732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1605126006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.1605126006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_acq.1459226428 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 574305611 ps |
| CPU time | 2.44 seconds |
| Started | Oct 02 08:29:47 PM UTC 24 |
| Finished | Oct 02 08:29:51 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459226 428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_acq.1459226428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_tx.1864685811 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 186438070 ps |
| CPU time | 1.45 seconds |
| Started | Oct 02 08:29:51 PM UTC 24 |
| Finished | Oct 02 08:29:53 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864685 811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_tx.1864685811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_acq.4233828074 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1343418042 ps |
| CPU time | 5.46 seconds |
| Started | Oct 02 08:30:07 PM UTC 24 |
| Finished | Oct 02 08:30:14 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233828 074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_watermark s_acq.4233828074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_tx.3724287706 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 264557975 ps |
| CPU time | 1.81 seconds |
| Started | Oct 02 08:30:12 PM UTC 24 |
| Finished | Oct 02 08:30:14 PM UTC 24 |
| Peak memory | 214784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724287 706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_watermarks _tx.3724287706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_intr_smoke.4143595249 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1139931413 ps |
| CPU time | 9.1 seconds |
| Started | Oct 02 08:29:33 PM UTC 24 |
| Finished | Oct 02 08:29:43 PM UTC 24 |
| Peak memory | 232184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414359 5249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_smoke.4143595249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_intr_stress_wr.3375104411 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 17624877928 ps |
| CPU time | 41.01 seconds |
| Started | Oct 02 08:29:38 PM UTC 24 |
| Finished | Oct 02 08:30:20 PM UTC 24 |
| Peak memory | 637720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3375104411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_stress _wr.3375104411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull.3797941192 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 559241794 ps |
| CPU time | 3.81 seconds |
| Started | Oct 02 08:30:14 PM UTC 24 |
| Finished | Oct 02 08:30:19 PM UTC 24 |
| Peak memory | 225704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797941 192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_acqfull.3797941192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull_addr.3270774058 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 436078708 ps |
| CPU time | 2.92 seconds |
| Started | Oct 02 08:30:15 PM UTC 24 |
| Finished | Oct 02 08:30:19 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270774 058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.3270774058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_perf.2191764187 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1854143252 ps |
| CPU time | 5.59 seconds |
| Started | Oct 02 08:29:51 PM UTC 24 |
| Finished | Oct 02 08:29:57 PM UTC 24 |
| Peak memory | 217308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191764 187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_perf.2191764187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_smbus_maxlen.49378649 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 436411850 ps |
| CPU time | 2.94 seconds |
| Started | Oct 02 08:30:13 PM UTC 24 |
| Finished | Oct 02 08:30:17 PM UTC 24 |
| Peak memory | 215008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4937864 9 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smbus_maxlen.49378649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_smoke.3677130948 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 4124152953 ps |
| CPU time | 42.5 seconds |
| Started | Oct 02 08:29:26 PM UTC 24 |
| Finished | Oct 02 08:30:11 PM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677130948 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smoke.3677130948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_stress_all.3284470540 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 24592411613 ps |
| CPU time | 383.74 seconds |
| Started | Oct 02 08:29:52 PM UTC 24 |
| Finished | Oct 02 08:36:20 PM UTC 24 |
| Peak memory | 2898808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328447 0540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_all.3284470540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_stress_rd.1823394833 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3277171178 ps |
| CPU time | 32.9 seconds |
| Started | Oct 02 08:29:31 PM UTC 24 |
| Finished | Oct 02 08:30:05 PM UTC 24 |
| Peak memory | 242720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823394833 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_rd.1823394833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_stress_wr.1519286711 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 55285139680 ps |
| CPU time | 175.83 seconds |
| Started | Oct 02 08:29:29 PM UTC 24 |
| Finished | Oct 02 08:32:28 PM UTC 24 |
| Peak memory | 2378788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519286711 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_wr.1519286711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_stretch.2806945470 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 4220059560 ps |
| CPU time | 58.4 seconds |
| Started | Oct 02 08:29:31 PM UTC 24 |
| Finished | Oct 02 08:30:31 PM UTC 24 |
| Peak memory | 955428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806945470 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stretch.2806945470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_timeout.1541139350 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 2300409228 ps |
| CPU time | 11.79 seconds |
| Started | Oct 02 08:29:41 PM UTC 24 |
| Finished | Oct 02 08:29:54 PM UTC 24 |
| Peak memory | 232432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541139 350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_timeout.1541139350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/8.i2c_target_tx_stretch_ctrl.4227440670 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 114775822 ps |
| CPU time | 2.57 seconds |
| Started | Oct 02 08:30:13 PM UTC 24 |
| Finished | Oct 02 08:30:16 PM UTC 24 |
| Peak memory | 215252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227440 670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.4227440670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_target_tx_stretch_ctrl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_alert_test.3755788364 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 34372448 ps |
| CPU time | 0.94 seconds |
| Started | Oct 02 08:31:27 PM UTC 24 |
| Finished | Oct 02 08:31:29 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755788364 -assert nopostproc +UVM_TESTNAME=i2c_ba se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.3755788364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_error_intr.221821792 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 63508418 ps |
| CPU time | 2.29 seconds |
| Started | Oct 02 08:30:23 PM UTC 24 |
| Finished | Oct 02 08:30:26 PM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221821792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.221821792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_host_error_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_fmt_empty.2243470355 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 3375085064 ps |
| CPU time | 12.74 seconds |
| Started | Oct 02 08:30:19 PM UTC 24 |
| Finished | Oct 02 08:30:33 PM UTC 24 |
| Peak memory | 336680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243470355 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty.2243470355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_host_fifo_fmt_empty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_full.3953946911 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 10257396672 ps |
| CPU time | 163.61 seconds |
| Started | Oct 02 08:30:20 PM UTC 24 |
| Finished | Oct 02 08:33:06 PM UTC 24 |
| Peak memory | 258852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953946911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3953946911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_host_fifo_full/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_overflow.2605373145 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 4077708234 ps |
| CPU time | 82.71 seconds |
| Started | Oct 02 08:30:19 PM UTC 24 |
| Finished | Oct 02 08:31:44 PM UTC 24 |
| Peak memory | 676664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605373145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.2605373145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_host_fifo_overflow/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_fmt.1466823558 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 79822987 ps |
| CPU time | 1.41 seconds |
| Started | Oct 02 08:30:19 PM UTC 24 |
| Finished | Oct 02 08:30:22 PM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466823558 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt.1466823558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_host_fifo_reset_fmt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_rx.2624590844 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 2459894602 ps |
| CPU time | 8.86 seconds |
| Started | Oct 02 08:30:20 PM UTC 24 |
| Finished | Oct 02 08:30:29 PM UTC 24 |
| Peak memory | 254888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624590844 -assert nopostproc +UVM_TESTNAME=i2c_ base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.2624590844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_host_fifo_reset_rx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_watermark.3736269457 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 12023901263 ps |
| CPU time | 84.95 seconds |
| Started | Oct 02 08:30:18 PM UTC 24 |
| Finished | Oct 02 08:31:45 PM UTC 24 |
| Peak memory | 762596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736269457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.3736269457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_host_fifo_watermark/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_may_nack.2730292575 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 711401451 ps |
| CPU time | 11.36 seconds |
| Started | Oct 02 08:31:08 PM UTC 24 |
| Finished | Oct 02 08:31:20 PM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730292575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.2730292575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_host_may_nack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_override.3685403803 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 17534179 ps |
| CPU time | 1.04 seconds |
| Started | Oct 02 08:30:17 PM UTC 24 |
| Finished | Oct 02 08:30:19 PM UTC 24 |
| Peak memory | 214100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685403803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.3685403803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_host_override/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_perf.2902458379 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 5117122353 ps |
| CPU time | 103.99 seconds |
| Started | Oct 02 08:30:21 PM UTC 24 |
| Finished | Oct 02 08:32:07 PM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902458379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2902458379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_host_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_perf_precise.1161324184 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 267876674 ps |
| CPU time | 10.86 seconds |
| Started | Oct 02 08:30:22 PM UTC 24 |
| Finished | Oct 02 08:30:34 PM UTC 24 |
| Peak memory | 235672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161324184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.1161324184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_host_perf_precise/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_smoke.4060669467 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1839151395 ps |
| CPU time | 83.64 seconds |
| Started | Oct 02 08:30:17 PM UTC 24 |
| Finished | Oct 02 08:31:43 PM UTC 24 |
| Peak memory | 383784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060669467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.4060669467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_host_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_host_stretch_timeout.1072082719 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 895629012 ps |
| CPU time | 19.26 seconds |
| Started | Oct 02 08:30:22 PM UTC 24 |
| Finished | Oct 02 08:30:42 PM UTC 24 |
| Peak memory | 242544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072082719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.1072082719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_host_stretch_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_bad_addr.1148847089 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 1240150202 ps |
| CPU time | 8.02 seconds |
| Started | Oct 02 08:30:52 PM UTC 24 |
| Finished | Oct 02 08:31:01 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1148847089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.1148847089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_bad_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_acq.1726429041 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 622109363 ps |
| CPU time | 2.15 seconds |
| Started | Oct 02 08:30:48 PM UTC 24 |
| Finished | Oct 02 08:30:51 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726429 041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_acq.1726429041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_fifo_reset_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_tx.794209826 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 350453008 ps |
| CPU time | 2.03 seconds |
| Started | Oct 02 08:30:48 PM UTC 24 |
| Finished | Oct 02 08:30:51 PM UTC 24 |
| Peak memory | 219556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7942098 26 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_tx.794209826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_fifo_reset_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_acq.123074334 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 4041956369 ps |
| CPU time | 3.5 seconds |
| Started | Oct 02 08:31:10 PM UTC 24 |
| Finished | Oct 02 08:31:14 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230743 34 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_watermarks _acq.123074334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_fifo_watermarks_acq/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_tx.3320343666 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 150301610 ps |
| CPU time | 1.69 seconds |
| Started | Oct 02 08:31:15 PM UTC 24 |
| Finished | Oct 02 08:31:17 PM UTC 24 |
| Peak memory | 214964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320343 666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_watermarks _tx.3320343666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_fifo_watermarks_tx/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_intr_smoke.662146585 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 5503653379 ps |
| CPU time | 10.11 seconds |
| Started | Oct 02 08:30:34 PM UTC 24 |
| Finished | Oct 02 08:30:46 PM UTC 24 |
| Peak memory | 231708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662146 585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_smoke.662146585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_intr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_intr_stress_wr.1283696838 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 23206330996 ps |
| CPU time | 146.09 seconds |
| Started | Oct 02 08:30:46 PM UTC 24 |
| Finished | Oct 02 08:33:15 PM UTC 24 |
| Peak memory | 2577180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow _acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1283696838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_stress _wr.1283696838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_intr_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull.2575254338 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 581403442 ps |
| CPU time | 5.06 seconds |
| Started | Oct 02 08:31:21 PM UTC 24 |
| Finished | Oct 02 08:31:27 PM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575254 338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_acqfull.2575254338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_nack_acqfull/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull_addr.2607570454 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2292494474 ps |
| CPU time | 4.95 seconds |
| Started | Oct 02 08:31:22 PM UTC 24 |
| Finished | Oct 02 08:31:28 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607570 454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.2607570454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_nack_acqfull_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_nack_txstretch.3679627249 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 463533743 ps |
| CPU time | 2.26 seconds |
| Started | Oct 02 08:31:23 PM UTC 24 |
| Finished | Oct 02 08:31:27 PM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679627 249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_txstretch.3679627249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_nack_txstretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_perf.2937200158 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 473981325 ps |
| CPU time | 5.46 seconds |
| Started | Oct 02 08:30:51 PM UTC 24 |
| Finished | Oct 02 08:30:57 PM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937200 158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_perf.2937200158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_perf/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_smbus_maxlen.4268663055 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1624500712 ps |
| CPU time | 3.7 seconds |
| Started | Oct 02 08:31:18 PM UTC 24 |
| Finished | Oct 02 08:31:23 PM UTC 24 |
| Peak memory | 215004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268663 055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smbus_maxlen.4268663055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_smbus_maxlen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_smoke.2986211387 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1441165508 ps |
| CPU time | 44.28 seconds |
| Started | Oct 02 08:30:30 PM UTC 24 |
| Finished | Oct 02 08:31:16 PM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986211387 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smoke.2986211387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_stress_all.3516693865 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 78332684022 ps |
| CPU time | 106.68 seconds |
| Started | Oct 02 08:30:52 PM UTC 24 |
| Finished | Oct 02 08:32:41 PM UTC 24 |
| Peak memory | 918392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351669 3865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_all.3516693865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_stress_rd.3254181003 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 293617915 ps |
| CPU time | 12.69 seconds |
| Started | Oct 02 08:30:32 PM UTC 24 |
| Finished | Oct 02 08:30:46 PM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254181003 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_rd.3254181003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_stress_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_stress_wr.4250373275 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 56060366208 ps |
| CPU time | 1341.44 seconds |
| Started | Oct 02 08:30:31 PM UTC 24 |
| Finished | Oct 02 08:53:06 PM UTC 24 |
| Peak memory | 9208676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250373275 -assert nopostp roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_wr.4250373275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_stress_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_stretch.426456844 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1657685283 ps |
| CPU time | 1.98 seconds |
| Started | Oct 02 08:30:34 PM UTC 24 |
| Finished | Oct 02 08:30:37 PM UTC 24 |
| Peak memory | 224844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426456844 -assert nopostpr oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stretch.426456844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_stretch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_timeout.1481223520 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1384540305 ps |
| CPU time | 7.76 seconds |
| Started | Oct 02 08:30:48 PM UTC 24 |
| Finished | Oct 02 08:30:57 PM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481223 520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_timeout.1481223520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default/9.i2c_target_tx_stretch_ctrl.2382368619 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 85001980 ps |
| CPU time | 3.71 seconds |
| Started | Oct 02 08:31:17 PM UTC 24 |
| Finished | Oct 02 08:31:22 PM UTC 24 |
| Peak memory | 215256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382368 619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.2382368619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/9.i2c_target_tx_stretch_ctrl/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |