| T846 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_nack_txstretch.631720741 |
|
|
Feb 08 01:14:18 PM UTC 25 |
Feb 08 01:14:22 PM UTC 25 |
285126877 ps |
| T145 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_override.2603059481 |
|
|
Feb 08 01:14:20 PM UTC 25 |
Feb 08 01:14:22 PM UTC 25 |
30219376 ps |
| T847 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull_addr.120482738 |
|
|
Feb 08 01:14:17 PM UTC 25 |
Feb 08 01:14:23 PM UTC 25 |
7187417564 ps |
| T848 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_perf.2870260824 |
|
|
Feb 08 01:15:46 PM UTC 25 |
Feb 08 01:15:56 PM UTC 25 |
1661151014 ps |
| T849 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_tx_stretch_ctrl.1350271154 |
|
|
Feb 08 01:14:15 PM UTC 25 |
Feb 08 01:14:24 PM UTC 25 |
265114493 ps |
| T850 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_fmt.2874994788 |
|
|
Feb 08 01:14:22 PM UTC 25 |
Feb 08 01:14:25 PM UTC 25 |
189898855 ps |
| T851 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_perf_precise.3983615551 |
|
|
Feb 08 01:14:24 PM UTC 25 |
Feb 08 01:14:27 PM UTC 25 |
197422268 ps |
| T852 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_intr_stress_wr.841780515 |
|
|
Feb 08 01:10:50 PM UTC 25 |
Feb 08 01:14:29 PM UTC 25 |
15775514014 ps |
| T853 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_rx.1776715269 |
|
|
Feb 08 01:14:23 PM UTC 25 |
Feb 08 01:14:29 PM UTC 25 |
584764389 ps |
| T854 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_error_intr.2846863791 |
|
|
Feb 08 01:14:25 PM UTC 25 |
Feb 08 01:14:33 PM UTC 25 |
248204066 ps |
| T247 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_may_nack.3673531653 |
|
|
Feb 08 01:14:13 PM UTC 25 |
Feb 08 01:14:34 PM UTC 25 |
1961484399 ps |
| T114 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_watermark.656592475 |
|
|
Feb 08 01:12:44 PM UTC 25 |
Feb 08 01:14:38 PM UTC 25 |
9603444167 ps |
| T855 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_fmt_empty.675857337 |
|
|
Feb 08 01:14:23 PM UTC 25 |
Feb 08 01:14:41 PM UTC 25 |
2187838102 ps |
| T856 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_intr_smoke.1591822416 |
|
|
Feb 08 01:14:35 PM UTC 25 |
Feb 08 01:14:46 PM UTC 25 |
3928851703 ps |
| T857 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_smoke.3891030862 |
|
|
Feb 08 01:13:30 PM UTC 25 |
Feb 08 01:14:47 PM UTC 25 |
5258919280 ps |
| T858 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_stretch.714952999 |
|
|
Feb 08 01:14:34 PM UTC 25 |
Feb 08 01:14:51 PM UTC 25 |
951639648 ps |
| T859 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_acq.3824943595 |
|
|
Feb 08 01:14:48 PM UTC 25 |
Feb 08 01:14:51 PM UTC 25 |
204312507 ps |
| T154 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_stress_all.3500914839 |
|
|
Feb 08 01:13:20 PM UTC 25 |
Feb 08 01:14:52 PM UTC 25 |
105701357237 ps |
| T860 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_full.4200879946 |
|
|
Feb 08 01:13:34 PM UTC 25 |
Feb 08 01:14:52 PM UTC 25 |
47108203100 ps |
| T861 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_tx.1500461879 |
|
|
Feb 08 01:14:49 PM UTC 25 |
Feb 08 01:14:52 PM UTC 25 |
377763714 ps |
| T862 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_watermark.3762583404 |
|
|
Feb 08 01:09:46 PM UTC 25 |
Feb 08 01:14:53 PM UTC 25 |
20239800495 ps |
| T863 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_stretch_timeout.2642217286 |
|
|
Feb 08 01:14:24 PM UTC 25 |
Feb 08 01:14:53 PM UTC 25 |
1837765142 ps |
| T864 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_timeout.2951174436 |
|
|
Feb 08 01:14:41 PM UTC 25 |
Feb 08 01:14:54 PM UTC 25 |
1216528186 ps |
| T865 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_hrst.1914159273 |
|
|
Feb 08 01:14:53 PM UTC 25 |
Feb 08 01:14:58 PM UTC 25 |
1171554193 ps |
| T258 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_mode_toggle.3619102140 |
|
|
Feb 08 01:14:54 PM UTC 25 |
Feb 08 01:14:58 PM UTC 25 |
294889897 ps |
| T866 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_tx.1875170207 |
|
|
Feb 08 01:14:55 PM UTC 25 |
Feb 08 01:14:59 PM UTC 25 |
562860569 ps |
| T867 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_smoke.1833956494 |
|
|
Feb 08 01:14:28 PM UTC 25 |
Feb 08 01:15:00 PM UTC 25 |
7364076292 ps |
| T868 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_acq.1571534335 |
|
|
Feb 08 01:14:54 PM UTC 25 |
Feb 08 01:15:00 PM UTC 25 |
450243222 ps |
| T869 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_perf.2112195702 |
|
|
Feb 08 01:14:51 PM UTC 25 |
Feb 08 01:15:01 PM UTC 25 |
933725744 ps |
| T870 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_bad_addr.2283607746 |
|
|
Feb 08 01:14:53 PM UTC 25 |
Feb 08 01:15:02 PM UTC 25 |
1568552557 ps |
| T871 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_tx_stretch_ctrl.3685644945 |
|
|
Feb 08 01:14:59 PM UTC 25 |
Feb 08 01:15:03 PM UTC 25 |
71565926 ps |
| T872 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_alert_test.4089610560 |
|
|
Feb 08 01:15:01 PM UTC 25 |
Feb 08 01:15:03 PM UTC 25 |
17338826 ps |
| T873 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_smbus_maxlen.2923756824 |
|
|
Feb 08 01:14:59 PM UTC 25 |
Feb 08 01:15:04 PM UTC 25 |
963444643 ps |
| T874 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull.1659061032 |
|
|
Feb 08 01:15:00 PM UTC 25 |
Feb 08 01:15:06 PM UTC 25 |
417565155 ps |
| T875 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_override.375089565 |
|
|
Feb 08 01:15:03 PM UTC 25 |
Feb 08 01:15:06 PM UTC 25 |
161266657 ps |
| T876 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull_addr.3936063930 |
|
|
Feb 08 01:15:00 PM UTC 25 |
Feb 08 01:15:06 PM UTC 25 |
2003784861 ps |
| T877 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_fmt.1324667150 |
|
|
Feb 08 01:15:06 PM UTC 25 |
Feb 08 01:15:09 PM UTC 25 |
161900117 ps |
| T878 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_smoke.3885105784 |
|
|
Feb 08 01:14:18 PM UTC 25 |
Feb 08 01:15:09 PM UTC 25 |
1174211133 ps |
| T879 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_may_nack.2737247876 |
|
|
Feb 08 01:14:54 PM UTC 25 |
Feb 08 01:15:10 PM UTC 25 |
1830998925 ps |
| T880 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_rx.582293597 |
|
|
Feb 08 01:15:07 PM UTC 25 |
Feb 08 01:15:13 PM UTC 25 |
701178627 ps |
| T881 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_perf_precise.621467092 |
|
|
Feb 08 01:15:10 PM UTC 25 |
Feb 08 01:15:15 PM UTC 25 |
240029431 ps |
| T882 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_error_intr.1823913112 |
|
|
Feb 08 01:15:14 PM UTC 25 |
Feb 08 01:15:17 PM UTC 25 |
85063782 ps |
| T883 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_fmt_empty.2508066096 |
|
|
Feb 08 01:15:07 PM UTC 25 |
Feb 08 01:15:19 PM UTC 25 |
1732076009 ps |
| T884 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_stretch_timeout.3578799308 |
|
|
Feb 08 01:15:11 PM UTC 25 |
Feb 08 01:15:27 PM UTC 25 |
258431307 ps |
| T885 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_smoke.71530034 |
|
|
Feb 08 01:15:18 PM UTC 25 |
Feb 08 01:15:33 PM UTC 25 |
2583203798 ps |
| T886 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_stress_rd.2235124830 |
|
|
Feb 08 01:15:28 PM UTC 25 |
Feb 08 01:15:38 PM UTC 25 |
681564178 ps |
| T887 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_intr_stress_wr.2348624969 |
|
|
Feb 08 01:13:09 PM UTC 25 |
Feb 08 01:15:38 PM UTC 25 |
8668105107 ps |
| T888 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_stress_rd.335246987 |
|
|
Feb 08 01:14:31 PM UTC 25 |
Feb 08 01:15:56 PM UTC 25 |
7684670961 ps |
| T889 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_stress_all.4143088028 |
|
|
Feb 08 01:13:01 PM UTC 25 |
Feb 08 01:15:40 PM UTC 25 |
6454938806 ps |
| T890 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_smoke.601864394 |
|
|
Feb 08 01:15:03 PM UTC 25 |
Feb 08 01:15:41 PM UTC 25 |
7599447810 ps |
| T891 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_acq.1856000304 |
|
|
Feb 08 01:15:42 PM UTC 25 |
Feb 08 01:15:45 PM UTC 25 |
551484642 ps |
| T892 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_intr_smoke.724607570 |
|
|
Feb 08 01:15:39 PM UTC 25 |
Feb 08 01:15:48 PM UTC 25 |
7420417861 ps |
| T893 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_tx.3189341556 |
|
|
Feb 08 01:15:46 PM UTC 25 |
Feb 08 01:15:49 PM UTC 25 |
298620992 ps |
| T894 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_timeout.2161530204 |
|
|
Feb 08 01:15:41 PM UTC 25 |
Feb 08 01:15:50 PM UTC 25 |
1031378213 ps |
| T895 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_full.3278199070 |
|
|
Feb 08 01:12:47 PM UTC 25 |
Feb 08 01:15:52 PM UTC 25 |
5076365303 ps |
| T896 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_hrst.3253893846 |
|
|
Feb 08 01:15:51 PM UTC 25 |
Feb 08 01:15:55 PM UTC 25 |
343014122 ps |
| T897 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_tx.3630482408 |
|
|
Feb 08 01:15:57 PM UTC 25 |
Feb 08 01:15:59 PM UTC 25 |
77981061 ps |
| T898 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_tx_stretch_ctrl.3237759457 |
|
|
Feb 08 01:15:57 PM UTC 25 |
Feb 08 01:16:01 PM UTC 25 |
113050108 ps |
| T899 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_acq.1328395980 |
|
|
Feb 08 01:15:57 PM UTC 25 |
Feb 08 01:16:03 PM UTC 25 |
7834521795 ps |
| T900 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_smbus_maxlen.1664948951 |
|
|
Feb 08 01:15:58 PM UTC 25 |
Feb 08 01:16:03 PM UTC 25 |
2998432178 ps |
| T901 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull.2501197668 |
|
|
Feb 08 01:15:59 PM UTC 25 |
Feb 08 01:16:04 PM UTC 25 |
1007485447 ps |
| T902 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_may_nack.4238819515 |
|
|
Feb 08 01:15:52 PM UTC 25 |
Feb 08 01:16:04 PM UTC 25 |
2215510212 ps |
| T903 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull_addr.3793851887 |
|
|
Feb 08 01:16:00 PM UTC 25 |
Feb 08 01:16:05 PM UTC 25 |
435560459 ps |
| T904 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_nack_txstretch.3845102831 |
|
|
Feb 08 01:16:02 PM UTC 25 |
Feb 08 01:16:06 PM UTC 25 |
219706454 ps |
| T905 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_alert_test.1537923737 |
|
|
Feb 08 01:16:04 PM UTC 25 |
Feb 08 01:16:06 PM UTC 25 |
16338747 ps |
| T146 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_override.3029599346 |
|
|
Feb 08 01:16:04 PM UTC 25 |
Feb 08 01:16:06 PM UTC 25 |
17474476 ps |
| T906 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_fmt.486520474 |
|
|
Feb 08 01:16:06 PM UTC 25 |
Feb 08 01:16:09 PM UTC 25 |
469290333 ps |
| T907 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_rx.739040424 |
|
|
Feb 08 01:16:07 PM UTC 25 |
Feb 08 01:16:15 PM UTC 25 |
163455552 ps |
| T908 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_watermark.4190888300 |
|
|
Feb 08 01:13:31 PM UTC 25 |
Feb 08 01:16:20 PM UTC 25 |
4897337895 ps |
| T909 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_perf_precise.290406426 |
|
|
Feb 08 01:16:21 PM UTC 25 |
Feb 08 01:16:23 PM UTC 25 |
86810186 ps |
| T910 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_fmt_empty.839941054 |
|
|
Feb 08 01:16:07 PM UTC 25 |
Feb 08 01:16:25 PM UTC 25 |
3085325459 ps |
| T911 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_overflow.1353238255 |
|
|
Feb 08 01:13:32 PM UTC 25 |
Feb 08 01:16:29 PM UTC 25 |
24400374432 ps |
| T912 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_error_intr.3706754423 |
|
|
Feb 08 01:16:26 PM UTC 25 |
Feb 08 01:16:32 PM UTC 25 |
690383912 ps |
| T913 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_stretch_timeout.248689609 |
|
|
Feb 08 01:16:25 PM UTC 25 |
Feb 08 01:16:42 PM UTC 25 |
3304724824 ps |
| T914 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_smoke.659823196 |
|
|
Feb 08 01:16:04 PM UTC 25 |
Feb 08 01:16:46 PM UTC 25 |
1513530717 ps |
| T915 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_smoke.1024449572 |
|
|
Feb 08 01:16:32 PM UTC 25 |
Feb 08 01:16:49 PM UTC 25 |
3357373908 ps |
| T916 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_stress_rd.3771088316 |
|
|
Feb 08 01:16:47 PM UTC 25 |
Feb 08 01:16:57 PM UTC 25 |
1039875268 ps |
| T917 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_full.1340909190 |
|
|
Feb 08 01:15:07 PM UTC 25 |
Feb 08 01:17:04 PM UTC 25 |
13425037704 ps |
| T918 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_intr_smoke.630387215 |
|
|
Feb 08 01:16:58 PM UTC 25 |
Feb 08 01:17:11 PM UTC 25 |
1850067300 ps |
| T919 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_intr_stress_wr.219358551 |
|
|
Feb 08 01:17:04 PM UTC 25 |
Feb 08 01:17:16 PM UTC 25 |
9602950375 ps |
| T920 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_acq.2527229621 |
|
|
Feb 08 01:17:14 PM UTC 25 |
Feb 08 01:17:16 PM UTC 25 |
257630939 ps |
| T921 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_tx.902655659 |
|
|
Feb 08 01:17:16 PM UTC 25 |
Feb 08 01:17:19 PM UTC 25 |
219761560 ps |
| T922 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_hrst.324985465 |
|
|
Feb 08 01:17:19 PM UTC 25 |
Feb 08 01:17:23 PM UTC 25 |
1008396087 ps |
| T923 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_timeout.3116765831 |
|
|
Feb 08 01:17:12 PM UTC 25 |
Feb 08 01:17:24 PM UTC 25 |
2626117188 ps |
| T924 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_perf.3574753987 |
|
|
Feb 08 01:17:17 PM UTC 25 |
Feb 08 01:17:24 PM UTC 25 |
1032756350 ps |
| T925 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_bad_addr.3056866784 |
|
|
Feb 08 01:17:19 PM UTC 25 |
Feb 08 01:17:28 PM UTC 25 |
782202695 ps |
| T926 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_acq.3343192555 |
|
|
Feb 08 01:17:25 PM UTC 25 |
Feb 08 01:17:30 PM UTC 25 |
2968856496 ps |
| T261 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_mode_toggle.2107438004 |
|
|
Feb 08 01:17:25 PM UTC 25 |
Feb 08 01:17:31 PM UTC 25 |
506517244 ps |
| T927 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_tx.1271571034 |
|
|
Feb 08 01:17:29 PM UTC 25 |
Feb 08 01:17:32 PM UTC 25 |
908056475 ps |
| T928 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_full.4024620325 |
|
|
Feb 08 01:14:23 PM UTC 25 |
Feb 08 01:17:34 PM UTC 25 |
12135418293 ps |
| T929 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_may_nack.138054345 |
|
|
Feb 08 01:17:25 PM UTC 25 |
Feb 08 01:17:35 PM UTC 25 |
952504115 ps |
| T930 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_stress_all.4117773030 |
|
|
Feb 08 01:06:28 PM UTC 25 |
Feb 08 01:17:36 PM UTC 25 |
52447713542 ps |
| T931 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_smbus_maxlen.1266499792 |
|
|
Feb 08 01:17:32 PM UTC 25 |
Feb 08 01:17:36 PM UTC 25 |
2208018556 ps |
| T932 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_tx_stretch_ctrl.3481506177 |
|
|
Feb 08 01:17:31 PM UTC 25 |
Feb 08 01:17:37 PM UTC 25 |
204090654 ps |
| T933 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull.1518961275 |
|
|
Feb 08 01:17:33 PM UTC 25 |
Feb 08 01:17:38 PM UTC 25 |
7091293378 ps |
| T40 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_host_perf.604087955 |
|
|
Feb 08 01:08:45 PM UTC 25 |
Feb 08 01:17:38 PM UTC 25 |
7196021638 ps |
| T934 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_perf.1411917850 |
|
|
Feb 08 01:14:24 PM UTC 25 |
Feb 08 01:17:38 PM UTC 25 |
13018522363 ps |
| T935 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_alert_test.1468931912 |
|
|
Feb 08 01:17:37 PM UTC 25 |
Feb 08 01:17:39 PM UTC 25 |
43689037 ps |
| T936 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_nack_txstretch.1932439650 |
|
|
Feb 08 01:17:36 PM UTC 25 |
Feb 08 01:17:39 PM UTC 25 |
406184668 ps |
| T937 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull_addr.4071754120 |
|
|
Feb 08 01:17:35 PM UTC 25 |
Feb 08 01:17:41 PM UTC 25 |
937680667 ps |
| T938 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_override.3625354853 |
|
|
Feb 08 01:17:38 PM UTC 25 |
Feb 08 01:17:41 PM UTC 25 |
33340852 ps |
| T939 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_fmt.4026628460 |
|
|
Feb 08 01:17:39 PM UTC 25 |
Feb 08 01:17:42 PM UTC 25 |
376787117 ps |
| T940 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_overflow.2539946418 |
|
|
Feb 08 01:15:06 PM UTC 25 |
Feb 08 01:17:44 PM UTC 25 |
2164792728 ps |
| T941 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_perf_precise.1349057808 |
|
|
Feb 08 01:17:43 PM UTC 25 |
Feb 08 01:17:45 PM UTC 25 |
55686930 ps |
| T942 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_rx.3787239558 |
|
|
Feb 08 01:17:41 PM UTC 25 |
Feb 08 01:17:47 PM UTC 25 |
1490056773 ps |
| T115 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_host_stress_all.2446783526 |
|
|
Feb 08 12:56:16 PM UTC 25 |
Feb 08 01:17:49 PM UTC 25 |
55253058185 ps |
| T943 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_error_intr.1051918330 |
|
|
Feb 08 01:17:46 PM UTC 25 |
Feb 08 01:17:49 PM UTC 25 |
44024712 ps |
| T944 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_perf.2557549242 |
|
|
Feb 08 01:17:42 PM UTC 25 |
Feb 08 01:17:49 PM UTC 25 |
1203989380 ps |
| T945 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_fmt_empty.2551108454 |
|
|
Feb 08 01:17:40 PM UTC 25 |
Feb 08 01:17:54 PM UTC 25 |
413640299 ps |
| T946 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_stretch.2054147466 |
|
|
Feb 08 01:17:50 PM UTC 25 |
Feb 08 01:18:01 PM UTC 25 |
2444735357 ps |
| T947 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_stretch_timeout.2582615300 |
|
|
Feb 08 01:17:45 PM UTC 25 |
Feb 08 01:18:01 PM UTC 25 |
751762770 ps |
| T41 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_host_stress_all.2761272887 |
|
|
Feb 08 01:03:55 PM UTC 25 |
Feb 08 01:18:02 PM UTC 25 |
21645186777 ps |
| T948 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_stress_rd.376904609 |
|
|
Feb 08 01:17:50 PM UTC 25 |
Feb 08 01:18:03 PM UTC 25 |
236266599 ps |
| T949 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_intr_smoke.3368301577 |
|
|
Feb 08 01:17:54 PM UTC 25 |
Feb 08 01:18:04 PM UTC 25 |
5745942747 ps |
| T950 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_overflow.822927954 |
|
|
Feb 08 01:16:06 PM UTC 25 |
Feb 08 01:18:06 PM UTC 25 |
1627174893 ps |
| T951 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_acq.2331849799 |
|
|
Feb 08 01:18:04 PM UTC 25 |
Feb 08 01:18:06 PM UTC 25 |
293695552 ps |
| T952 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_overflow.3351880828 |
|
|
Feb 08 01:14:22 PM UTC 25 |
Feb 08 01:18:07 PM UTC 25 |
11234731881 ps |
| T953 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_tx.642806483 |
|
|
Feb 08 01:18:05 PM UTC 25 |
Feb 08 01:18:08 PM UTC 25 |
283412266 ps |
| T954 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_watermark.2986793177 |
|
|
Feb 08 01:15:04 PM UTC 25 |
Feb 08 01:18:09 PM UTC 25 |
5253375215 ps |
| T955 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_stress_wr.4124144724 |
|
|
Feb 08 01:17:50 PM UTC 25 |
Feb 08 01:18:10 PM UTC 25 |
31824809006 ps |
| T956 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_perf.2481324155 |
|
|
Feb 08 01:16:16 PM UTC 25 |
Feb 08 01:18:11 PM UTC 25 |
30168615089 ps |
| T957 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_smoke.1509577901 |
|
|
Feb 08 01:17:49 PM UTC 25 |
Feb 08 01:18:11 PM UTC 25 |
5801051804 ps |
| T958 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_stress_wr.2596707292 |
|
|
Feb 08 01:13:03 PM UTC 25 |
Feb 08 01:18:12 PM UTC 25 |
33190639974 ps |
| T959 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_perf.2282413747 |
|
|
Feb 08 01:18:06 PM UTC 25 |
Feb 08 01:18:12 PM UTC 25 |
2243202024 ps |
| T960 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_timeout.3183870577 |
|
|
Feb 08 01:18:03 PM UTC 25 |
Feb 08 01:18:13 PM UTC 25 |
1707340396 ps |
| T262 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_mode_toggle.2522587483 |
|
|
Feb 08 01:18:09 PM UTC 25 |
Feb 08 01:18:15 PM UTC 25 |
507931681 ps |
| T961 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_tx.3611264709 |
|
|
Feb 08 01:18:12 PM UTC 25 |
Feb 08 01:18:15 PM UTC 25 |
134371442 ps |
| T962 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_acq.1739885417 |
|
|
Feb 08 01:18:11 PM UTC 25 |
Feb 08 01:18:17 PM UTC 25 |
489303448 ps |
| T963 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_bad_addr.457370570 |
|
|
Feb 08 01:18:07 PM UTC 25 |
Feb 08 01:18:18 PM UTC 25 |
5941406367 ps |
| T964 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_smbus_maxlen.1388432161 |
|
|
Feb 08 01:18:13 PM UTC 25 |
Feb 08 01:18:18 PM UTC 25 |
1026219013 ps |
| T965 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_nack_txstretch.2677324438 |
|
|
Feb 08 01:18:16 PM UTC 25 |
Feb 08 01:18:18 PM UTC 25 |
134789073 ps |
| T966 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_alert_test.236741878 |
|
|
Feb 08 01:18:17 PM UTC 25 |
Feb 08 01:18:19 PM UTC 25 |
25178806 ps |
| T967 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull_addr.4088810265 |
|
|
Feb 08 01:18:15 PM UTC 25 |
Feb 08 01:18:20 PM UTC 25 |
5432417753 ps |
| T250 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_may_nack.1394436180 |
|
|
Feb 08 01:18:10 PM UTC 25 |
Feb 08 01:18:20 PM UTC 25 |
5947823099 ps |
| T968 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull.912223460 |
|
|
Feb 08 01:18:13 PM UTC 25 |
Feb 08 01:18:20 PM UTC 25 |
674757047 ps |
| T969 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_override.741457884 |
|
|
Feb 08 01:18:19 PM UTC 25 |
Feb 08 01:18:21 PM UTC 25 |
31239284 ps |
| T970 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_tx_stretch_ctrl.2763206475 |
|
|
Feb 08 01:18:12 PM UTC 25 |
Feb 08 01:18:21 PM UTC 25 |
360163961 ps |
| T971 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_fmt.3535718846 |
|
|
Feb 08 01:18:20 PM UTC 25 |
Feb 08 01:18:23 PM UTC 25 |
109577971 ps |
| T972 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_perf_precise.1226803996 |
|
|
Feb 08 01:18:22 PM UTC 25 |
Feb 08 01:18:25 PM UTC 25 |
32249371 ps |
| T973 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_rx.1201541995 |
|
|
Feb 08 01:18:21 PM UTC 25 |
Feb 08 01:18:28 PM UTC 25 |
626499401 ps |
| T974 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_overflow.515799507 |
|
|
Feb 08 01:17:38 PM UTC 25 |
Feb 08 01:18:31 PM UTC 25 |
2889360467 ps |
| T975 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_stress_all.1702775804 |
|
|
Feb 08 01:15:49 PM UTC 25 |
Feb 08 01:18:33 PM UTC 25 |
33434376219 ps |
| T976 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_error_intr.4106133712 |
|
|
Feb 08 01:18:26 PM UTC 25 |
Feb 08 01:18:35 PM UTC 25 |
1415829822 ps |
| T977 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_fmt_empty.42317042 |
|
|
Feb 08 01:18:21 PM UTC 25 |
Feb 08 01:18:38 PM UTC 25 |
699925110 ps |
| T978 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_smoke.3088678546 |
|
|
Feb 08 01:17:37 PM UTC 25 |
Feb 08 01:18:39 PM UTC 25 |
2158857400 ps |
| T979 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_smoke.2777516884 |
|
|
Feb 08 01:18:30 PM UTC 25 |
Feb 08 01:18:40 PM UTC 25 |
4653948303 ps |
| T980 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_stress_wr.4200484041 |
|
|
Feb 08 01:14:30 PM UTC 25 |
Feb 08 01:18:41 PM UTC 25 |
42395246150 ps |
| T981 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_perf.1486998123 |
|
|
Feb 08 01:12:47 PM UTC 25 |
Feb 08 01:18:42 PM UTC 25 |
12652745869 ps |
| T982 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_intr_smoke.2919940951 |
|
|
Feb 08 01:20:09 PM UTC 25 |
Feb 08 01:20:17 PM UTC 25 |
1654721000 ps |
| T983 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_intr_smoke.260381078 |
|
|
Feb 08 01:18:36 PM UTC 25 |
Feb 08 01:18:44 PM UTC 25 |
1582640474 ps |
| T984 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_acq.3223383364 |
|
|
Feb 08 01:18:42 PM UTC 25 |
Feb 08 01:18:45 PM UTC 25 |
246598635 ps |
| T985 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_tx.3983572716 |
|
|
Feb 08 01:18:43 PM UTC 25 |
Feb 08 01:18:46 PM UTC 25 |
279575258 ps |
| T986 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_stretch_timeout.3580867316 |
|
|
Feb 08 01:18:24 PM UTC 25 |
Feb 08 01:18:49 PM UTC 25 |
1732868061 ps |
| T987 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_timeout.1896116792 |
|
|
Feb 08 01:18:39 PM UTC 25 |
Feb 08 01:18:49 PM UTC 25 |
4644232382 ps |
| T988 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_stretch.2872006019 |
|
|
Feb 08 01:18:35 PM UTC 25 |
Feb 08 01:18:49 PM UTC 25 |
2283102395 ps |
| T989 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_hrst.4046089204 |
|
|
Feb 08 01:18:48 PM UTC 25 |
Feb 08 01:18:52 PM UTC 25 |
1731749472 ps |
| T990 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_acq.2327400581 |
|
|
Feb 08 01:18:50 PM UTC 25 |
Feb 08 01:18:53 PM UTC 25 |
138899408 ps |
| T991 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_mode_toggle.911354894 |
|
|
Feb 08 01:18:50 PM UTC 25 |
Feb 08 01:18:54 PM UTC 25 |
236322720 ps |
| T992 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_perf.2382883859 |
|
|
Feb 08 01:18:45 PM UTC 25 |
Feb 08 01:18:54 PM UTC 25 |
3608113869 ps |
| T993 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_tx.1638362219 |
|
|
Feb 08 01:18:53 PM UTC 25 |
Feb 08 01:18:56 PM UTC 25 |
168046632 ps |
| T994 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_bad_addr.231480530 |
|
|
Feb 08 01:18:47 PM UTC 25 |
Feb 08 01:18:57 PM UTC 25 |
1064365403 ps |
| T995 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_full.1207175751 |
|
|
Feb 08 01:16:10 PM UTC 25 |
Feb 08 01:18:58 PM UTC 25 |
31784338696 ps |
| T996 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_smbus_maxlen.3736476434 |
|
|
Feb 08 01:18:54 PM UTC 25 |
Feb 08 01:18:58 PM UTC 25 |
761029940 ps |
| T997 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_alert_test.1168199790 |
|
|
Feb 08 01:18:58 PM UTC 25 |
Feb 08 01:19:01 PM UTC 25 |
18886373 ps |
| T274 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_host_stress_all.3120670646 |
|
|
Feb 08 01:12:04 PM UTC 25 |
Feb 08 01:20:16 PM UTC 25 |
7970921584 ps |
| T998 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull.1742368867 |
|
|
Feb 08 01:18:55 PM UTC 25 |
Feb 08 01:19:01 PM UTC 25 |
2298797243 ps |
| T999 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_nack_txstretch.1471450000 |
|
|
Feb 08 01:18:57 PM UTC 25 |
Feb 08 01:19:01 PM UTC 25 |
132110356 ps |
| T1000 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_tx_stretch_ctrl.452801574 |
|
|
Feb 08 01:18:54 PM UTC 25 |
Feb 08 01:19:02 PM UTC 25 |
267163303 ps |
| T1001 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull_addr.1436521431 |
|
|
Feb 08 01:18:57 PM UTC 25 |
Feb 08 01:19:03 PM UTC 25 |
3818905071 ps |
| T1002 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_smoke.2531064842 |
|
|
Feb 08 01:18:18 PM UTC 25 |
Feb 08 01:19:03 PM UTC 25 |
1881409891 ps |
| T1003 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_override.139527725 |
|
|
Feb 08 01:19:01 PM UTC 25 |
Feb 08 01:19:03 PM UTC 25 |
34949783 ps |
| T1004 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_fmt.1834944736 |
|
|
Feb 08 01:19:02 PM UTC 25 |
Feb 08 01:19:05 PM UTC 25 |
93420510 ps |
| T1005 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_perf_precise.4167964629 |
|
|
Feb 08 01:19:04 PM UTC 25 |
Feb 08 01:19:07 PM UTC 25 |
219924554 ps |
| T1006 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_stress_rd.549907216 |
|
|
Feb 08 01:18:34 PM UTC 25 |
Feb 08 01:19:08 PM UTC 25 |
745319897 ps |
| T1007 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_fmt_empty.47725363 |
|
|
Feb 08 01:19:02 PM UTC 25 |
Feb 08 01:19:09 PM UTC 25 |
251953874 ps |
| T1008 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_intr_stress_wr.4230992569 |
|
|
Feb 08 01:18:39 PM UTC 25 |
Feb 08 01:19:09 PM UTC 25 |
5873167620 ps |
| T1009 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_rx.3522378842 |
|
|
Feb 08 01:19:03 PM UTC 25 |
Feb 08 01:19:11 PM UTC 25 |
1222963346 ps |
| T1010 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_error_intr.689695333 |
|
|
Feb 08 01:19:08 PM UTC 25 |
Feb 08 01:19:13 PM UTC 25 |
449064360 ps |
| T1011 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_may_nack.2464009355 |
|
|
Feb 08 01:18:50 PM UTC 25 |
Feb 08 01:19:14 PM UTC 25 |
484744508 ps |
| T1012 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_stress_all.1135151522 |
|
|
Feb 08 01:03:38 PM UTC 25 |
Feb 08 01:19:17 PM UTC 25 |
43830989978 ps |
| T1013 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_stress_rd.3724888609 |
|
|
Feb 08 01:19:11 PM UTC 25 |
Feb 08 01:19:23 PM UTC 25 |
800328088 ps |
| T1014 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_intr_smoke.3200413385 |
|
|
Feb 08 01:19:15 PM UTC 25 |
Feb 08 01:19:26 PM UTC 25 |
9305696102 ps |
| T1015 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_acq.4115138454 |
|
|
Feb 08 01:19:27 PM UTC 25 |
Feb 08 01:19:29 PM UTC 25 |
248466164 ps |
| T1016 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_smoke.1234396395 |
|
|
Feb 08 01:19:09 PM UTC 25 |
Feb 08 01:19:30 PM UTC 25 |
5668492912 ps |
| T294 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_tx.1683720440 |
|
|
Feb 08 01:19:28 PM UTC 25 |
Feb 08 01:19:33 PM UTC 25 |
282289307 ps |
| T1017 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_watermark.3712844761 |
|
|
Feb 08 01:16:05 PM UTC 25 |
Feb 08 01:19:33 PM UTC 25 |
3330111620 ps |
| T1018 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_smoke.2677811035 |
|
|
Feb 08 01:18:59 PM UTC 25 |
Feb 08 01:19:34 PM UTC 25 |
1356890229 ps |
| T1019 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_timeout.1277918059 |
|
|
Feb 08 01:19:24 PM UTC 25 |
Feb 08 01:19:35 PM UTC 25 |
5046774107 ps |
| T1020 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_stretch_timeout.1067127013 |
|
|
Feb 08 01:19:06 PM UTC 25 |
Feb 08 01:19:36 PM UTC 25 |
590046410 ps |
| T1021 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_mode_toggle.2636148060 |
|
|
Feb 08 01:19:34 PM UTC 25 |
Feb 08 01:19:37 PM UTC 25 |
216833100 ps |
| T1022 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_perf.3695430229 |
|
|
Feb 08 01:19:28 PM UTC 25 |
Feb 08 01:19:38 PM UTC 25 |
3256073208 ps |
| T1023 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_bad_addr.2858254606 |
|
|
Feb 08 01:19:31 PM UTC 25 |
Feb 08 01:19:38 PM UTC 25 |
912341243 ps |
| T1024 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_hrst.3326091071 |
|
|
Feb 08 01:19:34 PM UTC 25 |
Feb 08 01:19:38 PM UTC 25 |
986909815 ps |
| T1025 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_tx.1188813752 |
|
|
Feb 08 01:19:37 PM UTC 25 |
Feb 08 01:19:39 PM UTC 25 |
65948734 ps |
| T1026 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_acq.2005604466 |
|
|
Feb 08 01:19:36 PM UTC 25 |
Feb 08 01:19:41 PM UTC 25 |
3430701837 ps |
| T1027 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_perf.2038141027 |
|
|
Feb 08 01:19:04 PM UTC 25 |
Feb 08 01:19:41 PM UTC 25 |
6704812079 ps |
| T1028 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_smbus_maxlen.1248592407 |
|
|
Feb 08 01:19:38 PM UTC 25 |
Feb 08 01:19:43 PM UTC 25 |
2381537692 ps |
| T1029 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_tx_stretch_ctrl.3872419879 |
|
|
Feb 08 01:19:38 PM UTC 25 |
Feb 08 01:19:43 PM UTC 25 |
139222577 ps |
| T1030 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_nack_txstretch.2749264879 |
|
|
Feb 08 01:19:40 PM UTC 25 |
Feb 08 01:19:44 PM UTC 25 |
315957944 ps |
| T1031 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull.970636296 |
|
|
Feb 08 01:19:39 PM UTC 25 |
Feb 08 01:19:44 PM UTC 25 |
3626664572 ps |
| T275 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_stress_all.2067013048 |
|
|
Feb 08 01:09:56 PM UTC 25 |
Feb 08 01:19:44 PM UTC 25 |
8172172559 ps |
| T1032 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_alert_test.2237701577 |
|
|
Feb 08 01:19:42 PM UTC 25 |
Feb 08 01:19:44 PM UTC 25 |
21812135 ps |
| T1033 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull_addr.1280961224 |
|
|
Feb 08 01:19:39 PM UTC 25 |
Feb 08 01:19:45 PM UTC 25 |
1079313015 ps |
| T1034 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_watermark.1054338511 |
|
|
Feb 08 01:17:38 PM UTC 25 |
Feb 08 01:19:45 PM UTC 25 |
4639795705 ps |
| T1035 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_override.2534675203 |
|
|
Feb 08 01:19:43 PM UTC 25 |
Feb 08 01:19:45 PM UTC 25 |
27704861 ps |
| T1036 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_fmt.1040992726 |
|
|
Feb 08 01:19:46 PM UTC 25 |
Feb 08 01:19:48 PM UTC 25 |
119251959 ps |
| T1037 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_rx.3444155319 |
|
|
Feb 08 01:19:46 PM UTC 25 |
Feb 08 01:19:52 PM UTC 25 |
164253667 ps |
| T1038 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_perf_precise.2471178707 |
|
|
Feb 08 01:19:47 PM UTC 25 |
Feb 08 01:19:52 PM UTC 25 |
167547665 ps |
| T1039 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_error_intr.1834938357 |
|
|
Feb 08 01:19:52 PM UTC 25 |
Feb 08 01:19:56 PM UTC 25 |
157758330 ps |
| T1040 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_full.1752802372 |
|
|
Feb 08 01:18:21 PM UTC 25 |
Feb 08 01:20:00 PM UTC 25 |
11573574916 ps |
| T1041 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_fmt_empty.3654229929 |
|
|
Feb 08 01:19:46 PM UTC 25 |
Feb 08 01:20:02 PM UTC 25 |
244619335 ps |
| T1042 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_stretch_timeout.2479692589 |
|
|
Feb 08 01:19:49 PM UTC 25 |
Feb 08 01:20:03 PM UTC 25 |
2789527577 ps |
| T1043 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_may_nack.4033074672 |
|
|
Feb 08 01:19:35 PM UTC 25 |
Feb 08 01:20:08 PM UTC 25 |
710122467 ps |
| T1044 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_smoke.2343415982 |
|
|
Feb 08 01:19:57 PM UTC 25 |
Feb 08 01:20:11 PM UTC 25 |
7080859238 ps |
| T1045 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_stress_all.2075925605 |
|
|
Feb 08 01:18:46 PM UTC 25 |
Feb 08 01:20:12 PM UTC 25 |
51468530554 ps |
| T1046 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_stress_rd.413006451 |
|
|
Feb 08 01:20:02 PM UTC 25 |
Feb 08 01:20:13 PM UTC 25 |
1695445607 ps |
| T1047 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_intr_stress_wr.3620507663 |
|
|
Feb 08 01:20:12 PM UTC 25 |
Feb 08 01:20:19 PM UTC 25 |
9249750144 ps |
| T1048 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_acq.2600728805 |
|
|
Feb 08 01:20:17 PM UTC 25 |
Feb 08 01:20:19 PM UTC 25 |
245427411 ps |
| T1049 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_tx.361368355 |
|
|
Feb 08 01:20:18 PM UTC 25 |
Feb 08 01:20:21 PM UTC 25 |
306424558 ps |
| T1050 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_perf.3818973012 |
|
|
Feb 08 01:20:18 PM UTC 25 |
Feb 08 01:20:25 PM UTC 25 |
1893387348 ps |
| T1051 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_timeout.2721509718 |
|
|
Feb 08 01:20:13 PM UTC 25 |
Feb 08 01:20:25 PM UTC 25 |
5377633515 ps |
| T1052 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_perf.2409228063 |
|
|
Feb 08 01:21:31 PM UTC 25 |
Feb 08 01:21:39 PM UTC 25 |
919978080 ps |
| T1053 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_bad_addr.2341103868 |
|
|
Feb 08 01:20:20 PM UTC 25 |
Feb 08 01:20:29 PM UTC 25 |
3833194549 ps |
| T1054 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_acq.2668666024 |
|
|
Feb 08 01:20:26 PM UTC 25 |
Feb 08 01:20:29 PM UTC 25 |
314075869 ps |
| T1055 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_overflow.3461149831 |
|
|
Feb 08 01:19:02 PM UTC 25 |
Feb 08 01:20:30 PM UTC 25 |
9682291655 ps |
| T1056 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_watermark.937297551 |
|
|
Feb 08 01:14:21 PM UTC 25 |
Feb 08 01:20:31 PM UTC 25 |
37386277044 ps |
| T1057 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_stretch.1649900990 |
|
|
Feb 08 01:20:03 PM UTC 25 |
Feb 08 01:20:33 PM UTC 25 |
3331757214 ps |
| T1058 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_tx.702178307 |
|
|
Feb 08 01:20:30 PM UTC 25 |
Feb 08 01:20:33 PM UTC 25 |
147305275 ps |
| T1059 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull.2330472260 |
|
|
Feb 08 01:20:31 PM UTC 25 |
Feb 08 01:20:35 PM UTC 25 |
952486893 ps |
| T1060 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_smbus_maxlen.298523223 |
|
|
Feb 08 01:20:31 PM UTC 25 |
Feb 08 01:20:35 PM UTC 25 |
1861260969 ps |
| T1061 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_stress_wr.1037189443 |
|
|
Feb 08 01:16:43 PM UTC 25 |
Feb 08 01:20:36 PM UTC 25 |
29752297304 ps |
| T1062 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_tx_stretch_ctrl.984274837 |
|
|
Feb 08 01:20:30 PM UTC 25 |
Feb 08 01:20:36 PM UTC 25 |
142429278 ps |
| T1063 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_alert_test.1390214147 |
|
|
Feb 08 01:20:34 PM UTC 25 |
Feb 08 01:20:36 PM UTC 25 |
44323751 ps |
| T1064 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull_addr.2362684324 |
|
|
Feb 08 01:20:32 PM UTC 25 |
Feb 08 01:20:37 PM UTC 25 |
620875991 ps |
| T1065 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_nack_txstretch.413567103 |
|
|
Feb 08 01:20:34 PM UTC 25 |
Feb 08 01:20:38 PM UTC 25 |
132034936 ps |
| T1066 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_may_nack.2152550964 |
|
|
Feb 08 01:20:26 PM UTC 25 |
Feb 08 01:20:38 PM UTC 25 |
977955628 ps |
| T1067 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_override.3884405756 |
|
|
Feb 08 01:20:36 PM UTC 25 |
Feb 08 01:20:38 PM UTC 25 |
81700529 ps |
| T1068 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_fmt.455664953 |
|
|
Feb 08 01:20:37 PM UTC 25 |
Feb 08 01:20:40 PM UTC 25 |
314292862 ps |
| T1069 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_host_stress_all.4131998483 |
|
|
Feb 08 01:11:23 PM UTC 25 |
Feb 08 01:20:43 PM UTC 25 |
9881796772 ps |
| T1070 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_rx.1533902538 |
|
|
Feb 08 01:20:39 PM UTC 25 |
Feb 08 01:20:45 PM UTC 25 |
515320189 ps |
| T1071 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_bad_addr.166586071 |
|
|
Feb 08 01:21:33 PM UTC 25 |
Feb 08 01:21:40 PM UTC 25 |
1242693057 ps |
| T1072 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_smoke.3807774926 |
|
|
Feb 08 01:19:42 PM UTC 25 |
Feb 08 01:20:46 PM UTC 25 |
1234269427 ps |
| T1073 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_fmt_empty.1307481464 |
|
|
Feb 08 01:20:38 PM UTC 25 |
Feb 08 01:20:47 PM UTC 25 |
310088568 ps |
| T1074 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_perf_precise.4003831911 |
|
|
Feb 08 01:20:41 PM UTC 25 |
Feb 08 01:20:49 PM UTC 25 |
314825536 ps |
| T1075 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_error_intr.2383967541 |
|
|
Feb 08 01:20:46 PM UTC 25 |
Feb 08 01:20:50 PM UTC 25 |
107495622 ps |
| T1076 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_stretch.1405327040 |
|
|
Feb 08 01:20:50 PM UTC 25 |
Feb 08 01:20:54 PM UTC 25 |
528508680 ps |
| T1077 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_overflow.268211492 |
|
|
Feb 08 01:18:20 PM UTC 25 |
Feb 08 01:20:54 PM UTC 25 |
2287471451 ps |
| T116 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_watermark.715941223 |
|
|
Feb 08 01:19:44 PM UTC 25 |
Feb 08 01:20:57 PM UTC 25 |
34071573940 ps |
| T1078 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_overflow.3172643145 |
|
|
Feb 08 01:19:45 PM UTC 25 |
Feb 08 01:20:58 PM UTC 25 |
4602741100 ps |
| T1079 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_stress_rd.869327605 |
|
|
Feb 08 01:20:50 PM UTC 25 |
Feb 08 01:20:58 PM UTC 25 |
691479901 ps |