| T1080 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_perf.3887403634 |
|
|
Feb 08 01:19:46 PM UTC 25 |
Feb 08 01:20:59 PM UTC 25 |
12648639584 ps |
| T1081 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_full.3196384513 |
|
|
Feb 08 01:19:04 PM UTC 25 |
Feb 08 01:21:00 PM UTC 25 |
13500608845 ps |
| T1082 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_acq.532640332 |
|
|
Feb 08 01:21:00 PM UTC 25 |
Feb 08 01:21:03 PM UTC 25 |
274983847 ps |
| T1083 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_tx.2716942163 |
|
|
Feb 08 01:21:00 PM UTC 25 |
Feb 08 01:21:04 PM UTC 25 |
217303250 ps |
| T1084 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_intr_smoke.3298426471 |
|
|
Feb 08 01:20:55 PM UTC 25 |
Feb 08 01:21:04 PM UTC 25 |
2993744096 ps |
| T1085 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_intr_stress_wr.661191798 |
|
|
Feb 08 01:20:55 PM UTC 25 |
Feb 08 01:21:06 PM UTC 25 |
14537855829 ps |
| T1086 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_tx.2630352417 |
|
|
Feb 08 01:21:38 PM UTC 25 |
Feb 08 01:21:41 PM UTC 25 |
89241976 ps |
| T1087 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_perf.1025229212 |
|
|
Feb 08 01:21:01 PM UTC 25 |
Feb 08 01:21:08 PM UTC 25 |
530444073 ps |
| T1088 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_hrst.3212190131 |
|
|
Feb 08 01:21:05 PM UTC 25 |
Feb 08 01:21:08 PM UTC 25 |
2287170652 ps |
| T1089 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_timeout.1744848311 |
|
|
Feb 08 01:20:58 PM UTC 25 |
Feb 08 01:21:11 PM UTC 25 |
2368150310 ps |
| T1090 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_tx.2419999689 |
|
|
Feb 08 01:21:08 PM UTC 25 |
Feb 08 01:21:11 PM UTC 25 |
158924084 ps |
| T1091 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_acq.3697470650 |
|
|
Feb 08 01:21:08 PM UTC 25 |
Feb 08 01:21:12 PM UTC 25 |
222014739 ps |
| T1092 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_tx_stretch_ctrl.4130509871 |
|
|
Feb 08 01:21:08 PM UTC 25 |
Feb 08 01:21:12 PM UTC 25 |
86818347 ps |
| T1093 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_smoke.3237735066 |
|
|
Feb 08 01:20:36 PM UTC 25 |
Feb 08 01:21:13 PM UTC 25 |
8762310024 ps |
| T1094 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_smbus_maxlen.1915024596 |
|
|
Feb 08 01:21:09 PM UTC 25 |
Feb 08 01:21:14 PM UTC 25 |
781336149 ps |
| T1095 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_bad_addr.1404215835 |
|
|
Feb 08 01:21:04 PM UTC 25 |
Feb 08 01:21:15 PM UTC 25 |
1245669088 ps |
| T1096 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_full.2811752821 |
|
|
Feb 08 01:17:42 PM UTC 25 |
Feb 08 01:21:15 PM UTC 25 |
6241541110 ps |
| T1097 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_may_nack.3505694010 |
|
|
Feb 08 01:21:07 PM UTC 25 |
Feb 08 01:21:16 PM UTC 25 |
1325000372 ps |
| T1098 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_stress_wr.26137666 |
|
|
Feb 08 01:20:48 PM UTC 25 |
Feb 08 01:21:16 PM UTC 25 |
10423873596 ps |
| T1099 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_alert_test.3566316461 |
|
|
Feb 08 01:21:14 PM UTC 25 |
Feb 08 01:21:16 PM UTC 25 |
22784426 ps |
| T1100 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_nack_txstretch.274822254 |
|
|
Feb 08 01:21:13 PM UTC 25 |
Feb 08 01:21:16 PM UTC 25 |
296759275 ps |
| T1101 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_override.2885236823 |
|
|
Feb 08 01:21:15 PM UTC 25 |
Feb 08 01:21:17 PM UTC 25 |
26495432 ps |
| T1102 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull.1490838567 |
|
|
Feb 08 01:21:12 PM UTC 25 |
Feb 08 01:21:17 PM UTC 25 |
1900198821 ps |
| T1103 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull_addr.128288304 |
|
|
Feb 08 01:21:12 PM UTC 25 |
Feb 08 01:21:17 PM UTC 25 |
1770545068 ps |
| T1104 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_intr_stress_wr.860178819 |
|
|
Feb 08 01:18:03 PM UTC 25 |
Feb 08 01:21:20 PM UTC 25 |
20134206711 ps |
| T1105 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_fmt.3093101123 |
|
|
Feb 08 01:21:17 PM UTC 25 |
Feb 08 01:21:20 PM UTC 25 |
418475525 ps |
| T1106 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_smoke.2386489021 |
|
|
Feb 08 01:20:47 PM UTC 25 |
Feb 08 01:21:21 PM UTC 25 |
4888486074 ps |
| T1107 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_perf_precise.1699657723 |
|
|
Feb 08 01:21:18 PM UTC 25 |
Feb 08 01:21:24 PM UTC 25 |
482449681 ps |
| T1108 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_error_intr.3510745966 |
|
|
Feb 08 01:21:20 PM UTC 25 |
Feb 08 01:21:25 PM UTC 25 |
427952963 ps |
| T1109 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_watermark.438916686 |
|
|
Feb 08 01:18:19 PM UTC 25 |
Feb 08 01:21:26 PM UTC 25 |
11286552918 ps |
| T1110 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_fmt_empty.1144562312 |
|
|
Feb 08 01:21:17 PM UTC 25 |
Feb 08 01:21:26 PM UTC 25 |
743768660 ps |
| T1111 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_rx.1250288914 |
|
|
Feb 08 01:21:17 PM UTC 25 |
Feb 08 01:21:27 PM UTC 25 |
1169783751 ps |
| T1112 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_perf.886781562 |
|
|
Feb 08 01:21:18 PM UTC 25 |
Feb 08 01:21:28 PM UTC 25 |
142792046 ps |
| T1113 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_stress_all.3284770136 |
|
|
Feb 08 01:14:08 PM UTC 25 |
Feb 08 01:21:30 PM UTC 25 |
67458839641 ps |
| T1114 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_stretch_timeout.684048901 |
|
|
Feb 08 01:20:45 PM UTC 25 |
Feb 08 01:21:31 PM UTC 25 |
4322868251 ps |
| T1115 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_acq.3934711552 |
|
|
Feb 08 01:21:29 PM UTC 25 |
Feb 08 01:21:32 PM UTC 25 |
140125315 ps |
| T1116 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_full.2115564754 |
|
|
Feb 08 01:20:39 PM UTC 25 |
Feb 08 01:21:32 PM UTC 25 |
12997274866 ps |
| T1117 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_tx.686195740 |
|
|
Feb 08 01:21:30 PM UTC 25 |
Feb 08 01:21:33 PM UTC 25 |
264905580 ps |
| T1118 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_stretch.2316512037 |
|
|
Feb 08 01:21:26 PM UTC 25 |
Feb 08 01:21:36 PM UTC 25 |
2887497203 ps |
| T117 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_watermark.1383166428 |
|
|
Feb 08 01:19:02 PM UTC 25 |
Feb 08 01:21:37 PM UTC 25 |
10875150173 ps |
| T1119 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_timeout.3162089646 |
|
|
Feb 08 01:21:27 PM UTC 25 |
Feb 08 01:21:37 PM UTC 25 |
5547496648 ps |
| T1120 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_intr_smoke.365468056 |
|
|
Feb 08 01:21:27 PM UTC 25 |
Feb 08 01:21:38 PM UTC 25 |
1029863621 ps |
| T1121 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_hrst.2166875255 |
|
|
Feb 08 01:21:33 PM UTC 25 |
Feb 08 01:21:39 PM UTC 25 |
986162257 ps |
| T1122 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_tx_stretch_ctrl.2762081565 |
|
|
Feb 08 01:21:39 PM UTC 25 |
Feb 08 01:21:43 PM UTC 25 |
74268918 ps |
| T1123 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_alert_test.1839345304 |
|
|
Feb 08 01:21:41 PM UTC 25 |
Feb 08 01:21:44 PM UTC 25 |
38821817 ps |
| T1124 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_intr_stress_wr.3484827451 |
|
|
Feb 08 01:21:27 PM UTC 25 |
Feb 08 01:21:44 PM UTC 25 |
7652671131 ps |
| T1125 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_may_nack.4128887369 |
|
|
Feb 08 01:21:37 PM UTC 25 |
Feb 08 01:21:44 PM UTC 25 |
738482444 ps |
| T1126 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_acq.4032635890 |
|
|
Feb 08 01:21:38 PM UTC 25 |
Feb 08 01:21:44 PM UTC 25 |
2307666512 ps |
| T1127 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_nack_txstretch.1834027549 |
|
|
Feb 08 01:21:41 PM UTC 25 |
Feb 08 01:21:45 PM UTC 25 |
145461351 ps |
| T1128 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_stress_wr.4156799943 |
|
|
Feb 08 01:21:25 PM UTC 25 |
Feb 08 01:21:45 PM UTC 25 |
10947946775 ps |
| T1129 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_smbus_maxlen.744800734 |
|
|
Feb 08 01:21:40 PM UTC 25 |
Feb 08 01:21:45 PM UTC 25 |
1719716704 ps |
| T1130 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull_addr.3764590233 |
|
|
Feb 08 01:21:40 PM UTC 25 |
Feb 08 01:21:45 PM UTC 25 |
392878235 ps |
| T1131 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull.3554732044 |
|
|
Feb 08 01:21:40 PM UTC 25 |
Feb 08 01:21:46 PM UTC 25 |
2446868939 ps |
| T1132 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_override.3036817958 |
|
|
Feb 08 01:21:44 PM UTC 25 |
Feb 08 01:21:46 PM UTC 25 |
21015624 ps |
| T244 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_fmt.362185198 |
|
|
Feb 08 01:21:46 PM UTC 25 |
Feb 08 01:21:48 PM UTC 25 |
242463048 ps |
| T1133 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_smoke.882771984 |
|
|
Feb 08 01:21:21 PM UTC 25 |
Feb 08 01:21:49 PM UTC 25 |
13640864549 ps |
| T1134 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_smoke.707783963 |
|
|
Feb 08 01:21:14 PM UTC 25 |
Feb 08 01:21:49 PM UTC 25 |
10139923701 ps |
| T1135 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_perf_precise.4171113895 |
|
|
Feb 08 01:21:47 PM UTC 25 |
Feb 08 01:21:50 PM UTC 25 |
55772803 ps |
| T1136 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_stretch_timeout.550422423 |
|
|
Feb 08 01:21:18 PM UTC 25 |
Feb 08 01:21:50 PM UTC 25 |
3607763981 ps |
| T1137 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_fmt_empty.2281139307 |
|
|
Feb 08 01:21:46 PM UTC 25 |
Feb 08 01:21:53 PM UTC 25 |
536715375 ps |
| T1138 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_rx.215341615 |
|
|
Feb 08 01:21:46 PM UTC 25 |
Feb 08 01:21:53 PM UTC 25 |
769365625 ps |
| T1139 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_error_intr.2211270391 |
|
|
Feb 08 01:21:49 PM UTC 25 |
Feb 08 01:21:53 PM UTC 25 |
243671819 ps |
| T1140 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_overflow.513390572 |
|
|
Feb 08 01:21:16 PM UTC 25 |
Feb 08 01:21:56 PM UTC 25 |
6335741592 ps |
| T1141 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_full.3036055413 |
|
|
Feb 08 01:19:46 PM UTC 25 |
Feb 08 01:21:57 PM UTC 25 |
3235801220 ps |
| T1142 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_stretch.2730981719 |
|
|
Feb 08 01:21:53 PM UTC 25 |
Feb 08 01:21:57 PM UTC 25 |
1345691261 ps |
| T1143 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_smoke.457739203 |
|
|
Feb 08 01:21:50 PM UTC 25 |
Feb 08 01:22:00 PM UTC 25 |
1148012324 ps |
| T1144 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_acq.785142173 |
|
|
Feb 08 01:21:58 PM UTC 25 |
Feb 08 01:22:01 PM UTC 25 |
163085095 ps |
| T1145 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_stretch_timeout.1361083992 |
|
|
Feb 08 01:21:47 PM UTC 25 |
Feb 08 01:22:01 PM UTC 25 |
619386707 ps |
| T1146 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_tx.1689478203 |
|
|
Feb 08 01:22:01 PM UTC 25 |
Feb 08 01:22:03 PM UTC 25 |
187937512 ps |
| T1147 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_stress_wr.752341892 |
|
|
Feb 08 01:19:10 PM UTC 25 |
Feb 08 01:22:05 PM UTC 25 |
48345320853 ps |
| T1148 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_timeout.4174704457 |
|
|
Feb 08 01:21:57 PM UTC 25 |
Feb 08 01:22:06 PM UTC 25 |
4332586126 ps |
| T1149 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_perf.3354929760 |
|
|
Feb 08 01:22:01 PM UTC 25 |
Feb 08 01:22:07 PM UTC 25 |
505994327 ps |
| T1150 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_intr_smoke.1907271909 |
|
|
Feb 08 01:21:54 PM UTC 25 |
Feb 08 01:22:07 PM UTC 25 |
1432189136 ps |
| T1151 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_intr_stress_wr.1864802302 |
|
|
Feb 08 01:19:19 PM UTC 25 |
Feb 08 01:22:09 PM UTC 25 |
14159450336 ps |
| T1152 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_mode_toggle.3433904834 |
|
|
Feb 08 01:22:06 PM UTC 25 |
Feb 08 01:22:09 PM UTC 25 |
223495762 ps |
| T1153 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_hrst.2164969450 |
|
|
Feb 08 01:22:04 PM UTC 25 |
Feb 08 01:22:09 PM UTC 25 |
2819659777 ps |
| T1154 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_bad_addr.3712231025 |
|
|
Feb 08 01:22:02 PM UTC 25 |
Feb 08 01:22:10 PM UTC 25 |
933780207 ps |
| T1155 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_tx.1308052916 |
|
|
Feb 08 01:22:07 PM UTC 25 |
Feb 08 01:22:10 PM UTC 25 |
83559205 ps |
| T1156 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_stress_rd.4267901182 |
|
|
Feb 08 01:21:51 PM UTC 25 |
Feb 08 01:22:12 PM UTC 25 |
781377825 ps |
| T1157 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_acq.2088838963 |
|
|
Feb 08 01:22:07 PM UTC 25 |
Feb 08 01:22:12 PM UTC 25 |
414232271 ps |
| T1158 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_alert_test.1754594924 |
|
|
Feb 08 01:22:11 PM UTC 25 |
Feb 08 01:22:13 PM UTC 25 |
44745913 ps |
| T1159 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_tx_stretch_ctrl.587242976 |
|
|
Feb 08 01:22:09 PM UTC 25 |
Feb 08 01:22:14 PM UTC 25 |
246759008 ps |
| T1160 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_nack_txstretch.3238656561 |
|
|
Feb 08 01:22:11 PM UTC 25 |
Feb 08 01:22:14 PM UTC 25 |
142166615 ps |
| T1161 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_smbus_maxlen.1672991881 |
|
|
Feb 08 01:22:10 PM UTC 25 |
Feb 08 01:22:15 PM UTC 25 |
567795932 ps |
| T118 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_watermark.3946834357 |
|
|
Feb 08 01:20:36 PM UTC 25 |
Feb 08 01:22:15 PM UTC 25 |
4059266849 ps |
| T1162 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull.3561414375 |
|
|
Feb 08 01:22:10 PM UTC 25 |
Feb 08 01:22:15 PM UTC 25 |
569922542 ps |
| T1163 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull_addr.1565643233 |
|
|
Feb 08 01:22:10 PM UTC 25 |
Feb 08 01:22:15 PM UTC 25 |
1099681667 ps |
| T147 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_override.3158648530 |
|
|
Feb 08 01:22:13 PM UTC 25 |
Feb 08 01:22:16 PM UTC 25 |
19633564 ps |
| T1164 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_fmt.1052808936 |
|
|
Feb 08 01:22:15 PM UTC 25 |
Feb 08 01:22:18 PM UTC 25 |
605429259 ps |
| T1165 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_smoke.3097098254 |
|
|
Feb 08 01:21:44 PM UTC 25 |
Feb 08 01:22:18 PM UTC 25 |
8561205880 ps |
| T1166 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_stress_rd.1677376660 |
|
|
Feb 08 01:21:26 PM UTC 25 |
Feb 08 01:22:21 PM UTC 25 |
5344453562 ps |
| T1167 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_perf.111952589 |
|
|
Feb 08 01:22:17 PM UTC 25 |
Feb 08 01:22:23 PM UTC 25 |
879631676 ps |
| T1168 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_error_intr.3584995955 |
|
|
Feb 08 01:22:19 PM UTC 25 |
Feb 08 01:22:24 PM UTC 25 |
940435764 ps |
| T1169 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_rx.1009662517 |
|
|
Feb 08 01:22:16 PM UTC 25 |
Feb 08 01:22:26 PM UTC 25 |
148124812 ps |
| T1170 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_perf_precise.3210789532 |
|
|
Feb 08 01:22:17 PM UTC 25 |
Feb 08 01:22:31 PM UTC 25 |
3364527258 ps |
| T1171 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_may_nack.4263178765 |
|
|
Feb 08 01:22:06 PM UTC 25 |
Feb 08 01:22:31 PM UTC 25 |
1231621479 ps |
| T1172 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_intr_stress_wr.3394417912 |
|
|
Feb 08 01:21:55 PM UTC 25 |
Feb 08 01:22:37 PM UTC 25 |
22726991624 ps |
| T1173 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_fmt_empty.3831415086 |
|
|
Feb 08 01:22:16 PM UTC 25 |
Feb 08 01:22:41 PM UTC 25 |
473737731 ps |
| T1174 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_overflow.993220200 |
|
|
Feb 08 01:21:46 PM UTC 25 |
Feb 08 01:22:43 PM UTC 25 |
1870033082 ps |
| T86 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_smoke.1200017220 |
|
|
Feb 08 01:22:24 PM UTC 25 |
Feb 08 01:22:43 PM UTC 25 |
4130631037 ps |
| T1175 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_intr_smoke.3506853588 |
|
|
Feb 08 01:22:32 PM UTC 25 |
Feb 08 01:22:44 PM UTC 25 |
1137282328 ps |
| T1176 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_tx.344460132 |
|
|
Feb 08 01:22:45 PM UTC 25 |
Feb 08 01:22:47 PM UTC 25 |
200193309 ps |
| T1177 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_stress_rd.53086433 |
|
|
Feb 08 01:22:27 PM UTC 25 |
Feb 08 01:22:47 PM UTC 25 |
1815108527 ps |
| T1178 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_acq.885642951 |
|
|
Feb 08 01:22:45 PM UTC 25 |
Feb 08 01:22:48 PM UTC 25 |
1990142307 ps |
| T1179 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_hrst.2384623517 |
|
|
Feb 08 01:22:48 PM UTC 25 |
Feb 08 01:22:52 PM UTC 25 |
220890824 ps |
| T1180 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_timeout.2450456372 |
|
|
Feb 08 01:22:41 PM UTC 25 |
Feb 08 01:22:52 PM UTC 25 |
1182299634 ps |
| T1181 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_smoke.1858068760 |
|
|
Feb 08 01:22:12 PM UTC 25 |
Feb 08 01:22:53 PM UTC 25 |
2058167536 ps |
| T1182 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_bad_addr.2018446534 |
|
|
Feb 08 01:22:48 PM UTC 25 |
Feb 08 01:22:53 PM UTC 25 |
2036318034 ps |
| T1183 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_perf.733867772 |
|
|
Feb 08 01:22:46 PM UTC 25 |
Feb 08 01:22:55 PM UTC 25 |
874161413 ps |
| T1184 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_acq.4226186815 |
|
|
Feb 08 01:22:52 PM UTC 25 |
Feb 08 01:22:55 PM UTC 25 |
4336421023 ps |
| T1185 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_may_nack.2998364527 |
|
|
Feb 08 01:22:50 PM UTC 25 |
Feb 08 01:22:56 PM UTC 25 |
940223165 ps |
| T1186 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_tx.2668953718 |
|
|
Feb 08 01:22:53 PM UTC 25 |
Feb 08 01:22:56 PM UTC 25 |
483846900 ps |
| T1187 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_tx_stretch_ctrl.2471654243 |
|
|
Feb 08 01:22:54 PM UTC 25 |
Feb 08 01:22:58 PM UTC 25 |
173324078 ps |
| T1188 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull.3577522500 |
|
|
Feb 08 01:22:54 PM UTC 25 |
Feb 08 01:22:59 PM UTC 25 |
1581221394 ps |
| T1189 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_nack_txstretch.1884794430 |
|
|
Feb 08 01:22:56 PM UTC 25 |
Feb 08 01:22:59 PM UTC 25 |
620538684 ps |
| T1190 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_alert_test.1580535003 |
|
|
Feb 08 01:22:57 PM UTC 25 |
Feb 08 01:22:59 PM UTC 25 |
39999183 ps |
| T1191 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_override.3414461555 |
|
|
Feb 08 01:22:57 PM UTC 25 |
Feb 08 01:22:59 PM UTC 25 |
89833142 ps |
| T1192 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_smbus_maxlen.3454865015 |
|
|
Feb 08 01:22:54 PM UTC 25 |
Feb 08 01:22:59 PM UTC 25 |
1024268185 ps |
| T1193 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_full.3594535885 |
|
|
Feb 08 01:21:46 PM UTC 25 |
Feb 08 01:23:00 PM UTC 25 |
8006244361 ps |
| T1194 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull_addr.3371741167 |
|
|
Feb 08 01:22:56 PM UTC 25 |
Feb 08 01:23:01 PM UTC 25 |
1805411756 ps |
| T1195 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_fmt.2439878037 |
|
|
Feb 08 01:23:00 PM UTC 25 |
Feb 08 01:23:03 PM UTC 25 |
141012588 ps |
| T1196 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_stretch_timeout.2294428336 |
|
|
Feb 08 01:22:19 PM UTC 25 |
Feb 08 01:23:03 PM UTC 25 |
3890308312 ps |
| T1197 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_perf_precise.115814917 |
|
|
Feb 08 01:23:02 PM UTC 25 |
Feb 08 01:23:07 PM UTC 25 |
275820915 ps |
| T1198 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_error_intr.4260568052 |
|
|
Feb 08 01:23:04 PM UTC 25 |
Feb 08 01:23:08 PM UTC 25 |
131127301 ps |
| T1199 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_rx.789919042 |
|
|
Feb 08 01:23:00 PM UTC 25 |
Feb 08 01:23:09 PM UTC 25 |
245584817 ps |
| T1200 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_overflow.891871362 |
|
|
Feb 08 01:20:37 PM UTC 25 |
Feb 08 01:23:15 PM UTC 25 |
17347532313 ps |
| T1201 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_stretch_timeout.4186658242 |
|
|
Feb 08 01:23:04 PM UTC 25 |
Feb 08 01:23:18 PM UTC 25 |
950738764 ps |
| T1202 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_fmt_empty.3908187206 |
|
|
Feb 08 01:23:00 PM UTC 25 |
Feb 08 01:23:18 PM UTC 25 |
1028603551 ps |
| T1203 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_smoke.2240983233 |
|
|
Feb 08 01:23:09 PM UTC 25 |
Feb 08 01:23:22 PM UTC 25 |
3302373969 ps |
| T1204 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_perf.3739121710 |
|
|
Feb 08 01:23:02 PM UTC 25 |
Feb 08 01:23:24 PM UTC 25 |
1252414683 ps |
| T1205 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_intr_stress_wr.2058173011 |
|
|
Feb 08 01:14:39 PM UTC 25 |
Feb 08 01:23:24 PM UTC 25 |
19414987312 ps |
| T1206 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_stretch.2175800533 |
|
|
Feb 08 01:23:18 PM UTC 25 |
Feb 08 01:23:28 PM UTC 25 |
489584745 ps |
| T1207 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_intr_smoke.1194991919 |
|
|
Feb 08 01:23:18 PM UTC 25 |
Feb 08 01:23:32 PM UTC 25 |
1409600846 ps |
| T1208 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_acq.1559824178 |
|
|
Feb 08 01:23:29 PM UTC 25 |
Feb 08 01:23:32 PM UTC 25 |
312428647 ps |
| T1209 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_tx.688116360 |
|
|
Feb 08 01:23:29 PM UTC 25 |
Feb 08 01:23:33 PM UTC 25 |
278747410 ps |
| T1210 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_overflow.791344692 |
|
|
Feb 08 01:22:14 PM UTC 25 |
Feb 08 01:23:36 PM UTC 25 |
2436744607 ps |
| T1211 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_perf.2615109377 |
|
|
Feb 08 01:23:33 PM UTC 25 |
Feb 08 01:23:39 PM UTC 25 |
648807418 ps |
| T1212 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_timeout.2686618612 |
|
|
Feb 08 01:23:25 PM UTC 25 |
Feb 08 01:23:39 PM UTC 25 |
5427491365 ps |
| T1213 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_bad_addr.3652470019 |
|
|
Feb 08 01:23:34 PM UTC 25 |
Feb 08 01:23:40 PM UTC 25 |
2667574488 ps |
| T1214 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_hrst.334281893 |
|
|
Feb 08 01:23:37 PM UTC 25 |
Feb 08 01:23:41 PM UTC 25 |
272357750 ps |
| T1215 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_stress_rd.3173532563 |
|
|
Feb 08 01:23:16 PM UTC 25 |
Feb 08 01:23:42 PM UTC 25 |
2575504026 ps |
| T1216 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_tx.1543448197 |
|
|
Feb 08 01:23:42 PM UTC 25 |
Feb 08 01:23:45 PM UTC 25 |
602955992 ps |
| T1217 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_may_nack.566552113 |
|
|
Feb 08 01:23:40 PM UTC 25 |
Feb 08 01:23:48 PM UTC 25 |
331527485 ps |
| T1218 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_acq.2891894573 |
|
|
Feb 08 01:23:41 PM UTC 25 |
Feb 08 01:23:48 PM UTC 25 |
941670950 ps |
| T1219 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_full.56422023 |
|
|
Feb 08 01:22:17 PM UTC 25 |
Feb 08 01:23:49 PM UTC 25 |
7713420386 ps |
| T1220 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_smbus_maxlen.275598268 |
|
|
Feb 08 01:23:44 PM UTC 25 |
Feb 08 01:23:49 PM UTC 25 |
1223505119 ps |
| T1221 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_alert_test.3009393867 |
|
|
Feb 08 01:23:48 PM UTC 25 |
Feb 08 01:23:51 PM UTC 25 |
90433204 ps |
| T1222 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull.379497732 |
|
|
Feb 08 01:23:45 PM UTC 25 |
Feb 08 01:23:51 PM UTC 25 |
7585196840 ps |
| T1223 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_nack_txstretch.3989547308 |
|
|
Feb 08 01:23:48 PM UTC 25 |
Feb 08 01:23:51 PM UTC 25 |
506588218 ps |
| T1224 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull_addr.2475529241 |
|
|
Feb 08 01:23:46 PM UTC 25 |
Feb 08 01:23:52 PM UTC 25 |
511471969 ps |
| T1225 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_stress_all.1884571630 |
|
|
Feb 08 01:22:47 PM UTC 25 |
Feb 08 01:23:53 PM UTC 25 |
41080245136 ps |
| T1226 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_override.3163211991 |
|
|
Feb 08 01:23:51 PM UTC 25 |
Feb 08 01:23:53 PM UTC 25 |
31902806 ps |
| T1227 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_tx_stretch_ctrl.27102947 |
|
|
Feb 08 01:23:43 PM UTC 25 |
Feb 08 01:23:54 PM UTC 25 |
515333283 ps |
| T1228 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_fmt.2838911874 |
|
|
Feb 08 01:23:53 PM UTC 25 |
Feb 08 01:23:56 PM UTC 25 |
143173957 ps |
| T1229 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.2350854889 |
|
|
Feb 08 01:21:50 PM UTC 25 |
Feb 08 01:23:58 PM UTC 25 |
28734060489 ps |
| T1230 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_fmt_empty.3743488478 |
|
|
Feb 08 01:23:53 PM UTC 25 |
Feb 08 01:23:59 PM UTC 25 |
806501094 ps |
| T1231 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_rx.2621513427 |
|
|
Feb 08 01:23:54 PM UTC 25 |
Feb 08 01:24:04 PM UTC 25 |
734966019 ps |
| T1232 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_smoke.3561125697 |
|
|
Feb 08 01:22:57 PM UTC 25 |
Feb 08 01:24:09 PM UTC 25 |
1305665657 ps |
| T1233 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_error_intr.1294251457 |
|
|
Feb 08 01:24:00 PM UTC 25 |
Feb 08 01:24:13 PM UTC 25 |
519455063 ps |
| T1234 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_stretch_timeout.1029672591 |
|
|
Feb 08 01:23:59 PM UTC 25 |
Feb 08 01:24:22 PM UTC 25 |
3482145749 ps |
| T1235 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_smoke.874014084 |
|
|
Feb 08 01:24:10 PM UTC 25 |
Feb 08 01:24:23 PM UTC 25 |
1119276353 ps |
| T1236 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_stress_wr.1511748909 |
|
|
Feb 08 01:22:25 PM UTC 25 |
Feb 08 01:24:25 PM UTC 25 |
26900910280 ps |
| T1237 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_smoke.2433844946 |
|
|
Feb 08 01:23:50 PM UTC 25 |
Feb 08 01:24:27 PM UTC 25 |
1558407985 ps |
| T1238 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_intr_smoke.1903915995 |
|
|
Feb 08 01:24:24 PM UTC 25 |
Feb 08 01:24:32 PM UTC 25 |
3123900199 ps |
| T1239 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_timeout.2853119524 |
|
|
Feb 08 01:24:27 PM UTC 25 |
Feb 08 01:24:36 PM UTC 25 |
1363466224 ps |
| T1240 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_acq.3559053833 |
|
|
Feb 08 01:24:36 PM UTC 25 |
Feb 08 01:24:39 PM UTC 25 |
167106994 ps |
| T1241 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_tx.2545074060 |
|
|
Feb 08 01:24:37 PM UTC 25 |
Feb 08 01:24:40 PM UTC 25 |
641278408 ps |
| T1242 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_stretch.853628136 |
|
|
Feb 08 01:24:23 PM UTC 25 |
Feb 08 01:24:42 PM UTC 25 |
3997311509 ps |
| T1243 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_watermark.2405906010 |
|
|
Feb 08 01:22:14 PM UTC 25 |
Feb 08 01:24:43 PM UTC 25 |
4608386122 ps |
| T1244 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_stress_wr.329982946 |
|
|
Feb 08 01:20:00 PM UTC 25 |
Feb 08 01:24:44 PM UTC 25 |
56711140279 ps |
| T1245 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_stress_all.2441516682 |
|
|
Feb 08 01:23:33 PM UTC 25 |
Feb 08 01:24:48 PM UTC 25 |
8164711896 ps |
| T1246 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_intr_stress_wr.2833622112 |
|
|
Feb 08 01:15:40 PM UTC 25 |
Feb 08 01:24:48 PM UTC 25 |
21333658384 ps |
| T1247 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_stress_rd.1124961322 |
|
|
Feb 08 01:24:19 PM UTC 25 |
Feb 08 01:24:51 PM UTC 25 |
609616135 ps |
| T1248 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_perf.1750422273 |
|
|
Feb 08 01:24:41 PM UTC 25 |
Feb 08 01:24:51 PM UTC 25 |
948600886 ps |
| T1249 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_full.1245728812 |
|
|
Feb 08 01:23:00 PM UTC 25 |
Feb 08 01:24:52 PM UTC 25 |
1741341763 ps |
| T1250 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_bad_addr.35351458 |
|
|
Feb 08 01:24:43 PM UTC 25 |
Feb 08 01:24:52 PM UTC 25 |
9456678052 ps |
| T1251 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_tx.3484929669 |
|
|
Feb 08 01:24:52 PM UTC 25 |
Feb 08 01:24:55 PM UTC 25 |
299992721 ps |
| T1252 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_acq.748596491 |
|
|
Feb 08 01:24:49 PM UTC 25 |
Feb 08 01:24:55 PM UTC 25 |
1089790173 ps |
| T1253 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_tx_stretch_ctrl.3042262963 |
|
|
Feb 08 01:24:52 PM UTC 25 |
Feb 08 01:24:56 PM UTC 25 |
135908648 ps |
| T1254 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_smbus_maxlen.3639277959 |
|
|
Feb 08 01:24:53 PM UTC 25 |
Feb 08 01:24:57 PM UTC 25 |
379847836 ps |
| T1255 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull.4112512008 |
|
|
Feb 08 01:24:53 PM UTC 25 |
Feb 08 01:24:58 PM UTC 25 |
488704173 ps |
| T76 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_mode_toggle.2559140597 |
|
|
Feb 08 01:24:45 PM UTC 25 |
Feb 08 01:24:59 PM UTC 25 |
976383516 ps |
| T1256 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_alert_test.1397425673 |
|
|
Feb 08 01:24:57 PM UTC 25 |
Feb 08 01:25:00 PM UTC 25 |
40145616 ps |
| T1257 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_nack_txstretch.1732379974 |
|
|
Feb 08 01:24:56 PM UTC 25 |
Feb 08 01:25:00 PM UTC 25 |
129754318 ps |
| T1258 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_override.2420411360 |
|
|
Feb 08 01:24:59 PM UTC 25 |
Feb 08 01:25:01 PM UTC 25 |
23155418 ps |
| T1259 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull_addr.2721757290 |
|
|
Feb 08 01:24:56 PM UTC 25 |
Feb 08 01:25:01 PM UTC 25 |
4431519390 ps |
| T1260 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_full.1961945099 |
|
|
Feb 08 01:21:17 PM UTC 25 |
Feb 08 01:25:02 PM UTC 25 |
17105674965 ps |
| T1261 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_perf_precise.1411561797 |
|
|
Feb 08 01:23:56 PM UTC 25 |
Feb 08 01:25:03 PM UTC 25 |
6274864927 ps |
| T1262 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_fmt.4133207418 |
|
|
Feb 08 01:25:01 PM UTC 25 |
Feb 08 01:25:03 PM UTC 25 |
208252601 ps |
| T1263 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_may_nack.1186426585 |
|
|
Feb 08 01:24:49 PM UTC 25 |
Feb 08 01:25:06 PM UTC 25 |
409585867 ps |
| T1264 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_perf.1021282292 |
|
|
Feb 08 01:18:22 PM UTC 25 |
Feb 08 01:25:06 PM UTC 25 |
5310340214 ps |
| T1265 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_full.2154512192 |
|
|
Feb 08 01:23:54 PM UTC 25 |
Feb 08 01:25:07 PM UTC 25 |
1956472645 ps |
| T1266 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_rx.1902826853 |
|
|
Feb 08 01:25:02 PM UTC 25 |
Feb 08 01:25:08 PM UTC 25 |
404466675 ps |
| T1267 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_fmt_empty.4282623522 |
|
|
Feb 08 01:25:02 PM UTC 25 |
Feb 08 01:25:11 PM UTC 25 |
1373669060 ps |
| T24 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_error_intr.2895801257 |
|
|
Feb 08 01:25:07 PM UTC 25 |
Feb 08 01:25:12 PM UTC 25 |
1253240532 ps |
| T1268 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_perf_precise.2154752990 |
|
|
Feb 08 01:25:04 PM UTC 25 |
Feb 08 01:25:15 PM UTC 25 |
731573671 ps |
| T1269 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_watermark.279790485 |
|
|
Feb 08 01:21:44 PM UTC 25 |
Feb 08 01:25:19 PM UTC 25 |
5426911289 ps |
| T1270 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_intr_stress_wr.3511808833 |
|
|
Feb 08 01:24:26 PM UTC 25 |
Feb 08 01:25:20 PM UTC 25 |
4652573278 ps |
| T1271 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_bad_addr.2055395620 |
|
|
Feb 08 01:26:53 PM UTC 25 |
Feb 08 01:27:00 PM UTC 25 |
3803535543 ps |
| T1272 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_intr_smoke.2312208938 |
|
|
Feb 08 01:25:16 PM UTC 25 |
Feb 08 01:25:24 PM UTC 25 |
945367977 ps |
| T1273 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_smoke.1882629571 |
|
|
Feb 08 01:24:58 PM UTC 25 |
Feb 08 01:25:26 PM UTC 25 |
1159849125 ps |
| T1274 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_smoke.2569805442 |
|
|
Feb 08 01:25:09 PM UTC 25 |
Feb 08 01:25:26 PM UTC 25 |
554002392 ps |
| T1275 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_acq.2122249848 |
|
|
Feb 08 01:25:25 PM UTC 25 |
Feb 08 01:25:28 PM UTC 25 |
175209261 ps |
| T1276 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_timeout.2361737089 |
|
|
Feb 08 01:25:20 PM UTC 25 |
Feb 08 01:25:28 PM UTC 25 |
2205684485 ps |
| T1277 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_tx.3897611327 |
|
|
Feb 08 01:25:25 PM UTC 25 |
Feb 08 01:25:28 PM UTC 25 |
625285091 ps |
| T1278 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_stretch_timeout.4007980329 |
|
|
Feb 08 01:25:06 PM UTC 25 |
Feb 08 01:25:30 PM UTC 25 |
3049067927 ps |
| T1279 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_intr_stress_wr.3341515815 |
|
|
Feb 08 01:22:38 PM UTC 25 |
Feb 08 01:25:31 PM UTC 25 |
15729000835 ps |
| T1280 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_stress_all.2688303657 |
|
|
Feb 08 01:17:17 PM UTC 25 |
Feb 08 01:25:31 PM UTC 25 |
40675005199 ps |
| T1281 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_tx.2573860439 |
|
|
Feb 08 01:25:32 PM UTC 25 |
Feb 08 01:25:35 PM UTC 25 |
160035086 ps |
| T1282 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_perf.1870578231 |
|
|
Feb 08 01:25:27 PM UTC 25 |
Feb 08 01:25:36 PM UTC 25 |
720817759 ps |
| T1283 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_perf.3110406671 |
|
|
Feb 08 01:25:04 PM UTC 25 |
Feb 08 01:25:37 PM UTC 25 |
2685941735 ps |
| T1284 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_acq.538549526 |
|
|
Feb 08 01:25:32 PM UTC 25 |
Feb 08 01:25:38 PM UTC 25 |
522071547 ps |
| T1285 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_bad_addr.17288203 |
|
|
Feb 08 01:25:29 PM UTC 25 |
Feb 08 01:25:41 PM UTC 25 |
4852642605 ps |
| T1286 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_stress_wr.3660153702 |
|
|
Feb 08 01:24:15 PM UTC 25 |
Feb 08 01:25:41 PM UTC 25 |
36686564860 ps |
| T1287 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_smbus_maxlen.2992236379 |
|
|
Feb 08 01:25:36 PM UTC 25 |
Feb 08 01:25:41 PM UTC 25 |
2004265331 ps |
| T1288 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_may_nack.948772491 |
|
|
Feb 08 01:25:31 PM UTC 25 |
Feb 08 01:25:42 PM UTC 25 |
2555361479 ps |
| T1289 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull.3563812262 |
|
|
Feb 08 01:25:37 PM UTC 25 |
Feb 08 01:25:42 PM UTC 25 |
1852436265 ps |
| T1290 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_perf.833680481 |
|
|
Feb 08 01:26:50 PM UTC 25 |
Feb 08 01:26:57 PM UTC 25 |
1065282227 ps |
| T1291 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull_addr.1590558084 |
|
|
Feb 08 01:25:38 PM UTC 25 |
Feb 08 01:25:43 PM UTC 25 |
3846716402 ps |
| T1292 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_overflow.512512506 |
|
|
Feb 08 01:23:52 PM UTC 25 |
Feb 08 01:25:43 PM UTC 25 |
4601630431 ps |
| T1293 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_tx_stretch_ctrl.1426961995 |
|
|
Feb 08 01:25:36 PM UTC 25 |
Feb 08 01:25:44 PM UTC 25 |
276535842 ps |
| T1294 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_alert_test.1408727373 |
|
|
Feb 08 01:25:41 PM UTC 25 |
Feb 08 01:25:44 PM UTC 25 |
15825807 ps |
| T1295 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_stress_rd.607390688 |
|
|
Feb 08 01:25:13 PM UTC 25 |
Feb 08 01:25:44 PM UTC 25 |
3496832482 ps |
| T1296 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_override.3533009474 |
|
|
Feb 08 01:25:43 PM UTC 25 |
Feb 08 01:25:45 PM UTC 25 |
50982493 ps |
| T1297 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_fmt.3995915033 |
|
|
Feb 08 01:25:44 PM UTC 25 |
Feb 08 01:25:46 PM UTC 25 |
76621577 ps |
| T1298 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_perf_precise.460759671 |
|
|
Feb 08 01:25:45 PM UTC 25 |
Feb 08 01:25:49 PM UTC 25 |
70555515 ps |
| T1299 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_error_intr.551305513 |
|
|
Feb 08 01:25:46 PM UTC 25 |
Feb 08 01:25:50 PM UTC 25 |
131105902 ps |
| T1300 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_stretch.360485426 |
|
|
Feb 08 01:25:14 PM UTC 25 |
Feb 08 01:25:54 PM UTC 25 |
4925187880 ps |
| T1301 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_rx.2296893725 |
|
|
Feb 08 01:25:44 PM UTC 25 |
Feb 08 01:25:57 PM UTC 25 |
320016006 ps |
| T1302 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_overflow.548023378 |
|
|
Feb 08 01:22:59 PM UTC 25 |
Feb 08 01:26:01 PM UTC 25 |
9244455276 ps |
| T1303 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_fmt_empty.1886584873 |
|
|
Feb 08 01:25:44 PM UTC 25 |
Feb 08 01:26:01 PM UTC 25 |
330327645 ps |
| T1304 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_stress_all.1234298892 |
|
|
Feb 08 01:14:52 PM UTC 25 |
Feb 08 01:26:02 PM UTC 25 |
53744917908 ps |
| T1305 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_smoke.1181523294 |
|
|
Feb 08 01:25:49 PM UTC 25 |
Feb 08 01:26:02 PM UTC 25 |
676713047 ps |
| T1306 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_stretch_timeout.3243867713 |
|
|
Feb 08 01:25:46 PM UTC 25 |
Feb 08 01:26:03 PM UTC 25 |
3176859120 ps |
| T1307 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_acq.913423276 |
|
|
Feb 08 01:26:04 PM UTC 25 |
Feb 08 01:26:08 PM UTC 25 |
509253060 ps |
| T1308 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_tx.2367842602 |
|
|
Feb 08 01:26:07 PM UTC 25 |
Feb 08 01:26:11 PM UTC 25 |
291519113 ps |
| T1309 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_timeout.3247618637 |
|
|
Feb 08 01:26:03 PM UTC 25 |
Feb 08 01:26:11 PM UTC 25 |
12694743822 ps |
| T1310 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_intr_smoke.1100527545 |
|
|
Feb 08 01:26:02 PM UTC 25 |
Feb 08 01:26:13 PM UTC 25 |
4572498719 ps |
| T1311 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_stress_all.1435902214 |
|
|
Feb 08 01:21:02 PM UTC 25 |
Feb 08 01:26:14 PM UTC 25 |
67736012528 ps |
| T269 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_stress_all.3306780287 |
|
|
Feb 08 01:22:02 PM UTC 25 |
Feb 08 01:26:17 PM UTC 25 |
62432932215 ps |
| T1312 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_stress_all.2556297964 |
|
|
Feb 08 01:19:31 PM UTC 25 |
Feb 08 01:26:17 PM UTC 25 |
25379376376 ps |
| T1313 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_perf.1796559665 |
|
|
Feb 08 01:26:09 PM UTC 25 |
Feb 08 01:26:19 PM UTC 25 |
6876380721 ps |
| T1314 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_bad_addr.3387630047 |
|
|
Feb 08 01:26:12 PM UTC 25 |
Feb 08 01:26:19 PM UTC 25 |
8286631632 ps |
| T1315 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_tx.3282129740 |
|
|
Feb 08 01:26:18 PM UTC 25 |
Feb 08 01:26:21 PM UTC 25 |
109035301 ps |
| T1316 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_acq.2205765893 |
|
|
Feb 08 01:26:17 PM UTC 25 |
Feb 08 01:26:22 PM UTC 25 |
2505874092 ps |
| T1317 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_stress_wr.4081928508 |
|
|
Feb 08 01:25:11 PM UTC 25 |
Feb 08 01:26:22 PM UTC 25 |
22973315907 ps |
| T1318 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_smoke.457927490 |
|
|
Feb 08 01:25:42 PM UTC 25 |
Feb 08 01:26:23 PM UTC 25 |
9503681043 ps |
| T1319 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_smbus_maxlen.3505752064 |
|
|
Feb 08 01:26:20 PM UTC 25 |
Feb 08 01:26:24 PM UTC 25 |
503814128 ps |
| T1320 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_tx_stretch_ctrl.3565773908 |
|
|
Feb 08 01:26:19 PM UTC 25 |
Feb 08 01:26:25 PM UTC 25 |
213989687 ps |
| T1321 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_alert_test.1957265660 |
|
|
Feb 08 01:26:23 PM UTC 25 |
Feb 08 01:26:25 PM UTC 25 |
43276746 ps |