| T1322 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_tx.1625229225 |
|
|
Feb 08 01:26:57 PM UTC 25 |
Feb 08 01:27:00 PM UTC 25 |
339283290 ps |
| T1323 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull_addr.3157616337 |
|
|
Feb 08 01:26:22 PM UTC 25 |
Feb 08 01:26:26 PM UTC 25 |
833588448 ps |
| T1324 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull.2444182389 |
|
|
Feb 08 01:26:20 PM UTC 25 |
Feb 08 01:26:26 PM UTC 25 |
1786605476 ps |
| T1325 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_stress_rd.2966863126 |
|
|
Feb 08 01:25:54 PM UTC 25 |
Feb 08 01:26:27 PM UTC 25 |
6664844986 ps |
| T1326 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_override.1710175179 |
|
|
Feb 08 01:26:25 PM UTC 25 |
Feb 08 01:26:28 PM UTC 25 |
16571934 ps |
| T1327 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_stress_all.2316774058 |
|
|
Feb 08 01:25:27 PM UTC 25 |
Feb 08 01:26:29 PM UTC 25 |
7460333799 ps |
| T1328 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_fmt.1982305080 |
|
|
Feb 08 01:26:27 PM UTC 25 |
Feb 08 01:26:29 PM UTC 25 |
558984926 ps |
| T1329 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_rx.3084029450 |
|
|
Feb 08 01:26:28 PM UTC 25 |
Feb 08 01:26:33 PM UTC 25 |
627996609 ps |
| T1330 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_watermark.549860661 |
|
|
Feb 08 01:25:00 PM UTC 25 |
Feb 08 01:26:33 PM UTC 25 |
4226356183 ps |
| T1331 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_perf_precise.266516480 |
|
|
Feb 08 01:26:30 PM UTC 25 |
Feb 08 01:26:33 PM UTC 25 |
123468720 ps |
| T1332 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_watermark.3931456450 |
|
|
Feb 08 01:21:16 PM UTC 25 |
Feb 08 01:26:36 PM UTC 25 |
17690205327 ps |
| T1333 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_fmt_empty.1946329373 |
|
|
Feb 08 01:26:28 PM UTC 25 |
Feb 08 01:26:38 PM UTC 25 |
1421410234 ps |
| T1334 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_error_intr.1255276352 |
|
|
Feb 08 01:26:33 PM UTC 25 |
Feb 08 01:26:38 PM UTC 25 |
185965918 ps |
| T1335 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_may_nack.4107839692 |
|
|
Feb 08 01:26:15 PM UTC 25 |
Feb 08 01:26:40 PM UTC 25 |
1051936664 ps |
| T1336 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_overflow.614976283 |
|
|
Feb 08 01:25:44 PM UTC 25 |
Feb 08 01:26:43 PM UTC 25 |
9847972299 ps |
| T1337 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_stretch_timeout.2414622960 |
|
|
Feb 08 01:26:31 PM UTC 25 |
Feb 08 01:26:48 PM UTC 25 |
841271787 ps |
| T1338 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_smoke.3877124816 |
|
|
Feb 08 01:26:34 PM UTC 25 |
Feb 08 01:26:49 PM UTC 25 |
3096642797 ps |
| T1339 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_stretch.2572510874 |
|
|
Feb 08 01:26:39 PM UTC 25 |
Feb 08 01:26:49 PM UTC 25 |
3300174314 ps |
| T1340 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_smoke.253264432 |
|
|
Feb 08 01:26:24 PM UTC 25 |
Feb 08 01:26:49 PM UTC 25 |
1133155750 ps |
| T1341 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_intr_smoke.3146847291 |
|
|
Feb 08 01:26:40 PM UTC 25 |
Feb 08 01:26:50 PM UTC 25 |
3212030172 ps |
| T1342 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_acq.3585927351 |
|
|
Feb 08 01:26:50 PM UTC 25 |
Feb 08 01:26:52 PM UTC 25 |
202237457 ps |
| T1343 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_tx.3823826357 |
|
|
Feb 08 01:26:50 PM UTC 25 |
Feb 08 01:26:53 PM UTC 25 |
413235502 ps |
| T1344 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_timeout.4101964098 |
|
|
Feb 08 01:26:44 PM UTC 25 |
Feb 08 01:26:54 PM UTC 25 |
1935899048 ps |
| T1345 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_hrst.3800136159 |
|
|
Feb 08 01:26:53 PM UTC 25 |
Feb 08 01:26:57 PM UTC 25 |
1119007244 ps |
| T1346 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_acq.933686092 |
|
|
Feb 08 01:26:56 PM UTC 25 |
Feb 08 01:27:03 PM UTC 25 |
3283289389 ps |
| T1347 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_stress_rd.1303158685 |
|
|
Feb 08 01:26:39 PM UTC 25 |
Feb 08 01:27:03 PM UTC 25 |
1104023630 ps |
| T1348 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_tx_stretch_ctrl.3399486769 |
|
|
Feb 08 01:26:58 PM UTC 25 |
Feb 08 01:27:04 PM UTC 25 |
258487945 ps |
| T251 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_may_nack.3378872999 |
|
|
Feb 08 01:26:55 PM UTC 25 |
Feb 08 01:27:05 PM UTC 25 |
491162038 ps |
| T1349 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_smbus_maxlen.474748762 |
|
|
Feb 08 01:27:01 PM UTC 25 |
Feb 08 01:27:06 PM UTC 25 |
1854372258 ps |
| T1350 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull.1627106932 |
|
|
Feb 08 01:27:02 PM UTC 25 |
Feb 08 01:27:07 PM UTC 25 |
1781252112 ps |
| T1351 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_alert_test.1923095591 |
|
|
Feb 08 01:27:05 PM UTC 25 |
Feb 08 01:27:07 PM UTC 25 |
18462988 ps |
| T1352 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull.833119265 |
|
|
Feb 08 01:28:31 PM UTC 25 |
Feb 08 01:28:36 PM UTC 25 |
561756560 ps |
| T1353 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull_addr.3746734752 |
|
|
Feb 08 01:27:04 PM UTC 25 |
Feb 08 01:27:09 PM UTC 25 |
549065220 ps |
| T1354 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_perf.3675251256 |
|
|
Feb 08 01:26:29 PM UTC 25 |
Feb 08 01:27:09 PM UTC 25 |
6801047836 ps |
| T1355 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_override.1128357991 |
|
|
Feb 08 01:27:07 PM UTC 25 |
Feb 08 01:27:10 PM UTC 25 |
26096813 ps |
| T1356 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_fmt.3430474323 |
|
|
Feb 08 01:27:09 PM UTC 25 |
Feb 08 01:27:12 PM UTC 25 |
1010919384 ps |
| T1357 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_rx.2153386878 |
|
|
Feb 08 01:27:10 PM UTC 25 |
Feb 08 01:27:18 PM UTC 25 |
1587348008 ps |
| T1358 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_stress_wr.790208413 |
|
|
Feb 08 01:23:10 PM UTC 25 |
Feb 08 01:27:21 PM UTC 25 |
31598210770 ps |
| T1359 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_alert_test.175961372 |
|
|
Feb 08 01:28:34 PM UTC 25 |
Feb 08 01:28:36 PM UTC 25 |
28812716 ps |
| T1360 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_fmt_empty.3497414201 |
|
|
Feb 08 01:27:09 PM UTC 25 |
Feb 08 01:27:26 PM UTC 25 |
1109656244 ps |
| T1361 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_stretch.3397362651 |
|
|
Feb 08 01:25:59 PM UTC 25 |
Feb 08 01:27:29 PM UTC 25 |
4329951037 ps |
| T1362 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_error_intr.2522046407 |
|
|
Feb 08 01:27:27 PM UTC 25 |
Feb 08 01:27:31 PM UTC 25 |
177314447 ps |
| T1363 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_perf.1829343592 |
|
|
Feb 08 01:25:45 PM UTC 25 |
Feb 08 01:27:37 PM UTC 25 |
2833032557 ps |
| T1364 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_smoke.313548538 |
|
|
Feb 08 01:27:06 PM UTC 25 |
Feb 08 01:27:37 PM UTC 25 |
25562792192 ps |
| T1365 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_stress_all.1869223888 |
|
|
Feb 08 01:26:51 PM UTC 25 |
Feb 08 01:27:38 PM UTC 25 |
5883690286 ps |
| T1366 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_smoke.117808464 |
|
|
Feb 08 01:27:30 PM UTC 25 |
Feb 08 01:27:46 PM UTC 25 |
3939986793 ps |
| T1367 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_stretch_timeout.1767633071 |
|
|
Feb 08 01:27:22 PM UTC 25 |
Feb 08 01:27:47 PM UTC 25 |
1812227925 ps |
| T1368 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_stress_wr.3830774638 |
|
|
Feb 08 01:25:50 PM UTC 25 |
Feb 08 01:27:47 PM UTC 25 |
38936639507 ps |
| T1369 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_perf.3522319664 |
|
|
Feb 08 01:27:13 PM UTC 25 |
Feb 08 01:27:47 PM UTC 25 |
2974155126 ps |
| T1370 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_intr_smoke.2415413726 |
|
|
Feb 08 01:27:39 PM UTC 25 |
Feb 08 01:27:48 PM UTC 25 |
781808110 ps |
| T1371 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_overflow.1949274751 |
|
|
Feb 08 01:26:27 PM UTC 25 |
Feb 08 01:27:49 PM UTC 25 |
10032360014 ps |
| T1372 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_perf_precise.308111096 |
|
|
Feb 08 01:27:18 PM UTC 25 |
Feb 08 01:27:50 PM UTC 25 |
667276571 ps |
| T1373 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_smbus_maxlen.2220030946 |
|
|
Feb 08 01:28:29 PM UTC 25 |
Feb 08 01:28:35 PM UTC 25 |
585887889 ps |
| T1374 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_acq.2334812937 |
|
|
Feb 08 01:27:48 PM UTC 25 |
Feb 08 01:27:52 PM UTC 25 |
201642076 ps |
| T1375 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_tx.2343536209 |
|
|
Feb 08 01:27:49 PM UTC 25 |
Feb 08 01:27:53 PM UTC 25 |
209606641 ps |
| T1376 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_intr_stress_wr.316359428 |
|
|
Feb 08 01:23:23 PM UTC 25 |
Feb 08 01:27:55 PM UTC 25 |
27365428990 ps |
| T1377 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_full.745303831 |
|
|
Feb 08 01:25:03 PM UTC 25 |
Feb 08 01:27:55 PM UTC 25 |
7186671091 ps |
| T1378 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_timeout.1667972353 |
|
|
Feb 08 01:27:48 PM UTC 25 |
Feb 08 01:27:56 PM UTC 25 |
7952873625 ps |
| T1379 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_mode_toggle.416776300 |
|
|
Feb 08 01:27:53 PM UTC 25 |
Feb 08 01:27:56 PM UTC 25 |
56904375 ps |
| T1380 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_hrst.3097892360 |
|
|
Feb 08 01:27:53 PM UTC 25 |
Feb 08 01:27:56 PM UTC 25 |
959593774 ps |
| T1381 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_stress_wr.2707995195 |
|
|
Feb 08 01:26:37 PM UTC 25 |
Feb 08 01:27:56 PM UTC 25 |
21456665414 ps |
| T1382 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_tx.4000090708 |
|
|
Feb 08 01:27:56 PM UTC 25 |
Feb 08 01:27:59 PM UTC 25 |
113523831 ps |
| T1383 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_bad_addr.1078449447 |
|
|
Feb 08 01:27:52 PM UTC 25 |
Feb 08 01:27:59 PM UTC 25 |
811500849 ps |
| T1384 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_intr_stress_wr.3785737914 |
|
|
Feb 08 01:27:46 PM UTC 25 |
Feb 08 01:28:00 PM UTC 25 |
3869782071 ps |
| T1385 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_intr_stress_wr.2077661802 |
|
|
Feb 08 01:26:03 PM UTC 25 |
Feb 08 01:28:00 PM UTC 25 |
22412007668 ps |
| T1386 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_may_nack.617597015 |
|
|
Feb 08 01:27:54 PM UTC 25 |
Feb 08 01:28:00 PM UTC 25 |
259473737 ps |
| T1387 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_acq.1335612570 |
|
|
Feb 08 01:27:56 PM UTC 25 |
Feb 08 01:28:01 PM UTC 25 |
1913695278 ps |
| T1388 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull_addr.2664755731 |
|
|
Feb 08 01:27:57 PM UTC 25 |
Feb 08 01:28:01 PM UTC 25 |
519862809 ps |
| T1389 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_smbus_maxlen.805653335 |
|
|
Feb 08 01:27:57 PM UTC 25 |
Feb 08 01:28:02 PM UTC 25 |
1803977028 ps |
| T1390 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_perf.1486160114 |
|
|
Feb 08 01:27:50 PM UTC 25 |
Feb 08 01:28:02 PM UTC 25 |
1794338697 ps |
| T1391 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull.3290483475 |
|
|
Feb 08 01:27:57 PM UTC 25 |
Feb 08 01:28:02 PM UTC 25 |
2066837318 ps |
| T1392 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_nack_txstretch.2974551011 |
|
|
Feb 08 01:27:59 PM UTC 25 |
Feb 08 01:28:02 PM UTC 25 |
511426835 ps |
| T1393 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_alert_test.2410658940 |
|
|
Feb 08 01:28:00 PM UTC 25 |
Feb 08 01:28:03 PM UTC 25 |
19522815 ps |
| T1394 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_override.3674651433 |
|
|
Feb 08 01:28:00 PM UTC 25 |
Feb 08 01:28:03 PM UTC 25 |
86363543 ps |
| T1395 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_fmt.3879493810 |
|
|
Feb 08 01:28:03 PM UTC 25 |
Feb 08 01:28:05 PM UTC 25 |
386745955 ps |
| T1396 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_full.3653022859 |
|
|
Feb 08 01:26:28 PM UTC 25 |
Feb 08 01:28:06 PM UTC 25 |
14867447281 ps |
| T1397 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_stress_wr.3791990362 |
|
|
Feb 08 01:27:32 PM UTC 25 |
Feb 08 01:28:07 PM UTC 25 |
12066223144 ps |
| T1398 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_perf_precise.2550904549 |
|
|
Feb 08 01:28:04 PM UTC 25 |
Feb 08 01:28:09 PM UTC 25 |
66524397 ps |
| T1399 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_tx_stretch_ctrl.4146156205 |
|
|
Feb 08 01:27:57 PM UTC 25 |
Feb 08 01:28:09 PM UTC 25 |
767403139 ps |
| T1400 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_overflow.1697558785 |
|
|
Feb 08 01:25:01 PM UTC 25 |
Feb 08 01:28:10 PM UTC 25 |
2520778213 ps |
| T1401 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_error_intr.2339809095 |
|
|
Feb 08 01:28:06 PM UTC 25 |
Feb 08 01:28:11 PM UTC 25 |
491202326 ps |
| T1402 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_rx.3931719139 |
|
|
Feb 08 01:28:03 PM UTC 25 |
Feb 08 01:28:11 PM UTC 25 |
934184520 ps |
| T1403 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_fmt_empty.2947549552 |
|
|
Feb 08 01:28:03 PM UTC 25 |
Feb 08 01:28:13 PM UTC 25 |
472464528 ps |
| T1404 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_stretch.4197438189 |
|
|
Feb 08 01:28:10 PM UTC 25 |
Feb 08 01:28:14 PM UTC 25 |
2857764527 ps |
| T1405 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_intr_smoke.719198472 |
|
|
Feb 08 01:28:11 PM UTC 25 |
Feb 08 01:28:19 PM UTC 25 |
1231794218 ps |
| T1406 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_smoke.3666696623 |
|
|
Feb 08 01:28:08 PM UTC 25 |
Feb 08 01:28:20 PM UTC 25 |
656134054 ps |
| T1407 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_acq.1749827319 |
|
|
Feb 08 01:28:18 PM UTC 25 |
Feb 08 01:28:21 PM UTC 25 |
208336518 ps |
| T1408 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_tx.2004075971 |
|
|
Feb 08 01:28:20 PM UTC 25 |
Feb 08 01:28:23 PM UTC 25 |
153690277 ps |
| T1409 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_watermark.1152645452 |
|
|
Feb 08 01:22:59 PM UTC 25 |
Feb 08 01:28:24 PM UTC 25 |
5052271669 ps |
| T1410 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_stretch_timeout.2380422825 |
|
|
Feb 08 01:28:04 PM UTC 25 |
Feb 08 01:28:26 PM UTC 25 |
443176981 ps |
| T1411 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_stress_rd.1073055773 |
|
|
Feb 08 01:28:10 PM UTC 25 |
Feb 08 01:28:27 PM UTC 25 |
726313657 ps |
| T1412 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_perf.1818228365 |
|
|
Feb 08 01:28:21 PM UTC 25 |
Feb 08 01:28:28 PM UTC 25 |
4252300338 ps |
| T1413 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_timeout.123789772 |
|
|
Feb 08 01:28:15 PM UTC 25 |
Feb 08 01:28:28 PM UTC 25 |
1456575491 ps |
| T1414 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_stress_all.4120341577 |
|
|
Feb 08 01:18:07 PM UTC 25 |
Feb 08 01:28:28 PM UTC 25 |
27787226729 ps |
| T1415 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_hrst.4036889613 |
|
|
Feb 08 01:28:25 PM UTC 25 |
Feb 08 01:28:29 PM UTC 25 |
4591115791 ps |
| T1416 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_mode_toggle.3175457933 |
|
|
Feb 08 01:28:26 PM UTC 25 |
Feb 08 01:28:29 PM UTC 25 |
336769093 ps |
| T1417 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_acq.3279020974 |
|
|
Feb 08 01:28:28 PM UTC 25 |
Feb 08 01:28:31 PM UTC 25 |
534921230 ps |
| T1418 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_tx.3377849347 |
|
|
Feb 08 01:28:29 PM UTC 25 |
Feb 08 01:28:32 PM UTC 25 |
379250308 ps |
| T1419 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_bad_addr.3161676157 |
|
|
Feb 08 01:28:24 PM UTC 25 |
Feb 08 01:28:33 PM UTC 25 |
1968086802 ps |
| T1420 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_intr_stress_wr.1060251057 |
|
|
Feb 08 01:28:12 PM UTC 25 |
Feb 08 01:28:33 PM UTC 25 |
10564163361 ps |
| T1421 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_smoke.815570134 |
|
|
Feb 08 01:28:00 PM UTC 25 |
Feb 08 01:28:34 PM UTC 25 |
1655783432 ps |
| T1422 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_perf.3430952226 |
|
|
Feb 08 01:23:55 PM UTC 25 |
Feb 08 01:28:35 PM UTC 25 |
18281527862 ps |
| T1423 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull_addr.2237548615 |
|
|
Feb 08 01:28:32 PM UTC 25 |
Feb 08 01:28:37 PM UTC 25 |
918421150 ps |
| T1424 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_nack_txstretch.4122563072 |
|
|
Feb 08 01:28:34 PM UTC 25 |
Feb 08 01:28:37 PM UTC 25 |
551805431 ps |
| T1425 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_override.2771887029 |
|
|
Feb 08 01:28:35 PM UTC 25 |
Feb 08 01:28:37 PM UTC 25 |
45239730 ps |
| T1426 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_stress_rd.2670343723 |
|
|
Feb 08 01:27:38 PM UTC 25 |
Feb 08 01:28:38 PM UTC 25 |
2719611874 ps |
| T1427 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_fmt.718018643 |
|
|
Feb 08 01:28:37 PM UTC 25 |
Feb 08 01:28:40 PM UTC 25 |
209834830 ps |
| T1428 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_tx_stretch_ctrl.3194931337 |
|
|
Feb 08 01:28:29 PM UTC 25 |
Feb 08 01:28:42 PM UTC 25 |
404578669 ps |
| T1429 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_perf_precise.1784553802 |
|
|
Feb 08 01:28:39 PM UTC 25 |
Feb 08 01:28:43 PM UTC 25 |
94574798 ps |
| T1430 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_rx.1135798502 |
|
|
Feb 08 01:28:37 PM UTC 25 |
Feb 08 01:28:46 PM UTC 25 |
453332641 ps |
| T1431 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_error_intr.4165605118 |
|
|
Feb 08 01:28:42 PM UTC 25 |
Feb 08 01:28:48 PM UTC 25 |
104368224 ps |
| T1432 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_may_nack.1118450807 |
|
|
Feb 08 01:28:27 PM UTC 25 |
Feb 08 01:28:49 PM UTC 25 |
1708672027 ps |
| T1433 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_full.112302967 |
|
|
Feb 08 01:25:45 PM UTC 25 |
Feb 08 01:28:57 PM UTC 25 |
18964232759 ps |
| T1434 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_fmt_empty.2236769784 |
|
|
Feb 08 01:28:37 PM UTC 25 |
Feb 08 01:28:57 PM UTC 25 |
1205462814 ps |
| T1435 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_stretch_timeout.2489600177 |
|
|
Feb 08 01:28:40 PM UTC 25 |
Feb 08 01:29:00 PM UTC 25 |
3671893268 ps |
| T1436 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_perf.2502830914 |
|
|
Feb 08 01:28:04 PM UTC 25 |
Feb 08 01:29:04 PM UTC 25 |
25464022936 ps |
| T1437 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_stress_wr.3549795235 |
|
|
Feb 08 01:28:50 PM UTC 25 |
Feb 08 01:29:05 PM UTC 25 |
16181062025 ps |
| T1438 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_overflow.16349485 |
|
|
Feb 08 01:27:08 PM UTC 25 |
Feb 08 01:29:06 PM UTC 25 |
17946032730 ps |
| T1439 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_stress_rd.1531992105 |
|
|
Feb 08 01:28:50 PM UTC 25 |
Feb 08 01:29:07 PM UTC 25 |
3680105536 ps |
| T1440 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_intr_smoke.958465050 |
|
|
Feb 08 01:28:58 PM UTC 25 |
Feb 08 01:29:07 PM UTC 25 |
970296040 ps |
| T1441 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_acq.1774213899 |
|
|
Feb 08 01:29:07 PM UTC 25 |
Feb 08 01:29:10 PM UTC 25 |
578416967 ps |
| T1442 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_tx.1233138130 |
|
|
Feb 08 01:29:07 PM UTC 25 |
Feb 08 01:29:12 PM UTC 25 |
314011715 ps |
| T1443 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_watermark.3337368642 |
|
|
Feb 08 01:23:52 PM UTC 25 |
Feb 08 01:29:12 PM UTC 25 |
9241608684 ps |
| T1444 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_perf.3732289268 |
|
|
Feb 08 01:29:08 PM UTC 25 |
Feb 08 01:29:15 PM UTC 25 |
856538074 ps |
| T1445 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_timeout.827967995 |
|
|
Feb 08 01:29:05 PM UTC 25 |
Feb 08 01:29:17 PM UTC 25 |
4845858265 ps |
| T1446 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_overflow.1537563658 |
|
|
Feb 08 01:28:02 PM UTC 25 |
Feb 08 01:29:17 PM UTC 25 |
4884992262 ps |
| T1447 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_hrst.2354087799 |
|
|
Feb 08 01:29:13 PM UTC 25 |
Feb 08 01:29:17 PM UTC 25 |
1153811929 ps |
| T1448 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_full.1847890351 |
|
|
Feb 08 01:27:10 PM UTC 25 |
Feb 08 01:29:17 PM UTC 25 |
2177088481 ps |
| T1449 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_smoke.2109429876 |
|
|
Feb 08 01:28:47 PM UTC 25 |
Feb 08 01:29:17 PM UTC 25 |
3146636503 ps |
| T1450 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_bad_addr.391200445 |
|
|
Feb 08 01:29:10 PM UTC 25 |
Feb 08 01:29:18 PM UTC 25 |
2052903718 ps |
| T1451 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_mode_toggle.3229771475 |
|
|
Feb 08 01:29:13 PM UTC 25 |
Feb 08 01:29:19 PM UTC 25 |
133034934 ps |
| T1452 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_tx.1819565444 |
|
|
Feb 08 01:29:18 PM UTC 25 |
Feb 08 01:29:20 PM UTC 25 |
879760762 ps |
| T1453 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_tx_stretch_ctrl.602644084 |
|
|
Feb 08 01:29:18 PM UTC 25 |
Feb 08 01:29:21 PM UTC 25 |
79105379 ps |
| T1454 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_acq.158790450 |
|
|
Feb 08 01:29:18 PM UTC 25 |
Feb 08 01:29:22 PM UTC 25 |
1133867220 ps |
| T1455 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_smbus_maxlen.166144322 |
|
|
Feb 08 01:29:18 PM UTC 25 |
Feb 08 01:29:22 PM UTC 25 |
743853885 ps |
| T1456 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_alert_test.1124463736 |
|
|
Feb 08 01:29:21 PM UTC 25 |
Feb 08 01:29:23 PM UTC 25 |
38657155 ps |
| T1457 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_nack_txstretch.1011759398 |
|
|
Feb 08 01:29:20 PM UTC 25 |
Feb 08 01:29:24 PM UTC 25 |
272223565 ps |
| T1458 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_override.674764286 |
|
|
Feb 08 01:29:22 PM UTC 25 |
Feb 08 01:29:24 PM UTC 25 |
81640004 ps |
| T1459 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull_addr.853612765 |
|
|
Feb 08 01:29:19 PM UTC 25 |
Feb 08 01:29:24 PM UTC 25 |
536586737 ps |
| T1460 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull.1710769359 |
|
|
Feb 08 01:29:19 PM UTC 25 |
Feb 08 01:29:25 PM UTC 25 |
2280051750 ps |
| T1461 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_may_nack.1814946923 |
|
|
Feb 08 01:29:16 PM UTC 25 |
Feb 08 01:29:26 PM UTC 25 |
2175192385 ps |
| T1462 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_fmt.2933236710 |
|
|
Feb 08 01:29:24 PM UTC 25 |
Feb 08 01:29:27 PM UTC 25 |
272974838 ps |
| T1463 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_rx.2183093289 |
|
|
Feb 08 01:29:26 PM UTC 25 |
Feb 08 01:29:31 PM UTC 25 |
126856886 ps |
| T1464 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_full.3652925038 |
|
|
Feb 08 01:28:03 PM UTC 25 |
Feb 08 01:29:31 PM UTC 25 |
3028557055 ps |
| T1465 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_smoke.1578772353 |
|
|
Feb 08 01:28:34 PM UTC 25 |
Feb 08 01:29:34 PM UTC 25 |
3993039534 ps |
| T1466 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_error_intr.2991790564 |
|
|
Feb 08 01:29:32 PM UTC 25 |
Feb 08 01:29:35 PM UTC 25 |
773796498 ps |
| T1467 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_fmt_empty.866993653 |
|
|
Feb 08 01:29:26 PM UTC 25 |
Feb 08 01:29:36 PM UTC 25 |
908857320 ps |
| T1468 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_stretch.3525750616 |
|
|
Feb 08 01:28:58 PM UTC 25 |
Feb 08 01:29:39 PM UTC 25 |
4283215488 ps |
| T1469 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_stretch_timeout.1184081934 |
|
|
Feb 08 01:29:32 PM UTC 25 |
Feb 08 01:29:49 PM UTC 25 |
9002139281 ps |
| T1470 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_watermark.1685316195 |
|
|
Feb 08 01:25:43 PM UTC 25 |
Feb 08 01:29:49 PM UTC 25 |
3679441913 ps |
| T1471 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_stretch.2545578283 |
|
|
Feb 08 01:29:49 PM UTC 25 |
Feb 08 01:29:53 PM UTC 25 |
208738520 ps |
| T270 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_stress_all.4151111611 |
|
|
Feb 08 01:26:12 PM UTC 25 |
Feb 08 01:29:55 PM UTC 25 |
41462056895 ps |
| T1472 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_intr_smoke.2119996611 |
|
|
Feb 08 01:29:49 PM UTC 25 |
Feb 08 01:29:59 PM UTC 25 |
1066501298 ps |
| T1473 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_smoke.2640601525 |
|
|
Feb 08 01:29:22 PM UTC 25 |
Feb 08 01:30:00 PM UTC 25 |
2124363370 ps |
| T1474 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_smoke.3220832432 |
|
|
Feb 08 01:30:27 PM UTC 25 |
Feb 08 01:30:52 PM UTC 25 |
1308243185 ps |
| T1475 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_acq.2884739840 |
|
|
Feb 08 01:30:01 PM UTC 25 |
Feb 08 01:30:03 PM UTC 25 |
230605665 ps |
| T1476 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_overflow.3555235667 |
|
|
Feb 08 01:28:36 PM UTC 25 |
Feb 08 01:30:06 PM UTC 25 |
13613475325 ps |
| T1477 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_tx.3881062268 |
|
|
Feb 08 01:30:04 PM UTC 25 |
Feb 08 01:30:07 PM UTC 25 |
235890153 ps |
| T1478 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_timeout.3070990397 |
|
|
Feb 08 01:29:55 PM UTC 25 |
Feb 08 01:30:07 PM UTC 25 |
5945135379 ps |
| T1479 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_hrst.43825244 |
|
|
Feb 08 01:30:08 PM UTC 25 |
Feb 08 01:30:12 PM UTC 25 |
561972852 ps |
| T1480 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_bad_addr.1998727796 |
|
|
Feb 08 01:30:08 PM UTC 25 |
Feb 08 01:30:13 PM UTC 25 |
411694388 ps |
| T1481 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_perf.3196951698 |
|
|
Feb 08 01:30:05 PM UTC 25 |
Feb 08 01:30:15 PM UTC 25 |
730591150 ps |
| T1482 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_mode_toggle.366158546 |
|
|
Feb 08 01:30:13 PM UTC 25 |
Feb 08 01:30:19 PM UTC 25 |
711947203 ps |
| T1483 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_acq.1294394131 |
|
|
Feb 08 01:30:15 PM UTC 25 |
Feb 08 01:30:20 PM UTC 25 |
1328377226 ps |
| T1484 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_may_nack.2339798442 |
|
|
Feb 08 01:30:14 PM UTC 25 |
Feb 08 01:30:20 PM UTC 25 |
221288697 ps |
| T1485 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_error_intr.4234144902 |
|
|
Feb 08 01:30:47 PM UTC 25 |
Feb 08 01:30:51 PM UTC 25 |
2634473776 ps |
| T1486 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_smoke.475888761 |
|
|
Feb 08 01:29:36 PM UTC 25 |
Feb 08 01:30:22 PM UTC 25 |
18648448822 ps |
| T1487 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_intr_stress_wr.3082522249 |
|
|
Feb 08 01:25:19 PM UTC 25 |
Feb 08 01:30:23 PM UTC 25 |
15346105721 ps |
| T1488 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_tx.2235653530 |
|
|
Feb 08 01:30:19 PM UTC 25 |
Feb 08 01:30:23 PM UTC 25 |
489406263 ps |
| T1489 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_tx_stretch_ctrl.309868562 |
|
|
Feb 08 01:30:20 PM UTC 25 |
Feb 08 01:30:25 PM UTC 25 |
109898347 ps |
| T1490 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_smbus_maxlen.4035724931 |
|
|
Feb 08 01:30:20 PM UTC 25 |
Feb 08 01:30:26 PM UTC 25 |
3028527236 ps |
| T1491 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_alert_test.2456776090 |
|
|
Feb 08 01:30:26 PM UTC 25 |
Feb 08 01:30:28 PM UTC 25 |
20927940 ps |
| T1492 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull_addr.1724046480 |
|
|
Feb 08 01:30:24 PM UTC 25 |
Feb 08 01:30:28 PM UTC 25 |
1601051892 ps |
| T1493 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull.2268407451 |
|
|
Feb 08 01:30:24 PM UTC 25 |
Feb 08 01:30:29 PM UTC 25 |
2073090260 ps |
| T1494 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_override.3367534403 |
|
|
Feb 08 01:30:28 PM UTC 25 |
Feb 08 01:30:30 PM UTC 25 |
29493416 ps |
| T1495 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_fmt.1545404214 |
|
|
Feb 08 01:30:30 PM UTC 25 |
Feb 08 01:30:33 PM UTC 25 |
285037863 ps |
| T1496 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_stress_rd.1527567590 |
|
|
Feb 08 01:29:39 PM UTC 25 |
Feb 08 01:30:35 PM UTC 25 |
5289464564 ps |
| T1497 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_rx.3233906453 |
|
|
Feb 08 01:30:33 PM UTC 25 |
Feb 08 01:30:40 PM UTC 25 |
738207105 ps |
| T1498 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.2176517846 |
|
|
Feb 08 01:29:23 PM UTC 25 |
Feb 08 01:30:43 PM UTC 25 |
3661158646 ps |
| T1499 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_fmt_empty.3358423902 |
|
|
Feb 08 01:30:31 PM UTC 25 |
Feb 08 01:30:43 PM UTC 25 |
2417243385 ps |
| T1500 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_full.3059458116 |
|
|
Feb 08 01:28:37 PM UTC 25 |
Feb 08 01:30:45 PM UTC 25 |
2154094607 ps |
| T1501 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_intr_stress_wr.153738261 |
|
|
Feb 08 01:29:53 PM UTC 25 |
Feb 08 01:30:52 PM UTC 25 |
23386950648 ps |
| T1502 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_watermark.3078910402 |
|
|
Feb 08 01:28:36 PM UTC 25 |
Feb 08 01:30:55 PM UTC 25 |
22644064440 ps |
| T1503 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_smoke.2879137580 |
|
|
Feb 08 01:30:53 PM UTC 25 |
Feb 08 01:31:02 PM UTC 25 |
4402613654 ps |
| T1504 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_stress_all.1537034002 |
|
|
Feb 08 01:27:51 PM UTC 25 |
Feb 08 01:31:04 PM UTC 25 |
39587808233 ps |
| T1505 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_full.4028521584 |
|
|
Feb 08 01:29:26 PM UTC 25 |
Feb 08 01:31:09 PM UTC 25 |
2446543005 ps |
| T1506 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_stretch_timeout.318978309 |
|
|
Feb 08 01:30:43 PM UTC 25 |
Feb 08 01:31:10 PM UTC 25 |
1007271694 ps |
| T1507 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_stress_rd.2632458534 |
|
|
Feb 08 01:30:56 PM UTC 25 |
Feb 08 01:31:11 PM UTC 25 |
2880662850 ps |
| T1508 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_intr_smoke.1037381087 |
|
|
Feb 08 01:31:05 PM UTC 25 |
Feb 08 01:31:14 PM UTC 25 |
1555365991 ps |
| T1509 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_mode_toggle.2004930522 |
|
|
Feb 08 01:33:17 PM UTC 25 |
Feb 08 01:33:21 PM UTC 25 |
77185135 ps |
| T1510 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_acq.2045790286 |
|
|
Feb 08 01:31:13 PM UTC 25 |
Feb 08 01:31:17 PM UTC 25 |
223516159 ps |
| T1511 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_perf.1741667890 |
|
|
Feb 08 01:21:47 PM UTC 25 |
Feb 08 01:31:17 PM UTC 25 |
51206328611 ps |
| T1512 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.2640330118 |
|
|
Feb 08 01:30:54 PM UTC 25 |
Feb 08 01:31:18 PM UTC 25 |
22263776963 ps |
| T1513 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_tx.562134320 |
|
|
Feb 08 01:31:15 PM UTC 25 |
Feb 08 01:31:19 PM UTC 25 |
525066229 ps |
| T1514 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_timeout.2335220158 |
|
|
Feb 08 01:31:10 PM UTC 25 |
Feb 08 01:31:20 PM UTC 25 |
2784064586 ps |
| T1515 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_perf.342540504 |
|
|
Feb 08 01:30:40 PM UTC 25 |
Feb 08 01:31:21 PM UTC 25 |
3385515570 ps |
| T1516 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_bad_addr.2565676007 |
|
|
Feb 08 01:31:18 PM UTC 25 |
Feb 08 01:31:23 PM UTC 25 |
528482191 ps |
| T1517 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_mode_toggle.592708429 |
|
|
Feb 08 01:31:20 PM UTC 25 |
Feb 08 01:31:24 PM UTC 25 |
966850932 ps |
| T1518 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_perf.1843070212 |
|
|
Feb 08 01:31:17 PM UTC 25 |
Feb 08 01:31:25 PM UTC 25 |
617526836 ps |
| T1519 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_acq.3277611473 |
|
|
Feb 08 01:31:22 PM UTC 25 |
Feb 08 01:31:26 PM UTC 25 |
414959744 ps |
| T1520 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_tx.1052048897 |
|
|
Feb 08 01:31:24 PM UTC 25 |
Feb 08 01:31:27 PM UTC 25 |
124508714 ps |
| T1521 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_perf_precise.3184135190 |
|
|
Feb 08 01:30:43 PM UTC 25 |
Feb 08 01:31:28 PM UTC 25 |
1755992452 ps |
| T1522 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_intr_stress_wr.2456844601 |
|
|
Feb 08 01:31:10 PM UTC 25 |
Feb 08 01:31:30 PM UTC 25 |
8233161506 ps |
| T1523 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_smbus_maxlen.109654211 |
|
|
Feb 08 01:31:26 PM UTC 25 |
Feb 08 01:31:30 PM UTC 25 |
494178080 ps |
| T1524 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull.2784120384 |
|
|
Feb 08 01:31:27 PM UTC 25 |
Feb 08 01:31:33 PM UTC 25 |
2272106284 ps |
| T1525 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_alert_test.1746142569 |
|
|
Feb 08 01:31:31 PM UTC 25 |
Feb 08 01:31:34 PM UTC 25 |
43287698 ps |
| T1526 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull_addr.2641431996 |
|
|
Feb 08 01:31:27 PM UTC 25 |
Feb 08 01:31:34 PM UTC 25 |
2113406682 ps |
| T1527 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_override.3147535436 |
|
|
Feb 08 01:31:32 PM UTC 25 |
Feb 08 01:31:35 PM UTC 25 |
21230407 ps |
| T1528 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_watermark.3590318027 |
|
|
Feb 08 01:28:01 PM UTC 25 |
Feb 08 01:31:37 PM UTC 25 |
3064467201 ps |
| T1529 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_fmt.53026618 |
|
|
Feb 08 01:31:35 PM UTC 25 |
Feb 08 01:31:37 PM UTC 25 |
80379961 ps |
| T1530 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_tx_stretch_ctrl.3669686296 |
|
|
Feb 08 01:31:25 PM UTC 25 |
Feb 08 01:31:38 PM UTC 25 |
617979691 ps |
| T1531 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_may_nack.2978252035 |
|
|
Feb 08 01:31:21 PM UTC 25 |
Feb 08 01:31:43 PM UTC 25 |
443191826 ps |
| T1532 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_rx.357312192 |
|
|
Feb 08 01:31:38 PM UTC 25 |
Feb 08 01:31:45 PM UTC 25 |
199233267 ps |
| T1533 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_watermark.324938044 |
|
|
Feb 08 01:27:08 PM UTC 25 |
Feb 08 01:31:46 PM UTC 25 |
8278404376 ps |
| T1534 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_error_intr.1391095099 |
|
|
Feb 08 01:31:45 PM UTC 25 |
Feb 08 01:31:49 PM UTC 25 |
128821924 ps |
| T1535 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_fmt_empty.339163800 |
|
|
Feb 08 01:31:36 PM UTC 25 |
Feb 08 01:31:50 PM UTC 25 |
971823869 ps |
| T1536 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_overflow.2235784361 |
|
|
Feb 08 01:29:24 PM UTC 25 |
Feb 08 01:31:55 PM UTC 25 |
1967079810 ps |
| T1537 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_stretch_timeout.2183756722 |
|
|
Feb 08 01:31:44 PM UTC 25 |
Feb 08 01:31:59 PM UTC 25 |
643283745 ps |
| T1538 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_perf_precise.1370974348 |
|
|
Feb 08 01:31:40 PM UTC 25 |
Feb 08 01:32:00 PM UTC 25 |
345205481 ps |
| T1539 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_smoke.2685181976 |
|
|
Feb 08 01:31:31 PM UTC 25 |
Feb 08 01:32:05 PM UTC 25 |
3858581710 ps |
| T1540 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_stretch.2300400801 |
|
|
Feb 08 01:32:00 PM UTC 25 |
Feb 08 01:32:11 PM UTC 25 |
2703204332 ps |
| T1541 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_intr_smoke.2302193693 |
|
|
Feb 08 01:32:00 PM UTC 25 |
Feb 08 01:32:12 PM UTC 25 |
2512205760 ps |
| T1542 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_acq.1476132796 |
|
|
Feb 08 01:32:12 PM UTC 25 |
Feb 08 01:32:15 PM UTC 25 |
370225552 ps |
| T1543 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_tx.3618543334 |
|
|
Feb 08 01:32:13 PM UTC 25 |
Feb 08 01:32:16 PM UTC 25 |
164591911 ps |
| T1544 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_overflow.3746896644 |
|
|
Feb 08 01:30:29 PM UTC 25 |
Feb 08 01:32:17 PM UTC 25 |
2755476070 ps |
| T1545 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_timeout.3381938222 |
|
|
Feb 08 01:32:06 PM UTC 25 |
Feb 08 01:32:18 PM UTC 25 |
15946870141 ps |
| T1546 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_perf.492977577 |
|
|
Feb 08 01:32:14 PM UTC 25 |
Feb 08 01:32:21 PM UTC 25 |
2640576224 ps |
| T1547 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_intr_stress_wr.95988465 |
|
|
Feb 08 01:26:41 PM UTC 25 |
Feb 08 01:32:23 PM UTC 25 |
25644621646 ps |
| T1548 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_stress_all.1195429596 |
|
|
Feb 08 01:28:22 PM UTC 25 |
Feb 08 01:32:25 PM UTC 25 |
69589923969 ps |
| T1549 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_bad_addr.1954404405 |
|
|
Feb 08 01:32:17 PM UTC 25 |
Feb 08 01:32:26 PM UTC 25 |
3499056736 ps |
| T1550 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_tx.2223403551 |
|
|
Feb 08 01:32:24 PM UTC 25 |
Feb 08 01:32:27 PM UTC 25 |
145620515 ps |
| T1551 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_smoke.813450872 |
|
|
Feb 08 01:31:49 PM UTC 25 |
Feb 08 01:32:29 PM UTC 25 |
973762393 ps |
| T1552 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_acq.4002911271 |
|
|
Feb 08 01:32:24 PM UTC 25 |
Feb 08 01:32:30 PM UTC 25 |
5014505752 ps |
| T1553 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_tx_stretch_ctrl.2705660777 |
|
|
Feb 08 01:32:27 PM UTC 25 |
Feb 08 01:32:31 PM UTC 25 |
138811048 ps |
| T1554 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_may_nack.1418207210 |
|
|
Feb 08 01:32:22 PM UTC 25 |
Feb 08 01:32:32 PM UTC 25 |
2262027781 ps |
| T1555 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_smbus_maxlen.2408128282 |
|
|
Feb 08 01:32:28 PM UTC 25 |
Feb 08 01:32:32 PM UTC 25 |
791168273 ps |
| T1556 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_alert_test.884637134 |
|
|
Feb 08 01:32:31 PM UTC 25 |
Feb 08 01:32:33 PM UTC 25 |
19286822 ps |
| T1557 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull.2665799482 |
|
|
Feb 08 01:32:29 PM UTC 25 |
Feb 08 01:32:34 PM UTC 25 |
2026852355 ps |
| T1558 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.321161026 |
|
|
Feb 08 01:30:07 PM UTC 25 |
Feb 08 01:32:34 PM UTC 25 |
19869923963 ps |
| T1559 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_nack_txstretch.1626477752 |
|
|
Feb 08 01:32:31 PM UTC 25 |
Feb 08 01:32:35 PM UTC 25 |
472484914 ps |
| T1560 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull_addr.4219695898 |
|
|
Feb 08 01:32:30 PM UTC 25 |
Feb 08 01:32:35 PM UTC 25 |
467900235 ps |
| T1561 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_override.3104091708 |
|
|
Feb 08 01:32:33 PM UTC 25 |
Feb 08 01:32:35 PM UTC 25 |
58520125 ps |
| T1562 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_fmt.2896342847 |
|
|
Feb 08 01:32:34 PM UTC 25 |
Feb 08 01:32:37 PM UTC 25 |
1047035061 ps |
| T1563 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_full.2778412829 |
|
|
Feb 08 01:30:36 PM UTC 25 |
Feb 08 01:32:38 PM UTC 25 |
1795089461 ps |
| T1564 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_watermark.2615618097 |
|
|
Feb 08 01:26:27 PM UTC 25 |
Feb 08 01:32:40 PM UTC 25 |
19870851997 ps |
| T1565 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_stress_rd.2277788644 |
|
|
Feb 08 01:31:55 PM UTC 25 |
Feb 08 01:32:43 PM UTC 25 |
960536893 ps |
| T1566 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_error_intr.975685883 |
|
|
Feb 08 01:32:41 PM UTC 25 |
Feb 08 01:32:45 PM UTC 25 |
99833027 ps |
| T1567 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_fmt_empty.3745466112 |
|
|
Feb 08 01:32:34 PM UTC 25 |
Feb 08 01:32:49 PM UTC 25 |
738186904 ps |
| T1568 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.1106618979 |
|
|
Feb 08 01:32:39 PM UTC 25 |
Feb 08 01:32:50 PM UTC 25 |
2367786632 ps |
| T1569 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.760459286 |
|
|
Feb 08 01:31:17 PM UTC 25 |
Feb 08 01:32:53 PM UTC 25 |
22754878215 ps |