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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.27 97.27 89.61 97.22 72.02 94.33 98.44 90.00


Total test records in report: 1856
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T1768 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.296813284 Feb 08 01:38:21 PM UTC 25 Feb 08 01:38:24 PM UTC 25 987558440 ps
T1769 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2581383018 Feb 08 01:38:22 PM UTC 25 Feb 08 01:38:24 PM UTC 25 29309912 ps
T205 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.4131215031 Feb 08 01:38:21 PM UTC 25 Feb 08 01:38:25 PM UTC 25 511187415 ps
T1770 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1961487934 Feb 08 01:38:22 PM UTC 25 Feb 08 01:38:25 PM UTC 25 177318913 ps
T1771 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.4270216387 Feb 08 01:38:22 PM UTC 25 Feb 08 01:38:26 PM UTC 25 34991895 ps
T202 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.1201626720 Feb 08 01:38:23 PM UTC 25 Feb 08 01:38:27 PM UTC 25 290845923 ps
T277 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.700348236 Feb 08 01:38:25 PM UTC 25 Feb 08 01:38:27 PM UTC 25 61983680 ps
T217 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.3347641795 Feb 08 01:38:25 PM UTC 25 Feb 08 01:38:27 PM UTC 25 39383431 ps
T1772 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.114011380 Feb 08 01:38:25 PM UTC 25 Feb 08 01:38:27 PM UTC 25 33278642 ps
T1773 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3929965608 Feb 08 01:38:25 PM UTC 25 Feb 08 01:38:27 PM UTC 25 47759038 ps
T218 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.3983790280 Feb 08 01:38:26 PM UTC 25 Feb 08 01:38:28 PM UTC 25 64314996 ps
T1774 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.2823213113 Feb 08 01:38:26 PM UTC 25 Feb 08 01:38:28 PM UTC 25 37130137 ps
T1775 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.2012627314 Feb 08 01:38:25 PM UTC 25 Feb 08 01:38:28 PM UTC 25 143571397 ps
T1776 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2843866996 Feb 08 01:38:26 PM UTC 25 Feb 08 01:38:29 PM UTC 25 47009333 ps
T198 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.3837792081 Feb 08 01:38:25 PM UTC 25 Feb 08 01:38:29 PM UTC 25 249425872 ps
T1777 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2602489693 Feb 08 01:38:26 PM UTC 25 Feb 08 01:38:29 PM UTC 25 61428019 ps
T1778 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.2302818947 Feb 08 01:38:28 PM UTC 25 Feb 08 01:38:30 PM UTC 25 38319760 ps
T285 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.2249510712 Feb 08 01:38:28 PM UTC 25 Feb 08 01:38:30 PM UTC 25 115695308 ps
T1779 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.2489264226 Feb 08 01:38:26 PM UTC 25 Feb 08 01:38:30 PM UTC 25 56124048 ps
T1780 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3302756102 Feb 08 01:38:29 PM UTC 25 Feb 08 01:38:32 PM UTC 25 75131352 ps
T1781 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.2871997038 Feb 08 01:38:28 PM UTC 25 Feb 08 01:38:32 PM UTC 25 341141888 ps
T1782 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1488337225 Feb 08 01:38:29 PM UTC 25 Feb 08 01:38:33 PM UTC 25 36896115 ps
T281 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.3555507407 Feb 08 01:38:30 PM UTC 25 Feb 08 01:38:33 PM UTC 25 19782513 ps
T1783 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.1371723619 Feb 08 01:38:30 PM UTC 25 Feb 08 01:38:33 PM UTC 25 44909028 ps
T1784 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.3780654481 Feb 08 01:38:29 PM UTC 25 Feb 08 01:38:33 PM UTC 25 86160312 ps
T1785 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.926290733 Feb 08 01:38:31 PM UTC 25 Feb 08 01:38:33 PM UTC 25 20211463 ps
T1786 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.257067593 Feb 08 01:38:30 PM UTC 25 Feb 08 01:38:33 PM UTC 25 552627593 ps
T192 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.1622881189 Feb 08 01:38:29 PM UTC 25 Feb 08 01:38:33 PM UTC 25 382523247 ps
T1787 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.2692563786 Feb 08 01:38:31 PM UTC 25 Feb 08 01:38:34 PM UTC 25 88433553 ps
T1788 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.3276643487 Feb 08 01:38:32 PM UTC 25 Feb 08 01:38:34 PM UTC 25 28993539 ps
T1789 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.1924859971 Feb 08 01:38:31 PM UTC 25 Feb 08 01:38:34 PM UTC 25 80681264 ps
T219 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.3247281612 Feb 08 01:38:33 PM UTC 25 Feb 08 01:38:35 PM UTC 25 36401244 ps
T1790 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2590859887 Feb 08 01:38:33 PM UTC 25 Feb 08 01:38:35 PM UTC 25 23655993 ps
T1791 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.2135397321 Feb 08 01:38:34 PM UTC 25 Feb 08 01:38:37 PM UTC 25 95692236 ps
T1792 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.755995812 Feb 08 01:38:34 PM UTC 25 Feb 08 01:38:37 PM UTC 25 56884368 ps
T1793 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2402987488 Feb 08 01:38:34 PM UTC 25 Feb 08 01:38:37 PM UTC 25 203742189 ps
T1794 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.852783837 Feb 08 01:38:35 PM UTC 25 Feb 08 01:38:37 PM UTC 25 18318925 ps
T1795 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2852505384 Feb 08 01:38:35 PM UTC 25 Feb 08 01:38:37 PM UTC 25 77377271 ps
T1796 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3544695570 Feb 08 01:38:35 PM UTC 25 Feb 08 01:38:38 PM UTC 25 158850733 ps
T221 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.3934043777 Feb 08 01:38:36 PM UTC 25 Feb 08 01:38:38 PM UTC 25 17222799 ps
T1797 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.2583988173 Feb 08 01:38:34 PM UTC 25 Feb 08 01:38:38 PM UTC 25 32127378 ps
T266 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.2699877166 Feb 08 01:38:34 PM UTC 25 Feb 08 01:38:38 PM UTC 25 1110983161 ps
T1798 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1300993680 Feb 08 01:38:36 PM UTC 25 Feb 08 01:38:38 PM UTC 25 19110619 ps
T1799 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.955483029 Feb 08 01:38:36 PM UTC 25 Feb 08 01:38:39 PM UTC 25 95757030 ps
T1800 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.3142640773 Feb 08 01:38:35 PM UTC 25 Feb 08 01:38:39 PM UTC 25 656462831 ps
T267 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.3556397738 Feb 08 01:38:35 PM UTC 25 Feb 08 01:38:39 PM UTC 25 766466103 ps
T1801 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.1862107673 Feb 08 01:38:38 PM UTC 25 Feb 08 01:38:41 PM UTC 25 22380939 ps
T199 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.2308092847 Feb 08 01:38:37 PM UTC 25 Feb 08 01:38:41 PM UTC 25 76680751 ps
T1802 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3207407811 Feb 08 01:38:39 PM UTC 25 Feb 08 01:38:41 PM UTC 25 24685075 ps
T1803 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.4148175306 Feb 08 01:38:38 PM UTC 25 Feb 08 01:38:41 PM UTC 25 24412411 ps
T1804 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2725615984 Feb 08 01:38:39 PM UTC 25 Feb 08 01:38:41 PM UTC 25 44573325 ps
T1805 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.2129087000 Feb 08 01:38:37 PM UTC 25 Feb 08 01:38:41 PM UTC 25 132528859 ps
T1806 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.3296168858 Feb 08 01:38:40 PM UTC 25 Feb 08 01:38:42 PM UTC 25 15666489 ps
T1807 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.2594811777 Feb 08 01:38:40 PM UTC 25 Feb 08 01:38:43 PM UTC 25 83140225 ps
T1808 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2075700127 Feb 08 01:38:40 PM UTC 25 Feb 08 01:38:43 PM UTC 25 42554058 ps
T1809 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.621224809 Feb 08 01:38:40 PM UTC 25 Feb 08 01:38:43 PM UTC 25 30823646 ps
T1810 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.3894079506 Feb 08 01:38:42 PM UTC 25 Feb 08 01:38:44 PM UTC 25 34428516 ps
T1811 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.1007909811 Feb 08 01:38:42 PM UTC 25 Feb 08 01:38:44 PM UTC 25 33504550 ps
T1812 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2209859982 Feb 08 01:38:42 PM UTC 25 Feb 08 01:38:44 PM UTC 25 74051062 ps
T1813 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.3675331732 Feb 08 01:38:41 PM UTC 25 Feb 08 01:38:44 PM UTC 25 74266955 ps
T200 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.3198869086 Feb 08 01:38:40 PM UTC 25 Feb 08 01:38:44 PM UTC 25 151869454 ps
T1814 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.1240850874 Feb 08 01:38:40 PM UTC 25 Feb 08 01:38:45 PM UTC 25 48905027 ps
T1815 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.3359314738 Feb 08 01:38:40 PM UTC 25 Feb 08 01:38:45 PM UTC 25 520851613 ps
T1816 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.880055013 Feb 08 01:38:43 PM UTC 25 Feb 08 01:38:45 PM UTC 25 101633581 ps
T1817 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.3376348089 Feb 08 01:38:44 PM UTC 25 Feb 08 01:38:46 PM UTC 25 58442349 ps
T1818 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.696202517 Feb 08 01:38:44 PM UTC 25 Feb 08 01:38:46 PM UTC 25 17753299 ps
T1819 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.325710914 Feb 08 01:38:43 PM UTC 25 Feb 08 01:38:47 PM UTC 25 1869307902 ps
T201 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.3876163681 Feb 08 01:38:43 PM UTC 25 Feb 08 01:38:47 PM UTC 25 126661249 ps
T1820 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1445563822 Feb 08 01:38:44 PM UTC 25 Feb 08 01:38:47 PM UTC 25 29080226 ps
T1821 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.1778693255 Feb 08 01:38:46 PM UTC 25 Feb 08 01:38:48 PM UTC 25 38750446 ps
T1822 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1497540740 Feb 08 01:38:45 PM UTC 25 Feb 08 01:38:48 PM UTC 25 216984610 ps
T1823 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2362771150 Feb 08 01:38:46 PM UTC 25 Feb 08 01:38:48 PM UTC 25 20807787 ps
T1824 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.3441349637 Feb 08 01:38:46 PM UTC 25 Feb 08 01:38:48 PM UTC 25 20696267 ps
T193 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.2441469492 Feb 08 01:38:46 PM UTC 25 Feb 08 01:38:49 PM UTC 25 88857640 ps
T1825 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.381642292 Feb 08 01:38:47 PM UTC 25 Feb 08 01:38:49 PM UTC 25 18281300 ps
T1826 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.750821134 Feb 08 01:38:47 PM UTC 25 Feb 08 01:38:50 PM UTC 25 15712129 ps
T1827 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.4190381829 Feb 08 01:38:47 PM UTC 25 Feb 08 01:38:50 PM UTC 25 17346262 ps
T1828 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1633040576 Feb 08 01:38:47 PM UTC 25 Feb 08 01:38:50 PM UTC 25 70265479 ps
T1829 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.3036264650 Feb 08 01:38:46 PM UTC 25 Feb 08 01:38:50 PM UTC 25 530665717 ps
T1830 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.3797255346 Feb 08 01:38:48 PM UTC 25 Feb 08 01:38:51 PM UTC 25 42587358 ps
T1831 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.929167923 Feb 08 01:38:48 PM UTC 25 Feb 08 01:38:51 PM UTC 25 79423736 ps
T1832 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.1360825690 Feb 08 01:38:48 PM UTC 25 Feb 08 01:38:51 PM UTC 25 43025069 ps
T1833 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.1475996227 Feb 08 01:38:49 PM UTC 25 Feb 08 01:38:51 PM UTC 25 27886613 ps
T1834 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.2509544095 Feb 08 01:38:50 PM UTC 25 Feb 08 01:38:52 PM UTC 25 16941332 ps
T1835 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.4014513254 Feb 08 01:38:50 PM UTC 25 Feb 08 01:38:52 PM UTC 25 24952259 ps
T1836 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.2707938986 Feb 08 01:38:50 PM UTC 25 Feb 08 01:38:52 PM UTC 25 47381749 ps
T1837 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.2964448138 Feb 08 01:38:50 PM UTC 25 Feb 08 01:38:52 PM UTC 25 24605413 ps
T1838 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.1943764633 Feb 08 01:38:51 PM UTC 25 Feb 08 01:38:54 PM UTC 25 19256545 ps
T1839 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.378359712 Feb 08 01:38:51 PM UTC 25 Feb 08 01:38:54 PM UTC 25 26413503 ps
T1840 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.2548967557 Feb 08 01:38:51 PM UTC 25 Feb 08 01:38:54 PM UTC 25 25612730 ps
T1841 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.2531738769 Feb 08 01:38:51 PM UTC 25 Feb 08 01:38:54 PM UTC 25 58272356 ps
T1842 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.3501837431 Feb 08 01:38:51 PM UTC 25 Feb 08 01:38:54 PM UTC 25 17794887 ps
T1843 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.285092868 Feb 08 01:38:52 PM UTC 25 Feb 08 01:38:54 PM UTC 25 25076190 ps
T1844 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.4092455542 Feb 08 01:38:52 PM UTC 25 Feb 08 01:38:54 PM UTC 25 45715181 ps
T1845 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.3275151763 Feb 08 01:38:52 PM UTC 25 Feb 08 01:38:54 PM UTC 25 16785136 ps
T1846 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.2940403346 Feb 08 01:38:53 PM UTC 25 Feb 08 01:38:55 PM UTC 25 19244858 ps
T1847 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.585692499 Feb 08 01:38:53 PM UTC 25 Feb 08 01:38:55 PM UTC 25 16447233 ps
T1848 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.1897758518 Feb 08 01:38:53 PM UTC 25 Feb 08 01:38:55 PM UTC 25 25876173 ps
T1849 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.2040803468 Feb 08 01:38:53 PM UTC 25 Feb 08 01:38:55 PM UTC 25 24970100 ps
T1850 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.307832370 Feb 08 01:38:53 PM UTC 25 Feb 08 01:38:55 PM UTC 25 43770475 ps
T1851 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.109741460 Feb 08 01:38:55 PM UTC 25 Feb 08 01:38:57 PM UTC 25 17980295 ps
T1852 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.1598354296 Feb 08 01:38:55 PM UTC 25 Feb 08 01:38:57 PM UTC 25 23153028 ps
T1853 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.355461062 Feb 08 01:38:55 PM UTC 25 Feb 08 01:38:57 PM UTC 25 17463991 ps
T1854 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.3083298902 Feb 08 01:38:55 PM UTC 25 Feb 08 01:38:57 PM UTC 25 31273005 ps
T1855 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.273647562 Feb 08 01:38:55 PM UTC 25 Feb 08 01:38:57 PM UTC 25 16282366 ps
T1856 /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.3802865474 Feb 08 01:38:55 PM UTC 25 Feb 08 01:38:57 PM UTC 25 26657822 ps

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_fmt_empty.4098645307
Short name T5
Test name
Test status
Simulation time 722285057 ps
CPU time 8.63 seconds
Started Feb 08 12:55:52 PM UTC 25
Finished Feb 08 12:56:02 PM UTC 25
Peak memory 282028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098645307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty.4098645307
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_glitch.3672996273
Short name T52
Test name
Test status
Simulation time 7686769342 ps
CPU time 12.92 seconds
Started Feb 08 12:55:56 PM UTC 25
Finished Feb 08 12:56:10 PM UTC 25
Peak memory 226780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672996273 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.3672996273
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_glitch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_host_stress_all.2098082964
Short name T23
Test name
Test status
Simulation time 11502120581 ps
CPU time 281.35 seconds
Started Feb 08 12:55:56 PM UTC 25
Finished Feb 08 01:00:41 PM UTC 25
Peak memory 874200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098082964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_host_stress_all.2098082964
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_host_error_intr.317105867
Short name T7
Test name
Test status
Simulation time 344713252 ps
CPU time 7.73 seconds
Started Feb 08 12:55:55 PM UTC 25
Finished Feb 08 12:56:04 PM UTC 25
Peak memory 282244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317105867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_host_error_intr.317105867
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_timeout.3474713795
Short name T46
Test name
Test status
Simulation time 3701298490 ps
CPU time 10.45 seconds
Started Feb 08 12:56:00 PM UTC 25
Finished Feb 08 12:56:12 PM UTC 25
Peak memory 232300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474713795 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_timeout.3474713795
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.660801319
Short name T104
Test name
Test status
Simulation time 140915698 ps
CPU time 2.72 seconds
Started Feb 08 01:38:01 PM UTC 25
Finished Feb 08 01:38:05 PM UTC 25
Peak memory 215340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660801319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.660801319
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_overflow.3342903789
Short name T79
Test name
Test status
Simulation time 1309079606 ps
CPU time 70.59 seconds
Started Feb 08 12:55:51 PM UTC 25
Finished Feb 08 12:57:03 PM UTC 25
Peak memory 544452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342903789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_host_fifo_overflow.3342903789
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_nack_txstretch.1081748179
Short name T60
Test name
Test status
Simulation time 525735488 ps
CPU time 2.07 seconds
Started Feb 08 12:56:45 PM UTC 25
Finished Feb 08 12:56:48 PM UTC 25
Peak memory 233168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081748179 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_txstretch.1081748179
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_host_override.598091828
Short name T98
Test name
Test status
Simulation time 58671601 ps
CPU time 1.02 seconds
Started Feb 08 12:56:48 PM UTC 25
Finished Feb 08 12:56:50 PM UTC 25
Peak memory 214516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598091828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overrid
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 2.i2c_host_override.598091828
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_host_may_nack.1307746262
Short name T13
Test name
Test status
Simulation time 1665469794 ps
CPU time 11.71 seconds
Started Feb 08 12:58:30 PM UTC 25
Finished Feb 08 12:58:43 PM UTC 25
Peak memory 216028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307746262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 4.i2c_host_may_nack.1307746262
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_tx.395319448
Short name T44
Test name
Test status
Simulation time 227403760 ps
CPU time 1.74 seconds
Started Feb 08 12:56:03 PM UTC 25
Finished Feb 08 12:56:06 PM UTC 25
Peak memory 213932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395319448 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_tx.395319448
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_sec_cm.3614193970
Short name T186
Test name
Test status
Simulation time 84617263 ps
CPU time 1.3 seconds
Started Feb 08 12:56:45 PM UTC 25
Finished Feb 08 12:56:47 PM UTC 25
Peak memory 246448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614193970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM
_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.3614193970
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull_addr.1950758745
Short name T49
Test name
Test status
Simulation time 945118057 ps
CPU time 3.62 seconds
Started Feb 08 12:57:56 PM UTC 25
Finished Feb 08 12:58:01 PM UTC 25
Peak memory 215916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950758745 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.1950758745
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_host_stress_all.1309938124
Short name T180
Test name
Test status
Simulation time 36103276249 ps
CPU time 252.64 seconds
Started Feb 08 01:02:02 PM UTC 25
Finished Feb 08 01:06:18 PM UTC 25
Peak memory 622360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309938124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_host_stress_all.1309938124
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.4291217311
Short name T101
Test name
Test status
Simulation time 73470575 ps
CPU time 0.96 seconds
Started Feb 08 01:37:57 PM UTC 25
Finished Feb 08 01:37:59 PM UTC 25
Peak memory 214744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291217311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.4291217311
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_stress_all.4226272790
Short name T176
Test name
Test status
Simulation time 90969707110 ps
CPU time 188.21 seconds
Started Feb 08 12:57:12 PM UTC 25
Finished Feb 08 01:00:23 PM UTC 25
Peak memory 1715716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226272790 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_all.4226272790
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.1528047788
Short name T109
Test name
Test status
Simulation time 158030463 ps
CPU time 3.26 seconds
Started Feb 08 01:38:09 PM UTC 25
Finished Feb 08 01:38:14 PM UTC 25
Peak memory 215332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528047788 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.1528047788
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull_addr.774075159
Short name T68
Test name
Test status
Simulation time 441975647 ps
CPU time 3.08 seconds
Started Feb 08 12:57:23 PM UTC 25
Finished Feb 08 12:57:27 PM UTC 25
Peak memory 215988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774075159 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.774075159
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_bad_addr.987314645
Short name T47
Test name
Test status
Simulation time 915318270 ps
CPU time 7.57 seconds
Started Feb 08 12:56:05 PM UTC 25
Finished Feb 08 12:56:14 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=987314645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.987314645
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_fmt.3591221945
Short name T240
Test name
Test status
Simulation time 152343251 ps
CPU time 1.93 seconds
Started Feb 08 12:58:40 PM UTC 25
Finished Feb 08 12:58:43 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591221945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt.3591221945
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_full.3248390477
Short name T31
Test name
Test status
Simulation time 7745872412 ps
CPU time 52.21 seconds
Started Feb 08 12:56:15 PM UTC 25
Finished Feb 08 12:57:09 PM UTC 25
Peak memory 351740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248390477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_host_fifo_full.3248390477
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_host_stress_all.2446783526
Short name T115
Test name
Test status
Simulation time 55253058185 ps
CPU time 1279.96 seconds
Started Feb 08 12:56:16 PM UTC 25
Finished Feb 08 01:17:49 PM UTC 25
Peak memory 2453520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446783526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_host_stress_all.2446783526
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull.789141266
Short name T57
Test name
Test status
Simulation time 2132991809 ps
CPU time 3.6 seconds
Started Feb 08 01:13:27 PM UTC 25
Finished Feb 08 01:13:32 PM UTC 25
Peak memory 226156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789141266 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_acqfull.789141266
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.3555507407
Short name T281
Test name
Test status
Simulation time 19782513 ps
CPU time 1.07 seconds
Started Feb 08 01:38:30 PM UTC 25
Finished Feb 08 01:38:33 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555507407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3555507407
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_stress_all.772528042
Short name T75
Test name
Test status
Simulation time 40679648942 ps
CPU time 61.8 seconds
Started Feb 08 12:56:05 PM UTC 25
Finished Feb 08 12:57:08 PM UTC 25
Peak memory 337492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772528042 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_all.772528042
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_rx.2602300906
Short name T78
Test name
Test status
Simulation time 128439051 ps
CPU time 6.1 seconds
Started Feb 08 12:56:49 PM UTC 25
Finished Feb 08 12:56:57 PM UTC 25
Peak memory 215920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602300906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.2602300906
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_alert_test.1415651367
Short name T94
Test name
Test status
Simulation time 50316613 ps
CPU time 0.92 seconds
Started Feb 08 12:56:11 PM UTC 25
Finished Feb 08 12:56:14 PM UTC 25
Peak memory 214932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415651367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.1415651367
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_host_stress_all.2761272887
Short name T41
Test name
Test status
Simulation time 21645186777 ps
CPU time 837.81 seconds
Started Feb 08 01:03:55 PM UTC 25
Finished Feb 08 01:18:02 PM UTC 25
Peak memory 2418372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761272887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_host_stress_all.2761272887
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_acq.350341768
Short name T162
Test name
Test status
Simulation time 543249530 ps
CPU time 1.68 seconds
Started Feb 08 12:56:07 PM UTC 25
Finished Feb 08 12:56:10 PM UTC 25
Peak memory 214532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350341768 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.350341768
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_may_nack.3673531653
Short name T247
Test name
Test status
Simulation time 1961484399 ps
CPU time 19.95 seconds
Started Feb 08 01:14:13 PM UTC 25
Finished Feb 08 01:14:34 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673531653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 22.i2c_host_may_nack.3673531653
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_host_may_nack.2253686255
Short name T245
Test name
Test status
Simulation time 719884699 ps
CPU time 9.05 seconds
Started Feb 08 12:57:52 PM UTC 25
Finished Feb 08 12:58:02 PM UTC 25
Peak memory 216172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253686255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 3.i2c_host_may_nack.2253686255
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.1186346144
Short name T181
Test name
Test status
Simulation time 142500508 ps
CPU time 1.03 seconds
Started Feb 08 01:38:21 PM UTC 25
Finished Feb 08 01:38:23 PM UTC 25
Peak memory 214564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186346144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1186346144
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_mode_toggle.3619102140
Short name T258
Test name
Test status
Simulation time 294889897 ps
CPU time 3.07 seconds
Started Feb 08 01:14:54 PM UTC 25
Finished Feb 08 01:14:58 PM UTC 25
Peak memory 215928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619102140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_t
oggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_host_mode_toggle.3619102140
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_watermark.3520973574
Short name T400
Test name
Test status
Simulation time 10318862207 ps
CPU time 167 seconds
Started Feb 08 01:00:37 PM UTC 25
Finished Feb 08 01:03:27 PM UTC 25
Peak memory 843272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520973574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 7.i2c_host_fifo_watermark.3520973574
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_smoke.3983273169
Short name T85
Test name
Test status
Simulation time 5897163657 ps
CPU time 44.78 seconds
Started Feb 08 01:03:56 PM UTC 25
Finished Feb 08 01:04:42 PM UTC 25
Peak memory 233044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983273169 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smoke.3983273169
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_override.2785726624
Short name T142
Test name
Test status
Simulation time 60894666 ps
CPU time 0.88 seconds
Started Feb 08 01:09:46 PM UTC 25
Finished Feb 08 01:09:48 PM UTC 25
Peak memory 213696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785726624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 17.i2c_host_override.2785726624
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_fmt.362185198
Short name T244
Test name
Test status
Simulation time 242463048 ps
CPU time 1.5 seconds
Started Feb 08 01:21:46 PM UTC 25
Finished Feb 08 01:21:48 PM UTC 25
Peak memory 214516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362185198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fmt.362185198
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.600065813
Short name T1744
Test name
Test status
Simulation time 48532082869 ps
CPU time 530.14 seconds
Started Feb 08 01:36:27 PM UTC 25
Finished Feb 08 01:45:23 PM UTC 25
Peak memory 3202808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600065813 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_all.600065813
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.998163623
Short name T233
Test name
Test status
Simulation time 399894626 ps
CPU time 1.45 seconds
Started Feb 08 01:37:29 PM UTC 25
Finished Feb 08 01:37:32 PM UTC 25
Peak memory 213924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998163623 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_tx.998163623
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_host_stress_all.1094720321
Short name T27
Test name
Test status
Simulation time 137881895012 ps
CPU time 276.29 seconds
Started Feb 08 01:06:44 PM UTC 25
Finished Feb 08 01:11:24 PM UTC 25
Peak memory 1349328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094720321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_host_stress_all.1094720321
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.1377687929
Short name T102
Test name
Test status
Simulation time 98114671 ps
CPU time 2.41 seconds
Started Feb 08 01:37:56 PM UTC 25
Finished Feb 08 01:38:00 PM UTC 25
Peak memory 215404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377687929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1377687929
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.3568448177
Short name T130
Test name
Test status
Simulation time 60333693 ps
CPU time 1.01 seconds
Started Feb 08 01:38:01 PM UTC 25
Finished Feb 08 01:38:03 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568448177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3568448177
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_host_smoke.4005466862
Short name T26
Test name
Test status
Simulation time 3107851210 ps
CPU time 27.45 seconds
Started Feb 08 12:55:49 PM UTC 25
Finished Feb 08 12:56:18 PM UTC 25
Peak memory 429572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005466862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_host_smoke.4005466862
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_acq.3994518641
Short name T9
Test name
Test status
Simulation time 1786869460 ps
CPU time 2.25 seconds
Started Feb 08 12:56:01 PM UTC 25
Finished Feb 08 12:56:05 PM UTC 25
Peak memory 215920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994518641 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_acq.3994518641
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_stress_rd.3652178977
Short name T151
Test name
Test status
Simulation time 5255389703 ps
CPU time 66.45 seconds
Started Feb 08 12:55:57 PM UTC 25
Finished Feb 08 12:57:06 PM UTC 25
Peak memory 228312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652178977 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_rd.3652178977
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_tx_stretch_ctrl.3812038198
Short name T69
Test name
Test status
Simulation time 58499200 ps
CPU time 1.74 seconds
Started Feb 08 12:56:09 PM UTC 25
Finished Feb 08 12:56:12 PM UTC 25
Peak memory 214348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812038198 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.3812038198
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_host_may_nack.1463958238
Short name T249
Test name
Test status
Simulation time 1098482656 ps
CPU time 8.64 seconds
Started Feb 08 01:07:14 PM UTC 25
Finished Feb 08 01:07:24 PM UTC 25
Peak memory 215980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463958238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 14.i2c_host_may_nack.1463958238
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.975209232
Short name T105
Test name
Test status
Simulation time 146694428 ps
CPU time 2.75 seconds
Started Feb 08 01:38:01 PM UTC 25
Finished Feb 08 01:38:05 PM UTC 25
Peak memory 215264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975209232 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.975209232
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.1622881189
Short name T192
Test name
Test status
Simulation time 382523247 ps
CPU time 2.74 seconds
Started Feb 08 01:38:29 PM UTC 25
Finished Feb 08 01:38:33 PM UTC 25
Peak memory 215452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622881189 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1622881189
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.2308092847
Short name T199
Test name
Test status
Simulation time 76680751 ps
CPU time 2.16 seconds
Started Feb 08 01:38:37 PM UTC 25
Finished Feb 08 01:38:41 PM UTC 25
Peak memory 215360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308092847 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2308092847
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_error_intr.2895801257
Short name T24
Test name
Test status
Simulation time 1253240532 ps
CPU time 3.57 seconds
Started Feb 08 01:25:07 PM UTC 25
Finished Feb 08 01:25:12 PM UTC 25
Peak memory 226324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895801257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_host_error_intr.2895801257
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.3699570113
Short name T191
Test name
Test status
Simulation time 121063713 ps
CPU time 1.92 seconds
Started Feb 08 01:38:04 PM UTC 25
Finished Feb 08 01:38:08 PM UTC 25
Peak memory 214760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699570113 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3699570113
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.373964735
Short name T194
Test name
Test status
Simulation time 664666428 ps
CPU time 1.83 seconds
Started Feb 08 01:38:17 PM UTC 25
Finished Feb 08 01:38:20 PM UTC 25
Peak memory 214712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373964735 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.373964735
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_hrst.3764772232
Short name T178
Test name
Test status
Simulation time 4197151631 ps
CPU time 3.56 seconds
Started Feb 08 01:04:27 PM UTC 25
Finished Feb 08 01:04:32 PM UTC 25
Peak memory 233024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764772232 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_hrst.3764772232
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_host_mode_toggle.1598747177
Short name T30
Test name
Test status
Simulation time 267626116 ps
CPU time 1.62 seconds
Started Feb 08 01:09:34 PM UTC 25
Finished Feb 08 01:09:37 PM UTC 25
Peak memory 226104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598747177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_t
oggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_host_mode_toggle.1598747177
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.1116681454
Short name T1752
Test name
Test status
Simulation time 449627087 ps
CPU time 1.92 seconds
Started Feb 08 01:37:59 PM UTC 25
Finished Feb 08 01:38:02 PM UTC 25
Peak memory 214684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116681454 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1116681454
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.427900593
Short name T220
Test name
Test status
Simulation time 66932757 ps
CPU time 3.53 seconds
Started Feb 08 01:37:58 PM UTC 25
Finished Feb 08 01:38:03 PM UTC 25
Peak memory 215084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427900593 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.427900593
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.3214360734
Short name T203
Test name
Test status
Simulation time 45862116 ps
CPU time 1.12 seconds
Started Feb 08 01:37:57 PM UTC 25
Finished Feb 08 01:38:00 PM UTC 25
Peak memory 214616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214360734 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3214360734
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2136674574
Short name T184
Test name
Test status
Simulation time 26515739 ps
CPU time 1.25 seconds
Started Feb 08 01:38:00 PM UTC 25
Finished Feb 08 01:38:02 PM UTC 25
Peak memory 214744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136674574
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2136674574
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.1791630500
Short name T279
Test name
Test status
Simulation time 41418691 ps
CPU time 1.01 seconds
Started Feb 08 01:37:56 PM UTC 25
Finished Feb 08 01:37:58 PM UTC 25
Peak memory 214424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791630500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1791630500
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1098684950
Short name T222
Test name
Test status
Simulation time 139808259 ps
CPU time 1.05 seconds
Started Feb 08 01:38:00 PM UTC 25
Finished Feb 08 01:38:02 PM UTC 25
Peak memory 214740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098684950 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_outstanding.1098684950
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.2464725913
Short name T100
Test name
Test status
Simulation time 80225431 ps
CPU time 1.62 seconds
Started Feb 08 01:37:56 PM UTC 25
Finished Feb 08 01:37:59 PM UTC 25
Peak memory 214752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464725913 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.2464725913
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.3368837387
Short name T106
Test name
Test status
Simulation time 292763738 ps
CPU time 1.7 seconds
Started Feb 08 01:38:03 PM UTC 25
Finished Feb 08 01:38:06 PM UTC 25
Peak memory 214652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368837387 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3368837387
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.3821285511
Short name T108
Test name
Test status
Simulation time 1032599659 ps
CPU time 5.61 seconds
Started Feb 08 01:38:03 PM UTC 25
Finished Feb 08 01:38:10 PM UTC 25
Peak memory 215260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821285511 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3821285511
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.2345542079
Short name T103
Test name
Test status
Simulation time 84477552 ps
CPU time 1.11 seconds
Started Feb 08 01:38:01 PM UTC 25
Finished Feb 08 01:38:03 PM UTC 25
Peak memory 214616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345542079 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2345542079
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3864214016
Short name T204
Test name
Test status
Simulation time 36704923 ps
CPU time 1.14 seconds
Started Feb 08 01:38:04 PM UTC 25
Finished Feb 08 01:38:07 PM UTC 25
Peak memory 214808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864214016
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.3864214016
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.2061414582
Short name T1753
Test name
Test status
Simulation time 216331626 ps
CPU time 1.12 seconds
Started Feb 08 01:38:03 PM UTC 25
Finished Feb 08 01:38:05 PM UTC 25
Peak memory 214744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061414582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2061414582
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3063267587
Short name T128
Test name
Test status
Simulation time 36019383 ps
CPU time 1.11 seconds
Started Feb 08 01:38:03 PM UTC 25
Finished Feb 08 01:38:05 PM UTC 25
Peak memory 214800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063267587 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_outstanding.3063267587
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1488337225
Short name T1782
Test name
Test status
Simulation time 36896115 ps
CPU time 2.26 seconds
Started Feb 08 01:38:29 PM UTC 25
Finished Feb 08 01:38:33 PM UTC 25
Peak memory 225636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488337225
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.1488337225
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.2302818947
Short name T1778
Test name
Test status
Simulation time 38319760 ps
CPU time 0.91 seconds
Started Feb 08 01:38:28 PM UTC 25
Finished Feb 08 01:38:30 PM UTC 25
Peak memory 214872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302818947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.2302818947
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.2249510712
Short name T285
Test name
Test status
Simulation time 115695308 ps
CPU time 1.02 seconds
Started Feb 08 01:38:28 PM UTC 25
Finished Feb 08 01:38:30 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249510712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2249510712
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3302756102
Short name T1780
Test name
Test status
Simulation time 75131352 ps
CPU time 1.26 seconds
Started Feb 08 01:38:29 PM UTC 25
Finished Feb 08 01:38:32 PM UTC 25
Peak memory 214580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302756102 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_outstanding.3302756102
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.2489264226
Short name T1779
Test name
Test status
Simulation time 56124048 ps
CPU time 2.68 seconds
Started Feb 08 01:38:26 PM UTC 25
Finished Feb 08 01:38:30 PM UTC 25
Peak memory 215336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489264226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2489264226
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.2871997038
Short name T1781
Test name
Test status
Simulation time 341141888 ps
CPU time 2.91 seconds
Started Feb 08 01:38:28 PM UTC 25
Finished Feb 08 01:38:32 PM UTC 25
Peak memory 215268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871997038 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.2871997038
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.926290733
Short name T1785
Test name
Test status
Simulation time 20211463 ps
CPU time 1.37 seconds
Started Feb 08 01:38:31 PM UTC 25
Finished Feb 08 01:38:33 PM UTC 25
Peak memory 214748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926290733
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.926290733
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.1371723619
Short name T1783
Test name
Test status
Simulation time 44909028 ps
CPU time 1.14 seconds
Started Feb 08 01:38:30 PM UTC 25
Finished Feb 08 01:38:33 PM UTC 25
Peak memory 214872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371723619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1371723619
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.257067593
Short name T1786
Test name
Test status
Simulation time 552627593 ps
CPU time 1.45 seconds
Started Feb 08 01:38:30 PM UTC 25
Finished Feb 08 01:38:33 PM UTC 25
Peak memory 214652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257067593 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_outstanding.257067593
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.3780654481
Short name T1784
Test name
Test status
Simulation time 86160312 ps
CPU time 2.52 seconds
Started Feb 08 01:38:29 PM UTC 25
Finished Feb 08 01:38:33 PM UTC 25
Peak memory 215364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780654481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3780654481
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2402987488
Short name T1793
Test name
Test status
Simulation time 203742189 ps
CPU time 1.35 seconds
Started Feb 08 01:38:34 PM UTC 25
Finished Feb 08 01:38:37 PM UTC 25
Peak memory 214696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402987488
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.2402987488
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.3247281612
Short name T219
Test name
Test status
Simulation time 36401244 ps
CPU time 1.11 seconds
Started Feb 08 01:38:33 PM UTC 25
Finished Feb 08 01:38:35 PM UTC 25
Peak memory 214872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247281612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3247281612
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.3276643487
Short name T1788
Test name
Test status
Simulation time 28993539 ps
CPU time 1.02 seconds
Started Feb 08 01:38:32 PM UTC 25
Finished Feb 08 01:38:34 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276643487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3276643487
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2590859887
Short name T1790
Test name
Test status
Simulation time 23655993 ps
CPU time 1.18 seconds
Started Feb 08 01:38:33 PM UTC 25
Finished Feb 08 01:38:35 PM UTC 25
Peak memory 214580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590859887 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_outstanding.2590859887
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.1924859971
Short name T1789
Test name
Test status
Simulation time 80681264 ps
CPU time 2.29 seconds
Started Feb 08 01:38:31 PM UTC 25
Finished Feb 08 01:38:34 PM UTC 25
Peak memory 215360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924859971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1924859971
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.2692563786
Short name T1787
Test name
Test status
Simulation time 88433553 ps
CPU time 1.84 seconds
Started Feb 08 01:38:31 PM UTC 25
Finished Feb 08 01:38:34 PM UTC 25
Peak memory 214752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692563786 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2692563786
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3544695570
Short name T1796
Test name
Test status
Simulation time 158850733 ps
CPU time 1.67 seconds
Started Feb 08 01:38:35 PM UTC 25
Finished Feb 08 01:38:38 PM UTC 25
Peak memory 214876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544695570
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.3544695570
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.755995812
Short name T1792
Test name
Test status
Simulation time 56884368 ps
CPU time 1.02 seconds
Started Feb 08 01:38:34 PM UTC 25
Finished Feb 08 01:38:37 PM UTC 25
Peak memory 214800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755995812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_T
EST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.755995812
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.2135397321
Short name T1791
Test name
Test status
Simulation time 95692236 ps
CPU time 0.99 seconds
Started Feb 08 01:38:34 PM UTC 25
Finished Feb 08 01:38:37 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135397321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2135397321
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2852505384
Short name T1795
Test name
Test status
Simulation time 77377271 ps
CPU time 1.26 seconds
Started Feb 08 01:38:35 PM UTC 25
Finished Feb 08 01:38:37 PM UTC 25
Peak memory 214580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852505384 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_outstanding.2852505384
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.2583988173
Short name T1797
Test name
Test status
Simulation time 32127378 ps
CPU time 2.77 seconds
Started Feb 08 01:38:34 PM UTC 25
Finished Feb 08 01:38:38 PM UTC 25
Peak memory 215392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583988173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2583988173
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.2699877166
Short name T266
Test name
Test status
Simulation time 1110983161 ps
CPU time 2.72 seconds
Started Feb 08 01:38:34 PM UTC 25
Finished Feb 08 01:38:38 PM UTC 25
Peak memory 215200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699877166 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.2699877166
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.955483029
Short name T1799
Test name
Test status
Simulation time 95757030 ps
CPU time 1.84 seconds
Started Feb 08 01:38:36 PM UTC 25
Finished Feb 08 01:38:39 PM UTC 25
Peak memory 224688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955483029
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.955483029
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.3934043777
Short name T221
Test name
Test status
Simulation time 17222799 ps
CPU time 1.09 seconds
Started Feb 08 01:38:36 PM UTC 25
Finished Feb 08 01:38:38 PM UTC 25
Peak memory 214712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934043777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.3934043777
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.852783837
Short name T1794
Test name
Test status
Simulation time 18318925 ps
CPU time 1.03 seconds
Started Feb 08 01:38:35 PM UTC 25
Finished Feb 08 01:38:37 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852783837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.852783837
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1300993680
Short name T1798
Test name
Test status
Simulation time 19110619 ps
CPU time 1.23 seconds
Started Feb 08 01:38:36 PM UTC 25
Finished Feb 08 01:38:38 PM UTC 25
Peak memory 214408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300993680 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_outstanding.1300993680
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.3142640773
Short name T1800
Test name
Test status
Simulation time 656462831 ps
CPU time 3.09 seconds
Started Feb 08 01:38:35 PM UTC 25
Finished Feb 08 01:38:39 PM UTC 25
Peak memory 225644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142640773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3142640773
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.3556397738
Short name T267
Test name
Test status
Simulation time 766466103 ps
CPU time 3.2 seconds
Started Feb 08 01:38:35 PM UTC 25
Finished Feb 08 01:38:39 PM UTC 25
Peak memory 215224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556397738 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3556397738
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3207407811
Short name T1802
Test name
Test status
Simulation time 24685075 ps
CPU time 0.87 seconds
Started Feb 08 01:38:39 PM UTC 25
Finished Feb 08 01:38:41 PM UTC 25
Peak memory 214932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207407811
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3207407811
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.4148175306
Short name T1803
Test name
Test status
Simulation time 24412411 ps
CPU time 1.14 seconds
Started Feb 08 01:38:38 PM UTC 25
Finished Feb 08 01:38:41 PM UTC 25
Peak memory 214872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148175306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.4148175306
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.1862107673
Short name T1801
Test name
Test status
Simulation time 22380939 ps
CPU time 0.96 seconds
Started Feb 08 01:38:38 PM UTC 25
Finished Feb 08 01:38:41 PM UTC 25
Peak memory 214676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862107673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1862107673
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2725615984
Short name T1804
Test name
Test status
Simulation time 44573325 ps
CPU time 1.58 seconds
Started Feb 08 01:38:39 PM UTC 25
Finished Feb 08 01:38:41 PM UTC 25
Peak memory 214740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725615984 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_outstanding.2725615984
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.2129087000
Short name T1805
Test name
Test status
Simulation time 132528859 ps
CPU time 2.86 seconds
Started Feb 08 01:38:37 PM UTC 25
Finished Feb 08 01:38:41 PM UTC 25
Peak memory 215492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129087000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2129087000
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.621224809
Short name T1809
Test name
Test status
Simulation time 30823646 ps
CPU time 1.66 seconds
Started Feb 08 01:38:40 PM UTC 25
Finished Feb 08 01:38:43 PM UTC 25
Peak memory 214768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621224809
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.621224809
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.2594811777
Short name T1807
Test name
Test status
Simulation time 83140225 ps
CPU time 1.14 seconds
Started Feb 08 01:38:40 PM UTC 25
Finished Feb 08 01:38:43 PM UTC 25
Peak memory 214872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594811777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2594811777
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.3296168858
Short name T1806
Test name
Test status
Simulation time 15666489 ps
CPU time 1.01 seconds
Started Feb 08 01:38:40 PM UTC 25
Finished Feb 08 01:38:42 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296168858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3296168858
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.2075700127
Short name T1808
Test name
Test status
Simulation time 42554058 ps
CPU time 1.14 seconds
Started Feb 08 01:38:40 PM UTC 25
Finished Feb 08 01:38:43 PM UTC 25
Peak memory 214580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075700127 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_outstanding.2075700127
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.3359314738
Short name T1815
Test name
Test status
Simulation time 520851613 ps
CPU time 3.99 seconds
Started Feb 08 01:38:40 PM UTC 25
Finished Feb 08 01:38:45 PM UTC 25
Peak memory 215328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359314738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.3359314738
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.3198869086
Short name T200
Test name
Test status
Simulation time 151869454 ps
CPU time 3.11 seconds
Started Feb 08 01:38:40 PM UTC 25
Finished Feb 08 01:38:44 PM UTC 25
Peak memory 215260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198869086 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.3198869086
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.880055013
Short name T1816
Test name
Test status
Simulation time 101633581 ps
CPU time 1.29 seconds
Started Feb 08 01:38:43 PM UTC 25
Finished Feb 08 01:38:45 PM UTC 25
Peak memory 214388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880055013
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.880055013
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.3894079506
Short name T1810
Test name
Test status
Simulation time 34428516 ps
CPU time 0.91 seconds
Started Feb 08 01:38:42 PM UTC 25
Finished Feb 08 01:38:44 PM UTC 25
Peak memory 214684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894079506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3894079506
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.1007909811
Short name T1811
Test name
Test status
Simulation time 33504550 ps
CPU time 1.05 seconds
Started Feb 08 01:38:42 PM UTC 25
Finished Feb 08 01:38:44 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007909811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1007909811
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2209859982
Short name T1812
Test name
Test status
Simulation time 74051062 ps
CPU time 1.39 seconds
Started Feb 08 01:38:42 PM UTC 25
Finished Feb 08 01:38:44 PM UTC 25
Peak memory 214580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209859982 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_outstanding.2209859982
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.1240850874
Short name T1814
Test name
Test status
Simulation time 48905027 ps
CPU time 3.04 seconds
Started Feb 08 01:38:40 PM UTC 25
Finished Feb 08 01:38:45 PM UTC 25
Peak memory 215456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240850874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1240850874
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.3675331732
Short name T1813
Test name
Test status
Simulation time 74266955 ps
CPU time 1.48 seconds
Started Feb 08 01:38:41 PM UTC 25
Finished Feb 08 01:38:44 PM UTC 25
Peak memory 214712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675331732 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3675331732
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1497540740
Short name T1822
Test name
Test status
Simulation time 216984610 ps
CPU time 1.18 seconds
Started Feb 08 01:38:45 PM UTC 25
Finished Feb 08 01:38:48 PM UTC 25
Peak memory 214684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497540740
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1497540740
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.3376348089
Short name T1817
Test name
Test status
Simulation time 58442349 ps
CPU time 0.99 seconds
Started Feb 08 01:38:44 PM UTC 25
Finished Feb 08 01:38:46 PM UTC 25
Peak memory 214872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376348089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3376348089
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.696202517
Short name T1818
Test name
Test status
Simulation time 17753299 ps
CPU time 1.08 seconds
Started Feb 08 01:38:44 PM UTC 25
Finished Feb 08 01:38:46 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696202517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.696202517
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1445563822
Short name T1820
Test name
Test status
Simulation time 29080226 ps
CPU time 1.64 seconds
Started Feb 08 01:38:44 PM UTC 25
Finished Feb 08 01:38:47 PM UTC 25
Peak memory 214532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445563822 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_outstanding.1445563822
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.325710914
Short name T1819
Test name
Test status
Simulation time 1869307902 ps
CPU time 2.72 seconds
Started Feb 08 01:38:43 PM UTC 25
Finished Feb 08 01:38:47 PM UTC 25
Peak memory 215112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325710914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.325710914
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.3876163681
Short name T201
Test name
Test status
Simulation time 126661249 ps
CPU time 2.87 seconds
Started Feb 08 01:38:43 PM UTC 25
Finished Feb 08 01:38:47 PM UTC 25
Peak memory 215268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876163681 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3876163681
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1633040576
Short name T1828
Test name
Test status
Simulation time 70265479 ps
CPU time 1.22 seconds
Started Feb 08 01:38:47 PM UTC 25
Finished Feb 08 01:38:50 PM UTC 25
Peak memory 214864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633040576
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.1633040576
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.3441349637
Short name T1824
Test name
Test status
Simulation time 20696267 ps
CPU time 1.2 seconds
Started Feb 08 01:38:46 PM UTC 25
Finished Feb 08 01:38:48 PM UTC 25
Peak memory 214872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441349637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3441349637
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.1778693255
Short name T1821
Test name
Test status
Simulation time 38750446 ps
CPU time 0.92 seconds
Started Feb 08 01:38:46 PM UTC 25
Finished Feb 08 01:38:48 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778693255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1778693255
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2362771150
Short name T1823
Test name
Test status
Simulation time 20807787 ps
CPU time 1.13 seconds
Started Feb 08 01:38:46 PM UTC 25
Finished Feb 08 01:38:48 PM UTC 25
Peak memory 214580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362771150 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_outstanding.2362771150
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.3036264650
Short name T1829
Test name
Test status
Simulation time 530665717 ps
CPU time 3.57 seconds
Started Feb 08 01:38:46 PM UTC 25
Finished Feb 08 01:38:50 PM UTC 25
Peak memory 215428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036264650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3036264650
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.2441469492
Short name T193
Test name
Test status
Simulation time 88857640 ps
CPU time 1.76 seconds
Started Feb 08 01:38:46 PM UTC 25
Finished Feb 08 01:38:49 PM UTC 25
Peak memory 214660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441469492 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2441469492
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.2026655193
Short name T1756
Test name
Test status
Simulation time 102866868 ps
CPU time 1.59 seconds
Started Feb 08 01:38:07 PM UTC 25
Finished Feb 08 01:38:09 PM UTC 25
Peak memory 214684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026655193 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2026655193
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.2997420746
Short name T1757
Test name
Test status
Simulation time 473901700 ps
CPU time 3.01 seconds
Started Feb 08 01:38:07 PM UTC 25
Finished Feb 08 01:38:11 PM UTC 25
Peak memory 215192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997420746 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2997420746
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.4250063151
Short name T214
Test name
Test status
Simulation time 21323725 ps
CPU time 1.09 seconds
Started Feb 08 01:38:06 PM UTC 25
Finished Feb 08 01:38:08 PM UTC 25
Peak memory 214616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250063151 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.4250063151
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.945916583
Short name T211
Test name
Test status
Simulation time 80368741 ps
CPU time 1.47 seconds
Started Feb 08 01:38:09 PM UTC 25
Finished Feb 08 01:38:12 PM UTC 25
Peak memory 214828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945916583
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.945916583
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.3497214194
Short name T1755
Test name
Test status
Simulation time 175928485 ps
CPU time 0.9 seconds
Started Feb 08 01:38:07 PM UTC 25
Finished Feb 08 01:38:09 PM UTC 25
Peak memory 214744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497214194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3497214194
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.3096464512
Short name T1754
Test name
Test status
Simulation time 19232218 ps
CPU time 1.03 seconds
Started Feb 08 01:38:06 PM UTC 25
Finished Feb 08 01:38:08 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096464512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3096464512
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2570679689
Short name T223
Test name
Test status
Simulation time 81336447 ps
CPU time 1.43 seconds
Started Feb 08 01:38:08 PM UTC 25
Finished Feb 08 01:38:10 PM UTC 25
Peak memory 214752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570679689 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_outstanding.2570679689
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.1292019157
Short name T107
Test name
Test status
Simulation time 77632869 ps
CPU time 2.45 seconds
Started Feb 08 01:38:04 PM UTC 25
Finished Feb 08 01:38:08 PM UTC 25
Peak memory 215432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292019157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1292019157
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.381642292
Short name T1825
Test name
Test status
Simulation time 18281300 ps
CPU time 0.92 seconds
Started Feb 08 01:38:47 PM UTC 25
Finished Feb 08 01:38:49 PM UTC 25
Peak memory 214684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381642292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.381642292
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.4190381829
Short name T1827
Test name
Test status
Simulation time 17346262 ps
CPU time 1.05 seconds
Started Feb 08 01:38:47 PM UTC 25
Finished Feb 08 01:38:50 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190381829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.4190381829
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.750821134
Short name T1826
Test name
Test status
Simulation time 15712129 ps
CPU time 0.94 seconds
Started Feb 08 01:38:47 PM UTC 25
Finished Feb 08 01:38:50 PM UTC 25
Peak memory 214548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750821134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.750821134
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.929167923
Short name T1831
Test name
Test status
Simulation time 79423736 ps
CPU time 1 seconds
Started Feb 08 01:38:48 PM UTC 25
Finished Feb 08 01:38:51 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929167923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.929167923
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.1360825690
Short name T1832
Test name
Test status
Simulation time 43025069 ps
CPU time 1.04 seconds
Started Feb 08 01:38:48 PM UTC 25
Finished Feb 08 01:38:51 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360825690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.1360825690
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.3797255346
Short name T1830
Test name
Test status
Simulation time 42587358 ps
CPU time 0.98 seconds
Started Feb 08 01:38:48 PM UTC 25
Finished Feb 08 01:38:51 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797255346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3797255346
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.1475996227
Short name T1833
Test name
Test status
Simulation time 27886613 ps
CPU time 1.03 seconds
Started Feb 08 01:38:49 PM UTC 25
Finished Feb 08 01:38:51 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475996227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1475996227
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.4014513254
Short name T1835
Test name
Test status
Simulation time 24952259 ps
CPU time 1.07 seconds
Started Feb 08 01:38:50 PM UTC 25
Finished Feb 08 01:38:52 PM UTC 25
Peak memory 213860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014513254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.4014513254
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.2509544095
Short name T1834
Test name
Test status
Simulation time 16941332 ps
CPU time 1.01 seconds
Started Feb 08 01:38:50 PM UTC 25
Finished Feb 08 01:38:52 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509544095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2509544095
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.2707938986
Short name T1836
Test name
Test status
Simulation time 47381749 ps
CPU time 1.01 seconds
Started Feb 08 01:38:50 PM UTC 25
Finished Feb 08 01:38:52 PM UTC 25
Peak memory 213692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707938986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2707938986
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.1024192589
Short name T215
Test name
Test status
Simulation time 157465091 ps
CPU time 2.52 seconds
Started Feb 08 01:38:11 PM UTC 25
Finished Feb 08 01:38:15 PM UTC 25
Peak memory 215196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024192589 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1024192589
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.1973262666
Short name T153
Test name
Test status
Simulation time 476207053 ps
CPU time 3.5 seconds
Started Feb 08 01:38:10 PM UTC 25
Finished Feb 08 01:38:15 PM UTC 25
Peak memory 215076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973262666 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1973262666
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.2881651321
Short name T1759
Test name
Test status
Simulation time 33278699 ps
CPU time 0.94 seconds
Started Feb 08 01:38:10 PM UTC 25
Finished Feb 08 01:38:12 PM UTC 25
Peak memory 214740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881651321 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2881651321
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3441719515
Short name T212
Test name
Test status
Simulation time 67886198 ps
CPU time 1.37 seconds
Started Feb 08 01:38:13 PM UTC 25
Finished Feb 08 01:38:15 PM UTC 25
Peak memory 214716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441719515
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3441719515
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.3054926381
Short name T224
Test name
Test status
Simulation time 16945069 ps
CPU time 1.06 seconds
Started Feb 08 01:38:10 PM UTC 25
Finished Feb 08 01:38:13 PM UTC 25
Peak memory 214744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054926381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3054926381
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.1222097148
Short name T1758
Test name
Test status
Simulation time 45419160 ps
CPU time 0.92 seconds
Started Feb 08 01:38:09 PM UTC 25
Finished Feb 08 01:38:11 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222097148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.1222097148
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2197834698
Short name T225
Test name
Test status
Simulation time 22373993 ps
CPU time 1.23 seconds
Started Feb 08 01:38:12 PM UTC 25
Finished Feb 08 01:38:14 PM UTC 25
Peak memory 214740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197834698 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_outstanding.2197834698
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.1554508436
Short name T195
Test name
Test status
Simulation time 46484317 ps
CPU time 2.9 seconds
Started Feb 08 01:38:09 PM UTC 25
Finished Feb 08 01:38:13 PM UTC 25
Peak memory 215432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554508436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1554508436
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.2964448138
Short name T1837
Test name
Test status
Simulation time 24605413 ps
CPU time 1.09 seconds
Started Feb 08 01:38:50 PM UTC 25
Finished Feb 08 01:38:52 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964448138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2964448138
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.2548967557
Short name T1840
Test name
Test status
Simulation time 25612730 ps
CPU time 1.14 seconds
Started Feb 08 01:38:51 PM UTC 25
Finished Feb 08 01:38:54 PM UTC 25
Peak memory 214396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548967557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2548967557
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.1943764633
Short name T1838
Test name
Test status
Simulation time 19256545 ps
CPU time 1.1 seconds
Started Feb 08 01:38:51 PM UTC 25
Finished Feb 08 01:38:54 PM UTC 25
Peak memory 214344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943764633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.1943764633
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.378359712
Short name T1839
Test name
Test status
Simulation time 26413503 ps
CPU time 1 seconds
Started Feb 08 01:38:51 PM UTC 25
Finished Feb 08 01:38:54 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378359712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.378359712
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.3501837431
Short name T1842
Test name
Test status
Simulation time 17794887 ps
CPU time 1.04 seconds
Started Feb 08 01:38:51 PM UTC 25
Finished Feb 08 01:38:54 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501837431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3501837431
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.2531738769
Short name T1841
Test name
Test status
Simulation time 58272356 ps
CPU time 1.02 seconds
Started Feb 08 01:38:51 PM UTC 25
Finished Feb 08 01:38:54 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531738769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.2531738769
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.4092455542
Short name T1844
Test name
Test status
Simulation time 45715181 ps
CPU time 1.07 seconds
Started Feb 08 01:38:52 PM UTC 25
Finished Feb 08 01:38:54 PM UTC 25
Peak memory 214612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092455542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.4092455542
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.3275151763
Short name T1845
Test name
Test status
Simulation time 16785136 ps
CPU time 1.01 seconds
Started Feb 08 01:38:52 PM UTC 25
Finished Feb 08 01:38:54 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275151763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3275151763
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.285092868
Short name T1843
Test name
Test status
Simulation time 25076190 ps
CPU time 0.94 seconds
Started Feb 08 01:38:52 PM UTC 25
Finished Feb 08 01:38:54 PM UTC 25
Peak memory 214488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285092868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.285092868
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.2940403346
Short name T1846
Test name
Test status
Simulation time 19244858 ps
CPU time 1.09 seconds
Started Feb 08 01:38:53 PM UTC 25
Finished Feb 08 01:38:55 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940403346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.2940403346
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.3714163935
Short name T1761
Test name
Test status
Simulation time 65421988 ps
CPU time 1.64 seconds
Started Feb 08 01:38:15 PM UTC 25
Finished Feb 08 01:38:18 PM UTC 25
Peak memory 214684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714163935 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3714163935
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.2358705169
Short name T216
Test name
Test status
Simulation time 268192889 ps
CPU time 3.01 seconds
Started Feb 08 01:38:15 PM UTC 25
Finished Feb 08 01:38:20 PM UTC 25
Peak memory 215164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358705169 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.2358705169
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.3403679551
Short name T1760
Test name
Test status
Simulation time 56045983 ps
CPU time 1.05 seconds
Started Feb 08 01:38:14 PM UTC 25
Finished Feb 08 01:38:16 PM UTC 25
Peak memory 214616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403679551 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3403679551
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2483110533
Short name T213
Test name
Test status
Simulation time 61121582 ps
CPU time 1.29 seconds
Started Feb 08 01:38:17 PM UTC 25
Finished Feb 08 01:38:19 PM UTC 25
Peak memory 214808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483110533
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.2483110533
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.2673680651
Short name T226
Test name
Test status
Simulation time 80264040 ps
CPU time 0.87 seconds
Started Feb 08 01:38:15 PM UTC 25
Finished Feb 08 01:38:17 PM UTC 25
Peak memory 214744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673680651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2673680651
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.540205555
Short name T283
Test name
Test status
Simulation time 158280675 ps
CPU time 0.93 seconds
Started Feb 08 01:38:14 PM UTC 25
Finished Feb 08 01:38:16 PM UTC 25
Peak memory 214620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540205555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.540205555
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3203443292
Short name T228
Test name
Test status
Simulation time 62567512 ps
CPU time 1.47 seconds
Started Feb 08 01:38:17 PM UTC 25
Finished Feb 08 01:38:19 PM UTC 25
Peak memory 214652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203443292 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_outstanding.3203443292
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.2413210417
Short name T206
Test name
Test status
Simulation time 623542015 ps
CPU time 1.59 seconds
Started Feb 08 01:38:13 PM UTC 25
Finished Feb 08 01:38:16 PM UTC 25
Peak memory 214696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413210417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2413210417
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.2432339050
Short name T196
Test name
Test status
Simulation time 445433786 ps
CPU time 2.75 seconds
Started Feb 08 01:38:14 PM UTC 25
Finished Feb 08 01:38:18 PM UTC 25
Peak memory 215304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432339050 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.2432339050
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.585692499
Short name T1847
Test name
Test status
Simulation time 16447233 ps
CPU time 0.99 seconds
Started Feb 08 01:38:53 PM UTC 25
Finished Feb 08 01:38:55 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585692499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.585692499
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.1897758518
Short name T1848
Test name
Test status
Simulation time 25876173 ps
CPU time 1.09 seconds
Started Feb 08 01:38:53 PM UTC 25
Finished Feb 08 01:38:55 PM UTC 25
Peak memory 214660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897758518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1897758518
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.2040803468
Short name T1849
Test name
Test status
Simulation time 24970100 ps
CPU time 0.99 seconds
Started Feb 08 01:38:53 PM UTC 25
Finished Feb 08 01:38:55 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040803468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2040803468
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.307832370
Short name T1850
Test name
Test status
Simulation time 43770475 ps
CPU time 0.94 seconds
Started Feb 08 01:38:53 PM UTC 25
Finished Feb 08 01:38:55 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307832370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.307832370
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.109741460
Short name T1851
Test name
Test status
Simulation time 17980295 ps
CPU time 1.01 seconds
Started Feb 08 01:38:55 PM UTC 25
Finished Feb 08 01:38:57 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109741460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.109741460
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.1598354296
Short name T1852
Test name
Test status
Simulation time 23153028 ps
CPU time 1 seconds
Started Feb 08 01:38:55 PM UTC 25
Finished Feb 08 01:38:57 PM UTC 25
Peak memory 214648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598354296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1598354296
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.3083298902
Short name T1854
Test name
Test status
Simulation time 31273005 ps
CPU time 1.08 seconds
Started Feb 08 01:38:55 PM UTC 25
Finished Feb 08 01:38:57 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083298902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.3083298902
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.355461062
Short name T1853
Test name
Test status
Simulation time 17463991 ps
CPU time 0.96 seconds
Started Feb 08 01:38:55 PM UTC 25
Finished Feb 08 01:38:57 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355461062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.355461062
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.273647562
Short name T1855
Test name
Test status
Simulation time 16282366 ps
CPU time 1.01 seconds
Started Feb 08 01:38:55 PM UTC 25
Finished Feb 08 01:38:57 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273647562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.273647562
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.3802865474
Short name T1856
Test name
Test status
Simulation time 26657822 ps
CPU time 0.99 seconds
Started Feb 08 01:38:55 PM UTC 25
Finished Feb 08 01:38:57 PM UTC 25
Peak memory 214680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802865474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.3802865474
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1669865629
Short name T1764
Test name
Test status
Simulation time 74283235 ps
CPU time 1.55 seconds
Started Feb 08 01:38:18 PM UTC 25
Finished Feb 08 01:38:21 PM UTC 25
Peak memory 214720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669865629
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.1669865629
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.1540774229
Short name T227
Test name
Test status
Simulation time 88129128 ps
CPU time 1.02 seconds
Started Feb 08 01:38:17 PM UTC 25
Finished Feb 08 01:38:19 PM UTC 25
Peak memory 214744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540774229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1540774229
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.2046551774
Short name T1762
Test name
Test status
Simulation time 62440957 ps
CPU time 1.01 seconds
Started Feb 08 01:38:17 PM UTC 25
Finished Feb 08 01:38:19 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046551774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2046551774
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3827439493
Short name T229
Test name
Test status
Simulation time 104995665 ps
CPU time 1.16 seconds
Started Feb 08 01:38:18 PM UTC 25
Finished Feb 08 01:38:20 PM UTC 25
Peak memory 214740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827439493 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_outstanding.3827439493
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.2818211063
Short name T1763
Test name
Test status
Simulation time 211057550 ps
CPU time 1.83 seconds
Started Feb 08 01:38:17 PM UTC 25
Finished Feb 08 01:38:20 PM UTC 25
Peak memory 214692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818211063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2818211063
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.579005610
Short name T182
Test name
Test status
Simulation time 101757417 ps
CPU time 1.82 seconds
Started Feb 08 01:38:21 PM UTC 25
Finished Feb 08 01:38:24 PM UTC 25
Peak memory 224788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579005610
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.579005610
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.3445859458
Short name T284
Test name
Test status
Simulation time 15234779 ps
CPU time 0.92 seconds
Started Feb 08 01:38:19 PM UTC 25
Finished Feb 08 01:38:21 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445859458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.3445859458
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2011811982
Short name T1767
Test name
Test status
Simulation time 103296382 ps
CPU time 1.38 seconds
Started Feb 08 01:38:21 PM UTC 25
Finished Feb 08 01:38:23 PM UTC 25
Peak memory 214416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011811982 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_outstanding.2011811982
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.3358809730
Short name T1765
Test name
Test status
Simulation time 64702358 ps
CPU time 2.51 seconds
Started Feb 08 01:38:19 PM UTC 25
Finished Feb 08 01:38:23 PM UTC 25
Peak memory 215324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358809730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3358809730
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.854278293
Short name T197
Test name
Test status
Simulation time 92445949 ps
CPU time 2.64 seconds
Started Feb 08 01:38:19 PM UTC 25
Finished Feb 08 01:38:23 PM UTC 25
Peak memory 215336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854278293 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.854278293
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2581383018
Short name T1769
Test name
Test status
Simulation time 29309912 ps
CPU time 1.12 seconds
Started Feb 08 01:38:22 PM UTC 25
Finished Feb 08 01:38:24 PM UTC 25
Peak memory 214804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581383018
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2581383018
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.3004935763
Short name T1766
Test name
Test status
Simulation time 56886630 ps
CPU time 0.97 seconds
Started Feb 08 01:38:21 PM UTC 25
Finished Feb 08 01:38:23 PM UTC 25
Peak memory 214744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004935763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3004935763
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.2584040875
Short name T280
Test name
Test status
Simulation time 27545188 ps
CPU time 0.97 seconds
Started Feb 08 01:38:21 PM UTC 25
Finished Feb 08 01:38:23 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584040875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2584040875
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1961487934
Short name T1770
Test name
Test status
Simulation time 177318913 ps
CPU time 1.42 seconds
Started Feb 08 01:38:22 PM UTC 25
Finished Feb 08 01:38:25 PM UTC 25
Peak memory 214752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961487934 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_outstanding.1961487934
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.296813284
Short name T1768
Test name
Test status
Simulation time 987558440 ps
CPU time 2.23 seconds
Started Feb 08 01:38:21 PM UTC 25
Finished Feb 08 01:38:24 PM UTC 25
Peak memory 215428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296813284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.296813284
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.4131215031
Short name T205
Test name
Test status
Simulation time 511187415 ps
CPU time 2.69 seconds
Started Feb 08 01:38:21 PM UTC 25
Finished Feb 08 01:38:25 PM UTC 25
Peak memory 215236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131215031 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.4131215031
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.114011380
Short name T1772
Test name
Test status
Simulation time 33278642 ps
CPU time 1.37 seconds
Started Feb 08 01:38:25 PM UTC 25
Finished Feb 08 01:38:27 PM UTC 25
Peak memory 214792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114011380
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.114011380
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.3347641795
Short name T217
Test name
Test status
Simulation time 39383431 ps
CPU time 0.99 seconds
Started Feb 08 01:38:25 PM UTC 25
Finished Feb 08 01:38:27 PM UTC 25
Peak memory 214744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347641795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.3347641795
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.700348236
Short name T277
Test name
Test status
Simulation time 61983680 ps
CPU time 0.99 seconds
Started Feb 08 01:38:25 PM UTC 25
Finished Feb 08 01:38:27 PM UTC 25
Peak memory 214620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700348236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST
_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.700348236
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3929965608
Short name T1773
Test name
Test status
Simulation time 47759038 ps
CPU time 1.36 seconds
Started Feb 08 01:38:25 PM UTC 25
Finished Feb 08 01:38:27 PM UTC 25
Peak memory 214752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929965608 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_outstanding.3929965608
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.4270216387
Short name T1771
Test name
Test status
Simulation time 34991895 ps
CPU time 2.14 seconds
Started Feb 08 01:38:22 PM UTC 25
Finished Feb 08 01:38:26 PM UTC 25
Peak memory 215276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270216387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.4270216387
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.1201626720
Short name T202
Test name
Test status
Simulation time 290845923 ps
CPU time 1.93 seconds
Started Feb 08 01:38:23 PM UTC 25
Finished Feb 08 01:38:27 PM UTC 25
Peak memory 214716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201626720 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.1201626720
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2843866996
Short name T1776
Test name
Test status
Simulation time 47009333 ps
CPU time 1.07 seconds
Started Feb 08 01:38:26 PM UTC 25
Finished Feb 08 01:38:29 PM UTC 25
Peak memory 214808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843866996
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2843866996
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.3983790280
Short name T218
Test name
Test status
Simulation time 64314996 ps
CPU time 0.89 seconds
Started Feb 08 01:38:26 PM UTC 25
Finished Feb 08 01:38:28 PM UTC 25
Peak memory 214864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983790280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.3983790280
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.2823213113
Short name T1774
Test name
Test status
Simulation time 37130137 ps
CPU time 1.01 seconds
Started Feb 08 01:38:26 PM UTC 25
Finished Feb 08 01:38:28 PM UTC 25
Peak memory 214556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823213113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2823213113
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2602489693
Short name T1777
Test name
Test status
Simulation time 61428019 ps
CPU time 1.77 seconds
Started Feb 08 01:38:26 PM UTC 25
Finished Feb 08 01:38:29 PM UTC 25
Peak memory 214760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602489693 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_outstanding.2602489693
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.2012627314
Short name T1775
Test name
Test status
Simulation time 143571397 ps
CPU time 2.34 seconds
Started Feb 08 01:38:25 PM UTC 25
Finished Feb 08 01:38:28 PM UTC 25
Peak memory 215400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012627314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TES
T_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2012627314
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.3837792081
Short name T198
Test name
Test status
Simulation time 249425872 ps
CPU time 2.92 seconds
Started Feb 08 01:38:25 PM UTC 25
Finished Feb 08 01:38:29 PM UTC 25
Peak memory 215360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837792081 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.3837792081
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_full.2592759767
Short name T123
Test name
Test status
Simulation time 22696554493 ps
CPU time 133.97 seconds
Started Feb 08 12:55:53 PM UTC 25
Finished Feb 08 12:58:10 PM UTC 25
Peak memory 546044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592759767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_host_fifo_full.2592759767
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_fmt.1161484619
Short name T2
Test name
Test status
Simulation time 566492119 ps
CPU time 1.54 seconds
Started Feb 08 12:55:51 PM UTC 25
Finished Feb 08 12:55:54 PM UTC 25
Peak memory 213916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161484619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt.1161484619
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_rx.145964846
Short name T4
Test name
Test status
Simulation time 384985319 ps
CPU time 6.95 seconds
Started Feb 08 12:55:52 PM UTC 25
Finished Feb 08 12:56:00 PM UTC 25
Peak memory 253460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145964846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.145964846
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_watermark.4265722822
Short name T81
Test name
Test status
Simulation time 4967613273 ps
CPU time 110.22 seconds
Started Feb 08 12:55:50 PM UTC 25
Finished Feb 08 12:57:42 PM UTC 25
Peak memory 1445436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265722822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.i2c_host_fifo_watermark.4265722822
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_host_may_nack.1979490582
Short name T11
Test name
Test status
Simulation time 301876894 ps
CPU time 5.24 seconds
Started Feb 08 12:56:06 PM UTC 25
Finished Feb 08 12:56:13 PM UTC 25
Peak memory 216036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979490582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 0.i2c_host_may_nack.1979490582
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_host_override.4000570605
Short name T1
Test name
Test status
Simulation time 18982737 ps
CPU time 0.85 seconds
Started Feb 08 12:55:50 PM UTC 25
Finished Feb 08 12:55:52 PM UTC 25
Peak memory 214992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000570605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 0.i2c_host_override.4000570605
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_host_perf.1700938357
Short name T15
Test name
Test status
Simulation time 1773968127 ps
CPU time 15.83 seconds
Started Feb 08 12:55:53 PM UTC 25
Finished Feb 08 12:56:12 PM UTC 25
Peak memory 282312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700938357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_host_perf.1700938357
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_host_perf_precise.3995890217
Short name T3
Test name
Test status
Simulation time 363309546 ps
CPU time 4.64 seconds
Started Feb 08 12:55:53 PM UTC 25
Finished Feb 08 12:55:59 PM UTC 25
Peak memory 240804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995890217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_host_perf_precise.3995890217
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_host_stretch_timeout.1501846351
Short name T14
Test name
Test status
Simulation time 3732758073 ps
CPU time 12.16 seconds
Started Feb 08 12:55:54 PM UTC 25
Finished Feb 08 12:56:08 PM UTC 25
Peak memory 230252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501846351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.i2c_host_stretch_timeout.1501846351
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.4290264249
Short name T183
Test name
Test status
Simulation time 482729754 ps
CPU time 1.32 seconds
Started Feb 08 12:56:11 PM UTC 25
Finished Feb 08 12:56:14 PM UTC 25
Peak memory 246448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290264249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM
_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.4290264249
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_tx.4101833998
Short name T73
Test name
Test status
Simulation time 182114015 ps
CPU time 1.44 seconds
Started Feb 08 12:56:09 PM UTC 25
Finished Feb 08 12:56:12 PM UTC 25
Peak memory 214532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101833998 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.4101833998
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_intr_smoke.4134168362
Short name T10
Test name
Test status
Simulation time 1408504228 ps
CPU time 5.66 seconds
Started Feb 08 12:55:58 PM UTC 25
Finished Feb 08 12:56:05 PM UTC 25
Peak memory 230208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134168362 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_smoke.4134168362
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_intr_stress_wr.930332213
Short name T207
Test name
Test status
Simulation time 16452288967 ps
CPU time 30.91 seconds
Started Feb 08 12:55:58 PM UTC 25
Finished Feb 08 12:56:31 PM UTC 25
Peak memory 929336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93033
2213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.930332213
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull.872883134
Short name T63
Test name
Test status
Simulation time 519939488 ps
CPU time 3.72 seconds
Started Feb 08 12:56:10 PM UTC 25
Finished Feb 08 12:56:15 PM UTC 25
Peak memory 226140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872883134 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_acqfull.872883134
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull_addr.1806007305
Short name T64
Test name
Test status
Simulation time 515303468 ps
CPU time 3.25 seconds
Started Feb 08 12:56:11 PM UTC 25
Finished Feb 08 12:56:16 PM UTC 25
Peak memory 215916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806007305 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.1806007305
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_perf.4108750378
Short name T71
Test name
Test status
Simulation time 455288619 ps
CPU time 3.48 seconds
Started Feb 08 12:56:03 PM UTC 25
Finished Feb 08 12:56:08 PM UTC 25
Peak memory 233148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108750378 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_perf.4108750378
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_smbus_maxlen.1878615105
Short name T189
Test name
Test status
Simulation time 2092180770 ps
CPU time 4.05 seconds
Started Feb 08 12:56:10 PM UTC 25
Finished Feb 08 12:56:16 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878615105 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smbus_maxlen.1878615105
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_smoke.1713160817
Short name T163
Test name
Test status
Simulation time 2244234290 ps
CPU time 13.74 seconds
Started Feb 08 12:55:57 PM UTC 25
Finished Feb 08 12:56:12 PM UTC 25
Peak memory 232980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713160817 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smoke.1713160817
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_stress_wr.756825805
Short name T54
Test name
Test status
Simulation time 40589953019 ps
CPU time 72.74 seconds
Started Feb 08 12:55:57 PM UTC 25
Finished Feb 08 12:57:12 PM UTC 25
Peak memory 1359688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756825805 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_wr.756825805
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/0.i2c_target_stretch.2083621365
Short name T6
Test name
Test status
Simulation time 893336340 ps
CPU time 3.35 seconds
Started Feb 08 12:55:58 PM UTC 25
Finished Feb 08 12:56:03 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083621365 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stretch.2083621365
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_alert_test.3289291068
Short name T95
Test name
Test status
Simulation time 41363686 ps
CPU time 0.9 seconds
Started Feb 08 12:56:46 PM UTC 25
Finished Feb 08 12:56:48 PM UTC 25
Peak memory 214992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289291068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.3289291068
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_host_error_intr.1325568656
Short name T19
Test name
Test status
Simulation time 83182149 ps
CPU time 1.75 seconds
Started Feb 08 12:56:16 PM UTC 25
Finished Feb 08 12:56:19 PM UTC 25
Peak memory 226160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325568656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_host_error_intr.1325568656
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_fmt_empty.1642605630
Short name T164
Test name
Test status
Simulation time 359594680 ps
CPU time 8.08 seconds
Started Feb 08 12:56:14 PM UTC 25
Finished Feb 08 12:56:23 PM UTC 25
Peak memory 292352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642605630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty.1642605630
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_overflow.2734342904
Short name T80
Test name
Test status
Simulation time 1977563726 ps
CPU time 52.29 seconds
Started Feb 08 12:56:14 PM UTC 25
Finished Feb 08 12:57:08 PM UTC 25
Peak memory 697784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734342904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_host_fifo_overflow.2734342904
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_fmt.1997231404
Short name T37
Test name
Test status
Simulation time 457238092 ps
CPU time 1.47 seconds
Started Feb 08 12:56:14 PM UTC 25
Finished Feb 08 12:56:16 PM UTC 25
Peak memory 214448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997231404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt.1997231404
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_rx.1928517939
Short name T155
Test name
Test status
Simulation time 1070520468 ps
CPU time 16.55 seconds
Started Feb 08 12:56:15 PM UTC 25
Finished Feb 08 12:56:33 PM UTC 25
Peak memory 265876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928517939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.1928517939
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_watermark.3094699082
Short name T386
Test name
Test status
Simulation time 13918868649 ps
CPU time 289.62 seconds
Started Feb 08 12:56:13 PM UTC 25
Finished Feb 08 01:01:06 PM UTC 25
Peak memory 1390288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094699082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.i2c_host_fifo_watermark.3094699082
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_host_may_nack.4247496896
Short name T12
Test name
Test status
Simulation time 484437385 ps
CPU time 7.35 seconds
Started Feb 08 12:56:35 PM UTC 25
Finished Feb 08 12:56:44 PM UTC 25
Peak memory 215908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247496896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 1.i2c_host_may_nack.4247496896
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_host_override.55827994
Short name T97
Test name
Test status
Simulation time 110135668 ps
CPU time 0.89 seconds
Started Feb 08 12:56:13 PM UTC 25
Finished Feb 08 12:56:15 PM UTC 25
Peak memory 214516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55827994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.i2c_host_override.55827994
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_host_perf.789516000
Short name T230
Test name
Test status
Simulation time 26781065005 ps
CPU time 278.1 seconds
Started Feb 08 12:56:15 PM UTC 25
Finished Feb 08 01:00:57 PM UTC 25
Peak memory 308952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789516000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_host_perf.789516000
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_host_perf_precise.3707880217
Short name T43
Test name
Test status
Simulation time 268131555 ps
CPU time 2.05 seconds
Started Feb 08 12:56:15 PM UTC 25
Finished Feb 08 12:56:18 PM UTC 25
Peak memory 232440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707880217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_host_perf_precise.3707880217
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_host_smoke.1817159379
Short name T152
Test name
Test status
Simulation time 5660111093 ps
CPU time 52.17 seconds
Started Feb 08 12:56:12 PM UTC 25
Finished Feb 08 12:57:06 PM UTC 25
Peak memory 378500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817159379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_host_smoke.1817159379
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_host_stretch_timeout.2932116273
Short name T149
Test name
Test status
Simulation time 3043870234 ps
CPU time 42 seconds
Started Feb 08 12:56:15 PM UTC 25
Finished Feb 08 12:56:59 PM UTC 25
Peak memory 226280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932116273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.i2c_host_stretch_timeout.2932116273
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_bad_addr.1662684295
Short name T66
Test name
Test status
Simulation time 1110783138 ps
CPU time 5.19 seconds
Started Feb 08 12:56:32 PM UTC 25
Finished Feb 08 12:56:38 PM UTC 25
Peak memory 232920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1662684295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.1662684295
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_acq.460801338
Short name T234
Test name
Test status
Simulation time 241576602 ps
CPU time 1.77 seconds
Started Feb 08 12:56:28 PM UTC 25
Finished Feb 08 12:56:31 PM UTC 25
Peak memory 226092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460801338 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_acq.460801338
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_tx.3452396890
Short name T237
Test name
Test status
Simulation time 275744684 ps
CPU time 1.83 seconds
Started Feb 08 12:56:29 PM UTC 25
Finished Feb 08 12:56:32 PM UTC 25
Peak memory 213924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452396890 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_tx.3452396890
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_acq.270553975
Short name T265
Test name
Test status
Simulation time 14169262323 ps
CPU time 5.54 seconds
Started Feb 08 12:56:38 PM UTC 25
Finished Feb 08 12:56:45 PM UTC 25
Peak memory 226224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270553975 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.270553975
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_tx.410009926
Short name T296
Test name
Test status
Simulation time 663481680 ps
CPU time 1.98 seconds
Started Feb 08 12:56:39 PM UTC 25
Finished Feb 08 12:56:43 PM UTC 25
Peak memory 214236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410009926 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.410009926
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_glitch.398591341
Short name T53
Test name
Test status
Simulation time 4499912555 ps
CPU time 12.22 seconds
Started Feb 08 12:56:16 PM UTC 25
Finished Feb 08 12:56:30 PM UTC 25
Peak memory 226720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398591341 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.398591341
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_glitch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_intr_smoke.296729588
Short name T48
Test name
Test status
Simulation time 745478253 ps
CPU time 6.31 seconds
Started Feb 08 12:56:20 PM UTC 25
Finished Feb 08 12:56:28 PM UTC 25
Peak memory 232572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296729588 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_smoke.296729588
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_intr_stress_wr.2422978972
Short name T301
Test name
Test status
Simulation time 16261264883 ps
CPU time 55.54 seconds
Started Feb 08 12:56:22 PM UTC 25
Finished Feb 08 12:57:20 PM UTC 25
Peak memory 1222408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24229
78972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.2422978972
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull.3207720420
Short name T156
Test name
Test status
Simulation time 1112015687 ps
CPU time 3.25 seconds
Started Feb 08 12:56:44 PM UTC 25
Finished Feb 08 12:56:48 PM UTC 25
Peak memory 225576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207720420 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_acqfull.3207720420
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull_addr.2418096941
Short name T65
Test name
Test status
Simulation time 408822896 ps
CPU time 3.14 seconds
Started Feb 08 12:56:44 PM UTC 25
Finished Feb 08 12:56:48 PM UTC 25
Peak memory 215920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418096941 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.2418096941
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_perf.822741746
Short name T295
Test name
Test status
Simulation time 13957523587 ps
CPU time 5.59 seconds
Started Feb 08 12:56:31 PM UTC 25
Finished Feb 08 12:56:38 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822741746 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_perf.822741746
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_smbus_maxlen.4261946174
Short name T298
Test name
Test status
Simulation time 464502802 ps
CPU time 3.22 seconds
Started Feb 08 12:56:39 PM UTC 25
Finished Feb 08 12:56:44 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261946174 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smbus_maxlen.4261946174
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_smoke.1740850801
Short name T297
Test name
Test status
Simulation time 1543385722 ps
CPU time 24.15 seconds
Started Feb 08 12:56:17 PM UTC 25
Finished Feb 08 12:56:43 PM UTC 25
Peak memory 226144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740850801 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smoke.1740850801
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_stress_all.4109731082
Short name T238
Test name
Test status
Simulation time 20641363409 ps
CPU time 62.28 seconds
Started Feb 08 12:56:32 PM UTC 25
Finished Feb 08 12:57:36 PM UTC 25
Peak memory 315012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109731082 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_all.4109731082
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_stress_rd.2283862106
Short name T190
Test name
Test status
Simulation time 6977183758 ps
CPU time 51.83 seconds
Started Feb 08 12:56:18 PM UTC 25
Finished Feb 08 12:57:12 PM UTC 25
Peak memory 230332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283862106 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_rd.2283862106
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_stress_wr.2327320533
Short name T472
Test name
Test status
Simulation time 53287141650 ps
CPU time 441.56 seconds
Started Feb 08 12:56:17 PM UTC 25
Finished Feb 08 01:03:44 PM UTC 25
Peak memory 4189764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327320533 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_wr.2327320533
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_stretch.1250322234
Short name T313
Test name
Test status
Simulation time 2131272900 ps
CPU time 91.55 seconds
Started Feb 08 12:56:19 PM UTC 25
Finished Feb 08 12:57:53 PM UTC 25
Peak memory 695808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250322234 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stretch.1250322234
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_timeout.3695249603
Short name T74
Test name
Test status
Simulation time 2998007503 ps
CPU time 9.03 seconds
Started Feb 08 12:56:23 PM UTC 25
Finished Feb 08 12:56:34 PM UTC 25
Peak memory 230564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695249603 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_timeout.3695249603
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/1.i2c_target_tx_stretch_ctrl.752938788
Short name T70
Test name
Test status
Simulation time 124388707 ps
CPU time 4.52 seconds
Started Feb 08 12:56:39 PM UTC 25
Finished Feb 08 12:56:45 PM UTC 25
Peak memory 216120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752938788 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.752938788
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_alert_test.2423831059
Short name T458
Test name
Test status
Simulation time 18712840 ps
CPU time 0.83 seconds
Started Feb 08 01:03:48 PM UTC 25
Finished Feb 08 01:03:50 PM UTC 25
Peak memory 213896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423831059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.2423831059
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_host_error_intr.3787070022
Short name T430
Test name
Test status
Simulation time 838199108 ps
CPU time 4.27 seconds
Started Feb 08 01:03:25 PM UTC 25
Finished Feb 08 01:03:31 PM UTC 25
Peak memory 226412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787070022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_host_error_intr.3787070022
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_fmt_empty.4083650259
Short name T459
Test name
Test status
Simulation time 750374810 ps
CPU time 22.41 seconds
Started Feb 08 01:03:08 PM UTC 25
Finished Feb 08 01:03:31 PM UTC 25
Peak memory 290436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083650259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empty.4083650259
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_full.395385632
Short name T537
Test name
Test status
Simulation time 5893139662 ps
CPU time 165.41 seconds
Started Feb 08 01:03:10 PM UTC 25
Finished Feb 08 01:05:58 PM UTC 25
Peak memory 423676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395385632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fu
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 10.i2c_host_fifo_full.395385632
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_overflow.2361977236
Short name T497
Test name
Test status
Simulation time 5088623203 ps
CPU time 78.91 seconds
Started Feb 08 01:03:06 PM UTC 25
Finished Feb 08 01:04:26 PM UTC 25
Peak memory 853588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361977236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_host_fifo_overflow.2361977236
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_fmt.2853256498
Short name T242
Test name
Test status
Simulation time 112348714 ps
CPU time 1.48 seconds
Started Feb 08 01:03:07 PM UTC 25
Finished Feb 08 01:03:09 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853256498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fmt.2853256498
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_rx.3020329663
Short name T454
Test name
Test status
Simulation time 812990665 ps
CPU time 15.11 seconds
Started Feb 08 01:03:08 PM UTC 25
Finished Feb 08 01:03:24 PM UTC 25
Peak memory 261696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020329663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.3020329663
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_watermark.408336787
Short name T535
Test name
Test status
Simulation time 7689167742 ps
CPU time 168 seconds
Started Feb 08 01:03:05 PM UTC 25
Finished Feb 08 01:05:56 PM UTC 25
Peak memory 894540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408336787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_wa
termark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_host_fifo_watermark.408336787
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_host_may_nack.3954388593
Short name T478
Test name
Test status
Simulation time 486562622 ps
CPU time 5.82 seconds
Started Feb 08 01:03:42 PM UTC 25
Finished Feb 08 01:03:49 PM UTC 25
Peak memory 216172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954388593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 10.i2c_host_may_nack.3954388593
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_host_override.4020387178
Short name T451
Test name
Test status
Simulation time 26309626 ps
CPU time 1.03 seconds
Started Feb 08 01:03:03 PM UTC 25
Finished Feb 08 01:03:06 PM UTC 25
Peak memory 213920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020387178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 10.i2c_host_override.4020387178
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_host_perf.3641068324
Short name T482
Test name
Test status
Simulation time 14327003120 ps
CPU time 38.46 seconds
Started Feb 08 01:03:11 PM UTC 25
Finished Feb 08 01:03:51 PM UTC 25
Peak memory 393008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641068324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_host_perf.3641068324
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_host_perf_precise.2831263080
Short name T465
Test name
Test status
Simulation time 6155620854 ps
CPU time 23.16 seconds
Started Feb 08 01:03:16 PM UTC 25
Finished Feb 08 01:03:40 PM UTC 25
Peak memory 216104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831263080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_host_perf_precise.2831263080
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_host_smoke.776142857
Short name T491
Test name
Test status
Simulation time 1519026586 ps
CPU time 66.33 seconds
Started Feb 08 01:03:02 PM UTC 25
Finished Feb 08 01:04:11 PM UTC 25
Peak memory 390664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776142857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_host_smoke.776142857
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_host_stretch_timeout.1221278557
Short name T490
Test name
Test status
Simulation time 3645129235 ps
CPU time 41.84 seconds
Started Feb 08 01:03:23 PM UTC 25
Finished Feb 08 01:04:07 PM UTC 25
Peak memory 226156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221278557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_host_stretch_timeout.1221278557
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_bad_addr.3135318697
Short name T474
Test name
Test status
Simulation time 7086266110 ps
CPU time 4.91 seconds
Started Feb 08 01:03:40 PM UTC 25
Finished Feb 08 01:03:47 PM UTC 25
Peak memory 226272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3135318697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.3135318697
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_acq.1941482952
Short name T464
Test name
Test status
Simulation time 392427001 ps
CPU time 1.61 seconds
Started Feb 08 01:03:37 PM UTC 25
Finished Feb 08 01:03:40 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941482952 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_acq.1941482952
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_tx.2003504960
Short name T466
Test name
Test status
Simulation time 301314093 ps
CPU time 2.04 seconds
Started Feb 08 01:03:38 PM UTC 25
Finished Feb 08 01:03:41 PM UTC 25
Peak memory 215980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003504960 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_tx.2003504960
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_acq.761751899
Short name T476
Test name
Test status
Simulation time 536955607 ps
CPU time 3.57 seconds
Started Feb 08 01:03:42 PM UTC 25
Finished Feb 08 01:03:47 PM UTC 25
Peak memory 215904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761751899 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.761751899
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_tx.2750402314
Short name T475
Test name
Test status
Simulation time 408465027 ps
CPU time 2.15 seconds
Started Feb 08 01:03:43 PM UTC 25
Finished Feb 08 01:03:47 PM UTC 25
Peak memory 215716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750402314 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.2750402314
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_intr_smoke.2032972455
Short name T461
Test name
Test status
Simulation time 4351161480 ps
CPU time 5.78 seconds
Started Feb 08 01:03:29 PM UTC 25
Finished Feb 08 01:03:37 PM UTC 25
Peak memory 226264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032972455 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_smoke.2032972455
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_intr_stress_wr.545204316
Short name T468
Test name
Test status
Simulation time 4257656444 ps
CPU time 10.14 seconds
Started Feb 08 01:03:32 PM UTC 25
Finished Feb 08 01:03:43 PM UTC 25
Peak memory 380488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54520
4316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.545204316
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull.695371818
Short name T483
Test name
Test status
Simulation time 1972635038 ps
CPU time 4.48 seconds
Started Feb 08 01:03:45 PM UTC 25
Finished Feb 08 01:03:51 PM UTC 25
Peak memory 226212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695371818 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_acqfull.695371818
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull_addr.2850236883
Short name T481
Test name
Test status
Simulation time 1822783901 ps
CPU time 3.46 seconds
Started Feb 08 01:03:46 PM UTC 25
Finished Feb 08 01:03:50 PM UTC 25
Peak memory 216000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850236883 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_acqfull_addr.2850236883
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_nack_txstretch.1831642466
Short name T480
Test name
Test status
Simulation time 569643720 ps
CPU time 1.81 seconds
Started Feb 08 01:03:47 PM UTC 25
Finished Feb 08 01:03:50 PM UTC 25
Peak memory 231920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831642466 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_txstretch.1831642466
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_perf.1973111571
Short name T469
Test name
Test status
Simulation time 488053818 ps
CPU time 3.9 seconds
Started Feb 08 01:03:38 PM UTC 25
Finished Feb 08 01:03:43 PM UTC 25
Peak memory 230372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973111571 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_perf.1973111571
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_smbus_maxlen.2097430900
Short name T479
Test name
Test status
Simulation time 482050098 ps
CPU time 3.94 seconds
Started Feb 08 01:03:44 PM UTC 25
Finished Feb 08 01:03:50 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097430900 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smbus_maxlen.2097430900
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_smoke.1725917081
Short name T460
Test name
Test status
Simulation time 2535775305 ps
CPU time 9.84 seconds
Started Feb 08 01:03:25 PM UTC 25
Finished Feb 08 01:03:36 PM UTC 25
Peak memory 215988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725917081 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smoke.1725917081
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_stress_all.1135151522
Short name T1012
Test name
Test status
Simulation time 43830989978 ps
CPU time 931.05 seconds
Started Feb 08 01:03:38 PM UTC 25
Finished Feb 08 01:19:17 PM UTC 25
Peak memory 4171340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135151522 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_all.1135151522
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_stress_rd.2535182783
Short name T467
Test name
Test status
Simulation time 3052176894 ps
CPU time 12.66 seconds
Started Feb 08 01:03:27 PM UTC 25
Finished Feb 08 01:03:41 PM UTC 25
Peak memory 220000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535182783 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_rd.2535182783
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_stress_wr.3253470400
Short name T477
Test name
Test status
Simulation time 21359652021 ps
CPU time 21.66 seconds
Started Feb 08 01:03:26 PM UTC 25
Finished Feb 08 01:03:49 PM UTC 25
Peak memory 216024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253470400 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_wr.3253470400
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_stretch.2579063103
Short name T485
Test name
Test status
Simulation time 857082932 ps
CPU time 25.37 seconds
Started Feb 08 01:03:27 PM UTC 25
Finished Feb 08 01:03:54 PM UTC 25
Peak memory 331476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579063103 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stretch.2579063103
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_timeout.3231860871
Short name T463
Test name
Test status
Simulation time 1401292040 ps
CPU time 6.63 seconds
Started Feb 08 01:03:32 PM UTC 25
Finished Feb 08 01:03:39 PM UTC 25
Peak memory 243400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231860871 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_timeout.3231860871
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/10.i2c_target_tx_stretch_ctrl.1056330185
Short name T487
Test name
Test status
Simulation time 461725474 ps
CPU time 8.63 seconds
Started Feb 08 01:03:44 PM UTC 25
Finished Feb 08 01:03:54 PM UTC 25
Peak memory 216120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056330185 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.1056330185
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_alert_test.2853218873
Short name T504
Test name
Test status
Simulation time 40510657 ps
CPU time 0.85 seconds
Started Feb 08 01:04:37 PM UTC 25
Finished Feb 08 01:04:39 PM UTC 25
Peak memory 214996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853218873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.2853218873
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_host_error_intr.2340623722
Short name T489
Test name
Test status
Simulation time 409933050 ps
CPU time 9.31 seconds
Started Feb 08 01:03:54 PM UTC 25
Finished Feb 08 01:04:05 PM UTC 25
Peak memory 243392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340623722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_host_error_intr.2340623722
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_fmt_empty.3499085128
Short name T492
Test name
Test status
Simulation time 916297873 ps
CPU time 19.78 seconds
Started Feb 08 01:03:51 PM UTC 25
Finished Feb 08 01:04:12 PM UTC 25
Peak memory 290164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499085128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empty.3499085128
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_full.1587078563
Short name T499
Test name
Test status
Simulation time 12535644398 ps
CPU time 111.1 seconds
Started Feb 08 01:03:51 PM UTC 25
Finished Feb 08 01:05:45 PM UTC 25
Peak memory 601664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587078563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_host_fifo_full.1587078563
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_overflow.1887382254
Short name T550
Test name
Test status
Simulation time 8601912746 ps
CPU time 159.94 seconds
Started Feb 08 01:03:50 PM UTC 25
Finished Feb 08 01:06:33 PM UTC 25
Peak memory 785820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887382254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_host_fifo_overflow.1887382254
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_fmt.4289411640
Short name T484
Test name
Test status
Simulation time 205026679 ps
CPU time 1.46 seconds
Started Feb 08 01:03:51 PM UTC 25
Finished Feb 08 01:03:54 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289411640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fmt.4289411640
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_rx.78081706
Short name T488
Test name
Test status
Simulation time 224627988 ps
CPU time 8.62 seconds
Started Feb 08 01:03:51 PM UTC 25
Finished Feb 08 01:04:01 PM UTC 25
Peak memory 255676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78081706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.78081706
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_watermark.1059833586
Short name T551
Test name
Test status
Simulation time 5343321955 ps
CPU time 160.93 seconds
Started Feb 08 01:03:50 PM UTC 25
Finished Feb 08 01:06:34 PM UTC 25
Peak memory 1580444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059833586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 11.i2c_host_fifo_watermark.1059833586
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_host_may_nack.3418750609
Short name T134
Test name
Test status
Simulation time 804860639 ps
CPU time 16.4 seconds
Started Feb 08 01:04:28 PM UTC 25
Finished Feb 08 01:04:45 PM UTC 25
Peak memory 215852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418750609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 11.i2c_host_may_nack.3418750609
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_host_override.2939113544
Short name T140
Test name
Test status
Simulation time 50877802 ps
CPU time 1 seconds
Started Feb 08 01:03:48 PM UTC 25
Finished Feb 08 01:03:50 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939113544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 11.i2c_host_override.2939113544
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_host_perf.2324367853
Short name T836
Test name
Test status
Simulation time 28337129265 ps
CPU time 617.53 seconds
Started Feb 08 01:03:51 PM UTC 25
Finished Feb 08 01:14:15 PM UTC 25
Peak memory 2440648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324367853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_host_perf.2324367853
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_host_perf_precise.2499455768
Short name T231
Test name
Test status
Simulation time 897641913 ps
CPU time 35.3 seconds
Started Feb 08 01:03:52 PM UTC 25
Finished Feb 08 01:04:29 PM UTC 25
Peak memory 296316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499455768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_host_perf_precise.2499455768
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_host_smoke.1801025453
Short name T494
Test name
Test status
Simulation time 1837495731 ps
CPU time 32.93 seconds
Started Feb 08 01:03:48 PM UTC 25
Finished Feb 08 01:04:22 PM UTC 25
Peak memory 347600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801025453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_host_smoke.1801025453
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_host_stretch_timeout.3518792025
Short name T493
Test name
Test status
Simulation time 3216636423 ps
CPU time 19.77 seconds
Started Feb 08 01:03:52 PM UTC 25
Finished Feb 08 01:04:14 PM UTC 25
Peak memory 230316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518792025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.i2c_host_stretch_timeout.3518792025
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_bad_addr.149878540
Short name T502
Test name
Test status
Simulation time 4784971289 ps
CPU time 6.84 seconds
Started Feb 08 01:04:27 PM UTC 25
Finished Feb 08 01:04:36 PM UTC 25
Peak memory 228584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=149878540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.149878540
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_acq.1902439510
Short name T293
Test name
Test status
Simulation time 272250097 ps
CPU time 1.86 seconds
Started Feb 08 01:04:23 PM UTC 25
Finished Feb 08 01:04:26 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902439510 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_acq.1902439510
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_tx.193834258
Short name T498
Test name
Test status
Simulation time 137663047 ps
CPU time 1.5 seconds
Started Feb 08 01:04:24 PM UTC 25
Finished Feb 08 01:04:27 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193834258 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_tx.193834258
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_acq.2470884780
Short name T503
Test name
Test status
Simulation time 1289873400 ps
CPU time 4.59 seconds
Started Feb 08 01:04:31 PM UTC 25
Finished Feb 08 01:04:37 PM UTC 25
Peak memory 215924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470884780 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.2470884780
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_tx.3761236054
Short name T501
Test name
Test status
Simulation time 283800998 ps
CPU time 2.21 seconds
Started Feb 08 01:04:31 PM UTC 25
Finished Feb 08 01:04:34 PM UTC 25
Peak memory 215652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761236054 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.3761236054
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_intr_smoke.2088202185
Short name T495
Test name
Test status
Simulation time 2251225855 ps
CPU time 12.58 seconds
Started Feb 08 01:04:12 PM UTC 25
Finished Feb 08 01:04:26 PM UTC 25
Peak memory 230628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088202185 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_smoke.2088202185
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_intr_stress_wr.3879659613
Short name T512
Test name
Test status
Simulation time 37017385110 ps
CPU time 45.6 seconds
Started Feb 08 01:04:13 PM UTC 25
Finished Feb 08 01:05:00 PM UTC 25
Peak memory 597512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38796
59613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.3879659613
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull.568061129
Short name T507
Test name
Test status
Simulation time 548936112 ps
CPU time 4.26 seconds
Started Feb 08 01:04:34 PM UTC 25
Finished Feb 08 01:04:39 PM UTC 25
Peak memory 226416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568061129 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_acqfull.568061129
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull_addr.2582521647
Short name T509
Test name
Test status
Simulation time 1671491489 ps
CPU time 3.55 seconds
Started Feb 08 01:04:35 PM UTC 25
Finished Feb 08 01:04:40 PM UTC 25
Peak memory 215924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582521647 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_acqfull_addr.2582521647
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_nack_txstretch.1757341984
Short name T506
Test name
Test status
Simulation time 553440154 ps
CPU time 2.07 seconds
Started Feb 08 01:04:36 PM UTC 25
Finished Feb 08 01:04:39 PM UTC 25
Peak memory 233228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757341984 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_txstretch.1757341984
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_perf.851367282
Short name T500
Test name
Test status
Simulation time 776934076 ps
CPU time 7.06 seconds
Started Feb 08 01:04:24 PM UTC 25
Finished Feb 08 01:04:33 PM UTC 25
Peak memory 230244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851367282 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_perf.851367282
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_smbus_maxlen.3080511040
Short name T508
Test name
Test status
Simulation time 1897140469 ps
CPU time 4.3 seconds
Started Feb 08 01:04:34 PM UTC 25
Finished Feb 08 01:04:39 PM UTC 25
Peak memory 215832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080511040 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smbus_maxlen.3080511040
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_stress_all.2148059995
Short name T542
Test name
Test status
Simulation time 53966632034 ps
CPU time 113.07 seconds
Started Feb 08 01:04:26 PM UTC 25
Finished Feb 08 01:06:22 PM UTC 25
Peak memory 663172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148059995 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_all.2148059995
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_stress_rd.3895820998
Short name T131
Test name
Test status
Simulation time 1487794338 ps
CPU time 35.19 seconds
Started Feb 08 01:04:06 PM UTC 25
Finished Feb 08 01:04:43 PM UTC 25
Peak memory 233024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895820998 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_rd.3895820998
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_stress_wr.1617386318
Short name T613
Test name
Test status
Simulation time 57875370202 ps
CPU time 261.46 seconds
Started Feb 08 01:04:02 PM UTC 25
Finished Feb 08 01:08:27 PM UTC 25
Peak memory 2432776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617386318 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_wr.1617386318
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_stretch.39490588
Short name T510
Test name
Test status
Simulation time 1876871395 ps
CPU time 31.41 seconds
Started Feb 08 01:04:08 PM UTC 25
Finished Feb 08 01:04:41 PM UTC 25
Peak memory 630464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39490588 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stretch.39490588
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_timeout.1580754085
Short name T496
Test name
Test status
Simulation time 3103900201 ps
CPU time 9.63 seconds
Started Feb 08 01:04:15 PM UTC 25
Finished Feb 08 01:04:26 PM UTC 25
Peak memory 232548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580754085 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_timeout.1580754085
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/11.i2c_target_tx_stretch_ctrl.3246404794
Short name T505
Test name
Test status
Simulation time 134521893 ps
CPU time 5.17 seconds
Started Feb 08 01:04:33 PM UTC 25
Finished Feb 08 01:04:39 PM UTC 25
Peak memory 215864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246404794 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.3246404794
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_alert_test.532179872
Short name T523
Test name
Test status
Simulation time 35937067 ps
CPU time 0.94 seconds
Started Feb 08 01:05:42 PM UTC 25
Finished Feb 08 01:05:44 PM UTC 25
Peak memory 214944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532179872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM
_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.532179872
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_host_error_intr.1196317876
Short name T137
Test name
Test status
Simulation time 421432666 ps
CPU time 4.92 seconds
Started Feb 08 01:04:45 PM UTC 25
Finished Feb 08 01:04:51 PM UTC 25
Peak memory 233048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196317876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_host_error_intr.1196317876
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_fmt_empty.1224415176
Short name T511
Test name
Test status
Simulation time 1816524141 ps
CPU time 16.63 seconds
Started Feb 08 01:04:41 PM UTC 25
Finished Feb 08 01:04:59 PM UTC 25
Peak memory 274100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224415176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empty.1224415176
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_full.2635588131
Short name T552
Test name
Test status
Simulation time 2998869136 ps
CPU time 111.29 seconds
Started Feb 08 01:04:42 PM UTC 25
Finished Feb 08 01:06:35 PM UTC 25
Peak memory 605960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635588131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_host_fifo_full.2635588131
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_overflow.3240383809
Short name T540
Test name
Test status
Simulation time 2603078996 ps
CPU time 94 seconds
Started Feb 08 01:04:40 PM UTC 25
Finished Feb 08 01:06:17 PM UTC 25
Peak memory 513748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240383809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_host_fifo_overflow.3240383809
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_fmt.3674619582
Short name T133
Test name
Test status
Simulation time 107509000 ps
CPU time 1.85 seconds
Started Feb 08 01:04:40 PM UTC 25
Finished Feb 08 01:04:44 PM UTC 25
Peak memory 213892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674619582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fmt.3674619582
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_rx.2147128297
Short name T136
Test name
Test status
Simulation time 125307029 ps
CPU time 4.74 seconds
Started Feb 08 01:04:42 PM UTC 25
Finished Feb 08 01:04:48 PM UTC 25
Peak memory 233096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147128297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.2147128297
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_watermark.2264405801
Short name T112
Test name
Test status
Simulation time 17086041366 ps
CPU time 102.33 seconds
Started Feb 08 01:04:40 PM UTC 25
Finished Feb 08 01:06:25 PM UTC 25
Peak memory 1308140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264405801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 12.i2c_host_fifo_watermark.2264405801
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_host_may_nack.976090696
Short name T246
Test name
Test status
Simulation time 2930780035 ps
CPU time 3.88 seconds
Started Feb 08 01:05:34 PM UTC 25
Finished Feb 08 01:05:39 PM UTC 25
Peak memory 216220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976090696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nac
k_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 12.i2c_host_may_nack.976090696
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_host_override.508821667
Short name T132
Test name
Test status
Simulation time 42734828 ps
CPU time 1 seconds
Started Feb 08 01:04:40 PM UTC 25
Finished Feb 08 01:04:43 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508821667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overrid
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 12.i2c_host_override.508821667
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_host_perf.2121226370
Short name T560
Test name
Test status
Simulation time 12071453011 ps
CPU time 115.4 seconds
Started Feb 08 01:04:43 PM UTC 25
Finished Feb 08 01:06:40 PM UTC 25
Peak memory 243224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121226370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_host_perf.2121226370
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_host_perf_precise.1103967574
Short name T135
Test name
Test status
Simulation time 97569204 ps
CPU time 1.7 seconds
Started Feb 08 01:04:44 PM UTC 25
Finished Feb 08 01:04:47 PM UTC 25
Peak memory 226100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103967574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_host_perf_precise.1103967574
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_host_smoke.350350167
Short name T515
Test name
Test status
Simulation time 3975604106 ps
CPU time 38.54 seconds
Started Feb 08 01:04:40 PM UTC 25
Finished Feb 08 01:05:20 PM UTC 25
Peak memory 423376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350350167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_host_smoke.350350167
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_host_stretch_timeout.3798456328
Short name T138
Test name
Test status
Simulation time 716063688 ps
CPU time 13.05 seconds
Started Feb 08 01:04:44 PM UTC 25
Finished Feb 08 01:04:58 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798456328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.i2c_host_stretch_timeout.3798456328
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_bad_addr.4216484000
Short name T471
Test name
Test status
Simulation time 1090591529 ps
CPU time 10.35 seconds
Started Feb 08 01:05:28 PM UTC 25
Finished Feb 08 01:05:40 PM UTC 25
Peak memory 232292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=4216484000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.4216484000
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_acq.1476743542
Short name T516
Test name
Test status
Simulation time 144349351 ps
CPU time 1.31 seconds
Started Feb 08 01:05:22 PM UTC 25
Finished Feb 08 01:05:24 PM UTC 25
Peak memory 213928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476743542 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_acq.1476743542
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_tx.3409226588
Short name T518
Test name
Test status
Simulation time 296791891 ps
CPU time 3.13 seconds
Started Feb 08 01:05:23 PM UTC 25
Finished Feb 08 01:05:27 PM UTC 25
Peak memory 215912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409226588 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_tx.3409226588
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_acq.2644985428
Short name T486
Test name
Test status
Simulation time 451384226 ps
CPU time 1.53 seconds
Started Feb 08 01:05:34 PM UTC 25
Finished Feb 08 01:05:37 PM UTC 25
Peak memory 213924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644985428 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.2644985428
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_tx.1522366247
Short name T524
Test name
Test status
Simulation time 462761678 ps
CPU time 1.55 seconds
Started Feb 08 01:05:36 PM UTC 25
Finished Feb 08 01:05:39 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522366247 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.1522366247
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_intr_smoke.243698004
Short name T513
Test name
Test status
Simulation time 7271650701 ps
CPU time 10.45 seconds
Started Feb 08 01:04:59 PM UTC 25
Finished Feb 08 01:05:11 PM UTC 25
Peak memory 230372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243698004 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_smoke.243698004
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_intr_stress_wr.960494742
Short name T580
Test name
Test status
Simulation time 25826153593 ps
CPU time 129.68 seconds
Started Feb 08 01:05:01 PM UTC 25
Finished Feb 08 01:07:13 PM UTC 25
Peak memory 1152512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96049
4742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.960494742
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull.3996481133
Short name T529
Test name
Test status
Simulation time 3777801344 ps
CPU time 4.17 seconds
Started Feb 08 01:05:39 PM UTC 25
Finished Feb 08 01:05:45 PM UTC 25
Peak memory 226284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996481133 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_acqfull.3996481133
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull_addr.373714978
Short name T530
Test name
Test status
Simulation time 546894524 ps
CPU time 5.08 seconds
Started Feb 08 01:05:41 PM UTC 25
Finished Feb 08 01:05:47 PM UTC 25
Peak memory 215924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373714978 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_acqfull_addr.373714978
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_perf.4130324257
Short name T522
Test name
Test status
Simulation time 14693791963 ps
CPU time 7.29 seconds
Started Feb 08 01:05:25 PM UTC 25
Finished Feb 08 01:05:33 PM UTC 25
Peak memory 232680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130324257 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_perf.4130324257
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_smbus_maxlen.2418779803
Short name T527
Test name
Test status
Simulation time 1046828599 ps
CPU time 3.75 seconds
Started Feb 08 01:05:39 PM UTC 25
Finished Feb 08 01:05:44 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418779803 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smbus_maxlen.2418779803
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_smoke.3110329492
Short name T519
Test name
Test status
Simulation time 7383403337 ps
CPU time 40.67 seconds
Started Feb 08 01:04:47 PM UTC 25
Finished Feb 08 01:05:29 PM UTC 25
Peak memory 230292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110329492 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smoke.3110329492
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_stress_all.2677969624
Short name T549
Test name
Test status
Simulation time 23533246777 ps
CPU time 124.66 seconds
Started Feb 08 01:05:26 PM UTC 25
Finished Feb 08 01:07:33 PM UTC 25
Peak memory 1310288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677969624 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_all.2677969624
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_stress_rd.1857371328
Short name T520
Test name
Test status
Simulation time 2184696043 ps
CPU time 37.36 seconds
Started Feb 08 01:04:52 PM UTC 25
Finished Feb 08 01:05:31 PM UTC 25
Peak memory 245264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857371328 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_rd.1857371328
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_stress_wr.2697673408
Short name T643
Test name
Test status
Simulation time 66915170593 ps
CPU time 284.8 seconds
Started Feb 08 01:04:48 PM UTC 25
Finished Feb 08 01:09:36 PM UTC 25
Peak memory 2252292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697673408 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_wr.2697673408
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_stretch.2698873112
Short name T521
Test name
Test status
Simulation time 4026260411 ps
CPU time 31.98 seconds
Started Feb 08 01:04:59 PM UTC 25
Finished Feb 08 01:05:33 PM UTC 25
Peak memory 462396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698873112 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stretch.2698873112
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_timeout.3922613755
Short name T517
Test name
Test status
Simulation time 1374768090 ps
CPU time 11.36 seconds
Started Feb 08 01:05:12 PM UTC 25
Finished Feb 08 01:05:25 PM UTC 25
Peak memory 243476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922613755 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_timeout.3922613755
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/12.i2c_target_tx_stretch_ctrl.3357905049
Short name T526
Test name
Test status
Simulation time 146343245 ps
CPU time 4.73 seconds
Started Feb 08 01:05:37 PM UTC 25
Finished Feb 08 01:05:43 PM UTC 25
Peak memory 215928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357905049 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.3357905049
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_alert_test.464960142
Short name T559
Test name
Test status
Simulation time 35460407 ps
CPU time 1 seconds
Started Feb 08 01:06:37 PM UTC 25
Finished Feb 08 01:06:40 PM UTC 25
Peak memory 213924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464960142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM
_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.464960142
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_host_error_intr.850583517
Short name T538
Test name
Test status
Simulation time 162908711 ps
CPU time 2.5 seconds
Started Feb 08 01:05:57 PM UTC 25
Finished Feb 08 01:06:01 PM UTC 25
Peak memory 226284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850583517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_host_error_intr.850583517
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_fmt_empty.3135045812
Short name T534
Test name
Test status
Simulation time 2203333226 ps
CPU time 6.96 seconds
Started Feb 08 01:05:46 PM UTC 25
Finished Feb 08 01:05:54 PM UTC 25
Peak memory 280124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135045812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empty.3135045812
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_full.3476471871
Short name T572
Test name
Test status
Simulation time 1867508809 ps
CPU time 66.52 seconds
Started Feb 08 01:05:48 PM UTC 25
Finished Feb 08 01:06:57 PM UTC 25
Peak memory 400904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476471871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_host_fifo_full.3476471871
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_overflow.166920975
Short name T599
Test name
Test status
Simulation time 3526917880 ps
CPU time 117.33 seconds
Started Feb 08 01:05:46 PM UTC 25
Finished Feb 08 01:07:46 PM UTC 25
Peak memory 517028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166920975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_host_fifo_overflow.166920975
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_fmt.1154008034
Short name T532
Test name
Test status
Simulation time 100059104 ps
CPU time 1.5 seconds
Started Feb 08 01:05:46 PM UTC 25
Finished Feb 08 01:05:49 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154008034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_fmt.1154008034
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_rx.4152076024
Short name T533
Test name
Test status
Simulation time 137742723 ps
CPU time 3.87 seconds
Started Feb 08 01:05:48 PM UTC 25
Finished Feb 08 01:05:53 PM UTC 25
Peak memory 215844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152076024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.4152076024
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_watermark.555158192
Short name T635
Test name
Test status
Simulation time 3272501061 ps
CPU time 218.05 seconds
Started Feb 08 01:05:45 PM UTC 25
Finished Feb 08 01:09:26 PM UTC 25
Peak memory 1021704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555158192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_wa
termark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_host_fifo_watermark.555158192
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_host_may_nack.3630582737
Short name T255
Test name
Test status
Simulation time 701720711 ps
CPU time 7.7 seconds
Started Feb 08 01:06:31 PM UTC 25
Finished Feb 08 01:06:40 PM UTC 25
Peak memory 216228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630582737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 13.i2c_host_may_nack.3630582737
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_host_override.1316350218
Short name T531
Test name
Test status
Simulation time 42260171 ps
CPU time 0.96 seconds
Started Feb 08 01:05:45 PM UTC 25
Finished Feb 08 01:05:47 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316350218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 13.i2c_host_override.1316350218
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_host_perf.1980620698
Short name T663
Test name
Test status
Simulation time 50731326718 ps
CPU time 266.46 seconds
Started Feb 08 01:05:49 PM UTC 25
Finished Feb 08 01:10:19 PM UTC 25
Peak memory 362188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980620698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_host_perf.1980620698
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_host_perf_precise.1137265988
Short name T536
Test name
Test status
Simulation time 382197011 ps
CPU time 1.69 seconds
Started Feb 08 01:05:54 PM UTC 25
Finished Feb 08 01:05:57 PM UTC 25
Peak memory 213860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137265988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_host_perf_precise.1137265988
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_host_smoke.3693025976
Short name T539
Test name
Test status
Simulation time 2797344853 ps
CPU time 21.9 seconds
Started Feb 08 01:05:44 PM UTC 25
Finished Feb 08 01:06:07 PM UTC 25
Peak memory 292340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693025976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_host_smoke.3693025976
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_host_stress_all.64761457
Short name T278
Test name
Test status
Simulation time 79222849205 ps
CPU time 1961.06 seconds
Started Feb 08 01:05:59 PM UTC 25
Finished Feb 08 01:38:58 PM UTC 25
Peak memory 2606856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64761457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 13.i2c_host_stress_all.64761457
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_host_stretch_timeout.1793329678
Short name T546
Test name
Test status
Simulation time 1468337129 ps
CPU time 32.23 seconds
Started Feb 08 01:05:55 PM UTC 25
Finished Feb 08 01:06:29 PM UTC 25
Peak memory 226200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793329678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.i2c_host_stretch_timeout.1793329678
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_bad_addr.3095451545
Short name T558
Test name
Test status
Simulation time 3666511282 ps
CPU time 8.24 seconds
Started Feb 08 01:06:30 PM UTC 25
Finished Feb 08 01:06:39 PM UTC 25
Peak memory 232416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3095451545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.3095451545
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_acq.3693700127
Short name T547
Test name
Test status
Simulation time 880808625 ps
CPU time 2.73 seconds
Started Feb 08 01:06:25 PM UTC 25
Finished Feb 08 01:06:29 PM UTC 25
Peak memory 215980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693700127 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_acq.3693700127
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_tx.1792547943
Short name T544
Test name
Test status
Simulation time 358952577 ps
CPU time 1.97 seconds
Started Feb 08 01:06:25 PM UTC 25
Finished Feb 08 01:06:29 PM UTC 25
Peak memory 216172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792547943 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_tx.1792547943
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_acq.1434708111
Short name T555
Test name
Test status
Simulation time 1073532153 ps
CPU time 3.73 seconds
Started Feb 08 01:06:32 PM UTC 25
Finished Feb 08 01:06:37 PM UTC 25
Peak memory 215984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434708111 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.1434708111
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_tx.2022212116
Short name T553
Test name
Test status
Simulation time 258812982 ps
CPU time 1.93 seconds
Started Feb 08 01:06:33 PM UTC 25
Finished Feb 08 01:06:36 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022212116 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.2022212116
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_hrst.1763149414
Short name T179
Test name
Test status
Simulation time 355904094 ps
CPU time 2.98 seconds
Started Feb 08 01:06:30 PM UTC 25
Finished Feb 08 01:06:34 PM UTC 25
Peak memory 226276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763149414 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_hrst.1763149414
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_intr_smoke.2437627644
Short name T545
Test name
Test status
Simulation time 1079367124 ps
CPU time 9.63 seconds
Started Feb 08 01:06:18 PM UTC 25
Finished Feb 08 01:06:29 PM UTC 25
Peak memory 232292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437627644 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_smoke.2437627644
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_intr_stress_wr.1495363821
Short name T570
Test name
Test status
Simulation time 20957499643 ps
CPU time 32.07 seconds
Started Feb 08 01:06:18 PM UTC 25
Finished Feb 08 01:06:52 PM UTC 25
Peak memory 579400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14953
63821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.1495363821
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull.1325610908
Short name T563
Test name
Test status
Simulation time 599337718 ps
CPU time 4.93 seconds
Started Feb 08 01:06:35 PM UTC 25
Finished Feb 08 01:06:41 PM UTC 25
Peak memory 226156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325610908 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_acqfull.1325610908
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull_addr.1621033247
Short name T561
Test name
Test status
Simulation time 1598120137 ps
CPU time 3.09 seconds
Started Feb 08 01:06:36 PM UTC 25
Finished Feb 08 01:06:41 PM UTC 25
Peak memory 216000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621033247 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_acqfull_addr.1621033247
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_nack_txstretch.1934431983
Short name T562
Test name
Test status
Simulation time 526753747 ps
CPU time 2.07 seconds
Started Feb 08 01:06:37 PM UTC 25
Finished Feb 08 01:06:41 PM UTC 25
Peak memory 232972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934431983 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_txstretch.1934431983
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_perf.552825617
Short name T554
Test name
Test status
Simulation time 1196152522 ps
CPU time 8.71 seconds
Started Feb 08 01:06:27 PM UTC 25
Finished Feb 08 01:06:36 PM UTC 25
Peak memory 232916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552825617 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_perf.552825617
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_smbus_maxlen.4023108197
Short name T557
Test name
Test status
Simulation time 479801197 ps
CPU time 3.43 seconds
Started Feb 08 01:06:34 PM UTC 25
Finished Feb 08 01:06:39 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023108197 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smbus_maxlen.4023108197
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_smoke.3593996389
Short name T565
Test name
Test status
Simulation time 1209965068 ps
CPU time 42.31 seconds
Started Feb 08 01:05:59 PM UTC 25
Finished Feb 08 01:06:43 PM UTC 25
Peak memory 230168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593996389 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smoke.3593996389
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_stress_all.4117773030
Short name T930
Test name
Test status
Simulation time 52447713542 ps
CPU time 662.7 seconds
Started Feb 08 01:06:28 PM UTC 25
Finished Feb 08 01:17:36 PM UTC 25
Peak memory 3067468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117773030 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_all.4117773030
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_stress_rd.3193530426
Short name T543
Test name
Test status
Simulation time 1908670489 ps
CPU time 22.5 seconds
Started Feb 08 01:06:02 PM UTC 25
Finished Feb 08 01:06:26 PM UTC 25
Peak memory 233092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193530426 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_rd.3193530426
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_stress_wr.3127591184
Short name T797
Test name
Test status
Simulation time 35290092587 ps
CPU time 428.04 seconds
Started Feb 08 01:05:59 PM UTC 25
Finished Feb 08 01:13:12 PM UTC 25
Peak memory 4087552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127591184 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_wr.3127591184
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_stretch.4265004062
Short name T541
Test name
Test status
Simulation time 1436089046 ps
CPU time 8.12 seconds
Started Feb 08 01:06:08 PM UTC 25
Finished Feb 08 01:06:17 PM UTC 25
Peak memory 251460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265004062 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stretch.4265004062
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_timeout.616466950
Short name T548
Test name
Test status
Simulation time 1438087524 ps
CPU time 10.48 seconds
Started Feb 08 01:06:19 PM UTC 25
Finished Feb 08 01:06:31 PM UTC 25
Peak memory 232980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616466950 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_timeout.616466950
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_target_tx_stretch_ctrl.1458233082
Short name T556
Test name
Test status
Simulation time 77369482 ps
CPU time 3.01 seconds
Started Feb 08 01:06:34 PM UTC 25
Finished Feb 08 01:06:38 PM UTC 25
Peak memory 215928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458233082 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.1458233082
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_alert_test.3400188567
Short name T593
Test name
Test status
Simulation time 27031841 ps
CPU time 0.96 seconds
Started Feb 08 01:07:23 PM UTC 25
Finished Feb 08 01:07:25 PM UTC 25
Peak memory 214996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400188567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.3400188567
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_host_error_intr.627457323
Short name T567
Test name
Test status
Simulation time 265232921 ps
CPU time 2.13 seconds
Started Feb 08 01:06:44 PM UTC 25
Finished Feb 08 01:06:47 PM UTC 25
Peak memory 230324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627457323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_host_error_intr.627457323
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_fmt_empty.1173496578
Short name T569
Test name
Test status
Simulation time 1862742855 ps
CPU time 9.17 seconds
Started Feb 08 01:06:41 PM UTC 25
Finished Feb 08 01:06:51 PM UTC 25
Peak memory 318912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173496578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empty.1173496578
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_full.4123609314
Short name T601
Test name
Test status
Simulation time 7363499616 ps
CPU time 64.73 seconds
Started Feb 08 01:06:42 PM UTC 25
Finished Feb 08 01:07:49 PM UTC 25
Peak memory 605620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123609314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_host_fifo_full.4123609314
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_overflow.957753661
Short name T623
Test name
Test status
Simulation time 8310294922 ps
CPU time 121.12 seconds
Started Feb 08 01:06:41 PM UTC 25
Finished Feb 08 01:08:44 PM UTC 25
Peak memory 681668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957753661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_host_fifo_overflow.957753661
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_fmt.1394619371
Short name T243
Test name
Test status
Simulation time 390753020 ps
CPU time 1.5 seconds
Started Feb 08 01:06:41 PM UTC 25
Finished Feb 08 01:06:44 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394619371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fmt.1394619371
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_rx.4142096651
Short name T571
Test name
Test status
Simulation time 188538458 ps
CPU time 9.87 seconds
Started Feb 08 01:06:42 PM UTC 25
Finished Feb 08 01:06:53 PM UTC 25
Peak memory 215880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142096651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.4142096651
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_watermark.623637938
Short name T113
Test name
Test status
Simulation time 14784172171 ps
CPU time 109.72 seconds
Started Feb 08 01:06:40 PM UTC 25
Finished Feb 08 01:08:32 PM UTC 25
Peak memory 1236808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623637938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_wa
termark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_host_fifo_watermark.623637938
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_host_override.1205582964
Short name T564
Test name
Test status
Simulation time 220996194 ps
CPU time 0.97 seconds
Started Feb 08 01:06:39 PM UTC 25
Finished Feb 08 01:06:42 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205582964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 14.i2c_host_override.1205582964
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_host_perf.1873503674
Short name T598
Test name
Test status
Simulation time 5827270052 ps
CPU time 59.45 seconds
Started Feb 08 01:06:42 PM UTC 25
Finished Feb 08 01:07:43 PM UTC 25
Peak memory 392712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873503674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_host_perf.1873503674
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_host_perf_precise.3889230733
Short name T566
Test name
Test status
Simulation time 380278346 ps
CPU time 3.04 seconds
Started Feb 08 01:06:42 PM UTC 25
Finished Feb 08 01:06:46 PM UTC 25
Peak memory 232764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889230733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_host_perf_precise.3889230733
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_host_smoke.1547919008
Short name T272
Test name
Test status
Simulation time 5019311270 ps
CPU time 50.41 seconds
Started Feb 08 01:06:37 PM UTC 25
Finished Feb 08 01:07:30 PM UTC 25
Peak memory 302720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547919008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_host_smoke.1547919008
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_host_stretch_timeout.909210386
Short name T582
Test name
Test status
Simulation time 5204833671 ps
CPU time 29.18 seconds
Started Feb 08 01:06:43 PM UTC 25
Finished Feb 08 01:07:14 PM UTC 25
Peak memory 226284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909210386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch
_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 14.i2c_host_stretch_timeout.909210386
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_bad_addr.4084851554
Short name T585
Test name
Test status
Simulation time 1773430811 ps
CPU time 7 seconds
Started Feb 08 01:07:09 PM UTC 25
Finished Feb 08 01:07:17 PM UTC 25
Peak memory 226136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=4084851554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.4084851554
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_acq.114853387
Short name T575
Test name
Test status
Simulation time 249073290 ps
CPU time 1.18 seconds
Started Feb 08 01:07:05 PM UTC 25
Finished Feb 08 01:07:07 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114853387 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_acq.114853387
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_tx.928047032
Short name T579
Test name
Test status
Simulation time 655667577 ps
CPU time 1.95 seconds
Started Feb 08 01:07:06 PM UTC 25
Finished Feb 08 01:07:09 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928047032 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_tx.928047032
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_acq.1337459248
Short name T587
Test name
Test status
Simulation time 8747795718 ps
CPU time 3.47 seconds
Started Feb 08 01:07:14 PM UTC 25
Finished Feb 08 01:07:19 PM UTC 25
Peak memory 215964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337459248 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.1337459248
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_tx.3334387046
Short name T586
Test name
Test status
Simulation time 619255845 ps
CPU time 1.55 seconds
Started Feb 08 01:07:15 PM UTC 25
Finished Feb 08 01:07:18 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334387046 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.3334387046
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_hrst.2097701010
Short name T583
Test name
Test status
Simulation time 1456573858 ps
CPU time 4.05 seconds
Started Feb 08 01:07:09 PM UTC 25
Finished Feb 08 01:07:14 PM UTC 25
Peak memory 226100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097701010 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_hrst.2097701010
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_intr_smoke.1348445731
Short name T573
Test name
Test status
Simulation time 1980826291 ps
CPU time 7.12 seconds
Started Feb 08 01:06:52 PM UTC 25
Finished Feb 08 01:07:01 PM UTC 25
Peak memory 233032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348445731 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_smoke.1348445731
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_intr_stress_wr.2378100295
Short name T758
Test name
Test status
Simulation time 14806653220 ps
CPU time 320.36 seconds
Started Feb 08 01:06:55 PM UTC 25
Finished Feb 08 01:12:19 PM UTC 25
Peak memory 3714760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23781
00295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.2378100295
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull.154096336
Short name T592
Test name
Test status
Simulation time 2133625401 ps
CPU time 4.93 seconds
Started Feb 08 01:07:19 PM UTC 25
Finished Feb 08 01:07:25 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154096336 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_acqfull.154096336
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull_addr.3964942611
Short name T591
Test name
Test status
Simulation time 448145892 ps
CPU time 4.71 seconds
Started Feb 08 01:07:19 PM UTC 25
Finished Feb 08 01:07:25 PM UTC 25
Peak memory 216184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964942611 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_acqfull_addr.3964942611
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_nack_txstretch.453135886
Short name T590
Test name
Test status
Simulation time 778346942 ps
CPU time 2.33 seconds
Started Feb 08 01:07:20 PM UTC 25
Finished Feb 08 01:07:24 PM UTC 25
Peak memory 233168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453135886 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_txstretch.453135886
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_perf.725103797
Short name T584
Test name
Test status
Simulation time 1569326203 ps
CPU time 8.13 seconds
Started Feb 08 01:07:08 PM UTC 25
Finished Feb 08 01:07:17 PM UTC 25
Peak memory 233112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725103797 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_perf.725103797
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_smbus_maxlen.468256682
Short name T589
Test name
Test status
Simulation time 400316120 ps
CPU time 3.17 seconds
Started Feb 08 01:07:18 PM UTC 25
Finished Feb 08 01:07:23 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468256682 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smbus_maxlen.468256682
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_smoke.2988237800
Short name T574
Test name
Test status
Simulation time 6799414778 ps
CPU time 16.52 seconds
Started Feb 08 01:06:47 PM UTC 25
Finished Feb 08 01:07:05 PM UTC 25
Peak memory 226520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988237800 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smoke.2988237800
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_stress_all.3726244598
Short name T665
Test name
Test status
Simulation time 94664470392 ps
CPU time 193.42 seconds
Started Feb 08 01:07:08 PM UTC 25
Finished Feb 08 01:10:24 PM UTC 25
Peak memory 1154508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726244598 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_all.3726244598
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_stress_rd.3187981094
Short name T581
Test name
Test status
Simulation time 11677389053 ps
CPU time 43.26 seconds
Started Feb 08 01:06:48 PM UTC 25
Finished Feb 08 01:07:33 PM UTC 25
Peak memory 249296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187981094 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_rd.3187981094
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_stress_wr.4169497125
Short name T576
Test name
Test status
Simulation time 9933161526 ps
CPU time 17.49 seconds
Started Feb 08 01:06:48 PM UTC 25
Finished Feb 08 01:07:07 PM UTC 25
Peak memory 215976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169497125 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_wr.4169497125
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_stretch.807943464
Short name T577
Test name
Test status
Simulation time 1750822397 ps
CPU time 14.06 seconds
Started Feb 08 01:06:52 PM UTC 25
Finished Feb 08 01:07:08 PM UTC 25
Peak memory 298500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807943464 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stretch.807943464
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_timeout.1045880864
Short name T578
Test name
Test status
Simulation time 6768688710 ps
CPU time 9.47 seconds
Started Feb 08 01:06:58 PM UTC 25
Finished Feb 08 01:07:09 PM UTC 25
Peak memory 232676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045880864 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_timeout.1045880864
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/14.i2c_target_tx_stretch_ctrl.318721982
Short name T588
Test name
Test status
Simulation time 139601438 ps
CPU time 4.73 seconds
Started Feb 08 01:07:15 PM UTC 25
Finished Feb 08 01:07:21 PM UTC 25
Peak memory 215864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318721982 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.318721982
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_alert_test.3682698707
Short name T618
Test name
Test status
Simulation time 15493190 ps
CPU time 0.91 seconds
Started Feb 08 01:08:33 PM UTC 25
Finished Feb 08 01:08:35 PM UTC 25
Peak memory 214936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682698707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.3682698707
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_host_error_intr.3560519572
Short name T597
Test name
Test status
Simulation time 148315698 ps
CPU time 5.76 seconds
Started Feb 08 01:07:35 PM UTC 25
Finished Feb 08 01:07:43 PM UTC 25
Peak memory 226480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560519572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_host_error_intr.3560519572
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_fmt_empty.284679541
Short name T595
Test name
Test status
Simulation time 254193395 ps
CPU time 7.36 seconds
Started Feb 08 01:07:26 PM UTC 25
Finished Feb 08 01:07:35 PM UTC 25
Peak memory 265892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284679541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empty.284679541
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_full.1354238168
Short name T640
Test name
Test status
Simulation time 7596667375 ps
CPU time 120.28 seconds
Started Feb 08 01:07:30 PM UTC 25
Finished Feb 08 01:09:33 PM UTC 25
Peak memory 417496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354238168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_host_fifo_full.1354238168
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_overflow.811566066
Short name T657
Test name
Test status
Simulation time 1744003810 ps
CPU time 144.38 seconds
Started Feb 08 01:07:26 PM UTC 25
Finished Feb 08 01:09:54 PM UTC 25
Peak memory 661248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811566066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_host_fifo_overflow.811566066
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_fmt.1999819862
Short name T594
Test name
Test status
Simulation time 456509123 ps
CPU time 1.63 seconds
Started Feb 08 01:07:26 PM UTC 25
Finished Feb 08 01:07:29 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999819862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fmt.1999819862
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_rx.2672194568
Short name T596
Test name
Test status
Simulation time 665663354 ps
CPU time 9.57 seconds
Started Feb 08 01:07:28 PM UTC 25
Finished Feb 08 01:07:40 PM UTC 25
Peak memory 215848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672194568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.2672194568
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_watermark.2116789410
Short name T662
Test name
Test status
Simulation time 30102640924 ps
CPU time 163.81 seconds
Started Feb 08 01:07:25 PM UTC 25
Finished Feb 08 01:10:11 PM UTC 25
Peak memory 1519052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116789410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 15.i2c_host_fifo_watermark.2116789410
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_host_may_nack.761747082
Short name T621
Test name
Test status
Simulation time 365270546 ps
CPU time 16.69 seconds
Started Feb 08 01:08:20 PM UTC 25
Finished Feb 08 01:08:38 PM UTC 25
Peak memory 215916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761747082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nac
k_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 15.i2c_host_may_nack.761747082
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_host_override.1757173685
Short name T528
Test name
Test status
Simulation time 37506407 ps
CPU time 0.92 seconds
Started Feb 08 01:07:25 PM UTC 25
Finished Feb 08 01:07:27 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757173685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 15.i2c_host_override.1757173685
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_host_perf.2784230823
Short name T610
Test name
Test status
Simulation time 5134108992 ps
CPU time 50.44 seconds
Started Feb 08 01:07:30 PM UTC 25
Finished Feb 08 01:08:23 PM UTC 25
Peak memory 238484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784230823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_host_perf.2784230823
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_host_perf_precise.345321164
Short name T736
Test name
Test status
Simulation time 24816944232 ps
CPU time 243.38 seconds
Started Feb 08 01:07:34 PM UTC 25
Finished Feb 08 01:11:41 PM UTC 25
Peak memory 746984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345321164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pr
ecise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_host_perf_precise.345321164
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_host_smoke.1818477056
Short name T631
Test name
Test status
Simulation time 1793817195 ps
CPU time 106.65 seconds
Started Feb 08 01:07:24 PM UTC 25
Finished Feb 08 01:09:13 PM UTC 25
Peak memory 446204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818477056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_host_smoke.1818477056
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_host_stress_all.3895909089
Short name T276
Test name
Test status
Simulation time 71053108114 ps
CPU time 2133.19 seconds
Started Feb 08 01:07:41 PM UTC 25
Finished Feb 08 01:43:34 PM UTC 25
Peak memory 3426088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895909089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_host_stress_all.3895909089
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_host_stretch_timeout.2524625652
Short name T600
Test name
Test status
Simulation time 565539793 ps
CPU time 11.94 seconds
Started Feb 08 01:07:34 PM UTC 25
Finished Feb 08 01:07:48 PM UTC 25
Peak memory 232796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524625652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.i2c_host_stretch_timeout.2524625652
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_bad_addr.1250484284
Short name T611
Test name
Test status
Simulation time 6014945990 ps
CPU time 11.39 seconds
Started Feb 08 01:08:10 PM UTC 25
Finished Feb 08 01:08:23 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1250484284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.1250484284
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_acq.2213245983
Short name T606
Test name
Test status
Simulation time 870635426 ps
CPU time 1.87 seconds
Started Feb 08 01:08:05 PM UTC 25
Finished Feb 08 01:08:08 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213245983 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_acq.2213245983
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_tx.2786310410
Short name T607
Test name
Test status
Simulation time 186274252 ps
CPU time 1.25 seconds
Started Feb 08 01:08:07 PM UTC 25
Finished Feb 08 01:08:10 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786310410 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_tx.2786310410
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_acq.4215802971
Short name T614
Test name
Test status
Simulation time 537121275 ps
CPU time 4.43 seconds
Started Feb 08 01:08:24 PM UTC 25
Finished Feb 08 01:08:29 PM UTC 25
Peak memory 215904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215802971 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.4215802971
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_tx.3910959095
Short name T612
Test name
Test status
Simulation time 142417871 ps
CPU time 1.46 seconds
Started Feb 08 01:08:24 PM UTC 25
Finished Feb 08 01:08:26 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910959095 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.3910959095
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_intr_smoke.3715210390
Short name T603
Test name
Test status
Simulation time 2646715143 ps
CPU time 12.22 seconds
Started Feb 08 01:07:49 PM UTC 25
Finished Feb 08 01:08:03 PM UTC 25
Peak memory 233176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715210390 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_smoke.3715210390
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_intr_stress_wr.2517408265
Short name T602
Test name
Test status
Simulation time 13107844924 ps
CPU time 11.14 seconds
Started Feb 08 01:07:50 PM UTC 25
Finished Feb 08 01:08:03 PM UTC 25
Peak memory 384584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25174
08265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.2517408265
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull.2506003193
Short name T619
Test name
Test status
Simulation time 560795925 ps
CPU time 4.26 seconds
Started Feb 08 01:08:30 PM UTC 25
Finished Feb 08 01:08:36 PM UTC 25
Peak memory 226100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506003193 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_acqfull.2506003193
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull_addr.3583558486
Short name T617
Test name
Test status
Simulation time 944352587 ps
CPU time 3.78 seconds
Started Feb 08 01:08:30 PM UTC 25
Finished Feb 08 01:08:35 PM UTC 25
Peak memory 215988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583558486 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_acqfull_addr.3583558486
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_nack_txstretch.1399710390
Short name T620
Test name
Test status
Simulation time 131179590 ps
CPU time 2.15 seconds
Started Feb 08 01:08:32 PM UTC 25
Finished Feb 08 01:08:36 PM UTC 25
Peak memory 232952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399710390 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_txstretch.1399710390
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_perf.958729658
Short name T608
Test name
Test status
Simulation time 886831049 ps
CPU time 6.52 seconds
Started Feb 08 01:08:07 PM UTC 25
Finished Feb 08 01:08:15 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958729658 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_perf.958729658
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_smbus_maxlen.2775253950
Short name T616
Test name
Test status
Simulation time 1712165977 ps
CPU time 3.37 seconds
Started Feb 08 01:08:28 PM UTC 25
Finished Feb 08 01:08:33 PM UTC 25
Peak memory 215636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775253950 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smbus_maxlen.2775253950
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_smoke.717309841
Short name T604
Test name
Test status
Simulation time 3054376765 ps
CPU time 19.52 seconds
Started Feb 08 01:07:44 PM UTC 25
Finished Feb 08 01:08:05 PM UTC 25
Peak memory 226272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717309841 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smoke.717309841
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_stress_all.1532282668
Short name T691
Test name
Test status
Simulation time 56342052606 ps
CPU time 153.17 seconds
Started Feb 08 01:08:09 PM UTC 25
Finished Feb 08 01:10:45 PM UTC 25
Peak memory 1451476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532282668 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_all.1532282668
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_stress_rd.2486394380
Short name T605
Test name
Test status
Simulation time 4045448816 ps
CPU time 18.87 seconds
Started Feb 08 01:07:46 PM UTC 25
Finished Feb 08 01:08:06 PM UTC 25
Peak memory 233028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486394380 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_rd.2486394380
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_stress_wr.2779323958
Short name T1748
Test name
Test status
Simulation time 68083949317 ps
CPU time 2520.62 seconds
Started Feb 08 01:07:45 PM UTC 25
Finished Feb 08 01:50:06 PM UTC 25
Peak memory 12525056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779323958 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_wr.2779323958
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_stretch.1608343502
Short name T626
Test name
Test status
Simulation time 5706732909 ps
CPU time 63.91 seconds
Started Feb 08 01:07:47 PM UTC 25
Finished Feb 08 01:08:53 PM UTC 25
Peak memory 1084936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608343502 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stretch.1608343502
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_timeout.2791078760
Short name T609
Test name
Test status
Simulation time 1472013666 ps
CPU time 11.3 seconds
Started Feb 08 01:08:03 PM UTC 25
Finished Feb 08 01:08:16 PM UTC 25
Peak memory 233040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791078760 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_timeout.2791078760
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_tx_stretch_ctrl.3730326655
Short name T615
Test name
Test status
Simulation time 141793075 ps
CPU time 3.58 seconds
Started Feb 08 01:08:27 PM UTC 25
Finished Feb 08 01:08:32 PM UTC 25
Peak memory 215864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730326655 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.3730326655
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_alert_test.4168174946
Short name T651
Test name
Test status
Simulation time 17654644 ps
CPU time 0.9 seconds
Started Feb 08 01:09:43 PM UTC 25
Finished Feb 08 01:09:45 PM UTC 25
Peak memory 213916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168174946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.4168174946
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_host_error_intr.455793363
Short name T628
Test name
Test status
Simulation time 330764080 ps
CPU time 2.72 seconds
Started Feb 08 01:08:54 PM UTC 25
Finished Feb 08 01:08:58 PM UTC 25
Peak memory 226224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455793363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_host_error_intr.455793363
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_fmt_empty.2744925751
Short name T629
Test name
Test status
Simulation time 1570783184 ps
CPU time 22.3 seconds
Started Feb 08 01:08:39 PM UTC 25
Finished Feb 08 01:09:02 PM UTC 25
Peak memory 273796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744925751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empty.2744925751
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_full.1177117524
Short name T715
Test name
Test status
Simulation time 11256075700 ps
CPU time 150.4 seconds
Started Feb 08 01:08:40 PM UTC 25
Finished Feb 08 01:11:13 PM UTC 25
Peak memory 765512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177117524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_host_fifo_full.1177117524
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_overflow.3128621264
Short name T678
Test name
Test status
Simulation time 5950647959 ps
CPU time 116.61 seconds
Started Feb 08 01:08:36 PM UTC 25
Finished Feb 08 01:10:35 PM UTC 25
Peak memory 943684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128621264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_host_fifo_overflow.3128621264
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_fmt.492144297
Short name T622
Test name
Test status
Simulation time 179863455 ps
CPU time 1.57 seconds
Started Feb 08 01:08:37 PM UTC 25
Finished Feb 08 01:08:39 PM UTC 25
Peak memory 214516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492144297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fmt.492144297
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_rx.2923906927
Short name T625
Test name
Test status
Simulation time 169827610 ps
CPU time 11.29 seconds
Started Feb 08 01:08:40 PM UTC 25
Finished Feb 08 01:08:52 PM UTC 25
Peak memory 249216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923906927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.2923906927
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_watermark.2662751169
Short name T712
Test name
Test status
Simulation time 14306226330 ps
CPU time 151.12 seconds
Started Feb 08 01:08:36 PM UTC 25
Finished Feb 08 01:11:10 PM UTC 25
Peak memory 1482192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662751169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 16.i2c_host_fifo_watermark.2662751169
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_host_may_nack.460615675
Short name T656
Test name
Test status
Simulation time 1311844624 ps
CPU time 16.45 seconds
Started Feb 08 01:09:35 PM UTC 25
Finished Feb 08 01:09:53 PM UTC 25
Peak memory 215932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460615675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nac
k_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 16.i2c_host_may_nack.460615675
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_host_override.2697741865
Short name T141
Test name
Test status
Simulation time 62331060 ps
CPU time 0.87 seconds
Started Feb 08 01:08:36 PM UTC 25
Finished Feb 08 01:08:38 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697741865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 16.i2c_host_override.2697741865
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_host_perf.604087955
Short name T40
Test name
Test status
Simulation time 7196021638 ps
CPU time 527.22 seconds
Started Feb 08 01:08:45 PM UTC 25
Finished Feb 08 01:17:38 PM UTC 25
Peak memory 1642044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604087955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_host_perf.604087955
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_host_perf_precise.2136047980
Short name T627
Test name
Test status
Simulation time 238450196 ps
CPU time 6.09 seconds
Started Feb 08 01:08:47 PM UTC 25
Finished Feb 08 01:08:54 PM UTC 25
Peak memory 215848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136047980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_host_perf_precise.2136047980
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_host_smoke.257535793
Short name T654
Test name
Test status
Simulation time 20728666550 ps
CPU time 74.4 seconds
Started Feb 08 01:08:33 PM UTC 25
Finished Feb 08 01:09:50 PM UTC 25
Peak memory 368144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257535793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_host_smoke.257535793
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_host_stretch_timeout.3458575078
Short name T653
Test name
Test status
Simulation time 4280181204 ps
CPU time 52.72 seconds
Started Feb 08 01:08:53 PM UTC 25
Finished Feb 08 01:09:48 PM UTC 25
Peak memory 226212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458575078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.i2c_host_stretch_timeout.3458575078
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_bad_addr.3778798167
Short name T644
Test name
Test status
Simulation time 2387172445 ps
CPU time 5.18 seconds
Started Feb 08 01:09:31 PM UTC 25
Finished Feb 08 01:09:38 PM UTC 25
Peak memory 226180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3778798167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.3778798167
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_acq.1855195448
Short name T638
Test name
Test status
Simulation time 240234851 ps
CPU time 2.23 seconds
Started Feb 08 01:09:27 PM UTC 25
Finished Feb 08 01:09:30 PM UTC 25
Peak memory 216176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855195448 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_acq.1855195448
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_tx.3479036711
Short name T637
Test name
Test status
Simulation time 255402783 ps
CPU time 1.34 seconds
Started Feb 08 01:09:27 PM UTC 25
Finished Feb 08 01:09:29 PM UTC 25
Peak memory 226140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479036711 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_tx.3479036711
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_acq.1180753572
Short name T647
Test name
Test status
Simulation time 671211906 ps
CPU time 4.53 seconds
Started Feb 08 01:09:36 PM UTC 25
Finished Feb 08 01:09:42 PM UTC 25
Peak memory 215944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180753572 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.1180753572
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_hrst.1037631270
Short name T645
Test name
Test status
Simulation time 3171721690 ps
CPU time 3.03 seconds
Started Feb 08 01:09:33 PM UTC 25
Finished Feb 08 01:09:38 PM UTC 25
Peak memory 226284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037631270 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_hrst.1037631270
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_intr_smoke.3020410925
Short name T636
Test name
Test status
Simulation time 1406175927 ps
CPU time 11.33 seconds
Started Feb 08 01:09:14 PM UTC 25
Finished Feb 08 01:09:26 PM UTC 25
Peak memory 247252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020410925 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_smoke.3020410925
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_intr_stress_wr.1596756889
Short name T634
Test name
Test status
Simulation time 674868192 ps
CPU time 1.91 seconds
Started Feb 08 01:09:20 PM UTC 25
Finished Feb 08 01:09:23 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15967
56889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.1596756889
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull.1312064593
Short name T649
Test name
Test status
Simulation time 2473717492 ps
CPU time 4.86 seconds
Started Feb 08 01:09:39 PM UTC 25
Finished Feb 08 01:09:45 PM UTC 25
Peak memory 226156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312064593 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_acqfull.1312064593
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull_addr.1283527596
Short name T652
Test name
Test status
Simulation time 426474035 ps
CPU time 4.21 seconds
Started Feb 08 01:09:41 PM UTC 25
Finished Feb 08 01:09:46 PM UTC 25
Peak memory 215924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283527596 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_acqfull_addr.1283527596
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_perf.1655753515
Short name T642
Test name
Test status
Simulation time 1489611831 ps
CPU time 7.45 seconds
Started Feb 08 01:09:27 PM UTC 25
Finished Feb 08 01:09:36 PM UTC 25
Peak memory 226344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655753515 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_perf.1655753515
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_smbus_maxlen.2321398213
Short name T648
Test name
Test status
Simulation time 953893517 ps
CPU time 3.5 seconds
Started Feb 08 01:09:39 PM UTC 25
Finished Feb 08 01:09:44 PM UTC 25
Peak memory 215640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321398213 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smbus_maxlen.2321398213
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_smoke.3619897376
Short name T639
Test name
Test status
Simulation time 911023123 ps
CPU time 32.04 seconds
Started Feb 08 01:08:59 PM UTC 25
Finished Feb 08 01:09:33 PM UTC 25
Peak memory 226060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619897376 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smoke.3619897376
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_stress_all.3261745035
Short name T650
Test name
Test status
Simulation time 94479923989 ps
CPU time 56.19 seconds
Started Feb 08 01:09:30 PM UTC 25
Finished Feb 08 01:10:28 PM UTC 25
Peak memory 259636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261745035 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_all.3261745035
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_stress_rd.4172620466
Short name T630
Test name
Test status
Simulation time 314847938 ps
CPU time 5.98 seconds
Started Feb 08 01:09:04 PM UTC 25
Finished Feb 08 01:09:11 PM UTC 25
Peak memory 215824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172620466 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_rd.4172620466
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_stress_wr.4107058145
Short name T632
Test name
Test status
Simulation time 14941658319 ps
CPU time 15.43 seconds
Started Feb 08 01:09:02 PM UTC 25
Finished Feb 08 01:09:19 PM UTC 25
Peak memory 216036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107058145 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_wr.4107058145
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_stretch.2470604549
Short name T633
Test name
Test status
Simulation time 1910726143 ps
CPU time 9.28 seconds
Started Feb 08 01:09:12 PM UTC 25
Finished Feb 08 01:09:22 PM UTC 25
Peak memory 226352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470604549 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stretch.2470604549
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_timeout.3174091036
Short name T641
Test name
Test status
Simulation time 2178677181 ps
CPU time 10.84 seconds
Started Feb 08 01:09:23 PM UTC 25
Finished Feb 08 01:09:35 PM UTC 25
Peak memory 233200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174091036 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_timeout.3174091036
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/16.i2c_target_tx_stretch_ctrl.3627130975
Short name T646
Test name
Test status
Simulation time 71904059 ps
CPU time 2.41 seconds
Started Feb 08 01:09:38 PM UTC 25
Finished Feb 08 01:09:41 PM UTC 25
Peak memory 215860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627130975 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.3627130975
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_alert_test.2834657276
Short name T685
Test name
Test status
Simulation time 19988157 ps
CPU time 0.9 seconds
Started Feb 08 01:10:37 PM UTC 25
Finished Feb 08 01:10:39 PM UTC 25
Peak memory 213916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834657276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2834657276
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_error_intr.2058000976
Short name T660
Test name
Test status
Simulation time 590576602 ps
CPU time 2.24 seconds
Started Feb 08 01:09:55 PM UTC 25
Finished Feb 08 01:09:58 PM UTC 25
Peak memory 226280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058000976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_host_error_intr.2058000976
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_fmt_empty.2738828080
Short name T661
Test name
Test status
Simulation time 454316380 ps
CPU time 15.63 seconds
Started Feb 08 01:09:48 PM UTC 25
Finished Feb 08 01:10:05 PM UTC 25
Peak memory 263620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738828080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empty.2738828080
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_full.1423297473
Short name T737
Test name
Test status
Simulation time 3529757698 ps
CPU time 111.77 seconds
Started Feb 08 01:09:51 PM UTC 25
Finished Feb 08 01:11:44 PM UTC 25
Peak memory 634444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423297473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_host_fifo_full.1423297473
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_overflow.4208142210
Short name T819
Test name
Test status
Simulation time 42335819830 ps
CPU time 223.79 seconds
Started Feb 08 01:09:46 PM UTC 25
Finished Feb 08 01:13:34 PM UTC 25
Peak memory 808456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208142210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_host_fifo_overflow.4208142210
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_fmt.1202607261
Short name T655
Test name
Test status
Simulation time 66966251 ps
CPU time 1.27 seconds
Started Feb 08 01:09:47 PM UTC 25
Finished Feb 08 01:09:50 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202607261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fmt.1202607261
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_rx.2676802933
Short name T659
Test name
Test status
Simulation time 386795915 ps
CPU time 5.64 seconds
Started Feb 08 01:09:49 PM UTC 25
Finished Feb 08 01:09:56 PM UTC 25
Peak memory 215892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676802933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.2676802933
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_watermark.3762583404
Short name T862
Test name
Test status
Simulation time 20239800495 ps
CPU time 302.43 seconds
Started Feb 08 01:09:46 PM UTC 25
Finished Feb 08 01:14:53 PM UTC 25
Peak memory 1345112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762583404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 17.i2c_host_fifo_watermark.3762583404
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_may_nack.2471294762
Short name T256
Test name
Test status
Simulation time 208160250 ps
CPU time 9.68 seconds
Started Feb 08 01:10:31 PM UTC 25
Finished Feb 08 01:10:42 PM UTC 25
Peak memory 216104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471294762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 17.i2c_host_may_nack.2471294762
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_mode_toggle.951853386
Short name T682
Test name
Test status
Simulation time 180076783 ps
CPU time 6.79 seconds
Started Feb 08 01:10:30 PM UTC 25
Finished Feb 08 01:10:38 PM UTC 25
Peak memory 241308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951853386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_to
ggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_host_mode_toggle.951853386
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_perf.3504807270
Short name T658
Test name
Test status
Simulation time 481423695 ps
CPU time 3.78 seconds
Started Feb 08 01:09:51 PM UTC 25
Finished Feb 08 01:09:56 PM UTC 25
Peak memory 241096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504807270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_host_perf.3504807270
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_perf_precise.672278049
Short name T804
Test name
Test status
Simulation time 24733242099 ps
CPU time 206.07 seconds
Started Feb 08 01:09:53 PM UTC 25
Finished Feb 08 01:13:22 PM UTC 25
Peak memory 215980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672278049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pr
ecise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_host_perf_precise.672278049
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_smoke.3360295031
Short name T674
Test name
Test status
Simulation time 966407253 ps
CPU time 46.63 seconds
Started Feb 08 01:09:44 PM UTC 25
Finished Feb 08 01:10:33 PM UTC 25
Peak memory 300492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360295031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_host_smoke.3360295031
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_stress_all.2067013048
Short name T275
Test name
Test status
Simulation time 8172172559 ps
CPU time 581.81 seconds
Started Feb 08 01:09:56 PM UTC 25
Finished Feb 08 01:19:44 PM UTC 25
Peak memory 1379916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067013048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_host_stress_all.2067013048
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_host_stretch_timeout.2964204830
Short name T672
Test name
Test status
Simulation time 2901413760 ps
CPU time 34.75 seconds
Started Feb 08 01:09:54 PM UTC 25
Finished Feb 08 01:10:30 PM UTC 25
Peak memory 226456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964204830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.i2c_host_stretch_timeout.2964204830
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_bad_addr.381047897
Short name T686
Test name
Test status
Simulation time 3672611252 ps
CPU time 9.13 seconds
Started Feb 08 01:10:29 PM UTC 25
Finished Feb 08 01:10:40 PM UTC 25
Peak memory 233216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=381047897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.381047897
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_acq.2299705154
Short name T670
Test name
Test status
Simulation time 283974647 ps
CPU time 1.72 seconds
Started Feb 08 01:10:26 PM UTC 25
Finished Feb 08 01:10:29 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299705154 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_acq.2299705154
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_tx.609374584
Short name T669
Test name
Test status
Simulation time 163145853 ps
CPU time 1.62 seconds
Started Feb 08 01:10:26 PM UTC 25
Finished Feb 08 01:10:29 PM UTC 25
Peak memory 224764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609374584 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_tx.609374584
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_acq.1434206419
Short name T679
Test name
Test status
Simulation time 1908215526 ps
CPU time 3.48 seconds
Started Feb 08 01:10:31 PM UTC 25
Finished Feb 08 01:10:36 PM UTC 25
Peak memory 215984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434206419 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.1434206419
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_tx.444744954
Short name T677
Test name
Test status
Simulation time 487210203 ps
CPU time 1.87 seconds
Started Feb 08 01:10:32 PM UTC 25
Finished Feb 08 01:10:35 PM UTC 25
Peak memory 214232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444744954 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.444744954
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_hrst.1953594480
Short name T676
Test name
Test status
Simulation time 287245507 ps
CPU time 3.13 seconds
Started Feb 08 01:10:30 PM UTC 25
Finished Feb 08 01:10:35 PM UTC 25
Peak memory 226176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953594480 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_hrst.1953594480
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_intr_smoke.2577264520
Short name T666
Test name
Test status
Simulation time 4036773299 ps
CPU time 8.55 seconds
Started Feb 08 01:10:15 PM UTC 25
Finished Feb 08 01:10:25 PM UTC 25
Peak memory 226536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577264520 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_smoke.2577264520
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_intr_stress_wr.4181538980
Short name T668
Test name
Test status
Simulation time 14893234623 ps
CPU time 8.65 seconds
Started Feb 08 01:10:16 PM UTC 25
Finished Feb 08 01:10:27 PM UTC 25
Peak memory 216028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41815
38980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.4181538980
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull.725954181
Short name T688
Test name
Test status
Simulation time 491552043 ps
CPU time 4.05 seconds
Started Feb 08 01:10:35 PM UTC 25
Finished Feb 08 01:10:41 PM UTC 25
Peak memory 226400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725954181 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_acqfull.725954181
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull_addr.2703723525
Short name T689
Test name
Test status
Simulation time 2261667659 ps
CPU time 3.94 seconds
Started Feb 08 01:10:36 PM UTC 25
Finished Feb 08 01:10:42 PM UTC 25
Peak memory 215984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703723525 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_acqfull_addr.2703723525
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_perf.472902028
Short name T675
Test name
Test status
Simulation time 590848323 ps
CPU time 5.45 seconds
Started Feb 08 01:10:27 PM UTC 25
Finished Feb 08 01:10:33 PM UTC 25
Peak memory 232884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472902028 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_perf.472902028
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_smbus_maxlen.3184652985
Short name T684
Test name
Test status
Simulation time 2461277245 ps
CPU time 3.08 seconds
Started Feb 08 01:10:34 PM UTC 25
Finished Feb 08 01:10:39 PM UTC 25
Peak memory 216024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184652985 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smbus_maxlen.3184652985
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_smoke.61016139
Short name T671
Test name
Test status
Simulation time 5813998194 ps
CPU time 31 seconds
Started Feb 08 01:09:57 PM UTC 25
Finished Feb 08 01:10:30 PM UTC 25
Peak memory 226272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61016139 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smoke.61016139
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_stress_all.3202631152
Short name T699
Test name
Test status
Simulation time 5171528513 ps
CPU time 26.68 seconds
Started Feb 08 01:10:28 PM UTC 25
Finished Feb 08 01:10:56 PM UTC 25
Peak memory 247324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202631152 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_all.3202631152
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_stress_rd.4153577852
Short name T664
Test name
Test status
Simulation time 2749865164 ps
CPU time 14.88 seconds
Started Feb 08 01:10:06 PM UTC 25
Finished Feb 08 01:10:22 PM UTC 25
Peak memory 233020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153577852 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_rd.4153577852
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_stress_wr.1840088673
Short name T719
Test name
Test status
Simulation time 28951445680 ps
CPU time 73.9 seconds
Started Feb 08 01:09:59 PM UTC 25
Finished Feb 08 01:11:15 PM UTC 25
Peak memory 1211904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840088673 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_wr.1840088673
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_stretch.1882634473
Short name T698
Test name
Test status
Simulation time 4325745985 ps
CPU time 41.75 seconds
Started Feb 08 01:10:12 PM UTC 25
Finished Feb 08 01:10:56 PM UTC 25
Peak memory 614216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882634473 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stretch.1882634473
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_timeout.1183567878
Short name T673
Test name
Test status
Simulation time 4985631749 ps
CPU time 9.42 seconds
Started Feb 08 01:10:20 PM UTC 25
Finished Feb 08 01:10:31 PM UTC 25
Peak memory 233172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183567878 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_timeout.1183567878
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/17.i2c_target_tx_stretch_ctrl.3286605037
Short name T681
Test name
Test status
Simulation time 103434994 ps
CPU time 2.53 seconds
Started Feb 08 01:10:33 PM UTC 25
Finished Feb 08 01:10:37 PM UTC 25
Peak memory 215924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286605037 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.3286605037
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_alert_test.1669113693
Short name T718
Test name
Test status
Simulation time 19122220 ps
CPU time 0.95 seconds
Started Feb 08 01:11:11 PM UTC 25
Finished Feb 08 01:11:13 PM UTC 25
Peak memory 214996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669113693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.1669113693
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_host_error_intr.666527660
Short name T695
Test name
Test status
Simulation time 402767913 ps
CPU time 2.39 seconds
Started Feb 08 01:10:44 PM UTC 25
Finished Feb 08 01:10:48 PM UTC 25
Peak memory 226276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666527660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_host_error_intr.666527660
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_fmt_empty.3744681709
Short name T692
Test name
Test status
Simulation time 197254414 ps
CPU time 3.9 seconds
Started Feb 08 01:10:41 PM UTC 25
Finished Feb 08 01:10:47 PM UTC 25
Peak memory 251644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744681709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empty.3744681709
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_full.2714905824
Short name T760
Test name
Test status
Simulation time 1920510751 ps
CPU time 96.47 seconds
Started Feb 08 01:10:41 PM UTC 25
Finished Feb 08 01:12:20 PM UTC 25
Peak memory 654860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714905824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_host_fifo_full.2714905824
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_overflow.244654374
Short name T761
Test name
Test status
Simulation time 2505036311 ps
CPU time 97.82 seconds
Started Feb 08 01:10:40 PM UTC 25
Finished Feb 08 01:12:20 PM UTC 25
Peak memory 855816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244654374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_host_fifo_overflow.244654374
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_fmt.1215990685
Short name T690
Test name
Test status
Simulation time 1499349139 ps
CPU time 1.52 seconds
Started Feb 08 01:10:40 PM UTC 25
Finished Feb 08 01:10:43 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215990685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fmt.1215990685
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_rx.410130581
Short name T694
Test name
Test status
Simulation time 729361750 ps
CPU time 4.6 seconds
Started Feb 08 01:10:41 PM UTC 25
Finished Feb 08 01:10:47 PM UTC 25
Peak memory 215892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410130581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.410130581
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_watermark.3992540476
Short name T790
Test name
Test status
Simulation time 10967785704 ps
CPU time 138.79 seconds
Started Feb 08 01:10:40 PM UTC 25
Finished Feb 08 01:13:02 PM UTC 25
Peak memory 708368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992540476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 18.i2c_host_fifo_watermark.3992540476
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_host_may_nack.1412448628
Short name T257
Test name
Test status
Simulation time 2392588196 ps
CPU time 7.58 seconds
Started Feb 08 01:11:05 PM UTC 25
Finished Feb 08 01:11:14 PM UTC 25
Peak memory 216276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412448628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 18.i2c_host_may_nack.1412448628
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_host_mode_toggle.1941073696
Short name T706
Test name
Test status
Simulation time 185294844 ps
CPU time 1.75 seconds
Started Feb 08 01:11:02 PM UTC 25
Finished Feb 08 01:11:05 PM UTC 25
Peak memory 214524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941073696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_t
oggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_host_mode_toggle.1941073696
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_host_override.2185587448
Short name T143
Test name
Test status
Simulation time 22823661 ps
CPU time 1.07 seconds
Started Feb 08 01:10:38 PM UTC 25
Finished Feb 08 01:10:41 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185587448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 18.i2c_host_override.2185587448
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_host_perf.4181055216
Short name T727
Test name
Test status
Simulation time 8224203310 ps
CPU time 41.7 seconds
Started Feb 08 01:10:42 PM UTC 25
Finished Feb 08 01:11:26 PM UTC 25
Peak memory 427508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181055216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_host_perf.4181055216
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_host_perf_precise.143871372
Short name T693
Test name
Test status
Simulation time 31110300 ps
CPU time 2.56 seconds
Started Feb 08 01:10:43 PM UTC 25
Finished Feb 08 01:10:47 PM UTC 25
Peak memory 236276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143871372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pr
ecise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_host_perf_precise.143871372
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_host_smoke.3459884844
Short name T724
Test name
Test status
Simulation time 1884457309 ps
CPU time 43.84 seconds
Started Feb 08 01:10:38 PM UTC 25
Finished Feb 08 01:11:24 PM UTC 25
Peak memory 429752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459884844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_host_smoke.3459884844
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_host_stretch_timeout.2189508429
Short name T696
Test name
Test status
Simulation time 1221815640 ps
CPU time 10.18 seconds
Started Feb 08 01:10:43 PM UTC 25
Finished Feb 08 01:10:55 PM UTC 25
Peak memory 232884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189508429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_host_stretch_timeout.2189508429
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_bad_addr.3140847629
Short name T707
Test name
Test status
Simulation time 535471493 ps
CPU time 4.59 seconds
Started Feb 08 01:11:01 PM UTC 25
Finished Feb 08 01:11:06 PM UTC 25
Peak memory 217896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3140847629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.3140847629
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_acq.1428274656
Short name T704
Test name
Test status
Simulation time 231452650 ps
CPU time 2.26 seconds
Started Feb 08 01:10:57 PM UTC 25
Finished Feb 08 01:11:01 PM UTC 25
Peak memory 215984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428274656 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_acq.1428274656
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_tx.1479282908
Short name T703
Test name
Test status
Simulation time 147278736 ps
CPU time 1.4 seconds
Started Feb 08 01:10:57 PM UTC 25
Finished Feb 08 01:11:00 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479282908 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_tx.1479282908
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_acq.4251279367
Short name T713
Test name
Test status
Simulation time 459917166 ps
CPU time 3.64 seconds
Started Feb 08 01:11:06 PM UTC 25
Finished Feb 08 01:11:11 PM UTC 25
Peak memory 215876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251279367 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.4251279367
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_tx.3157816761
Short name T711
Test name
Test status
Simulation time 583120032 ps
CPU time 1.58 seconds
Started Feb 08 01:11:07 PM UTC 25
Finished Feb 08 01:11:10 PM UTC 25
Peak memory 213928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157816761 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.3157816761
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_hrst.593999676
Short name T705
Test name
Test status
Simulation time 495673021 ps
CPU time 2.41 seconds
Started Feb 08 01:11:01 PM UTC 25
Finished Feb 08 01:11:04 PM UTC 25
Peak memory 226212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593999676 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_hrst.593999676
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_intr_smoke.3235658394
Short name T697
Test name
Test status
Simulation time 508157601 ps
CPU time 5.24 seconds
Started Feb 08 01:10:49 PM UTC 25
Finished Feb 08 01:10:56 PM UTC 25
Peak memory 232352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235658394 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_smoke.3235658394
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_intr_stress_wr.841780515
Short name T852
Test name
Test status
Simulation time 15775514014 ps
CPU time 215.35 seconds
Started Feb 08 01:10:50 PM UTC 25
Finished Feb 08 01:14:29 PM UTC 25
Peak memory 2317896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84178
0515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.841780515
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull.1464767
Short name T716
Test name
Test status
Simulation time 2675247282 ps
CPU time 2.99 seconds
Started Feb 08 01:11:09 PM UTC 25
Finished Feb 08 01:11:13 PM UTC 25
Peak memory 226472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464767 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_acqfull.1464767
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull_addr.1139918155
Short name T721
Test name
Test status
Simulation time 2293225169 ps
CPU time 4.6 seconds
Started Feb 08 01:11:10 PM UTC 25
Finished Feb 08 01:11:16 PM UTC 25
Peak memory 215988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139918155 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_acqfull_addr.1139918155
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_nack_txstretch.1171511365
Short name T720
Test name
Test status
Simulation time 158861519 ps
CPU time 2.51 seconds
Started Feb 08 01:11:11 PM UTC 25
Finished Feb 08 01:11:15 PM UTC 25
Peak memory 233232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171511365 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_txstretch.1171511365
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_perf.1915886491
Short name T709
Test name
Test status
Simulation time 4449514409 ps
CPU time 7.57 seconds
Started Feb 08 01:10:58 PM UTC 25
Finished Feb 08 01:11:07 PM UTC 25
Peak memory 233192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915886491 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_perf.1915886491
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_smbus_maxlen.2206447162
Short name T714
Test name
Test status
Simulation time 445566291 ps
CPU time 3.07 seconds
Started Feb 08 01:11:08 PM UTC 25
Finished Feb 08 01:11:12 PM UTC 25
Peak memory 215636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206447162 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smbus_maxlen.2206447162
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_smoke.2997349998
Short name T710
Test name
Test status
Simulation time 1051631514 ps
CPU time 18.5 seconds
Started Feb 08 01:10:48 PM UTC 25
Finished Feb 08 01:11:08 PM UTC 25
Peak memory 226128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997349998 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smoke.2997349998
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_stress_all.1723008650
Short name T751
Test name
Test status
Simulation time 46255132383 ps
CPU time 60.26 seconds
Started Feb 08 01:10:59 PM UTC 25
Finished Feb 08 01:12:02 PM UTC 25
Peak memory 317020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723008650 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_all.1723008650
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_stress_rd.1521839876
Short name T701
Test name
Test status
Simulation time 1363716015 ps
CPU time 7.69 seconds
Started Feb 08 01:10:49 PM UTC 25
Finished Feb 08 01:10:58 PM UTC 25
Peak memory 216164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521839876 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_rd.1521839876
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_stress_wr.2020264926
Short name T729
Test name
Test status
Simulation time 30022411035 ps
CPU time 37.37 seconds
Started Feb 08 01:10:48 PM UTC 25
Finished Feb 08 01:11:27 PM UTC 25
Peak memory 652804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020264926 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_wr.2020264926
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_stretch.1040210672
Short name T700
Test name
Test status
Simulation time 1022123184 ps
CPU time 6.65 seconds
Started Feb 08 01:10:49 PM UTC 25
Finished Feb 08 01:10:57 PM UTC 25
Peak memory 229076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040210672 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stretch.1040210672
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_timeout.3220749653
Short name T708
Test name
Test status
Simulation time 4296483637 ps
CPU time 9.3 seconds
Started Feb 08 01:10:56 PM UTC 25
Finished Feb 08 01:11:07 PM UTC 25
Peak memory 226212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220749653 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_timeout.3220749653
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/18.i2c_target_tx_stretch_ctrl.648903338
Short name T717
Test name
Test status
Simulation time 146783334 ps
CPU time 4.18 seconds
Started Feb 08 01:11:08 PM UTC 25
Finished Feb 08 01:11:13 PM UTC 25
Peak memory 215928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648903338 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.648903338
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_alert_test.380033311
Short name T739
Test name
Test status
Simulation time 24608407 ps
CPU time 0.94 seconds
Started Feb 08 01:11:51 PM UTC 25
Finished Feb 08 01:11:53 PM UTC 25
Peak memory 214908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380033311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM
_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.380033311
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_host_error_intr.4133684556
Short name T726
Test name
Test status
Simulation time 254259912 ps
CPU time 3 seconds
Started Feb 08 01:11:21 PM UTC 25
Finished Feb 08 01:11:25 PM UTC 25
Peak memory 232484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133684556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_host_error_intr.4133684556
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_fmt_empty.1391181146
Short name T733
Test name
Test status
Simulation time 2506039824 ps
CPU time 22.2 seconds
Started Feb 08 01:11:15 PM UTC 25
Finished Feb 08 01:11:38 PM UTC 25
Peak memory 294388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391181146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empty.1391181146
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_full.756815590
Short name T835
Test name
Test status
Simulation time 2582586928 ps
CPU time 176.07 seconds
Started Feb 08 01:11:16 PM UTC 25
Finished Feb 08 01:14:15 PM UTC 25
Peak memory 683516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756815590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fu
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 19.i2c_host_fifo_full.756815590
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_overflow.486403122
Short name T778
Test name
Test status
Simulation time 5001364683 ps
CPU time 83.49 seconds
Started Feb 08 01:11:15 PM UTC 25
Finished Feb 08 01:12:40 PM UTC 25
Peak memory 827100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486403122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_host_fifo_overflow.486403122
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_fmt.2647441643
Short name T722
Test name
Test status
Simulation time 269045167 ps
CPU time 1.39 seconds
Started Feb 08 01:11:15 PM UTC 25
Finished Feb 08 01:11:17 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647441643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fmt.2647441643
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_rx.845367901
Short name T725
Test name
Test status
Simulation time 204854256 ps
CPU time 7.57 seconds
Started Feb 08 01:11:16 PM UTC 25
Finished Feb 08 01:11:25 PM UTC 25
Peak memory 253584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845367901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.845367901
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_watermark.1669831136
Short name T792
Test name
Test status
Simulation time 4491189174 ps
CPU time 106.14 seconds
Started Feb 08 01:11:15 PM UTC 25
Finished Feb 08 01:13:03 PM UTC 25
Peak memory 1205716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669831136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 19.i2c_host_fifo_watermark.1669831136
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_host_may_nack.2997489763
Short name T755
Test name
Test status
Simulation time 519678831 ps
CPU time 20.42 seconds
Started Feb 08 01:11:45 PM UTC 25
Finished Feb 08 01:12:07 PM UTC 25
Peak memory 215856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997489763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 19.i2c_host_may_nack.2997489763
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_host_override.1116142059
Short name T144
Test name
Test status
Simulation time 54442210 ps
CPU time 0.93 seconds
Started Feb 08 01:11:13 PM UTC 25
Finished Feb 08 01:11:16 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116142059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 19.i2c_host_override.1116142059
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_host_perf.2359016247
Short name T728
Test name
Test status
Simulation time 607371850 ps
CPU time 7.96 seconds
Started Feb 08 01:11:17 PM UTC 25
Finished Feb 08 01:11:26 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359016247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_host_perf.2359016247
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_host_perf_precise.321632584
Short name T723
Test name
Test status
Simulation time 81030181 ps
CPU time 1.69 seconds
Started Feb 08 01:11:17 PM UTC 25
Finished Feb 08 01:11:20 PM UTC 25
Peak memory 239900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321632584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pr
ecise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_host_perf_precise.321632584
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_host_smoke.2524033746
Short name T742
Test name
Test status
Simulation time 5304211281 ps
CPU time 32.88 seconds
Started Feb 08 01:11:13 PM UTC 25
Finished Feb 08 01:11:48 PM UTC 25
Peak memory 380736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524033746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_host_smoke.2524033746
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_host_stress_all.4131998483
Short name T1069
Test name
Test status
Simulation time 9881796772 ps
CPU time 553.71 seconds
Started Feb 08 01:11:23 PM UTC 25
Finished Feb 08 01:20:43 PM UTC 25
Peak memory 1641980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131998483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_host_stress_all.4131998483
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_host_stretch_timeout.1462869119
Short name T730
Test name
Test status
Simulation time 4675055078 ps
CPU time 12.06 seconds
Started Feb 08 01:11:18 PM UTC 25
Finished Feb 08 01:11:31 PM UTC 25
Peak memory 232480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462869119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.i2c_host_stretch_timeout.1462869119
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_bad_addr.4036282672
Short name T741
Test name
Test status
Simulation time 8952792408 ps
CPU time 6.34 seconds
Started Feb 08 01:11:39 PM UTC 25
Finished Feb 08 01:11:47 PM UTC 25
Peak memory 232924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=4036282672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.4036282672
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_acq.2929061774
Short name T732
Test name
Test status
Simulation time 730046735 ps
CPU time 2.26 seconds
Started Feb 08 01:11:34 PM UTC 25
Finished Feb 08 01:11:37 PM UTC 25
Peak memory 216176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929061774 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_acq.2929061774
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_tx.1571975302
Short name T734
Test name
Test status
Simulation time 209473044 ps
CPU time 1.27 seconds
Started Feb 08 01:11:36 PM UTC 25
Finished Feb 08 01:11:39 PM UTC 25
Peak memory 213920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571975302 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_tx.1571975302
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_acq.1366391154
Short name T687
Test name
Test status
Simulation time 2442272919 ps
CPU time 3.17 seconds
Started Feb 08 01:11:46 PM UTC 25
Finished Feb 08 01:11:50 PM UTC 25
Peak memory 215996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366391154 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.1366391154
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_tx.4122104908
Short name T743
Test name
Test status
Simulation time 305775851 ps
CPU time 1.78 seconds
Started Feb 08 01:11:47 PM UTC 25
Finished Feb 08 01:11:50 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122104908 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.4122104908
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_hrst.231250247
Short name T740
Test name
Test status
Simulation time 347944621 ps
CPU time 3.84 seconds
Started Feb 08 01:11:41 PM UTC 25
Finished Feb 08 01:11:46 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231250247 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_hrst.231250247
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_intr_smoke.1093500083
Short name T731
Test name
Test status
Simulation time 1216749547 ps
CPU time 5.53 seconds
Started Feb 08 01:11:27 PM UTC 25
Finished Feb 08 01:11:33 PM UTC 25
Peak memory 233152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093500083 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_smoke.1093500083
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_intr_stress_wr.3482064191
Short name T752
Test name
Test status
Simulation time 9210404101 ps
CPU time 34.33 seconds
Started Feb 08 01:11:27 PM UTC 25
Finished Feb 08 01:12:03 PM UTC 25
Peak memory 583236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34820
64191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.3482064191
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull.3219458993
Short name T745
Test name
Test status
Simulation time 1877639868 ps
CPU time 3.47 seconds
Started Feb 08 01:11:49 PM UTC 25
Finished Feb 08 01:11:54 PM UTC 25
Peak memory 226088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219458993 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_acqfull.3219458993
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull_addr.2991012110
Short name T747
Test name
Test status
Simulation time 504578974 ps
CPU time 4.65 seconds
Started Feb 08 01:11:51 PM UTC 25
Finished Feb 08 01:11:57 PM UTC 25
Peak memory 215868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991012110 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_acqfull_addr.2991012110
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_perf.1130629180
Short name T738
Test name
Test status
Simulation time 7531069541 ps
CPU time 5.53 seconds
Started Feb 08 01:11:38 PM UTC 25
Finished Feb 08 01:11:45 PM UTC 25
Peak memory 226224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130629180 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_perf.1130629180
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_smbus_maxlen.552204188
Short name T702
Test name
Test status
Simulation time 885197503 ps
CPU time 3.9 seconds
Started Feb 08 01:11:48 PM UTC 25
Finished Feb 08 01:11:53 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552204188 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smbus_maxlen.552204188
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_smoke.2510321720
Short name T683
Test name
Test status
Simulation time 2977819793 ps
CPU time 23.95 seconds
Started Feb 08 01:11:24 PM UTC 25
Finished Feb 08 01:11:50 PM UTC 25
Peak memory 226192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510321720 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smoke.2510321720
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_stress_all.2680026706
Short name T767
Test name
Test status
Simulation time 8687669721 ps
CPU time 48.87 seconds
Started Feb 08 01:11:39 PM UTC 25
Finished Feb 08 01:12:30 PM UTC 25
Peak memory 237020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680026706 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_all.2680026706
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_stress_rd.1111194616
Short name T749
Test name
Test status
Simulation time 10663115261 ps
CPU time 30.91 seconds
Started Feb 08 01:11:26 PM UTC 25
Finished Feb 08 01:11:58 PM UTC 25
Peak memory 249308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111194616 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_rd.1111194616
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_stress_wr.3560420809
Short name T805
Test name
Test status
Simulation time 43120903993 ps
CPU time 114.27 seconds
Started Feb 08 01:11:25 PM UTC 25
Finished Feb 08 01:13:22 PM UTC 25
Peak memory 1601096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560420809 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_wr.3560420809
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_stretch.1737821785
Short name T680
Test name
Test status
Simulation time 1516936980 ps
CPU time 24.57 seconds
Started Feb 08 01:11:27 PM UTC 25
Finished Feb 08 01:11:53 PM UTC 25
Peak memory 306612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737821785 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stretch.1737821785
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_timeout.1504401174
Short name T735
Test name
Test status
Simulation time 2302550178 ps
CPU time 10.97 seconds
Started Feb 08 01:11:28 PM UTC 25
Finished Feb 08 01:11:40 PM UTC 25
Peak memory 226416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504401174 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_timeout.1504401174
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/19.i2c_target_tx_stretch_ctrl.3707467552
Short name T744
Test name
Test status
Simulation time 77253840 ps
CPU time 2.04 seconds
Started Feb 08 01:11:48 PM UTC 25
Finished Feb 08 01:11:51 PM UTC 25
Peak memory 226360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707467552 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.3707467552
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_alert_test.2711213167
Short name T96
Test name
Test status
Simulation time 15418282 ps
CPU time 0.97 seconds
Started Feb 08 12:57:25 PM UTC 25
Finished Feb 08 12:57:27 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711213167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.2711213167
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_host_error_intr.819214790
Short name T20
Test name
Test status
Simulation time 69080518 ps
CPU time 1.77 seconds
Started Feb 08 12:56:57 PM UTC 25
Finished Feb 08 12:57:00 PM UTC 25
Peak memory 225944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819214790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_host_error_intr.819214790
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_fmt_empty.3950087083
Short name T148
Test name
Test status
Simulation time 880052729 ps
CPU time 6.57 seconds
Started Feb 08 12:56:49 PM UTC 25
Finished Feb 08 12:56:57 PM UTC 25
Peak memory 257488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950087083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty.3950087083
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_full.533618369
Short name T127
Test name
Test status
Simulation time 26055995245 ps
CPU time 84 seconds
Started Feb 08 12:56:49 PM UTC 25
Finished Feb 08 12:58:15 PM UTC 25
Peak memory 259600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533618369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fu
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 2.i2c_host_fifo_full.533618369
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_overflow.2645796263
Short name T99
Test name
Test status
Simulation time 1298011598 ps
CPU time 39.57 seconds
Started Feb 08 12:56:48 PM UTC 25
Finished Feb 08 12:57:29 PM UTC 25
Peak memory 544152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645796263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_host_fifo_overflow.2645796263
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_fmt.4028816893
Short name T38
Test name
Test status
Simulation time 176187413 ps
CPU time 1.29 seconds
Started Feb 08 12:56:49 PM UTC 25
Finished Feb 08 12:56:52 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028816893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt.4028816893
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_watermark.981082828
Short name T82
Test name
Test status
Simulation time 6382369326 ps
CPU time 74.69 seconds
Started Feb 08 12:56:48 PM UTC 25
Finished Feb 08 12:58:05 PM UTC 25
Peak memory 982652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981082828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_wa
termark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_host_fifo_watermark.981082828
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_host_may_nack.718528729
Short name T253
Test name
Test status
Simulation time 533321180 ps
CPU time 21.96 seconds
Started Feb 08 12:57:17 PM UTC 25
Finished Feb 08 12:57:41 PM UTC 25
Peak memory 215920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718528729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nac
k_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 2.i2c_host_may_nack.718528729
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_host_perf.2174542467
Short name T150
Test name
Test status
Simulation time 1374168084 ps
CPU time 8.74 seconds
Started Feb 08 12:56:51 PM UTC 25
Finished Feb 08 12:57:01 PM UTC 25
Peak memory 226088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174542467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_host_perf.2174542467
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_host_perf_precise.3557172153
Short name T16
Test name
Test status
Simulation time 24907999825 ps
CPU time 29.71 seconds
Started Feb 08 12:56:52 PM UTC 25
Finished Feb 08 12:57:24 PM UTC 25
Peak memory 523736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557172153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_host_perf_precise.3557172153
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_host_smoke.1608130656
Short name T36
Test name
Test status
Simulation time 7220369503 ps
CPU time 92.1 seconds
Started Feb 08 12:56:46 PM UTC 25
Finished Feb 08 12:58:20 PM UTC 25
Peak memory 374344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608130656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_host_smoke.1608130656
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_host_stretch_timeout.2789925702
Short name T304
Test name
Test status
Simulation time 2573049154 ps
CPU time 34.57 seconds
Started Feb 08 12:56:53 PM UTC 25
Finished Feb 08 12:57:30 PM UTC 25
Peak memory 226508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789925702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.i2c_host_stretch_timeout.2789925702
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_sec_cm.738149596
Short name T185
Test name
Test status
Simulation time 107132278 ps
CPU time 1.4 seconds
Started Feb 08 12:57:24 PM UTC 25
Finished Feb 08 12:57:27 PM UTC 25
Peak memory 246268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738149596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.738149596
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_bad_addr.3306748625
Short name T67
Test name
Test status
Simulation time 11737956037 ps
CPU time 11.95 seconds
Started Feb 08 12:57:13 PM UTC 25
Finished Feb 08 12:57:27 PM UTC 25
Peak memory 230308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3306748625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.3306748625
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_acq.3275246748
Short name T173
Test name
Test status
Simulation time 193017010 ps
CPU time 1.31 seconds
Started Feb 08 12:57:10 PM UTC 25
Finished Feb 08 12:57:12 PM UTC 25
Peak memory 214524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275246748 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_acq.3275246748
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_tx.1352961929
Short name T174
Test name
Test status
Simulation time 258265003 ps
CPU time 2.05 seconds
Started Feb 08 12:57:11 PM UTC 25
Finished Feb 08 12:57:14 PM UTC 25
Peak memory 222320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352961929 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_tx.1352961929
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_acq.2427392631
Short name T273
Test name
Test status
Simulation time 1604692423 ps
CPU time 2.55 seconds
Started Feb 08 12:57:17 PM UTC 25
Finished Feb 08 12:57:21 PM UTC 25
Peak memory 215652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427392631 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.2427392631
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_tx.4293614653
Short name T303
Test name
Test status
Simulation time 754024831 ps
CPU time 1.72 seconds
Started Feb 08 12:57:20 PM UTC 25
Finished Feb 08 12:57:22 PM UTC 25
Peak memory 214532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293614653 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.4293614653
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_intr_smoke.1437814890
Short name T175
Test name
Test status
Simulation time 4665568173 ps
CPU time 8.15 seconds
Started Feb 08 12:57:07 PM UTC 25
Finished Feb 08 12:57:16 PM UTC 25
Peak memory 247308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437814890 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_smoke.1437814890
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_intr_stress_wr.2107391920
Short name T58
Test name
Test status
Simulation time 16639427681 ps
CPU time 32.43 seconds
Started Feb 08 12:57:07 PM UTC 25
Finished Feb 08 12:57:41 PM UTC 25
Peak memory 687688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21073
91920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.2107391920
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull.2357861945
Short name T157
Test name
Test status
Simulation time 4622055721 ps
CPU time 5.54 seconds
Started Feb 08 12:57:23 PM UTC 25
Finished Feb 08 12:57:30 PM UTC 25
Peak memory 226008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357861945 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_acqfull.2357861945
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_nack_txstretch.2715947392
Short name T61
Test name
Test status
Simulation time 249249469 ps
CPU time 1.82 seconds
Started Feb 08 12:57:24 PM UTC 25
Finished Feb 08 12:57:27 PM UTC 25
Peak memory 231968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715947392 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_txstretch.2715947392
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_perf.471697395
Short name T299
Test name
Test status
Simulation time 2664294342 ps
CPU time 4.23 seconds
Started Feb 08 12:57:11 PM UTC 25
Finished Feb 08 12:57:17 PM UTC 25
Peak memory 226156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471697395 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_perf.471697395
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_smbus_maxlen.1002830236
Short name T302
Test name
Test status
Simulation time 2780493937 ps
CPU time 3.45 seconds
Started Feb 08 12:57:22 PM UTC 25
Finished Feb 08 12:57:26 PM UTC 25
Peak memory 215960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002830236 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smbus_maxlen.1002830236
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_smoke.622524795
Short name T8
Test name
Test status
Simulation time 577918317 ps
CPU time 9.27 seconds
Started Feb 08 12:57:00 PM UTC 25
Finished Feb 08 12:57:10 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622524795 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smoke.622524795
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_stress_rd.943238959
Short name T72
Test name
Test status
Simulation time 330070714 ps
CPU time 7.74 seconds
Started Feb 08 12:57:03 PM UTC 25
Finished Feb 08 12:57:12 PM UTC 25
Peak memory 216172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943238959 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_rd.943238959
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_stress_wr.2228712984
Short name T1717
Test name
Test status
Simulation time 67216082207 ps
CPU time 2434.61 seconds
Started Feb 08 12:57:02 PM UTC 25
Finished Feb 08 01:37:56 PM UTC 25
Peak memory 11843140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228712984 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_wr.2228712984
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_stretch.2235439327
Short name T45
Test name
Test status
Simulation time 6487846469 ps
CPU time 4.3 seconds
Started Feb 08 12:57:05 PM UTC 25
Finished Feb 08 12:57:10 PM UTC 25
Peak memory 247552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235439327 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stretch.2235439327
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_timeout.1021277039
Short name T300
Test name
Test status
Simulation time 2920375086 ps
CPU time 8.45 seconds
Started Feb 08 12:57:09 PM UTC 25
Finished Feb 08 12:57:19 PM UTC 25
Peak memory 232952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021277039 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_timeout.1021277039
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_tx_stretch_ctrl.2728497412
Short name T292
Test name
Test status
Simulation time 84306636 ps
CPU time 2.28 seconds
Started Feb 08 12:57:21 PM UTC 25
Finished Feb 08 12:57:24 PM UTC 25
Peak memory 226104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728497412 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.2728497412
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_alert_test.3267519715
Short name T781
Test name
Test status
Simulation time 38718810 ps
CPU time 0.84 seconds
Started Feb 08 01:12:41 PM UTC 25
Finished Feb 08 01:12:43 PM UTC 25
Peak memory 214996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267519715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.3267519715
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_host_error_intr.1078480755
Short name T754
Test name
Test status
Simulation time 319681404 ps
CPU time 2.18 seconds
Started Feb 08 01:12:03 PM UTC 25
Finished Feb 08 01:12:06 PM UTC 25
Peak memory 228300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078480755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_host_error_intr.1078480755
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_fmt_empty.2123318109
Short name T756
Test name
Test status
Simulation time 448633284 ps
CPU time 15.33 seconds
Started Feb 08 01:11:55 PM UTC 25
Finished Feb 08 01:12:12 PM UTC 25
Peak memory 282056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123318109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empty.2123318109
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_full.1923139735
Short name T824
Test name
Test status
Simulation time 3595119918 ps
CPU time 120.09 seconds
Started Feb 08 01:11:57 PM UTC 25
Finished Feb 08 01:14:00 PM UTC 25
Peak memory 331460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923139735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_host_fifo_full.1923139735
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_overflow.955716175
Short name T801
Test name
Test status
Simulation time 43200493463 ps
CPU time 83.27 seconds
Started Feb 08 01:11:54 PM UTC 25
Finished Feb 08 01:13:20 PM UTC 25
Peak memory 769556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955716175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_host_fifo_overflow.955716175
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_fmt.3789518348
Short name T748
Test name
Test status
Simulation time 240581152 ps
CPU time 1.88 seconds
Started Feb 08 01:11:54 PM UTC 25
Finished Feb 08 01:11:57 PM UTC 25
Peak memory 214472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789518348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fmt.3789518348
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_rx.2987898904
Short name T753
Test name
Test status
Simulation time 881567558 ps
CPU time 7.25 seconds
Started Feb 08 01:11:56 PM UTC 25
Finished Feb 08 01:12:05 PM UTC 25
Peak memory 215960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987898904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.2987898904
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_watermark.787824548
Short name T838
Test name
Test status
Simulation time 19775514910 ps
CPU time 140.34 seconds
Started Feb 08 01:11:54 PM UTC 25
Finished Feb 08 01:14:17 PM UTC 25
Peak memory 1324716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787824548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_wa
termark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_host_fifo_watermark.787824548
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_host_may_nack.1754371233
Short name T793
Test name
Test status
Simulation time 4055608010 ps
CPU time 28.83 seconds
Started Feb 08 01:12:33 PM UTC 25
Finished Feb 08 01:13:03 PM UTC 25
Peak memory 216176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754371233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 20.i2c_host_may_nack.1754371233
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_host_override.1254828674
Short name T746
Test name
Test status
Simulation time 34756870 ps
CPU time 0.86 seconds
Started Feb 08 01:11:53 PM UTC 25
Finished Feb 08 01:11:55 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254828674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 20.i2c_host_override.1254828674
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_host_perf.3504824351
Short name T764
Test name
Test status
Simulation time 2798452737 ps
CPU time 25.38 seconds
Started Feb 08 01:11:59 PM UTC 25
Finished Feb 08 01:12:25 PM UTC 25
Peak memory 216040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504824351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_host_perf.3504824351
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_host_perf_precise.2033541143
Short name T750
Test name
Test status
Simulation time 61532294 ps
CPU time 1.6 seconds
Started Feb 08 01:11:59 PM UTC 25
Finished Feb 08 01:12:02 PM UTC 25
Peak memory 213860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033541143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_host_perf_precise.2033541143
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_host_smoke.1250457996
Short name T762
Test name
Test status
Simulation time 6831518557 ps
CPU time 101.4 seconds
Started Feb 08 01:11:52 PM UTC 25
Finished Feb 08 01:13:36 PM UTC 25
Peak memory 445964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250457996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_host_smoke.1250457996
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_host_stress_all.3120670646
Short name T274
Test name
Test status
Simulation time 7970921584 ps
CPU time 486.95 seconds
Started Feb 08 01:12:04 PM UTC 25
Finished Feb 08 01:20:16 PM UTC 25
Peak memory 898668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120670646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_host_stress_all.3120670646
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_host_stretch_timeout.1656776922
Short name T759
Test name
Test status
Simulation time 1367600480 ps
CPU time 15.64 seconds
Started Feb 08 01:12:03 PM UTC 25
Finished Feb 08 01:12:20 PM UTC 25
Peak memory 232840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656776922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.i2c_host_stretch_timeout.1656776922
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_bad_addr.1554818605
Short name T774
Test name
Test status
Simulation time 3831561182 ps
CPU time 8.28 seconds
Started Feb 08 01:12:28 PM UTC 25
Finished Feb 08 01:12:37 PM UTC 25
Peak memory 220068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1554818605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.1554818605
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_acq.1443766612
Short name T763
Test name
Test status
Simulation time 276912927 ps
CPU time 1.85 seconds
Started Feb 08 01:12:21 PM UTC 25
Finished Feb 08 01:12:25 PM UTC 25
Peak memory 216208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443766612 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_acq.1443766612
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_tx.3200491549
Short name T766
Test name
Test status
Simulation time 263502921 ps
CPU time 1.69 seconds
Started Feb 08 01:12:26 PM UTC 25
Finished Feb 08 01:12:28 PM UTC 25
Peak memory 214404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200491549 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_tx.3200491549
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_acq.828801197
Short name T776
Test name
Test status
Simulation time 1988889622 ps
CPU time 3.88 seconds
Started Feb 08 01:12:33 PM UTC 25
Finished Feb 08 01:12:38 PM UTC 25
Peak memory 215916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828801197 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.828801197
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_tx.414597624
Short name T773
Test name
Test status
Simulation time 162274598 ps
CPU time 1.27 seconds
Started Feb 08 01:12:34 PM UTC 25
Finished Feb 08 01:12:37 PM UTC 25
Peak memory 213932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414597624 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.414597624
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_hrst.1250525682
Short name T772
Test name
Test status
Simulation time 822702220 ps
CPU time 1.82 seconds
Started Feb 08 01:12:30 PM UTC 25
Finished Feb 08 01:12:33 PM UTC 25
Peak memory 226092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250525682 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_hrst.1250525682
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_intr_smoke.689944419
Short name T765
Test name
Test status
Simulation time 880356325 ps
CPU time 8.61 seconds
Started Feb 08 01:12:17 PM UTC 25
Finished Feb 08 01:12:27 PM UTC 25
Peak memory 230444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689944419 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_smoke.689944419
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_intr_stress_wr.2253630668
Short name T770
Test name
Test status
Simulation time 8499166551 ps
CPU time 11.47 seconds
Started Feb 08 01:12:19 PM UTC 25
Finished Feb 08 01:12:32 PM UTC 25
Peak memory 263880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22536
30668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.2253630668
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull.2927893735
Short name T783
Test name
Test status
Simulation time 1379246061 ps
CPU time 4.53 seconds
Started Feb 08 01:12:38 PM UTC 25
Finished Feb 08 01:12:44 PM UTC 25
Peak memory 225516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927893735 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_acqfull.2927893735
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull_addr.3344162200
Short name T784
Test name
Test status
Simulation time 2230344653 ps
CPU time 4.84 seconds
Started Feb 08 01:12:38 PM UTC 25
Finished Feb 08 01:12:44 PM UTC 25
Peak memory 215984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344162200 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_acqfull_addr.3344162200
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_nack_txstretch.2356863144
Short name T782
Test name
Test status
Simulation time 131772271 ps
CPU time 2.28 seconds
Started Feb 08 01:12:39 PM UTC 25
Finished Feb 08 01:12:43 PM UTC 25
Peak memory 232952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356863144 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_txstretch.2356863144
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_perf.2920797042
Short name T769
Test name
Test status
Simulation time 552962141 ps
CPU time 4.93 seconds
Started Feb 08 01:12:26 PM UTC 25
Finished Feb 08 01:12:32 PM UTC 25
Peak memory 226020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920797042 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_perf.2920797042
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_smbus_maxlen.2701183561
Short name T780
Test name
Test status
Simulation time 9729164190 ps
CPU time 4.18 seconds
Started Feb 08 01:12:37 PM UTC 25
Finished Feb 08 01:12:43 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701183561 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smbus_maxlen.2701183561
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_smoke.1686658452
Short name T787
Test name
Test status
Simulation time 6520952640 ps
CPU time 44.47 seconds
Started Feb 08 01:12:06 PM UTC 25
Finished Feb 08 01:12:52 PM UTC 25
Peak memory 226280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686658452 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smoke.1686658452
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_stress_all.3075957717
Short name T808
Test name
Test status
Simulation time 15163923177 ps
CPU time 56.26 seconds
Started Feb 08 01:12:27 PM UTC 25
Finished Feb 08 01:13:25 PM UTC 25
Peak memory 249372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075957717 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_all.3075957717
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_stress_rd.3676203381
Short name T779
Test name
Test status
Simulation time 1925709324 ps
CPU time 32.89 seconds
Started Feb 08 01:12:08 PM UTC 25
Finished Feb 08 01:12:42 PM UTC 25
Peak memory 249256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676203381 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_rd.3676203381
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_stress_wr.2472260515
Short name T794
Test name
Test status
Simulation time 22297980157 ps
CPU time 57.74 seconds
Started Feb 08 01:12:07 PM UTC 25
Finished Feb 08 01:13:06 PM UTC 25
Peak memory 740932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472260515 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_wr.2472260515
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_stretch.1051298917
Short name T757
Test name
Test status
Simulation time 488226789 ps
CPU time 2.12 seconds
Started Feb 08 01:12:13 PM UTC 25
Finished Feb 08 01:12:16 PM UTC 25
Peak memory 226160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051298917 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stretch.1051298917
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_timeout.2958731872
Short name T771
Test name
Test status
Simulation time 1482498518 ps
CPU time 11.05 seconds
Started Feb 08 01:12:20 PM UTC 25
Finished Feb 08 01:12:33 PM UTC 25
Peak memory 232872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958731872 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_timeout.2958731872
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/20.i2c_target_tx_stretch_ctrl.1001573380
Short name T775
Test name
Test status
Simulation time 95015206 ps
CPU time 2.21 seconds
Started Feb 08 01:12:34 PM UTC 25
Finished Feb 08 01:12:38 PM UTC 25
Peak memory 216184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001573380 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.1001573380
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_alert_test.3528107731
Short name T816
Test name
Test status
Simulation time 28045280 ps
CPU time 0.95 seconds
Started Feb 08 01:13:29 PM UTC 25
Finished Feb 08 01:13:31 PM UTC 25
Peak memory 214936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528107731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3528107731
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_error_intr.1310914692
Short name T795
Test name
Test status
Simulation time 672596200 ps
CPU time 6.89 seconds
Started Feb 08 01:12:59 PM UTC 25
Finished Feb 08 01:13:07 PM UTC 25
Peak memory 243320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310914692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_host_error_intr.1310914692
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_fmt_empty.4242346040
Short name T791
Test name
Test status
Simulation time 244508870 ps
CPU time 15.63 seconds
Started Feb 08 01:12:45 PM UTC 25
Finished Feb 08 01:13:02 PM UTC 25
Peak memory 263604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242346040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empty.4242346040
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_full.3278199070
Short name T895
Test name
Test status
Simulation time 5076365303 ps
CPU time 181.7 seconds
Started Feb 08 01:12:47 PM UTC 25
Finished Feb 08 01:15:52 PM UTC 25
Peak memory 636432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278199070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 21.i2c_host_fifo_full.3278199070
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_overflow.1757530416
Short name T807
Test name
Test status
Simulation time 1934691908 ps
CPU time 37.94 seconds
Started Feb 08 01:12:44 PM UTC 25
Finished Feb 08 01:13:23 PM UTC 25
Peak memory 546308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757530416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_host_fifo_overflow.1757530416
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_fmt.882388935
Short name T786
Test name
Test status
Simulation time 414749188 ps
CPU time 1.38 seconds
Started Feb 08 01:12:44 PM UTC 25
Finished Feb 08 01:12:47 PM UTC 25
Peak memory 214516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882388935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fmt.882388935
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_rx.3145834358
Short name T788
Test name
Test status
Simulation time 860030135 ps
CPU time 6.08 seconds
Started Feb 08 01:12:45 PM UTC 25
Finished Feb 08 01:12:52 PM UTC 25
Peak memory 270016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145834358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.3145834358
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_watermark.656592475
Short name T114
Test name
Test status
Simulation time 9603444167 ps
CPU time 111.61 seconds
Started Feb 08 01:12:44 PM UTC 25
Finished Feb 08 01:14:38 PM UTC 25
Peak memory 1414712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656592475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_wa
termark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_host_fifo_watermark.656592475
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_may_nack.4025282512
Short name T810
Test name
Test status
Simulation time 3405691739 ps
CPU time 3.67 seconds
Started Feb 08 01:13:22 PM UTC 25
Finished Feb 08 01:13:27 PM UTC 25
Peak memory 215892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025282512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 21.i2c_host_may_nack.4025282512
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_override.2756756875
Short name T785
Test name
Test status
Simulation time 28718196 ps
CPU time 0.95 seconds
Started Feb 08 01:12:44 PM UTC 25
Finished Feb 08 01:12:46 PM UTC 25
Peak memory 213920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756756875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 21.i2c_host_override.2756756875
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_perf.1486998123
Short name T981
Test name
Test status
Simulation time 12652745869 ps
CPU time 350.56 seconds
Started Feb 08 01:12:47 PM UTC 25
Finished Feb 08 01:18:42 PM UTC 25
Peak memory 1562128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486998123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_host_perf.1486998123
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_perf_precise.3022791318
Short name T789
Test name
Test status
Simulation time 561410323 ps
CPU time 4.07 seconds
Started Feb 08 01:12:53 PM UTC 25
Finished Feb 08 01:12:59 PM UTC 25
Peak memory 239052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022791318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_host_perf_precise.3022791318
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_smoke.278227573
Short name T800
Test name
Test status
Simulation time 7226319329 ps
CPU time 35.58 seconds
Started Feb 08 01:12:41 PM UTC 25
Finished Feb 08 01:13:18 PM UTC 25
Peak memory 296540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278227573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_host_smoke.278227573
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_stress_all.4143088028
Short name T889
Test name
Test status
Simulation time 6454938806 ps
CPU time 155.85 seconds
Started Feb 08 01:13:01 PM UTC 25
Finished Feb 08 01:15:40 PM UTC 25
Peak memory 675532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143088028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_host_stress_all.4143088028
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_host_stretch_timeout.846873714
Short name T817
Test name
Test status
Simulation time 2083749221 ps
CPU time 42.15 seconds
Started Feb 08 01:12:53 PM UTC 25
Finished Feb 08 01:13:37 PM UTC 25
Peak memory 226332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846873714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch
_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 21.i2c_host_stretch_timeout.846873714
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_bad_addr.3970980130
Short name T813
Test name
Test status
Simulation time 1341100109 ps
CPU time 6.74 seconds
Started Feb 08 01:13:21 PM UTC 25
Finished Feb 08 01:13:29 PM UTC 25
Peak memory 230248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3970980130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.3970980130
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_acq.1310966198
Short name T803
Test name
Test status
Simulation time 336710178 ps
CPU time 1.88 seconds
Started Feb 08 01:13:17 PM UTC 25
Finished Feb 08 01:13:20 PM UTC 25
Peak memory 216180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310966198 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_acq.1310966198
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_tx.1539017852
Short name T802
Test name
Test status
Simulation time 175884046 ps
CPU time 1.75 seconds
Started Feb 08 01:13:17 PM UTC 25
Finished Feb 08 01:13:20 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539017852 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_tx.1539017852
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_acq.1698329334
Short name T812
Test name
Test status
Simulation time 1317960166 ps
CPU time 3.69 seconds
Started Feb 08 01:13:24 PM UTC 25
Finished Feb 08 01:13:28 PM UTC 25
Peak memory 215852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698329334 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.1698329334
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_tx.3075439491
Short name T811
Test name
Test status
Simulation time 497622239 ps
CPU time 1.62 seconds
Started Feb 08 01:13:25 PM UTC 25
Finished Feb 08 01:13:27 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075439491 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.3075439491
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_intr_smoke.1155779559
Short name T799
Test name
Test status
Simulation time 20078604731 ps
CPU time 7.59 seconds
Started Feb 08 01:13:08 PM UTC 25
Finished Feb 08 01:13:17 PM UTC 25
Peak memory 233104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155779559 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_smoke.1155779559
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_intr_stress_wr.2348624969
Short name T887
Test name
Test status
Simulation time 8668105107 ps
CPU time 147.01 seconds
Started Feb 08 01:13:09 PM UTC 25
Finished Feb 08 01:15:38 PM UTC 25
Peak memory 2322244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23486
24969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.2348624969
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull_addr.2132695209
Short name T820
Test name
Test status
Simulation time 639949627 ps
CPU time 4.94 seconds
Started Feb 08 01:13:28 PM UTC 25
Finished Feb 08 01:13:34 PM UTC 25
Peak memory 215920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132695209 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_acqfull_addr.2132695209
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_perf.1637127081
Short name T809
Test name
Test status
Simulation time 2552265840 ps
CPU time 5.89 seconds
Started Feb 08 01:13:19 PM UTC 25
Finished Feb 08 01:13:26 PM UTC 25
Peak memory 226340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637127081 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_perf.1637127081
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_smbus_maxlen.111909188
Short name T814
Test name
Test status
Simulation time 415560596 ps
CPU time 2.95 seconds
Started Feb 08 01:13:26 PM UTC 25
Finished Feb 08 01:13:30 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111909188 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smbus_maxlen.111909188
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_smoke.2034850188
Short name T667
Test name
Test status
Simulation time 2517137582 ps
CPU time 39.73 seconds
Started Feb 08 01:13:02 PM UTC 25
Finished Feb 08 01:13:44 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034850188 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smoke.2034850188
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_stress_all.3500914839
Short name T154
Test name
Test status
Simulation time 105701357237 ps
CPU time 89.58 seconds
Started Feb 08 01:13:20 PM UTC 25
Finished Feb 08 01:14:52 PM UTC 25
Peak memory 687708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500914839 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_all.3500914839
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_stress_rd.2193735223
Short name T796
Test name
Test status
Simulation time 752227630 ps
CPU time 6.49 seconds
Started Feb 08 01:13:04 PM UTC 25
Finished Feb 08 01:13:11 PM UTC 25
Peak memory 216216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193735223 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_rd.2193735223
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_stress_wr.2596707292
Short name T958
Test name
Test status
Simulation time 33190639974 ps
CPU time 305.78 seconds
Started Feb 08 01:13:03 PM UTC 25
Finished Feb 08 01:18:12 PM UTC 25
Peak memory 3372796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596707292 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_wr.2596707292
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_stretch.1905059809
Short name T827
Test name
Test status
Simulation time 2368515307 ps
CPU time 58.57 seconds
Started Feb 08 01:13:05 PM UTC 25
Finished Feb 08 01:14:05 PM UTC 25
Peak memory 738760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905059809 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stretch.1905059809
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_timeout.1376718401
Short name T806
Test name
Test status
Simulation time 2725613787 ps
CPU time 9.18 seconds
Started Feb 08 01:13:12 PM UTC 25
Finished Feb 08 01:13:22 PM UTC 25
Peak memory 226284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376718401 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_timeout.1376718401
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/21.i2c_target_tx_stretch_ctrl.2764961028
Short name T815
Test name
Test status
Simulation time 121446281 ps
CPU time 3.58 seconds
Started Feb 08 01:13:26 PM UTC 25
Finished Feb 08 01:13:31 PM UTC 25
Peak memory 215860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764961028 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.2764961028
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_alert_test.2809306580
Short name T843
Test name
Test status
Simulation time 42056663 ps
CPU time 0.87 seconds
Started Feb 08 01:14:18 PM UTC 25
Finished Feb 08 01:14:21 PM UTC 25
Peak memory 214996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809306580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.2809306580
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_error_intr.330549373
Short name T798
Test name
Test status
Simulation time 377241455 ps
CPU time 2.51 seconds
Started Feb 08 01:13:37 PM UTC 25
Finished Feb 08 01:13:40 PM UTC 25
Peak memory 226224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330549373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_host_error_intr.330549373
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_fmt_empty.3597705652
Short name T822
Test name
Test status
Simulation time 978400171 ps
CPU time 13.68 seconds
Started Feb 08 01:13:32 PM UTC 25
Finished Feb 08 01:13:47 PM UTC 25
Peak memory 304580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597705652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empty.3597705652
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_full.4200879946
Short name T860
Test name
Test status
Simulation time 47108203100 ps
CPU time 75.42 seconds
Started Feb 08 01:13:34 PM UTC 25
Finished Feb 08 01:14:52 PM UTC 25
Peak memory 587216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200879946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_host_fifo_full.4200879946
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_overflow.1353238255
Short name T911
Test name
Test status
Simulation time 24400374432 ps
CPU time 173.44 seconds
Started Feb 08 01:13:32 PM UTC 25
Finished Feb 08 01:16:29 PM UTC 25
Peak memory 804620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353238255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_host_fifo_overflow.1353238255
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_fmt.4064568334
Short name T821
Test name
Test status
Simulation time 307652031 ps
CPU time 1.27 seconds
Started Feb 08 01:13:32 PM UTC 25
Finished Feb 08 01:13:35 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064568334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fmt.4064568334
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_rx.3860168625
Short name T768
Test name
Test status
Simulation time 273690079 ps
CPU time 3.42 seconds
Started Feb 08 01:13:34 PM UTC 25
Finished Feb 08 01:13:39 PM UTC 25
Peak memory 215840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860168625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.3860168625
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_watermark.4190888300
Short name T908
Test name
Test status
Simulation time 4897337895 ps
CPU time 165.81 seconds
Started Feb 08 01:13:31 PM UTC 25
Finished Feb 08 01:16:20 PM UTC 25
Peak memory 1494612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190888300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 22.i2c_host_fifo_watermark.4190888300
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_override.1866677407
Short name T818
Test name
Test status
Simulation time 19444178 ps
CPU time 0.89 seconds
Started Feb 08 01:13:31 PM UTC 25
Finished Feb 08 01:13:33 PM UTC 25
Peak memory 213920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866677407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 22.i2c_host_override.1866677407
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_perf.2527637821
Short name T777
Test name
Test status
Simulation time 413332060 ps
CPU time 2.81 seconds
Started Feb 08 01:13:36 PM UTC 25
Finished Feb 08 01:13:40 PM UTC 25
Peak memory 243100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527637821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_host_perf.2527637821
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_perf_precise.3370358128
Short name T825
Test name
Test status
Simulation time 6141134253 ps
CPU time 23.35 seconds
Started Feb 08 01:13:36 PM UTC 25
Finished Feb 08 01:14:00 PM UTC 25
Peak memory 216168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370358128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_host_perf_precise.3370358128
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_smoke.3891030862
Short name T857
Test name
Test status
Simulation time 5258919280 ps
CPU time 75.11 seconds
Started Feb 08 01:13:30 PM UTC 25
Finished Feb 08 01:14:47 PM UTC 25
Peak memory 306692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891030862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_host_smoke.3891030862
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_host_stretch_timeout.742024880
Short name T826
Test name
Test status
Simulation time 4086031794 ps
CPU time 24.24 seconds
Started Feb 08 01:13:37 PM UTC 25
Finished Feb 08 01:14:02 PM UTC 25
Peak memory 243196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742024880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch
_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 22.i2c_host_stretch_timeout.742024880
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_bad_addr.995957179
Short name T840
Test name
Test status
Simulation time 3909331407 ps
CPU time 7.96 seconds
Started Feb 08 01:14:09 PM UTC 25
Finished Feb 08 01:14:18 PM UTC 25
Peak memory 226212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=995957179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.995957179
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_acq.1746801288
Short name T828
Test name
Test status
Simulation time 484906097 ps
CPU time 1.86 seconds
Started Feb 08 01:14:03 PM UTC 25
Finished Feb 08 01:14:07 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746801288 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_acq.1746801288
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_tx.466330713
Short name T829
Test name
Test status
Simulation time 302230144 ps
CPU time 2.25 seconds
Started Feb 08 01:14:04 PM UTC 25
Finished Feb 08 01:14:08 PM UTC 25
Peak memory 215640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466330713 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_tx.466330713
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_acq.41608561
Short name T841
Test name
Test status
Simulation time 280420603 ps
CPU time 3.04 seconds
Started Feb 08 01:14:14 PM UTC 25
Finished Feb 08 01:14:18 PM UTC 25
Peak memory 215712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41608561 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.41608561
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_tx.2867923231
Short name T839
Test name
Test status
Simulation time 457446870 ps
CPU time 1.46 seconds
Started Feb 08 01:14:15 PM UTC 25
Finished Feb 08 01:14:18 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867923231 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.2867923231
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_intr_smoke.1537640217
Short name T823
Test name
Test status
Simulation time 2219385612 ps
CPU time 8.17 seconds
Started Feb 08 01:13:48 PM UTC 25
Finished Feb 08 01:13:58 PM UTC 25
Peak memory 226220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537640217 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_smoke.1537640217
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_intr_stress_wr.848835026
Short name T845
Test name
Test status
Simulation time 10021636161 ps
CPU time 22.21 seconds
Started Feb 08 01:13:58 PM UTC 25
Finished Feb 08 01:14:22 PM UTC 25
Peak memory 431684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84883
5026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.848835026
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull.2740153752
Short name T844
Test name
Test status
Simulation time 549221373 ps
CPU time 3.87 seconds
Started Feb 08 01:14:16 PM UTC 25
Finished Feb 08 01:14:21 PM UTC 25
Peak memory 226084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740153752 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_acqfull.2740153752
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull_addr.120482738
Short name T847
Test name
Test status
Simulation time 7187417564 ps
CPU time 3.93 seconds
Started Feb 08 01:14:17 PM UTC 25
Finished Feb 08 01:14:23 PM UTC 25
Peak memory 215984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120482738 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_acqfull_addr.120482738
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_nack_txstretch.631720741
Short name T846
Test name
Test status
Simulation time 285126877 ps
CPU time 2.25 seconds
Started Feb 08 01:14:18 PM UTC 25
Finished Feb 08 01:14:22 PM UTC 25
Peak memory 232900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631720741 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_txstretch.631720741
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_perf.6708939
Short name T833
Test name
Test status
Simulation time 582756719 ps
CPU time 6.84 seconds
Started Feb 08 01:14:06 PM UTC 25
Finished Feb 08 01:14:14 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6708939 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_perf.6708939
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_smbus_maxlen.537765751
Short name T842
Test name
Test status
Simulation time 965151793 ps
CPU time 2.69 seconds
Started Feb 08 01:14:16 PM UTC 25
Finished Feb 08 01:14:20 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537765751 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smbus_maxlen.537765751
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_smoke.4029279105
Short name T832
Test name
Test status
Simulation time 3482874389 ps
CPU time 32 seconds
Started Feb 08 01:13:40 PM UTC 25
Finished Feb 08 01:14:13 PM UTC 25
Peak memory 226264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029279105 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smoke.4029279105
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_stress_all.3284770136
Short name T1113
Test name
Test status
Simulation time 67458839641 ps
CPU time 437.06 seconds
Started Feb 08 01:14:08 PM UTC 25
Finished Feb 08 01:21:30 PM UTC 25
Peak memory 2113228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284770136 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_all.3284770136
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_stress_rd.3727797329
Short name T830
Test name
Test status
Simulation time 3554886226 ps
CPU time 29.09 seconds
Started Feb 08 01:13:41 PM UTC 25
Finished Feb 08 01:14:12 PM UTC 25
Peak memory 243328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727797329 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_rd.3727797329
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_stress_wr.2422689188
Short name T831
Test name
Test status
Simulation time 8145682079 ps
CPU time 29.38 seconds
Started Feb 08 01:13:41 PM UTC 25
Finished Feb 08 01:14:12 PM UTC 25
Peak memory 215960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422689188 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_wr.2422689188
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_timeout.2759097075
Short name T834
Test name
Test status
Simulation time 5480119600 ps
CPU time 11.31 seconds
Started Feb 08 01:14:01 PM UTC 25
Finished Feb 08 01:14:14 PM UTC 25
Peak memory 243220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759097075 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_timeout.2759097075
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/22.i2c_target_tx_stretch_ctrl.1350271154
Short name T849
Test name
Test status
Simulation time 265114493 ps
CPU time 7.11 seconds
Started Feb 08 01:14:15 PM UTC 25
Finished Feb 08 01:14:24 PM UTC 25
Peak memory 215864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350271154 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.1350271154
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_alert_test.4089610560
Short name T872
Test name
Test status
Simulation time 17338826 ps
CPU time 0.84 seconds
Started Feb 08 01:15:01 PM UTC 25
Finished Feb 08 01:15:03 PM UTC 25
Peak memory 214996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089610560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.4089610560
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_error_intr.2846863791
Short name T854
Test name
Test status
Simulation time 248204066 ps
CPU time 6.38 seconds
Started Feb 08 01:14:25 PM UTC 25
Finished Feb 08 01:14:33 PM UTC 25
Peak memory 259732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846863791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_host_error_intr.2846863791
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_fmt_empty.675857337
Short name T855
Test name
Test status
Simulation time 2187838102 ps
CPU time 16.49 seconds
Started Feb 08 01:14:23 PM UTC 25
Finished Feb 08 01:14:41 PM UTC 25
Peak memory 335292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675857337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empty.675857337
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_full.4024620325
Short name T928
Test name
Test status
Simulation time 12135418293 ps
CPU time 188.24 seconds
Started Feb 08 01:14:23 PM UTC 25
Finished Feb 08 01:17:34 PM UTC 25
Peak memory 765452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024620325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_host_fifo_full.4024620325
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_overflow.3351880828
Short name T952
Test name
Test status
Simulation time 11234731881 ps
CPU time 221.32 seconds
Started Feb 08 01:14:22 PM UTC 25
Finished Feb 08 01:18:07 PM UTC 25
Peak memory 865900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351880828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_host_fifo_overflow.3351880828
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_fmt.2874994788
Short name T850
Test name
Test status
Simulation time 189898855 ps
CPU time 1.63 seconds
Started Feb 08 01:14:22 PM UTC 25
Finished Feb 08 01:14:25 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874994788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fmt.2874994788
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_rx.1776715269
Short name T853
Test name
Test status
Simulation time 584764389 ps
CPU time 5.27 seconds
Started Feb 08 01:14:23 PM UTC 25
Finished Feb 08 01:14:29 PM UTC 25
Peak memory 215832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776715269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.1776715269
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_watermark.937297551
Short name T1056
Test name
Test status
Simulation time 37386277044 ps
CPU time 365.59 seconds
Started Feb 08 01:14:21 PM UTC 25
Finished Feb 08 01:20:31 PM UTC 25
Peak memory 1586952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937297551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_wa
termark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_host_fifo_watermark.937297551
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_may_nack.2737247876
Short name T879
Test name
Test status
Simulation time 1830998925 ps
CPU time 14.63 seconds
Started Feb 08 01:14:54 PM UTC 25
Finished Feb 08 01:15:10 PM UTC 25
Peak memory 216228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737247876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 23.i2c_host_may_nack.2737247876
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_override.2603059481
Short name T145
Test name
Test status
Simulation time 30219376 ps
CPU time 1.12 seconds
Started Feb 08 01:14:20 PM UTC 25
Finished Feb 08 01:14:22 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603059481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 23.i2c_host_override.2603059481
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_perf.1411917850
Short name T934
Test name
Test status
Simulation time 13018522363 ps
CPU time 190.63 seconds
Started Feb 08 01:14:24 PM UTC 25
Finished Feb 08 01:17:38 PM UTC 25
Peak memory 1003144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411917850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_host_perf.1411917850
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_perf_precise.3983615551
Short name T851
Test name
Test status
Simulation time 197422268 ps
CPU time 1.31 seconds
Started Feb 08 01:14:24 PM UTC 25
Finished Feb 08 01:14:27 PM UTC 25
Peak memory 213812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983615551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_host_perf_precise.3983615551
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_smoke.3885105784
Short name T878
Test name
Test status
Simulation time 1174211133 ps
CPU time 49.29 seconds
Started Feb 08 01:14:18 PM UTC 25
Finished Feb 08 01:15:09 PM UTC 25
Peak memory 298636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885105784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_host_smoke.3885105784
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_host_stretch_timeout.2642217286
Short name T863
Test name
Test status
Simulation time 1837765142 ps
CPU time 26.82 seconds
Started Feb 08 01:14:24 PM UTC 25
Finished Feb 08 01:14:53 PM UTC 25
Peak memory 226064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642217286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 23.i2c_host_stretch_timeout.2642217286
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_bad_addr.2283607746
Short name T870
Test name
Test status
Simulation time 1568552557 ps
CPU time 8.17 seconds
Started Feb 08 01:14:53 PM UTC 25
Finished Feb 08 01:15:02 PM UTC 25
Peak memory 232488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2283607746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.2283607746
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_acq.3824943595
Short name T859
Test name
Test status
Simulation time 204312507 ps
CPU time 1.79 seconds
Started Feb 08 01:14:48 PM UTC 25
Finished Feb 08 01:14:51 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824943595 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_acq.3824943595
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_tx.1500461879
Short name T861
Test name
Test status
Simulation time 377763714 ps
CPU time 1.6 seconds
Started Feb 08 01:14:49 PM UTC 25
Finished Feb 08 01:14:52 PM UTC 25
Peak memory 213920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500461879 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_tx.1500461879
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_acq.1571534335
Short name T868
Test name
Test status
Simulation time 450243222 ps
CPU time 4.64 seconds
Started Feb 08 01:14:54 PM UTC 25
Finished Feb 08 01:15:00 PM UTC 25
Peak memory 215988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571534335 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.1571534335
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_tx.1875170207
Short name T866
Test name
Test status
Simulation time 562860569 ps
CPU time 2.06 seconds
Started Feb 08 01:14:55 PM UTC 25
Finished Feb 08 01:14:59 PM UTC 25
Peak memory 215716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875170207 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.1875170207
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_hrst.1914159273
Short name T865
Test name
Test status
Simulation time 1171554193 ps
CPU time 3.56 seconds
Started Feb 08 01:14:53 PM UTC 25
Finished Feb 08 01:14:58 PM UTC 25
Peak memory 226408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914159273 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_hrst.1914159273
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_intr_smoke.1591822416
Short name T856
Test name
Test status
Simulation time 3928851703 ps
CPU time 9.19 seconds
Started Feb 08 01:14:35 PM UTC 25
Finished Feb 08 01:14:46 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591822416 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_smoke.1591822416
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_intr_stress_wr.2058173011
Short name T1205
Test name
Test status
Simulation time 19414987312 ps
CPU time 519.57 seconds
Started Feb 08 01:14:39 PM UTC 25
Finished Feb 08 01:23:24 PM UTC 25
Peak memory 4925000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20581
73011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.2058173011
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull.1659061032
Short name T874
Test name
Test status
Simulation time 417565155 ps
CPU time 3.97 seconds
Started Feb 08 01:15:00 PM UTC 25
Finished Feb 08 01:15:06 PM UTC 25
Peak memory 226212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659061032 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_acqfull.1659061032
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull_addr.3936063930
Short name T876
Test name
Test status
Simulation time 2003784861 ps
CPU time 4.05 seconds
Started Feb 08 01:15:00 PM UTC 25
Finished Feb 08 01:15:06 PM UTC 25
Peak memory 216116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936063930 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_acqfull_addr.3936063930
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_perf.2112195702
Short name T869
Test name
Test status
Simulation time 933725744 ps
CPU time 8.13 seconds
Started Feb 08 01:14:51 PM UTC 25
Finished Feb 08 01:15:01 PM UTC 25
Peak memory 232488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112195702 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_perf.2112195702
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_smbus_maxlen.2923756824
Short name T873
Test name
Test status
Simulation time 963444643 ps
CPU time 3.81 seconds
Started Feb 08 01:14:59 PM UTC 25
Finished Feb 08 01:15:04 PM UTC 25
Peak memory 215616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923756824 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smbus_maxlen.2923756824
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_smoke.1833956494
Short name T867
Test name
Test status
Simulation time 7364076292 ps
CPU time 30.47 seconds
Started Feb 08 01:14:28 PM UTC 25
Finished Feb 08 01:15:00 PM UTC 25
Peak memory 226268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833956494 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smoke.1833956494
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_stress_all.1234298892
Short name T1304
Test name
Test status
Simulation time 53744917908 ps
CPU time 662.52 seconds
Started Feb 08 01:14:52 PM UTC 25
Finished Feb 08 01:26:02 PM UTC 25
Peak memory 3468828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234298892 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_all.1234298892
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_stress_rd.335246987
Short name T888
Test name
Test status
Simulation time 7684670961 ps
CPU time 83.46 seconds
Started Feb 08 01:14:31 PM UTC 25
Finished Feb 08 01:15:56 PM UTC 25
Peak memory 232412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335246987 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_rd.335246987
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_stress_wr.4200484041
Short name T980
Test name
Test status
Simulation time 42395246150 ps
CPU time 248.48 seconds
Started Feb 08 01:14:30 PM UTC 25
Finished Feb 08 01:18:41 PM UTC 25
Peak memory 2610688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200484041 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_wr.4200484041
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_stretch.714952999
Short name T858
Test name
Test status
Simulation time 951639648 ps
CPU time 15.12 seconds
Started Feb 08 01:14:34 PM UTC 25
Finished Feb 08 01:14:51 PM UTC 25
Peak memory 361980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714952999 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stretch.714952999
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_timeout.2951174436
Short name T864
Test name
Test status
Simulation time 1216528186 ps
CPU time 11.36 seconds
Started Feb 08 01:14:41 PM UTC 25
Finished Feb 08 01:14:54 PM UTC 25
Peak memory 243144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951174436 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_timeout.2951174436
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/23.i2c_target_tx_stretch_ctrl.3685644945
Short name T871
Test name
Test status
Simulation time 71565926 ps
CPU time 2.09 seconds
Started Feb 08 01:14:59 PM UTC 25
Finished Feb 08 01:15:03 PM UTC 25
Peak memory 215908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685644945 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.3685644945
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_alert_test.1537923737
Short name T905
Test name
Test status
Simulation time 16338747 ps
CPU time 0.93 seconds
Started Feb 08 01:16:04 PM UTC 25
Finished Feb 08 01:16:06 PM UTC 25
Peak memory 213916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537923737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.1537923737
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_error_intr.1823913112
Short name T882
Test name
Test status
Simulation time 85063782 ps
CPU time 1.7 seconds
Started Feb 08 01:15:14 PM UTC 25
Finished Feb 08 01:15:17 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823913112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_host_error_intr.1823913112
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_fmt_empty.2508066096
Short name T883
Test name
Test status
Simulation time 1732076009 ps
CPU time 11.08 seconds
Started Feb 08 01:15:07 PM UTC 25
Finished Feb 08 01:15:19 PM UTC 25
Peak memory 286344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508066096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empty.2508066096
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_full.1340909190
Short name T917
Test name
Test status
Simulation time 13425037704 ps
CPU time 114.5 seconds
Started Feb 08 01:15:07 PM UTC 25
Finished Feb 08 01:17:04 PM UTC 25
Peak memory 753420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340909190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_host_fifo_full.1340909190
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_overflow.2539946418
Short name T940
Test name
Test status
Simulation time 2164792728 ps
CPU time 155.96 seconds
Started Feb 08 01:15:06 PM UTC 25
Finished Feb 08 01:17:44 PM UTC 25
Peak memory 704012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539946418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_host_fifo_overflow.2539946418
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_fmt.1324667150
Short name T877
Test name
Test status
Simulation time 161900117 ps
CPU time 2.1 seconds
Started Feb 08 01:15:06 PM UTC 25
Finished Feb 08 01:15:09 PM UTC 25
Peak memory 215776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324667150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fmt.1324667150
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_rx.582293597
Short name T880
Test name
Test status
Simulation time 701178627 ps
CPU time 4.76 seconds
Started Feb 08 01:15:07 PM UTC 25
Finished Feb 08 01:15:13 PM UTC 25
Peak memory 215960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582293597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.582293597
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_watermark.2986793177
Short name T954
Test name
Test status
Simulation time 5253375215 ps
CPU time 181.36 seconds
Started Feb 08 01:15:04 PM UTC 25
Finished Feb 08 01:18:09 PM UTC 25
Peak memory 1531384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986793177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 24.i2c_host_fifo_watermark.2986793177
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_may_nack.4238819515
Short name T902
Test name
Test status
Simulation time 2215510212 ps
CPU time 10 seconds
Started Feb 08 01:15:52 PM UTC 25
Finished Feb 08 01:16:04 PM UTC 25
Peak memory 216084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238819515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 24.i2c_host_may_nack.4238819515
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_override.375089565
Short name T875
Test name
Test status
Simulation time 161266657 ps
CPU time 1.04 seconds
Started Feb 08 01:15:03 PM UTC 25
Finished Feb 08 01:15:06 PM UTC 25
Peak memory 213804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375089565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overrid
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 24.i2c_host_override.375089565
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_perf.592531930
Short name T1666
Test name
Test status
Simulation time 26607924503 ps
CPU time 1249.84 seconds
Started Feb 08 01:15:10 PM UTC 25
Finished Feb 08 01:36:13 PM UTC 25
Peak memory 603660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592531930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_host_perf.592531930
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_perf_precise.621467092
Short name T881
Test name
Test status
Simulation time 240029431 ps
CPU time 3.55 seconds
Started Feb 08 01:15:10 PM UTC 25
Finished Feb 08 01:15:15 PM UTC 25
Peak memory 234960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621467092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pr
ecise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_host_perf_precise.621467092
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_smoke.601864394
Short name T890
Test name
Test status
Simulation time 7599447810 ps
CPU time 36.07 seconds
Started Feb 08 01:15:03 PM UTC 25
Finished Feb 08 01:15:41 PM UTC 25
Peak memory 425344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601864394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_host_smoke.601864394
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_stretch_timeout.3578799308
Short name T884
Test name
Test status
Simulation time 258431307 ps
CPU time 14.96 seconds
Started Feb 08 01:15:11 PM UTC 25
Finished Feb 08 01:15:27 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578799308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 24.i2c_host_stretch_timeout.3578799308
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_bad_addr.2656329489
Short name T837
Test name
Test status
Simulation time 11499236392 ps
CPU time 6.46 seconds
Started Feb 08 01:15:50 PM UTC 25
Finished Feb 08 01:15:58 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2656329489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.2656329489
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_acq.1856000304
Short name T891
Test name
Test status
Simulation time 551484642 ps
CPU time 1.9 seconds
Started Feb 08 01:15:42 PM UTC 25
Finished Feb 08 01:15:45 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856000304 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_acq.1856000304
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_tx.3189341556
Short name T893
Test name
Test status
Simulation time 298620992 ps
CPU time 2.05 seconds
Started Feb 08 01:15:46 PM UTC 25
Finished Feb 08 01:15:49 PM UTC 25
Peak memory 228460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189341556 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_tx.3189341556
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_acq.1328395980
Short name T899
Test name
Test status
Simulation time 7834521795 ps
CPU time 5.29 seconds
Started Feb 08 01:15:57 PM UTC 25
Finished Feb 08 01:16:03 PM UTC 25
Peak memory 215924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328395980 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.1328395980
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_tx.3630482408
Short name T897
Test name
Test status
Simulation time 77981061 ps
CPU time 1.26 seconds
Started Feb 08 01:15:57 PM UTC 25
Finished Feb 08 01:15:59 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630482408 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.3630482408
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_hrst.3253893846
Short name T896
Test name
Test status
Simulation time 343014122 ps
CPU time 2.68 seconds
Started Feb 08 01:15:51 PM UTC 25
Finished Feb 08 01:15:55 PM UTC 25
Peak memory 226160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253893846 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_hrst.3253893846
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_intr_smoke.724607570
Short name T892
Test name
Test status
Simulation time 7420417861 ps
CPU time 7.58 seconds
Started Feb 08 01:15:39 PM UTC 25
Finished Feb 08 01:15:48 PM UTC 25
Peak memory 226276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724607570 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_smoke.724607570
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_intr_stress_wr.2833622112
Short name T1246
Test name
Test status
Simulation time 21333658384 ps
CPU time 543.09 seconds
Started Feb 08 01:15:40 PM UTC 25
Finished Feb 08 01:24:48 PM UTC 25
Peak memory 5402112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28336
22112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.2833622112
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull.2501197668
Short name T901
Test name
Test status
Simulation time 1007485447 ps
CPU time 3.69 seconds
Started Feb 08 01:15:59 PM UTC 25
Finished Feb 08 01:16:04 PM UTC 25
Peak memory 226412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501197668 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_acqfull.2501197668
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull_addr.3793851887
Short name T903
Test name
Test status
Simulation time 435560459 ps
CPU time 4.17 seconds
Started Feb 08 01:16:00 PM UTC 25
Finished Feb 08 01:16:05 PM UTC 25
Peak memory 216188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793851887 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_acqfull_addr.3793851887
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_nack_txstretch.3845102831
Short name T904
Test name
Test status
Simulation time 219706454 ps
CPU time 2.41 seconds
Started Feb 08 01:16:02 PM UTC 25
Finished Feb 08 01:16:06 PM UTC 25
Peak memory 233032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845102831 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_txstretch.3845102831
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_perf.2870260824
Short name T848
Test name
Test status
Simulation time 1661151014 ps
CPU time 8.75 seconds
Started Feb 08 01:15:46 PM UTC 25
Finished Feb 08 01:15:56 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870260824 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_perf.2870260824
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_smbus_maxlen.1664948951
Short name T900
Test name
Test status
Simulation time 2998432178 ps
CPU time 4.4 seconds
Started Feb 08 01:15:58 PM UTC 25
Finished Feb 08 01:16:03 PM UTC 25
Peak memory 215700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664948951 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smbus_maxlen.1664948951
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_smoke.71530034
Short name T885
Test name
Test status
Simulation time 2583203798 ps
CPU time 13.18 seconds
Started Feb 08 01:15:18 PM UTC 25
Finished Feb 08 01:15:33 PM UTC 25
Peak memory 226144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71530034 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smoke.71530034
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_stress_all.1702775804
Short name T975
Test name
Test status
Simulation time 33434376219 ps
CPU time 161.72 seconds
Started Feb 08 01:15:49 PM UTC 25
Finished Feb 08 01:18:33 PM UTC 25
Peak memory 1207832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702775804 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_all.1702775804
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_stress_rd.2235124830
Short name T886
Test name
Test status
Simulation time 681564178 ps
CPU time 8.41 seconds
Started Feb 08 01:15:28 PM UTC 25
Finished Feb 08 01:15:38 PM UTC 25
Peak memory 216164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235124830 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_rd.2235124830
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_stress_wr.1180981644
Short name T1750
Test name
Test status
Simulation time 68958327788 ps
CPU time 2480.62 seconds
Started Feb 08 01:15:20 PM UTC 25
Finished Feb 08 01:57:02 PM UTC 25
Peak memory 12881416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180981644 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_wr.1180981644
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_timeout.2161530204
Short name T894
Test name
Test status
Simulation time 1031378213 ps
CPU time 7.79 seconds
Started Feb 08 01:15:41 PM UTC 25
Finished Feb 08 01:15:50 PM UTC 25
Peak memory 228392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161530204 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_timeout.2161530204
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_tx_stretch_ctrl.3237759457
Short name T898
Test name
Test status
Simulation time 113050108 ps
CPU time 3.54 seconds
Started Feb 08 01:15:57 PM UTC 25
Finished Feb 08 01:16:01 PM UTC 25
Peak memory 215800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237759457 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.3237759457
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_alert_test.1468931912
Short name T935
Test name
Test status
Simulation time 43689037 ps
CPU time 1.01 seconds
Started Feb 08 01:17:37 PM UTC 25
Finished Feb 08 01:17:39 PM UTC 25
Peak memory 214996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468931912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1468931912
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_error_intr.3706754423
Short name T912
Test name
Test status
Simulation time 690383912 ps
CPU time 4.43 seconds
Started Feb 08 01:16:26 PM UTC 25
Finished Feb 08 01:16:32 PM UTC 25
Peak memory 243520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706754423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_host_error_intr.3706754423
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_fmt_empty.839941054
Short name T910
Test name
Test status
Simulation time 3085325459 ps
CPU time 16.4 seconds
Started Feb 08 01:16:07 PM UTC 25
Finished Feb 08 01:16:25 PM UTC 25
Peak memory 271804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839941054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empty.839941054
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_full.1207175751
Short name T995
Test name
Test status
Simulation time 31784338696 ps
CPU time 165.5 seconds
Started Feb 08 01:16:10 PM UTC 25
Finished Feb 08 01:18:58 PM UTC 25
Peak memory 626392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207175751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_host_fifo_full.1207175751
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_overflow.822927954
Short name T950
Test name
Test status
Simulation time 1627174893 ps
CPU time 117.69 seconds
Started Feb 08 01:16:06 PM UTC 25
Finished Feb 08 01:18:06 PM UTC 25
Peak memory 474412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822927954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_host_fifo_overflow.822927954
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_fmt.486520474
Short name T906
Test name
Test status
Simulation time 469290333 ps
CPU time 1.57 seconds
Started Feb 08 01:16:06 PM UTC 25
Finished Feb 08 01:16:09 PM UTC 25
Peak memory 214224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486520474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fmt.486520474
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_rx.739040424
Short name T907
Test name
Test status
Simulation time 163455552 ps
CPU time 6.33 seconds
Started Feb 08 01:16:07 PM UTC 25
Finished Feb 08 01:16:15 PM UTC 25
Peak memory 245240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739040424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.739040424
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_watermark.3712844761
Short name T1017
Test name
Test status
Simulation time 3330111620 ps
CPU time 204.54 seconds
Started Feb 08 01:16:05 PM UTC 25
Finished Feb 08 01:19:33 PM UTC 25
Peak memory 984536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712844761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 25.i2c_host_fifo_watermark.3712844761
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_may_nack.138054345
Short name T929
Test name
Test status
Simulation time 952504115 ps
CPU time 8.93 seconds
Started Feb 08 01:17:25 PM UTC 25
Finished Feb 08 01:17:35 PM UTC 25
Peak memory 216152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138054345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nac
k_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 25.i2c_host_may_nack.138054345
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_mode_toggle.2107438004
Short name T261
Test name
Test status
Simulation time 506517244 ps
CPU time 5.38 seconds
Started Feb 08 01:17:25 PM UTC 25
Finished Feb 08 01:17:31 PM UTC 25
Peak memory 226464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107438004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_t
oggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_host_mode_toggle.2107438004
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_override.3029599346
Short name T146
Test name
Test status
Simulation time 17474476 ps
CPU time 0.93 seconds
Started Feb 08 01:16:04 PM UTC 25
Finished Feb 08 01:16:06 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029599346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 25.i2c_host_override.3029599346
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_perf.2481324155
Short name T956
Test name
Test status
Simulation time 30168615089 ps
CPU time 113.17 seconds
Started Feb 08 01:16:16 PM UTC 25
Finished Feb 08 01:18:11 PM UTC 25
Peak memory 368120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481324155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_host_perf.2481324155
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_perf_precise.290406426
Short name T909
Test name
Test status
Simulation time 86810186 ps
CPU time 1.63 seconds
Started Feb 08 01:16:21 PM UTC 25
Finished Feb 08 01:16:23 PM UTC 25
Peak memory 234204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290406426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pr
ecise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_host_perf_precise.290406426
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_smoke.659823196
Short name T914
Test name
Test status
Simulation time 1513530717 ps
CPU time 40.63 seconds
Started Feb 08 01:16:04 PM UTC 25
Finished Feb 08 01:16:46 PM UTC 25
Peak memory 394624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659823196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_host_smoke.659823196
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_host_stretch_timeout.248689609
Short name T913
Test name
Test status
Simulation time 3304724824 ps
CPU time 15.76 seconds
Started Feb 08 01:16:25 PM UTC 25
Finished Feb 08 01:16:42 PM UTC 25
Peak memory 232948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248689609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch
_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 25.i2c_host_stretch_timeout.248689609
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_bad_addr.3056866784
Short name T925
Test name
Test status
Simulation time 782202695 ps
CPU time 7.3 seconds
Started Feb 08 01:17:19 PM UTC 25
Finished Feb 08 01:17:28 PM UTC 25
Peak memory 226328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3056866784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.3056866784
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_acq.2527229621
Short name T920
Test name
Test status
Simulation time 257630939 ps
CPU time 1.15 seconds
Started Feb 08 01:17:14 PM UTC 25
Finished Feb 08 01:17:16 PM UTC 25
Peak memory 214224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527229621 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_acq.2527229621
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_tx.902655659
Short name T921
Test name
Test status
Simulation time 219761560 ps
CPU time 1.8 seconds
Started Feb 08 01:17:16 PM UTC 25
Finished Feb 08 01:17:19 PM UTC 25
Peak memory 216180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902655659 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_tx.902655659
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_acq.3343192555
Short name T926
Test name
Test status
Simulation time 2968856496 ps
CPU time 4.1 seconds
Started Feb 08 01:17:25 PM UTC 25
Finished Feb 08 01:17:30 PM UTC 25
Peak memory 215980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343192555 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.3343192555
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_tx.1271571034
Short name T927
Test name
Test status
Simulation time 908056475 ps
CPU time 1.6 seconds
Started Feb 08 01:17:29 PM UTC 25
Finished Feb 08 01:17:32 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271571034 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.1271571034
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_hrst.324985465
Short name T922
Test name
Test status
Simulation time 1008396087 ps
CPU time 2.79 seconds
Started Feb 08 01:17:19 PM UTC 25
Finished Feb 08 01:17:23 PM UTC 25
Peak memory 226096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324985465 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_hrst.324985465
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_intr_smoke.630387215
Short name T918
Test name
Test status
Simulation time 1850067300 ps
CPU time 11.45 seconds
Started Feb 08 01:16:58 PM UTC 25
Finished Feb 08 01:17:11 PM UTC 25
Peak memory 243264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630387215 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_smoke.630387215
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_intr_stress_wr.219358551
Short name T919
Test name
Test status
Simulation time 9602950375 ps
CPU time 10.23 seconds
Started Feb 08 01:17:04 PM UTC 25
Finished Feb 08 01:17:16 PM UTC 25
Peak memory 226820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21935
8551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.219358551
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull.1518961275
Short name T933
Test name
Test status
Simulation time 7091293378 ps
CPU time 3.4 seconds
Started Feb 08 01:17:33 PM UTC 25
Finished Feb 08 01:17:38 PM UTC 25
Peak memory 226272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518961275 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_acqfull.1518961275
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull_addr.4071754120
Short name T937
Test name
Test status
Simulation time 937680667 ps
CPU time 4.41 seconds
Started Feb 08 01:17:35 PM UTC 25
Finished Feb 08 01:17:41 PM UTC 25
Peak memory 215924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071754120 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_acqfull_addr.4071754120
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_nack_txstretch.1932439650
Short name T936
Test name
Test status
Simulation time 406184668 ps
CPU time 2.16 seconds
Started Feb 08 01:17:36 PM UTC 25
Finished Feb 08 01:17:39 PM UTC 25
Peak memory 232856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932439650 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_txstretch.1932439650
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_perf.3574753987
Short name T924
Test name
Test status
Simulation time 1032756350 ps
CPU time 5.67 seconds
Started Feb 08 01:17:17 PM UTC 25
Finished Feb 08 01:17:24 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574753987 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_perf.3574753987
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_smbus_maxlen.1266499792
Short name T931
Test name
Test status
Simulation time 2208018556 ps
CPU time 3.55 seconds
Started Feb 08 01:17:32 PM UTC 25
Finished Feb 08 01:17:36 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266499792 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smbus_maxlen.1266499792
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_smoke.1024449572
Short name T915
Test name
Test status
Simulation time 3357373908 ps
CPU time 15.99 seconds
Started Feb 08 01:16:32 PM UTC 25
Finished Feb 08 01:16:49 PM UTC 25
Peak memory 232972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024449572 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smoke.1024449572
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_stress_all.2688303657
Short name T1280
Test name
Test status
Simulation time 40675005199 ps
CPU time 489.09 seconds
Started Feb 08 01:17:17 PM UTC 25
Finished Feb 08 01:25:31 PM UTC 25
Peak memory 2965044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688303657 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_all.2688303657
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_stress_rd.3771088316
Short name T916
Test name
Test status
Simulation time 1039875268 ps
CPU time 8.81 seconds
Started Feb 08 01:16:47 PM UTC 25
Finished Feb 08 01:16:57 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771088316 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_rd.3771088316
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_stress_wr.1037189443
Short name T1061
Test name
Test status
Simulation time 29752297304 ps
CPU time 229.25 seconds
Started Feb 08 01:16:43 PM UTC 25
Finished Feb 08 01:20:36 PM UTC 25
Peak memory 2606656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037189443 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_wr.1037189443
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_timeout.3116765831
Short name T923
Test name
Test status
Simulation time 2626117188 ps
CPU time 10.61 seconds
Started Feb 08 01:17:12 PM UTC 25
Finished Feb 08 01:17:24 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116765831 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_timeout.3116765831
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/25.i2c_target_tx_stretch_ctrl.3481506177
Short name T932
Test name
Test status
Simulation time 204090654 ps
CPU time 5.21 seconds
Started Feb 08 01:17:31 PM UTC 25
Finished Feb 08 01:17:37 PM UTC 25
Peak memory 216120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481506177 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.3481506177
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_alert_test.236741878
Short name T966
Test name
Test status
Simulation time 25178806 ps
CPU time 0.96 seconds
Started Feb 08 01:18:17 PM UTC 25
Finished Feb 08 01:18:19 PM UTC 25
Peak memory 214944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236741878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM
_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.236741878
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_error_intr.1051918330
Short name T943
Test name
Test status
Simulation time 44024712 ps
CPU time 1.85 seconds
Started Feb 08 01:17:46 PM UTC 25
Finished Feb 08 01:17:49 PM UTC 25
Peak memory 226024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051918330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_host_error_intr.1051918330
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_fmt_empty.2551108454
Short name T945
Test name
Test status
Simulation time 413640299 ps
CPU time 11.86 seconds
Started Feb 08 01:17:40 PM UTC 25
Finished Feb 08 01:17:54 PM UTC 25
Peak memory 306620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551108454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empty.2551108454
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_full.2811752821
Short name T1096
Test name
Test status
Simulation time 6241541110 ps
CPU time 209.99 seconds
Started Feb 08 01:17:42 PM UTC 25
Finished Feb 08 01:21:15 PM UTC 25
Peak memory 661332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811752821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_host_fifo_full.2811752821
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_overflow.515799507
Short name T974
Test name
Test status
Simulation time 2889360467 ps
CPU time 50.97 seconds
Started Feb 08 01:17:38 PM UTC 25
Finished Feb 08 01:18:31 PM UTC 25
Peak memory 577024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515799507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_host_fifo_overflow.515799507
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_fmt.4026628460
Short name T939
Test name
Test status
Simulation time 376787117 ps
CPU time 1.7 seconds
Started Feb 08 01:17:39 PM UTC 25
Finished Feb 08 01:17:42 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026628460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fmt.4026628460
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_rx.3787239558
Short name T942
Test name
Test status
Simulation time 1490056773 ps
CPU time 4.7 seconds
Started Feb 08 01:17:41 PM UTC 25
Finished Feb 08 01:17:47 PM UTC 25
Peak memory 216148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787239558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.3787239558
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_watermark.1054338511
Short name T1034
Test name
Test status
Simulation time 4639795705 ps
CPU time 124.53 seconds
Started Feb 08 01:17:38 PM UTC 25
Finished Feb 08 01:19:45 PM UTC 25
Peak memory 1400308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054338511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 26.i2c_host_fifo_watermark.1054338511
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_may_nack.1394436180
Short name T250
Test name
Test status
Simulation time 5947823099 ps
CPU time 8.35 seconds
Started Feb 08 01:18:10 PM UTC 25
Finished Feb 08 01:18:20 PM UTC 25
Peak memory 216176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394436180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 26.i2c_host_may_nack.1394436180
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_mode_toggle.2522587483
Short name T262
Test name
Test status
Simulation time 507931681 ps
CPU time 4.78 seconds
Started Feb 08 01:18:09 PM UTC 25
Finished Feb 08 01:18:15 PM UTC 25
Peak memory 234904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522587483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_t
oggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_host_mode_toggle.2522587483
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_override.3625354853
Short name T938
Test name
Test status
Simulation time 33340852 ps
CPU time 1.06 seconds
Started Feb 08 01:17:38 PM UTC 25
Finished Feb 08 01:17:41 PM UTC 25
Peak memory 213848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625354853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 26.i2c_host_override.3625354853
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_perf.2557549242
Short name T944
Test name
Test status
Simulation time 1203989380 ps
CPU time 6.15 seconds
Started Feb 08 01:17:42 PM UTC 25
Finished Feb 08 01:17:49 PM UTC 25
Peak memory 228444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557549242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_host_perf.2557549242
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_perf_precise.1349057808
Short name T941
Test name
Test status
Simulation time 55686930 ps
CPU time 1.51 seconds
Started Feb 08 01:17:43 PM UTC 25
Finished Feb 08 01:17:45 PM UTC 25
Peak memory 236204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349057808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_host_perf_precise.1349057808
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_smoke.3088678546
Short name T978
Test name
Test status
Simulation time 2158857400 ps
CPU time 59.49 seconds
Started Feb 08 01:17:37 PM UTC 25
Finished Feb 08 01:18:39 PM UTC 25
Peak memory 452356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088678546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_host_smoke.3088678546
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_stress_all.661546476
Short name T25
Test name
Test status
Simulation time 51862623366 ps
CPU time 994.71 seconds
Started Feb 08 01:17:47 PM UTC 25
Finished Feb 08 01:34:32 PM UTC 25
Peak memory 1818448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661546476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_host_stress_all.661546476
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_stretch_timeout.2582615300
Short name T947
Test name
Test status
Simulation time 751762770 ps
CPU time 15.27 seconds
Started Feb 08 01:17:45 PM UTC 25
Finished Feb 08 01:18:01 PM UTC 25
Peak memory 232284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582615300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.i2c_host_stretch_timeout.2582615300
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_bad_addr.457370570
Short name T963
Test name
Test status
Simulation time 5941406367 ps
CPU time 9.35 seconds
Started Feb 08 01:18:07 PM UTC 25
Finished Feb 08 01:18:18 PM UTC 25
Peak memory 232648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=457370570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.457370570
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_acq.2331849799
Short name T951
Test name
Test status
Simulation time 293695552 ps
CPU time 1.63 seconds
Started Feb 08 01:18:04 PM UTC 25
Finished Feb 08 01:18:06 PM UTC 25
Peak memory 216240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331849799 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_acq.2331849799
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_tx.642806483
Short name T953
Test name
Test status
Simulation time 283412266 ps
CPU time 1.77 seconds
Started Feb 08 01:18:05 PM UTC 25
Finished Feb 08 01:18:08 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642806483 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_tx.642806483
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_acq.1739885417
Short name T962
Test name
Test status
Simulation time 489303448 ps
CPU time 4.81 seconds
Started Feb 08 01:18:11 PM UTC 25
Finished Feb 08 01:18:17 PM UTC 25
Peak memory 215920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739885417 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.1739885417
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_tx.3611264709
Short name T961
Test name
Test status
Simulation time 134371442 ps
CPU time 1.91 seconds
Started Feb 08 01:18:12 PM UTC 25
Finished Feb 08 01:18:15 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611264709 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.3611264709
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_intr_smoke.3368301577
Short name T949
Test name
Test status
Simulation time 5745942747 ps
CPU time 8.68 seconds
Started Feb 08 01:17:54 PM UTC 25
Finished Feb 08 01:18:04 PM UTC 25
Peak memory 232944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368301577 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_smoke.3368301577
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_intr_stress_wr.860178819
Short name T1104
Test name
Test status
Simulation time 20134206711 ps
CPU time 194.27 seconds
Started Feb 08 01:18:03 PM UTC 25
Finished Feb 08 01:21:20 PM UTC 25
Peak memory 1791500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86017
8819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.860178819
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull.912223460
Short name T968
Test name
Test status
Simulation time 674757047 ps
CPU time 5.28 seconds
Started Feb 08 01:18:13 PM UTC 25
Finished Feb 08 01:18:20 PM UTC 25
Peak memory 226100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912223460 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_acqfull.912223460
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull_addr.4088810265
Short name T967
Test name
Test status
Simulation time 5432417753 ps
CPU time 3.86 seconds
Started Feb 08 01:18:15 PM UTC 25
Finished Feb 08 01:18:20 PM UTC 25
Peak memory 215992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088810265 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_acqfull_addr.4088810265
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_nack_txstretch.2677324438
Short name T965
Test name
Test status
Simulation time 134789073 ps
CPU time 1.74 seconds
Started Feb 08 01:18:16 PM UTC 25
Finished Feb 08 01:18:18 PM UTC 25
Peak memory 231936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677324438 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_txstretch.2677324438
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_perf.2282413747
Short name T959
Test name
Test status
Simulation time 2243202024 ps
CPU time 5.39 seconds
Started Feb 08 01:18:06 PM UTC 25
Finished Feb 08 01:18:12 PM UTC 25
Peak memory 233012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282413747 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_perf.2282413747
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_smbus_maxlen.1388432161
Short name T964
Test name
Test status
Simulation time 1026219013 ps
CPU time 3.31 seconds
Started Feb 08 01:18:13 PM UTC 25
Finished Feb 08 01:18:18 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388432161 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smbus_maxlen.1388432161
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_smoke.1509577901
Short name T957
Test name
Test status
Simulation time 5801051804 ps
CPU time 20.92 seconds
Started Feb 08 01:17:49 PM UTC 25
Finished Feb 08 01:18:11 PM UTC 25
Peak memory 226192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509577901 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smoke.1509577901
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_stress_all.4120341577
Short name T1414
Test name
Test status
Simulation time 27787226729 ps
CPU time 614.93 seconds
Started Feb 08 01:18:07 PM UTC 25
Finished Feb 08 01:28:28 PM UTC 25
Peak memory 5981704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120341577 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_all.4120341577
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_stress_rd.376904609
Short name T948
Test name
Test status
Simulation time 236266599 ps
CPU time 11.14 seconds
Started Feb 08 01:17:50 PM UTC 25
Finished Feb 08 01:18:03 PM UTC 25
Peak memory 215964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376904609 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_rd.376904609
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_stress_wr.4124144724
Short name T955
Test name
Test status
Simulation time 31824809006 ps
CPU time 18.54 seconds
Started Feb 08 01:17:50 PM UTC 25
Finished Feb 08 01:18:10 PM UTC 25
Peak memory 374288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124144724 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_wr.4124144724
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_stretch.2054147466
Short name T946
Test name
Test status
Simulation time 2444735357 ps
CPU time 9.72 seconds
Started Feb 08 01:17:50 PM UTC 25
Finished Feb 08 01:18:01 PM UTC 25
Peak memory 282428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054147466 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stretch.2054147466
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_timeout.3183870577
Short name T960
Test name
Test status
Simulation time 1707340396 ps
CPU time 9.44 seconds
Started Feb 08 01:18:03 PM UTC 25
Finished Feb 08 01:18:13 PM UTC 25
Peak memory 232972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183870577 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_timeout.3183870577
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_target_tx_stretch_ctrl.2763206475
Short name T970
Test name
Test status
Simulation time 360163961 ps
CPU time 7.56 seconds
Started Feb 08 01:18:12 PM UTC 25
Finished Feb 08 01:18:21 PM UTC 25
Peak memory 215924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763206475 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.2763206475
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_alert_test.1168199790
Short name T997
Test name
Test status
Simulation time 18886373 ps
CPU time 0.95 seconds
Started Feb 08 01:18:58 PM UTC 25
Finished Feb 08 01:19:01 PM UTC 25
Peak memory 213916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168199790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.1168199790
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_error_intr.4106133712
Short name T976
Test name
Test status
Simulation time 1415829822 ps
CPU time 7.24 seconds
Started Feb 08 01:18:26 PM UTC 25
Finished Feb 08 01:18:35 PM UTC 25
Peak memory 226348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106133712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_host_error_intr.4106133712
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_fmt_empty.42317042
Short name T977
Test name
Test status
Simulation time 699925110 ps
CPU time 15.85 seconds
Started Feb 08 01:18:21 PM UTC 25
Finished Feb 08 01:18:38 PM UTC 25
Peak memory 376256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42317042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empty.42317042
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_full.1752802372
Short name T1040
Test name
Test status
Simulation time 11573574916 ps
CPU time 96.48 seconds
Started Feb 08 01:18:21 PM UTC 25
Finished Feb 08 01:20:00 PM UTC 25
Peak memory 577272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752802372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_host_fifo_full.1752802372
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_overflow.268211492
Short name T1077
Test name
Test status
Simulation time 2287471451 ps
CPU time 151.94 seconds
Started Feb 08 01:18:20 PM UTC 25
Finished Feb 08 01:20:54 PM UTC 25
Peak memory 675336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268211492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_host_fifo_overflow.268211492
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_fmt.3535718846
Short name T971
Test name
Test status
Simulation time 109577971 ps
CPU time 1.82 seconds
Started Feb 08 01:18:20 PM UTC 25
Finished Feb 08 01:18:23 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535718846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fmt.3535718846
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_rx.1201541995
Short name T973
Test name
Test status
Simulation time 626499401 ps
CPU time 5.97 seconds
Started Feb 08 01:18:21 PM UTC 25
Finished Feb 08 01:18:28 PM UTC 25
Peak memory 247564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201541995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.1201541995
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_watermark.438916686
Short name T1109
Test name
Test status
Simulation time 11286552918 ps
CPU time 183.48 seconds
Started Feb 08 01:18:19 PM UTC 25
Finished Feb 08 01:21:26 PM UTC 25
Peak memory 908808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438916686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_wa
termark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_host_fifo_watermark.438916686
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_may_nack.2464009355
Short name T1011
Test name
Test status
Simulation time 484744508 ps
CPU time 22.67 seconds
Started Feb 08 01:18:50 PM UTC 25
Finished Feb 08 01:19:14 PM UTC 25
Peak memory 215980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464009355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 27.i2c_host_may_nack.2464009355
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_mode_toggle.911354894
Short name T991
Test name
Test status
Simulation time 236322720 ps
CPU time 2.54 seconds
Started Feb 08 01:18:50 PM UTC 25
Finished Feb 08 01:18:54 PM UTC 25
Peak memory 228192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911354894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_to
ggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_host_mode_toggle.911354894
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_override.741457884
Short name T969
Test name
Test status
Simulation time 31239284 ps
CPU time 0.93 seconds
Started Feb 08 01:18:19 PM UTC 25
Finished Feb 08 01:18:21 PM UTC 25
Peak memory 213920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741457884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overrid
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 27.i2c_host_override.741457884
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_perf.1021282292
Short name T1264
Test name
Test status
Simulation time 5310340214 ps
CPU time 399.22 seconds
Started Feb 08 01:18:22 PM UTC 25
Finished Feb 08 01:25:06 PM UTC 25
Peak memory 1437248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021282292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_host_perf.1021282292
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_perf_precise.1226803996
Short name T972
Test name
Test status
Simulation time 32249371 ps
CPU time 1.89 seconds
Started Feb 08 01:18:22 PM UTC 25
Finished Feb 08 01:18:25 PM UTC 25
Peak memory 236060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226803996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_host_perf_precise.1226803996
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_smoke.2531064842
Short name T1002
Test name
Test status
Simulation time 1881409891 ps
CPU time 43.65 seconds
Started Feb 08 01:18:18 PM UTC 25
Finished Feb 08 01:19:03 PM UTC 25
Peak memory 343556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531064842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_host_smoke.2531064842
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_host_stretch_timeout.3580867316
Short name T986
Test name
Test status
Simulation time 1732868061 ps
CPU time 22.91 seconds
Started Feb 08 01:18:24 PM UTC 25
Finished Feb 08 01:18:49 PM UTC 25
Peak memory 226092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580867316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_host_stretch_timeout.3580867316
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_bad_addr.231480530
Short name T994
Test name
Test status
Simulation time 1064365403 ps
CPU time 8.64 seconds
Started Feb 08 01:18:47 PM UTC 25
Finished Feb 08 01:18:57 PM UTC 25
Peak memory 230272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=231480530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.231480530
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_acq.3223383364
Short name T984
Test name
Test status
Simulation time 246598635 ps
CPU time 1.64 seconds
Started Feb 08 01:18:42 PM UTC 25
Finished Feb 08 01:18:45 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223383364 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_acq.3223383364
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_tx.3983572716
Short name T985
Test name
Test status
Simulation time 279575258 ps
CPU time 1.29 seconds
Started Feb 08 01:18:43 PM UTC 25
Finished Feb 08 01:18:46 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983572716 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_tx.3983572716
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_acq.2327400581
Short name T990
Test name
Test status
Simulation time 138899408 ps
CPU time 2.09 seconds
Started Feb 08 01:18:50 PM UTC 25
Finished Feb 08 01:18:53 PM UTC 25
Peak memory 215904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327400581 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.2327400581
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_tx.1638362219
Short name T993
Test name
Test status
Simulation time 168046632 ps
CPU time 1.72 seconds
Started Feb 08 01:18:53 PM UTC 25
Finished Feb 08 01:18:56 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638362219 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.1638362219
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_hrst.4046089204
Short name T989
Test name
Test status
Simulation time 1731749472 ps
CPU time 3.26 seconds
Started Feb 08 01:18:48 PM UTC 25
Finished Feb 08 01:18:52 PM UTC 25
Peak memory 226164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046089204 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_hrst.4046089204
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_intr_smoke.260381078
Short name T983
Test name
Test status
Simulation time 1582640474 ps
CPU time 6.61 seconds
Started Feb 08 01:18:36 PM UTC 25
Finished Feb 08 01:18:44 PM UTC 25
Peak memory 226340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260381078 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_smoke.260381078
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_intr_stress_wr.4230992569
Short name T1008
Test name
Test status
Simulation time 5873167620 ps
CPU time 28.2 seconds
Started Feb 08 01:18:39 PM UTC 25
Finished Feb 08 01:19:09 PM UTC 25
Peak memory 878088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42309
92569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.4230992569
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull.1742368867
Short name T998
Test name
Test status
Simulation time 2298797243 ps
CPU time 4.31 seconds
Started Feb 08 01:18:55 PM UTC 25
Finished Feb 08 01:19:01 PM UTC 25
Peak memory 226284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742368867 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_acqfull.1742368867
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull_addr.1436521431
Short name T1001
Test name
Test status
Simulation time 3818905071 ps
CPU time 4.03 seconds
Started Feb 08 01:18:57 PM UTC 25
Finished Feb 08 01:19:03 PM UTC 25
Peak memory 216064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436521431 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_acqfull_addr.1436521431
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_nack_txstretch.1471450000
Short name T999
Test name
Test status
Simulation time 132110356 ps
CPU time 2.29 seconds
Started Feb 08 01:18:57 PM UTC 25
Finished Feb 08 01:19:01 PM UTC 25
Peak memory 233104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471450000 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_txstretch.1471450000
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_perf.2382883859
Short name T992
Test name
Test status
Simulation time 3608113869 ps
CPU time 7.19 seconds
Started Feb 08 01:18:45 PM UTC 25
Finished Feb 08 01:18:54 PM UTC 25
Peak memory 233032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382883859 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_perf.2382883859
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_smbus_maxlen.3736476434
Short name T996
Test name
Test status
Simulation time 761029940 ps
CPU time 2.83 seconds
Started Feb 08 01:18:54 PM UTC 25
Finished Feb 08 01:18:58 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736476434 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smbus_maxlen.3736476434
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_smoke.2777516884
Short name T979
Test name
Test status
Simulation time 4653948303 ps
CPU time 8.74 seconds
Started Feb 08 01:18:30 PM UTC 25
Finished Feb 08 01:18:40 PM UTC 25
Peak memory 228192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777516884 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smoke.2777516884
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_stress_all.2075925605
Short name T1045
Test name
Test status
Simulation time 51468530554 ps
CPU time 83.84 seconds
Started Feb 08 01:18:46 PM UTC 25
Finished Feb 08 01:20:12 PM UTC 25
Peak memory 485148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075925605 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_all.2075925605
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_stress_rd.549907216
Short name T1006
Test name
Test status
Simulation time 745319897 ps
CPU time 32.38 seconds
Started Feb 08 01:18:34 PM UTC 25
Finished Feb 08 01:19:08 PM UTC 25
Peak memory 216236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549907216 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_rd.549907216
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_stress_wr.157555332
Short name T1739
Test name
Test status
Simulation time 54256571033 ps
CPU time 1419.52 seconds
Started Feb 08 01:18:32 PM UTC 25
Finished Feb 08 01:42:23 PM UTC 25
Peak memory 8679176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157555332 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_wr.157555332
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_stretch.2872006019
Short name T988
Test name
Test status
Simulation time 2283102395 ps
CPU time 12.95 seconds
Started Feb 08 01:18:35 PM UTC 25
Finished Feb 08 01:18:49 PM UTC 25
Peak memory 306704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872006019 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stretch.2872006019
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_timeout.1896116792
Short name T987
Test name
Test status
Simulation time 4644232382 ps
CPU time 8.53 seconds
Started Feb 08 01:18:39 PM UTC 25
Finished Feb 08 01:18:49 PM UTC 25
Peak memory 233228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896116792 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_timeout.1896116792
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_tx_stretch_ctrl.452801574
Short name T1000
Test name
Test status
Simulation time 267163303 ps
CPU time 6.55 seconds
Started Feb 08 01:18:54 PM UTC 25
Finished Feb 08 01:19:02 PM UTC 25
Peak memory 232312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452801574 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.452801574
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_alert_test.2237701577
Short name T1032
Test name
Test status
Simulation time 21812135 ps
CPU time 0.89 seconds
Started Feb 08 01:19:42 PM UTC 25
Finished Feb 08 01:19:44 PM UTC 25
Peak memory 214936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237701577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.2237701577
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_error_intr.689695333
Short name T1010
Test name
Test status
Simulation time 449064360 ps
CPU time 3.21 seconds
Started Feb 08 01:19:08 PM UTC 25
Finished Feb 08 01:19:13 PM UTC 25
Peak memory 232692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689695333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_host_error_intr.689695333
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_fmt_empty.47725363
Short name T1007
Test name
Test status
Simulation time 251953874 ps
CPU time 5.36 seconds
Started Feb 08 01:19:02 PM UTC 25
Finished Feb 08 01:19:09 PM UTC 25
Peak memory 259756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47725363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empty.47725363
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_full.3196384513
Short name T1081
Test name
Test status
Simulation time 13500608845 ps
CPU time 113.53 seconds
Started Feb 08 01:19:04 PM UTC 25
Finished Feb 08 01:21:00 PM UTC 25
Peak memory 665376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196384513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_host_fifo_full.3196384513
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_overflow.3461149831
Short name T1055
Test name
Test status
Simulation time 9682291655 ps
CPU time 85.81 seconds
Started Feb 08 01:19:02 PM UTC 25
Finished Feb 08 01:20:30 PM UTC 25
Peak memory 820704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461149831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_host_fifo_overflow.3461149831
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_fmt.1834944736
Short name T1004
Test name
Test status
Simulation time 93420510 ps
CPU time 1.45 seconds
Started Feb 08 01:19:02 PM UTC 25
Finished Feb 08 01:19:05 PM UTC 25
Peak memory 214440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834944736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fmt.1834944736
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_rx.3522378842
Short name T1009
Test name
Test status
Simulation time 1222963346 ps
CPU time 6.15 seconds
Started Feb 08 01:19:03 PM UTC 25
Finished Feb 08 01:19:11 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522378842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.3522378842
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_watermark.1383166428
Short name T117
Test name
Test status
Simulation time 10875150173 ps
CPU time 152.36 seconds
Started Feb 08 01:19:02 PM UTC 25
Finished Feb 08 01:21:37 PM UTC 25
Peak memory 1664776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383166428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 28.i2c_host_fifo_watermark.1383166428
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_may_nack.4033074672
Short name T1043
Test name
Test status
Simulation time 710122467 ps
CPU time 31.39 seconds
Started Feb 08 01:19:35 PM UTC 25
Finished Feb 08 01:20:08 PM UTC 25
Peak memory 215856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033074672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 28.i2c_host_may_nack.4033074672
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_mode_toggle.2636148060
Short name T1021
Test name
Test status
Simulation time 216833100 ps
CPU time 2.25 seconds
Started Feb 08 01:19:34 PM UTC 25
Finished Feb 08 01:19:37 PM UTC 25
Peak memory 227876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636148060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_t
oggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_host_mode_toggle.2636148060
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_override.139527725
Short name T1003
Test name
Test status
Simulation time 34949783 ps
CPU time 0.99 seconds
Started Feb 08 01:19:01 PM UTC 25
Finished Feb 08 01:19:03 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139527725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overrid
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 28.i2c_host_override.139527725
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_perf.2038141027
Short name T1027
Test name
Test status
Simulation time 6704812079 ps
CPU time 35.1 seconds
Started Feb 08 01:19:04 PM UTC 25
Finished Feb 08 01:19:41 PM UTC 25
Peak memory 526056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038141027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_host_perf.2038141027
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_perf_precise.4167964629
Short name T1005
Test name
Test status
Simulation time 219924554 ps
CPU time 1.43 seconds
Started Feb 08 01:19:04 PM UTC 25
Finished Feb 08 01:19:07 PM UTC 25
Peak memory 213840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167964629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_host_perf_precise.4167964629
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_smoke.2677811035
Short name T1018
Test name
Test status
Simulation time 1356890229 ps
CPU time 32.46 seconds
Started Feb 08 01:18:59 PM UTC 25
Finished Feb 08 01:19:34 PM UTC 25
Peak memory 429516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677811035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_host_smoke.2677811035
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_stress_all.809358623
Short name T282
Test name
Test status
Simulation time 47638623011 ps
CPU time 2524.88 seconds
Started Feb 08 01:19:08 PM UTC 25
Finished Feb 08 02:01:36 PM UTC 25
Peak memory 3595788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809358623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_host_stress_all.809358623
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_stretch_timeout.1067127013
Short name T1020
Test name
Test status
Simulation time 590046410 ps
CPU time 28.3 seconds
Started Feb 08 01:19:06 PM UTC 25
Finished Feb 08 01:19:36 PM UTC 25
Peak memory 226160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067127013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.i2c_host_stretch_timeout.1067127013
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_bad_addr.2858254606
Short name T1023
Test name
Test status
Simulation time 912341243 ps
CPU time 6.1 seconds
Started Feb 08 01:19:31 PM UTC 25
Finished Feb 08 01:19:38 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2858254606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.2858254606
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_acq.4115138454
Short name T1015
Test name
Test status
Simulation time 248466164 ps
CPU time 1.21 seconds
Started Feb 08 01:19:27 PM UTC 25
Finished Feb 08 01:19:29 PM UTC 25
Peak memory 213928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115138454 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_acq.4115138454
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_tx.1683720440
Short name T294
Test name
Test status
Simulation time 282289307 ps
CPU time 2.92 seconds
Started Feb 08 01:19:28 PM UTC 25
Finished Feb 08 01:19:33 PM UTC 25
Peak memory 226212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683720440 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_tx.1683720440
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_acq.2005604466
Short name T1026
Test name
Test status
Simulation time 3430701837 ps
CPU time 3.82 seconds
Started Feb 08 01:19:36 PM UTC 25
Finished Feb 08 01:19:41 PM UTC 25
Peak memory 215988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005604466 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.2005604466
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_tx.1188813752
Short name T1025
Test name
Test status
Simulation time 65948734 ps
CPU time 1.26 seconds
Started Feb 08 01:19:37 PM UTC 25
Finished Feb 08 01:19:39 PM UTC 25
Peak memory 213928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188813752 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.1188813752
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_hrst.3326091071
Short name T1024
Test name
Test status
Simulation time 986909815 ps
CPU time 2.94 seconds
Started Feb 08 01:19:34 PM UTC 25
Finished Feb 08 01:19:38 PM UTC 25
Peak memory 226040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326091071 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_hrst.3326091071
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_intr_smoke.3200413385
Short name T1014
Test name
Test status
Simulation time 9305696102 ps
CPU time 9.88 seconds
Started Feb 08 01:19:15 PM UTC 25
Finished Feb 08 01:19:26 PM UTC 25
Peak memory 232960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200413385 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_smoke.3200413385
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_intr_stress_wr.1864802302
Short name T1151
Test name
Test status
Simulation time 14159450336 ps
CPU time 167.44 seconds
Started Feb 08 01:19:19 PM UTC 25
Finished Feb 08 01:22:09 PM UTC 25
Peak memory 1969928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18648
02302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.1864802302
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull.970636296
Short name T1031
Test name
Test status
Simulation time 3626664572 ps
CPU time 3.87 seconds
Started Feb 08 01:19:39 PM UTC 25
Finished Feb 08 01:19:44 PM UTC 25
Peak memory 226600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970636296 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_acqfull.970636296
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull_addr.1280961224
Short name T1033
Test name
Test status
Simulation time 1079313015 ps
CPU time 4.12 seconds
Started Feb 08 01:19:39 PM UTC 25
Finished Feb 08 01:19:45 PM UTC 25
Peak memory 216000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280961224 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_acqfull_addr.1280961224
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_nack_txstretch.2749264879
Short name T1030
Test name
Test status
Simulation time 315957944 ps
CPU time 2.07 seconds
Started Feb 08 01:19:40 PM UTC 25
Finished Feb 08 01:19:44 PM UTC 25
Peak memory 232972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749264879 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_txstretch.2749264879
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_perf.3695430229
Short name T1022
Test name
Test status
Simulation time 3256073208 ps
CPU time 7.68 seconds
Started Feb 08 01:19:28 PM UTC 25
Finished Feb 08 01:19:38 PM UTC 25
Peak memory 243152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695430229 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_perf.3695430229
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_smbus_maxlen.1248592407
Short name T1028
Test name
Test status
Simulation time 2381537692 ps
CPU time 3.29 seconds
Started Feb 08 01:19:38 PM UTC 25
Finished Feb 08 01:19:43 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248592407 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smbus_maxlen.1248592407
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_smoke.1234396395
Short name T1016
Test name
Test status
Simulation time 5668492912 ps
CPU time 19.12 seconds
Started Feb 08 01:19:09 PM UTC 25
Finished Feb 08 01:19:30 PM UTC 25
Peak memory 226272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234396395 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smoke.1234396395
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_stress_all.2556297964
Short name T1312
Test name
Test status
Simulation time 25379376376 ps
CPU time 401.66 seconds
Started Feb 08 01:19:31 PM UTC 25
Finished Feb 08 01:26:17 PM UTC 25
Peak memory 3341844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556297964 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_all.2556297964
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_stress_rd.3724888609
Short name T1013
Test name
Test status
Simulation time 800328088 ps
CPU time 10.36 seconds
Started Feb 08 01:19:11 PM UTC 25
Finished Feb 08 01:19:23 PM UTC 25
Peak memory 216032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724888609 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_rd.3724888609
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_stress_wr.752341892
Short name T1147
Test name
Test status
Simulation time 48345320853 ps
CPU time 172.16 seconds
Started Feb 08 01:19:10 PM UTC 25
Finished Feb 08 01:22:05 PM UTC 25
Peak memory 1906180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752341892 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_wr.752341892
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_timeout.1277918059
Short name T1019
Test name
Test status
Simulation time 5046774107 ps
CPU time 9.86 seconds
Started Feb 08 01:19:24 PM UTC 25
Finished Feb 08 01:19:35 PM UTC 25
Peak memory 233296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277918059 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_timeout.1277918059
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_target_tx_stretch_ctrl.3872419879
Short name T1029
Test name
Test status
Simulation time 139222577 ps
CPU time 3.75 seconds
Started Feb 08 01:19:38 PM UTC 25
Finished Feb 08 01:19:43 PM UTC 25
Peak memory 215864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872419879 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.3872419879
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_alert_test.1390214147
Short name T1063
Test name
Test status
Simulation time 44323751 ps
CPU time 0.87 seconds
Started Feb 08 01:20:34 PM UTC 25
Finished Feb 08 01:20:36 PM UTC 25
Peak memory 214936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390214147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1390214147
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_error_intr.1834938357
Short name T1039
Test name
Test status
Simulation time 157758330 ps
CPU time 3.06 seconds
Started Feb 08 01:19:52 PM UTC 25
Finished Feb 08 01:19:56 PM UTC 25
Peak memory 226268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834938357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_host_error_intr.1834938357
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_fmt_empty.3654229929
Short name T1041
Test name
Test status
Simulation time 244619335 ps
CPU time 14.51 seconds
Started Feb 08 01:19:46 PM UTC 25
Finished Feb 08 01:20:02 PM UTC 25
Peak memory 265872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654229929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empty.3654229929
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_full.3036055413
Short name T1141
Test name
Test status
Simulation time 3235801220 ps
CPU time 128.65 seconds
Started Feb 08 01:19:46 PM UTC 25
Finished Feb 08 01:21:57 PM UTC 25
Peak memory 730712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036055413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_host_fifo_full.3036055413
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_overflow.3172643145
Short name T1078
Test name
Test status
Simulation time 4602741100 ps
CPU time 71.51 seconds
Started Feb 08 01:19:45 PM UTC 25
Finished Feb 08 01:20:58 PM UTC 25
Peak memory 779860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172643145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_host_fifo_overflow.3172643145
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_fmt.1040992726
Short name T1036
Test name
Test status
Simulation time 119251959 ps
CPU time 1.28 seconds
Started Feb 08 01:19:46 PM UTC 25
Finished Feb 08 01:19:48 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040992726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fmt.1040992726
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_rx.3444155319
Short name T1037
Test name
Test status
Simulation time 164253667 ps
CPU time 4.41 seconds
Started Feb 08 01:19:46 PM UTC 25
Finished Feb 08 01:19:52 PM UTC 25
Peak memory 215908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444155319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.3444155319
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_watermark.715941223
Short name T116
Test name
Test status
Simulation time 34071573940 ps
CPU time 71.8 seconds
Started Feb 08 01:19:44 PM UTC 25
Finished Feb 08 01:20:57 PM UTC 25
Peak memory 910856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715941223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_wa
termark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_host_fifo_watermark.715941223
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_may_nack.2152550964
Short name T1066
Test name
Test status
Simulation time 977955628 ps
CPU time 10.84 seconds
Started Feb 08 01:20:26 PM UTC 25
Finished Feb 08 01:20:38 PM UTC 25
Peak memory 216112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152550964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 29.i2c_host_may_nack.2152550964
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_override.2534675203
Short name T1035
Test name
Test status
Simulation time 27704861 ps
CPU time 0.8 seconds
Started Feb 08 01:19:43 PM UTC 25
Finished Feb 08 01:19:45 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534675203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 29.i2c_host_override.2534675203
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_perf.3887403634
Short name T1080
Test name
Test status
Simulation time 12648639584 ps
CPU time 71.16 seconds
Started Feb 08 01:19:46 PM UTC 25
Finished Feb 08 01:20:59 PM UTC 25
Peak memory 215980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887403634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_host_perf.3887403634
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_perf_precise.2471178707
Short name T1038
Test name
Test status
Simulation time 167547665 ps
CPU time 3.73 seconds
Started Feb 08 01:19:47 PM UTC 25
Finished Feb 08 01:19:52 PM UTC 25
Peak memory 243336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471178707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_host_perf_precise.2471178707
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_smoke.3807774926
Short name T1072
Test name
Test status
Simulation time 1234269427 ps
CPU time 61.86 seconds
Started Feb 08 01:19:42 PM UTC 25
Finished Feb 08 01:20:46 PM UTC 25
Peak memory 380464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807774926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_host_smoke.3807774926
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_host_stretch_timeout.2479692589
Short name T1042
Test name
Test status
Simulation time 2789527577 ps
CPU time 12.43 seconds
Started Feb 08 01:19:49 PM UTC 25
Finished Feb 08 01:20:03 PM UTC 25
Peak memory 232704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479692589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.i2c_host_stretch_timeout.2479692589
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_bad_addr.2341103868
Short name T1053
Test name
Test status
Simulation time 3833194549 ps
CPU time 7.8 seconds
Started Feb 08 01:20:20 PM UTC 25
Finished Feb 08 01:20:29 PM UTC 25
Peak memory 232900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2341103868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.2341103868
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_acq.2600728805
Short name T1048
Test name
Test status
Simulation time 245427411 ps
CPU time 1.15 seconds
Started Feb 08 01:20:17 PM UTC 25
Finished Feb 08 01:20:19 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600728805 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_acq.2600728805
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_tx.361368355
Short name T1049
Test name
Test status
Simulation time 306424558 ps
CPU time 1.41 seconds
Started Feb 08 01:20:18 PM UTC 25
Finished Feb 08 01:20:21 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361368355 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_tx.361368355
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_acq.2668666024
Short name T1054
Test name
Test status
Simulation time 314075869 ps
CPU time 2.67 seconds
Started Feb 08 01:20:26 PM UTC 25
Finished Feb 08 01:20:29 PM UTC 25
Peak memory 215644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668666024 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.2668666024
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_tx.702178307
Short name T1058
Test name
Test status
Simulation time 147305275 ps
CPU time 2.1 seconds
Started Feb 08 01:20:30 PM UTC 25
Finished Feb 08 01:20:33 PM UTC 25
Peak memory 215716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702178307 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.702178307
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_intr_smoke.2919940951
Short name T982
Test name
Test status
Simulation time 1654721000 ps
CPU time 7.27 seconds
Started Feb 08 01:20:09 PM UTC 25
Finished Feb 08 01:20:17 PM UTC 25
Peak memory 228144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919940951 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_smoke.2919940951
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_intr_stress_wr.3620507663
Short name T1047
Test name
Test status
Simulation time 9249750144 ps
CPU time 5.73 seconds
Started Feb 08 01:20:12 PM UTC 25
Finished Feb 08 01:20:19 PM UTC 25
Peak memory 215980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36205
07663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.3620507663
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull.2330472260
Short name T1059
Test name
Test status
Simulation time 952486893 ps
CPU time 2.98 seconds
Started Feb 08 01:20:31 PM UTC 25
Finished Feb 08 01:20:35 PM UTC 25
Peak memory 226072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330472260 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_acqfull.2330472260
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull_addr.2362684324
Short name T1064
Test name
Test status
Simulation time 620875991 ps
CPU time 4.3 seconds
Started Feb 08 01:20:32 PM UTC 25
Finished Feb 08 01:20:37 PM UTC 25
Peak memory 216056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362684324 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_acqfull_addr.2362684324
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_nack_txstretch.413567103
Short name T1065
Test name
Test status
Simulation time 132034936 ps
CPU time 2.32 seconds
Started Feb 08 01:20:34 PM UTC 25
Finished Feb 08 01:20:38 PM UTC 25
Peak memory 232896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413567103 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_txstretch.413567103
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_perf.3818973012
Short name T1050
Test name
Test status
Simulation time 1893387348 ps
CPU time 5.95 seconds
Started Feb 08 01:20:18 PM UTC 25
Finished Feb 08 01:20:25 PM UTC 25
Peak memory 232960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818973012 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_perf.3818973012
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_smbus_maxlen.298523223
Short name T1060
Test name
Test status
Simulation time 1861260969 ps
CPU time 3.26 seconds
Started Feb 08 01:20:31 PM UTC 25
Finished Feb 08 01:20:35 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298523223 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smbus_maxlen.298523223
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_smoke.2343415982
Short name T1044
Test name
Test status
Simulation time 7080859238 ps
CPU time 12.19 seconds
Started Feb 08 01:19:57 PM UTC 25
Finished Feb 08 01:20:11 PM UTC 25
Peak memory 226144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343415982 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smoke.2343415982
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_stress_rd.413006451
Short name T1046
Test name
Test status
Simulation time 1695445607 ps
CPU time 9.85 seconds
Started Feb 08 01:20:02 PM UTC 25
Finished Feb 08 01:20:13 PM UTC 25
Peak memory 215916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413006451 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_rd.413006451
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_stress_wr.329982946
Short name T1244
Test name
Test status
Simulation time 56711140279 ps
CPU time 280.29 seconds
Started Feb 08 01:20:00 PM UTC 25
Finished Feb 08 01:24:44 PM UTC 25
Peak memory 2475524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329982946 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_wr.329982946
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_stretch.1649900990
Short name T1057
Test name
Test status
Simulation time 3331757214 ps
CPU time 28.15 seconds
Started Feb 08 01:20:03 PM UTC 25
Finished Feb 08 01:20:33 PM UTC 25
Peak memory 589384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649900990 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stretch.1649900990
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_timeout.2721509718
Short name T1051
Test name
Test status
Simulation time 5377633515 ps
CPU time 11.17 seconds
Started Feb 08 01:20:13 PM UTC 25
Finished Feb 08 01:20:25 PM UTC 25
Peak memory 232424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721509718 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_timeout.2721509718
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/29.i2c_target_tx_stretch_ctrl.984274837
Short name T1062
Test name
Test status
Simulation time 142429278 ps
CPU time 4.8 seconds
Started Feb 08 01:20:30 PM UTC 25
Finished Feb 08 01:20:36 PM UTC 25
Peak memory 215916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984274837 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.984274837
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_alert_test.3390295583
Short name T320
Test name
Test status
Simulation time 62373105 ps
CPU time 0.82 seconds
Started Feb 08 12:57:59 PM UTC 25
Finished Feb 08 12:58:01 PM UTC 25
Peak memory 214992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390295583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.3390295583
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_host_error_intr.266648960
Short name T21
Test name
Test status
Simulation time 261453611 ps
CPU time 12 seconds
Started Feb 08 12:57:33 PM UTC 25
Finished Feb 08 12:57:46 PM UTC 25
Peak memory 249412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266648960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_host_error_intr.266648960
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_fmt_empty.1985899801
Short name T307
Test name
Test status
Simulation time 1301402313 ps
CPU time 6.45 seconds
Started Feb 08 12:57:28 PM UTC 25
Finished Feb 08 12:57:36 PM UTC 25
Peak memory 284160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985899801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty.1985899801
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_full.3437981341
Short name T42
Test name
Test status
Simulation time 7928485824 ps
CPU time 58.46 seconds
Started Feb 08 12:57:30 PM UTC 25
Finished Feb 08 12:58:30 PM UTC 25
Peak memory 423680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437981341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_host_fifo_full.3437981341
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_overflow.1867604653
Short name T170
Test name
Test status
Simulation time 2049415856 ps
CPU time 120.04 seconds
Started Feb 08 12:57:27 PM UTC 25
Finished Feb 08 12:59:30 PM UTC 25
Peak memory 663000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867604653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_host_fifo_overflow.1867604653
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_fmt.3019357144
Short name T305
Test name
Test status
Simulation time 176427069 ps
CPU time 1.59 seconds
Started Feb 08 12:57:28 PM UTC 25
Finished Feb 08 12:57:31 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019357144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt.3019357144
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_rx.3476039383
Short name T158
Test name
Test status
Simulation time 201270363 ps
CPU time 12.45 seconds
Started Feb 08 12:57:28 PM UTC 25
Finished Feb 08 12:57:43 PM UTC 25
Peak memory 253436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476039383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.3476039383
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_watermark.1989201905
Short name T83
Test name
Test status
Simulation time 12236222412 ps
CPU time 66.24 seconds
Started Feb 08 12:57:27 PM UTC 25
Finished Feb 08 12:58:35 PM UTC 25
Peak memory 927440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989201905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.i2c_host_fifo_watermark.1989201905
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_host_override.2442490792
Short name T291
Test name
Test status
Simulation time 19353955 ps
CPU time 0.93 seconds
Started Feb 08 12:57:27 PM UTC 25
Finished Feb 08 12:57:29 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442490792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 3.i2c_host_override.2442490792
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_host_perf.4111447211
Short name T161
Test name
Test status
Simulation time 26297820894 ps
CPU time 66.1 seconds
Started Feb 08 12:57:31 PM UTC 25
Finished Feb 08 12:58:39 PM UTC 25
Peak memory 215980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111447211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_host_perf.4111447211
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_host_perf_precise.3366399932
Short name T306
Test name
Test status
Simulation time 239736643 ps
CPU time 4.18 seconds
Started Feb 08 12:57:31 PM UTC 25
Finished Feb 08 12:57:36 PM UTC 25
Peak memory 215860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366399932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_host_perf_precise.3366399932
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_host_smoke.3512719383
Short name T35
Test name
Test status
Simulation time 3685598905 ps
CPU time 32.93 seconds
Started Feb 08 12:57:27 PM UTC 25
Finished Feb 08 12:58:02 PM UTC 25
Peak memory 379892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512719383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_host_smoke.3512719383
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_host_stretch_timeout.1832644967
Short name T263
Test name
Test status
Simulation time 2827132136 ps
CPU time 30.52 seconds
Started Feb 08 12:57:31 PM UTC 25
Finished Feb 08 12:58:03 PM UTC 25
Peak memory 243516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832644967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.i2c_host_stretch_timeout.1832644967
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_sec_cm.821838571
Short name T187
Test name
Test status
Simulation time 114616799 ps
CPU time 1.3 seconds
Started Feb 08 12:57:59 PM UTC 25
Finished Feb 08 12:58:02 PM UTC 25
Peak memory 246208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821838571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_
TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.821838571
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_bad_addr.1042484157
Short name T314
Test name
Test status
Simulation time 1167209116 ps
CPU time 6.62 seconds
Started Feb 08 12:57:47 PM UTC 25
Finished Feb 08 12:57:55 PM UTC 25
Peak memory 232976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1042484157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.1042484157
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_acq.1029532860
Short name T239
Test name
Test status
Simulation time 254429325 ps
CPU time 1.65 seconds
Started Feb 08 12:57:44 PM UTC 25
Finished Feb 08 12:57:47 PM UTC 25
Peak memory 213908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029532860 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_acq.1029532860
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_tx.2270849120
Short name T308
Test name
Test status
Simulation time 954029678 ps
CPU time 1.8 seconds
Started Feb 08 12:57:44 PM UTC 25
Finished Feb 08 12:57:47 PM UTC 25
Peak memory 216148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270849120 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_tx.2270849120
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_acq.505637618
Short name T318
Test name
Test status
Simulation time 555331812 ps
CPU time 4.32 seconds
Started Feb 08 12:57:53 PM UTC 25
Finished Feb 08 12:57:58 PM UTC 25
Peak memory 216116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505637618 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.505637618
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_tx.3809984263
Short name T315
Test name
Test status
Simulation time 461466348 ps
CPU time 1.49 seconds
Started Feb 08 12:57:53 PM UTC 25
Finished Feb 08 12:57:56 PM UTC 25
Peak memory 214532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809984263 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.3809984263
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_intr_smoke.3525722511
Short name T309
Test name
Test status
Simulation time 15944662006 ps
CPU time 8.09 seconds
Started Feb 08 12:57:39 PM UTC 25
Finished Feb 08 12:57:49 PM UTC 25
Peak memory 226280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525722511 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_smoke.3525722511
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_intr_stress_wr.2732233228
Short name T126
Test name
Test status
Simulation time 14049713456 ps
CPU time 32.03 seconds
Started Feb 08 12:57:41 PM UTC 25
Finished Feb 08 12:58:15 PM UTC 25
Peak memory 930972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27322
33228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.2732233228
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull.400285609
Short name T159
Test name
Test status
Simulation time 576760035 ps
CPU time 3.41 seconds
Started Feb 08 12:57:56 PM UTC 25
Finished Feb 08 12:58:01 PM UTC 25
Peak memory 226168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400285609 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_acqfull.400285609
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_nack_txstretch.91466701
Short name T62
Test name
Test status
Simulation time 149083321 ps
CPU time 2.25 seconds
Started Feb 08 12:57:57 PM UTC 25
Finished Feb 08 12:58:01 PM UTC 25
Peak memory 232892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91466701 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_txstretch.91466701
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_perf.4198144428
Short name T317
Test name
Test status
Simulation time 4469056153 ps
CPU time 10.93 seconds
Started Feb 08 12:57:46 PM UTC 25
Finished Feb 08 12:57:58 PM UTC 25
Peak memory 233012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198144428 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_perf.4198144428
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_smbus_maxlen.2758319802
Short name T319
Test name
Test status
Simulation time 438584396 ps
CPU time 3.3 seconds
Started Feb 08 12:57:54 PM UTC 25
Finished Feb 08 12:57:59 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758319802 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smbus_maxlen.2758319802
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_smoke.4004809914
Short name T121
Test name
Test status
Simulation time 822799237 ps
CPU time 29.27 seconds
Started Feb 08 12:57:37 PM UTC 25
Finished Feb 08 12:58:08 PM UTC 25
Peak memory 226468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004809914 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smoke.4004809914
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_stress_all.1041283840
Short name T59
Test name
Test status
Simulation time 36270926946 ps
CPU time 69.5 seconds
Started Feb 08 12:57:47 PM UTC 25
Finished Feb 08 12:58:58 PM UTC 25
Peak memory 982552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041283840 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_all.1041283840
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_stress_rd.3456476775
Short name T331
Test name
Test status
Simulation time 1026486737 ps
CPU time 54.47 seconds
Started Feb 08 12:57:37 PM UTC 25
Finished Feb 08 12:58:34 PM UTC 25
Peak memory 226136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456476775 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_rd.3456476775
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_stress_wr.779881516
Short name T311
Test name
Test status
Simulation time 6677769923 ps
CPU time 13.41 seconds
Started Feb 08 12:57:37 PM UTC 25
Finished Feb 08 12:57:52 PM UTC 25
Peak memory 215700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779881516 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_wr.779881516
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_stretch.3485570849
Short name T310
Test name
Test status
Simulation time 2961369973 ps
CPU time 11.22 seconds
Started Feb 08 12:57:38 PM UTC 25
Finished Feb 08 12:57:51 PM UTC 25
Peak memory 351792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485570849 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stretch.3485570849
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_timeout.754279462
Short name T312
Test name
Test status
Simulation time 1161839940 ps
CPU time 9.86 seconds
Started Feb 08 12:57:41 PM UTC 25
Finished Feb 08 12:57:53 PM UTC 25
Peak memory 242716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754279462 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_timeout.754279462
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/3.i2c_target_tx_stretch_ctrl.670356265
Short name T316
Test name
Test status
Simulation time 39572485 ps
CPU time 1.46 seconds
Started Feb 08 12:57:54 PM UTC 25
Finished Feb 08 12:57:57 PM UTC 25
Peak memory 214344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670356265 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.670356265
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_alert_test.3566316461
Short name T1099
Test name
Test status
Simulation time 22784426 ps
CPU time 0.97 seconds
Started Feb 08 01:21:14 PM UTC 25
Finished Feb 08 01:21:16 PM UTC 25
Peak memory 214936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566316461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.3566316461
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_error_intr.2383967541
Short name T1075
Test name
Test status
Simulation time 107495622 ps
CPU time 2.6 seconds
Started Feb 08 01:20:46 PM UTC 25
Finished Feb 08 01:20:50 PM UTC 25
Peak memory 226232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383967541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_host_error_intr.2383967541
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_fmt_empty.1307481464
Short name T1073
Test name
Test status
Simulation time 310088568 ps
CPU time 7.51 seconds
Started Feb 08 01:20:38 PM UTC 25
Finished Feb 08 01:20:47 PM UTC 25
Peak memory 275928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307481464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empty.1307481464
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_full.2115564754
Short name T1116
Test name
Test status
Simulation time 12997274866 ps
CPU time 51.77 seconds
Started Feb 08 01:20:39 PM UTC 25
Finished Feb 08 01:21:32 PM UTC 25
Peak memory 574996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115564754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_host_fifo_full.2115564754
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_overflow.891871362
Short name T1200
Test name
Test status
Simulation time 17347532313 ps
CPU time 155.51 seconds
Started Feb 08 01:20:37 PM UTC 25
Finished Feb 08 01:23:15 PM UTC 25
Peak memory 749132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891871362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_host_fifo_overflow.891871362
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_fmt.455664953
Short name T1068
Test name
Test status
Simulation time 314292862 ps
CPU time 1.51 seconds
Started Feb 08 01:20:37 PM UTC 25
Finished Feb 08 01:20:40 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455664953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fmt.455664953
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_rx.1533902538
Short name T1070
Test name
Test status
Simulation time 515320189 ps
CPU time 5.08 seconds
Started Feb 08 01:20:39 PM UTC 25
Finished Feb 08 01:20:45 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533902538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.1533902538
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_watermark.3946834357
Short name T118
Test name
Test status
Simulation time 4059266849 ps
CPU time 96.69 seconds
Started Feb 08 01:20:36 PM UTC 25
Finished Feb 08 01:22:15 PM UTC 25
Peak memory 1232400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946834357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 30.i2c_host_fifo_watermark.3946834357
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_may_nack.3505694010
Short name T1097
Test name
Test status
Simulation time 1325000372 ps
CPU time 7.41 seconds
Started Feb 08 01:21:07 PM UTC 25
Finished Feb 08 01:21:16 PM UTC 25
Peak memory 215972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505694010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 30.i2c_host_may_nack.3505694010
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_override.3884405756
Short name T1067
Test name
Test status
Simulation time 81700529 ps
CPU time 0.93 seconds
Started Feb 08 01:20:36 PM UTC 25
Finished Feb 08 01:20:38 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884405756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 30.i2c_host_override.3884405756
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_perf.3040481630
Short name T1718
Test name
Test status
Simulation time 48136324208 ps
CPU time 1027.7 seconds
Started Feb 08 01:20:40 PM UTC 25
Finished Feb 08 01:37:57 PM UTC 25
Peak memory 2227788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040481630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_host_perf.3040481630
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_perf_precise.4003831911
Short name T1074
Test name
Test status
Simulation time 314825536 ps
CPU time 7.37 seconds
Started Feb 08 01:20:41 PM UTC 25
Finished Feb 08 01:20:49 PM UTC 25
Peak memory 265800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003831911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_host_perf_precise.4003831911
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_smoke.3237735066
Short name T1093
Test name
Test status
Simulation time 8762310024 ps
CPU time 35.6 seconds
Started Feb 08 01:20:36 PM UTC 25
Finished Feb 08 01:21:13 PM UTC 25
Peak memory 341568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237735066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_host_smoke.3237735066
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_stretch_timeout.684048901
Short name T1114
Test name
Test status
Simulation time 4322868251 ps
CPU time 44.14 seconds
Started Feb 08 01:20:45 PM UTC 25
Finished Feb 08 01:21:31 PM UTC 25
Peak memory 226288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684048901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch
_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 30.i2c_host_stretch_timeout.684048901
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_bad_addr.1404215835
Short name T1095
Test name
Test status
Simulation time 1245669088 ps
CPU time 9.38 seconds
Started Feb 08 01:21:04 PM UTC 25
Finished Feb 08 01:21:15 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1404215835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.1404215835
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_acq.532640332
Short name T1082
Test name
Test status
Simulation time 274983847 ps
CPU time 1.71 seconds
Started Feb 08 01:21:00 PM UTC 25
Finished Feb 08 01:21:03 PM UTC 25
Peak memory 213920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532640332 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_acq.532640332
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_tx.2716942163
Short name T1083
Test name
Test status
Simulation time 217303250 ps
CPU time 2.66 seconds
Started Feb 08 01:21:00 PM UTC 25
Finished Feb 08 01:21:04 PM UTC 25
Peak memory 226220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716942163 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_tx.2716942163
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_acq.3697470650
Short name T1091
Test name
Test status
Simulation time 222014739 ps
CPU time 2.43 seconds
Started Feb 08 01:21:08 PM UTC 25
Finished Feb 08 01:21:12 PM UTC 25
Peak memory 215644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697470650 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.3697470650
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_tx.2419999689
Short name T1090
Test name
Test status
Simulation time 158924084 ps
CPU time 1.93 seconds
Started Feb 08 01:21:08 PM UTC 25
Finished Feb 08 01:21:11 PM UTC 25
Peak memory 214508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419999689 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.2419999689
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_hrst.3212190131
Short name T1088
Test name
Test status
Simulation time 2287170652 ps
CPU time 2.25 seconds
Started Feb 08 01:21:05 PM UTC 25
Finished Feb 08 01:21:08 PM UTC 25
Peak memory 233032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212190131 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_hrst.3212190131
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_intr_smoke.3298426471
Short name T1084
Test name
Test status
Simulation time 2993744096 ps
CPU time 7.52 seconds
Started Feb 08 01:20:55 PM UTC 25
Finished Feb 08 01:21:04 PM UTC 25
Peak memory 232380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298426471 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_smoke.3298426471
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_intr_stress_wr.661191798
Short name T1085
Test name
Test status
Simulation time 14537855829 ps
CPU time 9.54 seconds
Started Feb 08 01:20:55 PM UTC 25
Finished Feb 08 01:21:06 PM UTC 25
Peak memory 215932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66119
1798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.661191798
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull.1490838567
Short name T1102
Test name
Test status
Simulation time 1900198821 ps
CPU time 3.43 seconds
Started Feb 08 01:21:12 PM UTC 25
Finished Feb 08 01:21:17 PM UTC 25
Peak memory 225960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490838567 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_acqfull.1490838567
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull_addr.128288304
Short name T1103
Test name
Test status
Simulation time 1770545068 ps
CPU time 3.76 seconds
Started Feb 08 01:21:12 PM UTC 25
Finished Feb 08 01:21:17 PM UTC 25
Peak memory 215916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128288304 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_acqfull_addr.128288304
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_nack_txstretch.274822254
Short name T1100
Test name
Test status
Simulation time 296759275 ps
CPU time 2.38 seconds
Started Feb 08 01:21:13 PM UTC 25
Finished Feb 08 01:21:16 PM UTC 25
Peak memory 232900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274822254 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_txstretch.274822254
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_perf.1025229212
Short name T1087
Test name
Test status
Simulation time 530444073 ps
CPU time 5.61 seconds
Started Feb 08 01:21:01 PM UTC 25
Finished Feb 08 01:21:08 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025229212 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_perf.1025229212
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_smbus_maxlen.1915024596
Short name T1094
Test name
Test status
Simulation time 781336149 ps
CPU time 3.6 seconds
Started Feb 08 01:21:09 PM UTC 25
Finished Feb 08 01:21:14 PM UTC 25
Peak memory 215640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915024596 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smbus_maxlen.1915024596
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_smoke.2386489021
Short name T1106
Test name
Test status
Simulation time 4888486074 ps
CPU time 32.55 seconds
Started Feb 08 01:20:47 PM UTC 25
Finished Feb 08 01:21:21 PM UTC 25
Peak memory 228064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386489021 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smoke.2386489021
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_stress_all.1435902214
Short name T1311
Test name
Test status
Simulation time 67736012528 ps
CPU time 308.53 seconds
Started Feb 08 01:21:02 PM UTC 25
Finished Feb 08 01:26:14 PM UTC 25
Peak memory 2045508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435902214 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_all.1435902214
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_stress_rd.869327605
Short name T1079
Test name
Test status
Simulation time 691479901 ps
CPU time 7.02 seconds
Started Feb 08 01:20:50 PM UTC 25
Finished Feb 08 01:20:58 PM UTC 25
Peak memory 215656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869327605 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_rd.869327605
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_stress_wr.26137666
Short name T1098
Test name
Test status
Simulation time 10423873596 ps
CPU time 26.21 seconds
Started Feb 08 01:20:48 PM UTC 25
Finished Feb 08 01:21:16 PM UTC 25
Peak memory 215972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26137666 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_wr.26137666
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_stretch.1405327040
Short name T1076
Test name
Test status
Simulation time 528508680 ps
CPU time 2.69 seconds
Started Feb 08 01:20:50 PM UTC 25
Finished Feb 08 01:20:54 PM UTC 25
Peak memory 217760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405327040 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stretch.1405327040
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_timeout.1744848311
Short name T1089
Test name
Test status
Simulation time 2368150310 ps
CPU time 11.46 seconds
Started Feb 08 01:20:58 PM UTC 25
Finished Feb 08 01:21:11 PM UTC 25
Peak memory 233032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744848311 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_timeout.1744848311
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_target_tx_stretch_ctrl.4130509871
Short name T1092
Test name
Test status
Simulation time 86818347 ps
CPU time 2.77 seconds
Started Feb 08 01:21:08 PM UTC 25
Finished Feb 08 01:21:12 PM UTC 25
Peak memory 215856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130509871 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.4130509871
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_alert_test.1839345304
Short name T1123
Test name
Test status
Simulation time 38821817 ps
CPU time 0.83 seconds
Started Feb 08 01:21:41 PM UTC 25
Finished Feb 08 01:21:44 PM UTC 25
Peak memory 214936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839345304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.1839345304
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_error_intr.3510745966
Short name T1108
Test name
Test status
Simulation time 427952963 ps
CPU time 3.35 seconds
Started Feb 08 01:21:20 PM UTC 25
Finished Feb 08 01:21:25 PM UTC 25
Peak memory 226224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510745966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_host_error_intr.3510745966
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_fmt_empty.1144562312
Short name T1110
Test name
Test status
Simulation time 743768660 ps
CPU time 7.2 seconds
Started Feb 08 01:21:17 PM UTC 25
Finished Feb 08 01:21:26 PM UTC 25
Peak memory 294592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144562312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empty.1144562312
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_full.1961945099
Short name T1260
Test name
Test status
Simulation time 17105674965 ps
CPU time 221.28 seconds
Started Feb 08 01:21:17 PM UTC 25
Finished Feb 08 01:25:02 PM UTC 25
Peak memory 448280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961945099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_host_fifo_full.1961945099
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_overflow.513390572
Short name T1140
Test name
Test status
Simulation time 6335741592 ps
CPU time 38.45 seconds
Started Feb 08 01:21:16 PM UTC 25
Finished Feb 08 01:21:56 PM UTC 25
Peak memory 534276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513390572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_host_fifo_overflow.513390572
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_fmt.3093101123
Short name T1105
Test name
Test status
Simulation time 418475525 ps
CPU time 1.69 seconds
Started Feb 08 01:21:17 PM UTC 25
Finished Feb 08 01:21:20 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093101123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fmt.3093101123
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_rx.1250288914
Short name T1111
Test name
Test status
Simulation time 1169783751 ps
CPU time 8.68 seconds
Started Feb 08 01:21:17 PM UTC 25
Finished Feb 08 01:21:27 PM UTC 25
Peak memory 237056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250288914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.1250288914
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_watermark.3931456450
Short name T1332
Test name
Test status
Simulation time 17690205327 ps
CPU time 315.91 seconds
Started Feb 08 01:21:16 PM UTC 25
Finished Feb 08 01:26:36 PM UTC 25
Peak memory 1302080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931456450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 31.i2c_host_fifo_watermark.3931456450
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_may_nack.4128887369
Short name T1125
Test name
Test status
Simulation time 738482444 ps
CPU time 6.08 seconds
Started Feb 08 01:21:37 PM UTC 25
Finished Feb 08 01:21:44 PM UTC 25
Peak memory 215848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128887369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 31.i2c_host_may_nack.4128887369
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_override.2885236823
Short name T1101
Test name
Test status
Simulation time 26495432 ps
CPU time 0.92 seconds
Started Feb 08 01:21:15 PM UTC 25
Finished Feb 08 01:21:17 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885236823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 31.i2c_host_override.2885236823
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_perf.886781562
Short name T1112
Test name
Test status
Simulation time 142792046 ps
CPU time 8.63 seconds
Started Feb 08 01:21:18 PM UTC 25
Finished Feb 08 01:21:28 PM UTC 25
Peak memory 241104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886781562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_host_perf.886781562
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_perf_precise.1699657723
Short name T1107
Test name
Test status
Simulation time 482449681 ps
CPU time 4.39 seconds
Started Feb 08 01:21:18 PM UTC 25
Finished Feb 08 01:21:24 PM UTC 25
Peak memory 226352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699657723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_host_perf_precise.1699657723
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_smoke.707783963
Short name T1134
Test name
Test status
Simulation time 10139923701 ps
CPU time 33.89 seconds
Started Feb 08 01:21:14 PM UTC 25
Finished Feb 08 01:21:49 PM UTC 25
Peak memory 300560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707783963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_host_smoke.707783963
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_host_stretch_timeout.550422423
Short name T1136
Test name
Test status
Simulation time 3607763981 ps
CPU time 30.6 seconds
Started Feb 08 01:21:18 PM UTC 25
Finished Feb 08 01:21:50 PM UTC 25
Peak memory 232792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550422423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch
_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 31.i2c_host_stretch_timeout.550422423
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_bad_addr.166586071
Short name T1071
Test name
Test status
Simulation time 1242693057 ps
CPU time 5.85 seconds
Started Feb 08 01:21:33 PM UTC 25
Finished Feb 08 01:21:40 PM UTC 25
Peak memory 226464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=166586071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.166586071
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_acq.3934711552
Short name T1115
Test name
Test status
Simulation time 140125315 ps
CPU time 1.34 seconds
Started Feb 08 01:21:29 PM UTC 25
Finished Feb 08 01:21:32 PM UTC 25
Peak memory 214524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934711552 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_acq.3934711552
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_tx.686195740
Short name T1117
Test name
Test status
Simulation time 264905580 ps
CPU time 1.65 seconds
Started Feb 08 01:21:30 PM UTC 25
Finished Feb 08 01:21:33 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686195740 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_tx.686195740
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_acq.4032635890
Short name T1126
Test name
Test status
Simulation time 2307666512 ps
CPU time 5.11 seconds
Started Feb 08 01:21:38 PM UTC 25
Finished Feb 08 01:21:44 PM UTC 25
Peak memory 215916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032635890 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.4032635890
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_tx.2630352417
Short name T1086
Test name
Test status
Simulation time 89241976 ps
CPU time 1.41 seconds
Started Feb 08 01:21:38 PM UTC 25
Finished Feb 08 01:21:41 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630352417 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.2630352417
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_hrst.2166875255
Short name T1121
Test name
Test status
Simulation time 986162257 ps
CPU time 4.95 seconds
Started Feb 08 01:21:33 PM UTC 25
Finished Feb 08 01:21:39 PM UTC 25
Peak memory 232900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166875255 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_hrst.2166875255
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_intr_smoke.365468056
Short name T1120
Test name
Test status
Simulation time 1029863621 ps
CPU time 9.9 seconds
Started Feb 08 01:21:27 PM UTC 25
Finished Feb 08 01:21:38 PM UTC 25
Peak memory 232356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365468056 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_smoke.365468056
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_intr_stress_wr.3484827451
Short name T1124
Test name
Test status
Simulation time 7652671131 ps
CPU time 15.15 seconds
Started Feb 08 01:21:27 PM UTC 25
Finished Feb 08 01:21:44 PM UTC 25
Peak memory 503364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34848
27451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.3484827451
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull.3554732044
Short name T1131
Test name
Test status
Simulation time 2446868939 ps
CPU time 4.23 seconds
Started Feb 08 01:21:40 PM UTC 25
Finished Feb 08 01:21:46 PM UTC 25
Peak memory 226408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554732044 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_acqfull.3554732044
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull_addr.3764590233
Short name T1130
Test name
Test status
Simulation time 392878235 ps
CPU time 3.74 seconds
Started Feb 08 01:21:40 PM UTC 25
Finished Feb 08 01:21:45 PM UTC 25
Peak memory 215928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764590233 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_acqfull_addr.3764590233
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_nack_txstretch.1834027549
Short name T1127
Test name
Test status
Simulation time 145461351 ps
CPU time 2.16 seconds
Started Feb 08 01:21:41 PM UTC 25
Finished Feb 08 01:21:45 PM UTC 25
Peak memory 232848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834027549 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_txstretch.1834027549
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_perf.2409228063
Short name T1052
Test name
Test status
Simulation time 919978080 ps
CPU time 6.5 seconds
Started Feb 08 01:21:31 PM UTC 25
Finished Feb 08 01:21:39 PM UTC 25
Peak memory 232296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409228063 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_perf.2409228063
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_smbus_maxlen.744800734
Short name T1129
Test name
Test status
Simulation time 1719716704 ps
CPU time 3.72 seconds
Started Feb 08 01:21:40 PM UTC 25
Finished Feb 08 01:21:45 PM UTC 25
Peak memory 215636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744800734 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smbus_maxlen.744800734
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_smoke.882771984
Short name T1133
Test name
Test status
Simulation time 13640864549 ps
CPU time 26.04 seconds
Started Feb 08 01:21:21 PM UTC 25
Finished Feb 08 01:21:49 PM UTC 25
Peak memory 233028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882771984 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smoke.882771984
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_stress_all.692577397
Short name T1745
Test name
Test status
Simulation time 57394632294 ps
CPU time 1428.45 seconds
Started Feb 08 01:21:32 PM UTC 25
Finished Feb 08 01:45:34 PM UTC 25
Peak memory 6004308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692577397 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_all.692577397
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_stress_rd.1677376660
Short name T1166
Test name
Test status
Simulation time 5344453562 ps
CPU time 53.06 seconds
Started Feb 08 01:21:26 PM UTC 25
Finished Feb 08 01:22:21 PM UTC 25
Peak memory 228316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677376660 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_rd.1677376660
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_stress_wr.4156799943
Short name T1128
Test name
Test status
Simulation time 10947946775 ps
CPU time 19.15 seconds
Started Feb 08 01:21:25 PM UTC 25
Finished Feb 08 01:21:45 PM UTC 25
Peak memory 215976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156799943 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_wr.4156799943
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_stretch.2316512037
Short name T1118
Test name
Test status
Simulation time 2887497203 ps
CPU time 9.16 seconds
Started Feb 08 01:21:26 PM UTC 25
Finished Feb 08 01:21:36 PM UTC 25
Peak memory 294656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316512037 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stretch.2316512037
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_timeout.3162089646
Short name T1119
Test name
Test status
Simulation time 5547496648 ps
CPU time 8.86 seconds
Started Feb 08 01:21:27 PM UTC 25
Finished Feb 08 01:21:37 PM UTC 25
Peak memory 232420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162089646 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_timeout.3162089646
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_tx_stretch_ctrl.2762081565
Short name T1122
Test name
Test status
Simulation time 74268918 ps
CPU time 2.89 seconds
Started Feb 08 01:21:39 PM UTC 25
Finished Feb 08 01:21:43 PM UTC 25
Peak memory 215928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762081565 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.2762081565
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_alert_test.1754594924
Short name T1158
Test name
Test status
Simulation time 44745913 ps
CPU time 0.93 seconds
Started Feb 08 01:22:11 PM UTC 25
Finished Feb 08 01:22:13 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754594924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.1754594924
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_error_intr.2211270391
Short name T1139
Test name
Test status
Simulation time 243671819 ps
CPU time 2.9 seconds
Started Feb 08 01:21:49 PM UTC 25
Finished Feb 08 01:21:53 PM UTC 25
Peak memory 230424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211270391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_host_error_intr.2211270391
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_fmt_empty.2281139307
Short name T1137
Test name
Test status
Simulation time 536715375 ps
CPU time 5.67 seconds
Started Feb 08 01:21:46 PM UTC 25
Finished Feb 08 01:21:53 PM UTC 25
Peak memory 267652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281139307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empty.2281139307
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_full.3594535885
Short name T1193
Test name
Test status
Simulation time 8006244361 ps
CPU time 72.49 seconds
Started Feb 08 01:21:46 PM UTC 25
Finished Feb 08 01:23:00 PM UTC 25
Peak memory 554500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594535885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_host_fifo_full.3594535885
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_overflow.993220200
Short name T1174
Test name
Test status
Simulation time 1870033082 ps
CPU time 55.64 seconds
Started Feb 08 01:21:46 PM UTC 25
Finished Feb 08 01:22:43 PM UTC 25
Peak memory 511488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993220200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_host_fifo_overflow.993220200
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_rx.215341615
Short name T1138
Test name
Test status
Simulation time 769365625 ps
CPU time 5.77 seconds
Started Feb 08 01:21:46 PM UTC 25
Finished Feb 08 01:21:53 PM UTC 25
Peak memory 215892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215341615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.215341615
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_watermark.279790485
Short name T1269
Test name
Test status
Simulation time 5426911289 ps
CPU time 211.18 seconds
Started Feb 08 01:21:44 PM UTC 25
Finished Feb 08 01:25:19 PM UTC 25
Peak memory 1058260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279790485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_wa
termark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_host_fifo_watermark.279790485
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_may_nack.4263178765
Short name T1171
Test name
Test status
Simulation time 1231621479 ps
CPU time 23.3 seconds
Started Feb 08 01:22:06 PM UTC 25
Finished Feb 08 01:22:31 PM UTC 25
Peak memory 215920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263178765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 32.i2c_host_may_nack.4263178765
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_mode_toggle.3433904834
Short name T1152
Test name
Test status
Simulation time 223495762 ps
CPU time 1.5 seconds
Started Feb 08 01:22:06 PM UTC 25
Finished Feb 08 01:22:09 PM UTC 25
Peak memory 226144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433904834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_t
oggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_host_mode_toggle.3433904834
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_override.3036817958
Short name T1132
Test name
Test status
Simulation time 21015624 ps
CPU time 0.88 seconds
Started Feb 08 01:21:44 PM UTC 25
Finished Feb 08 01:21:46 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036817958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 32.i2c_host_override.3036817958
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_perf.1741667890
Short name T1511
Test name
Test status
Simulation time 51206328611 ps
CPU time 563.55 seconds
Started Feb 08 01:21:47 PM UTC 25
Finished Feb 08 01:31:17 PM UTC 25
Peak memory 955912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741667890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_host_perf.1741667890
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_perf_precise.4171113895
Short name T1135
Test name
Test status
Simulation time 55772803 ps
CPU time 1.65 seconds
Started Feb 08 01:21:47 PM UTC 25
Finished Feb 08 01:21:50 PM UTC 25
Peak memory 213860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171113895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_host_perf_precise.4171113895
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_smoke.3097098254
Short name T1165
Test name
Test status
Simulation time 8561205880 ps
CPU time 32.49 seconds
Started Feb 08 01:21:44 PM UTC 25
Finished Feb 08 01:22:18 PM UTC 25
Peak memory 380344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097098254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_host_smoke.3097098254
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_host_stretch_timeout.1361083992
Short name T1145
Test name
Test status
Simulation time 619386707 ps
CPU time 12.61 seconds
Started Feb 08 01:21:47 PM UTC 25
Finished Feb 08 01:22:01 PM UTC 25
Peak memory 232964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361083992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.i2c_host_stretch_timeout.1361083992
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_bad_addr.3712231025
Short name T1154
Test name
Test status
Simulation time 933780207 ps
CPU time 6.37 seconds
Started Feb 08 01:22:02 PM UTC 25
Finished Feb 08 01:22:10 PM UTC 25
Peak memory 230564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3712231025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.3712231025
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_acq.785142173
Short name T1144
Test name
Test status
Simulation time 163085095 ps
CPU time 1.77 seconds
Started Feb 08 01:21:58 PM UTC 25
Finished Feb 08 01:22:01 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785142173 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_acq.785142173
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_tx.1689478203
Short name T1146
Test name
Test status
Simulation time 187937512 ps
CPU time 1.3 seconds
Started Feb 08 01:22:01 PM UTC 25
Finished Feb 08 01:22:03 PM UTC 25
Peak memory 213920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689478203 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_tx.1689478203
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_acq.2088838963
Short name T1157
Test name
Test status
Simulation time 414232271 ps
CPU time 3.37 seconds
Started Feb 08 01:22:07 PM UTC 25
Finished Feb 08 01:22:12 PM UTC 25
Peak memory 215776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088838963 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.2088838963
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_tx.1308052916
Short name T1155
Test name
Test status
Simulation time 83559205 ps
CPU time 1.52 seconds
Started Feb 08 01:22:07 PM UTC 25
Finished Feb 08 01:22:10 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308052916 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.1308052916
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_hrst.2164969450
Short name T1153
Test name
Test status
Simulation time 2819659777 ps
CPU time 4.07 seconds
Started Feb 08 01:22:04 PM UTC 25
Finished Feb 08 01:22:09 PM UTC 25
Peak memory 226492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164969450 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_hrst.2164969450
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_intr_smoke.1907271909
Short name T1150
Test name
Test status
Simulation time 1432189136 ps
CPU time 11.91 seconds
Started Feb 08 01:21:54 PM UTC 25
Finished Feb 08 01:22:07 PM UTC 25
Peak memory 226168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907271909 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_smoke.1907271909
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_intr_stress_wr.3394417912
Short name T1172
Test name
Test status
Simulation time 22726991624 ps
CPU time 41.15 seconds
Started Feb 08 01:21:55 PM UTC 25
Finished Feb 08 01:22:37 PM UTC 25
Peak memory 519676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33944
17912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.3394417912
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull.3561414375
Short name T1162
Test name
Test status
Simulation time 569922542 ps
CPU time 4.15 seconds
Started Feb 08 01:22:10 PM UTC 25
Finished Feb 08 01:22:15 PM UTC 25
Peak memory 226220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561414375 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_acqfull.3561414375
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull_addr.1565643233
Short name T1163
Test name
Test status
Simulation time 1099681667 ps
CPU time 4.13 seconds
Started Feb 08 01:22:10 PM UTC 25
Finished Feb 08 01:22:15 PM UTC 25
Peak memory 216184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565643233 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_acqfull_addr.1565643233
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_nack_txstretch.3238656561
Short name T1160
Test name
Test status
Simulation time 142166615 ps
CPU time 2.05 seconds
Started Feb 08 01:22:11 PM UTC 25
Finished Feb 08 01:22:14 PM UTC 25
Peak memory 232936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238656561 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_txstretch.3238656561
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_perf.3354929760
Short name T1149
Test name
Test status
Simulation time 505994327 ps
CPU time 4.37 seconds
Started Feb 08 01:22:01 PM UTC 25
Finished Feb 08 01:22:07 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354929760 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_perf.3354929760
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_smbus_maxlen.1672991881
Short name T1161
Test name
Test status
Simulation time 567795932 ps
CPU time 3.71 seconds
Started Feb 08 01:22:10 PM UTC 25
Finished Feb 08 01:22:15 PM UTC 25
Peak memory 215640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672991881 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smbus_maxlen.1672991881
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_smoke.457739203
Short name T1143
Test name
Test status
Simulation time 1148012324 ps
CPU time 8.14 seconds
Started Feb 08 01:21:50 PM UTC 25
Finished Feb 08 01:22:00 PM UTC 25
Peak memory 233108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457739203 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smoke.457739203
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_stress_all.3306780287
Short name T269
Test name
Test status
Simulation time 62432932215 ps
CPU time 251.15 seconds
Started Feb 08 01:22:02 PM UTC 25
Finished Feb 08 01:26:17 PM UTC 25
Peak memory 1881628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306780287 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_all.3306780287
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_stress_rd.4267901182
Short name T1156
Test name
Test status
Simulation time 781377825 ps
CPU time 19.08 seconds
Started Feb 08 01:21:51 PM UTC 25
Finished Feb 08 01:22:12 PM UTC 25
Peak memory 226464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267901182 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_rd.4267901182
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.2350854889
Short name T1229
Test name
Test status
Simulation time 28734060489 ps
CPU time 125.76 seconds
Started Feb 08 01:21:50 PM UTC 25
Finished Feb 08 01:23:58 PM UTC 25
Peak memory 1390344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350854889 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_wr.2350854889
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_stretch.2730981719
Short name T1142
Test name
Test status
Simulation time 1345691261 ps
CPU time 2.45 seconds
Started Feb 08 01:21:53 PM UTC 25
Finished Feb 08 01:21:57 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730981719 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stretch.2730981719
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_timeout.4174704457
Short name T1148
Test name
Test status
Simulation time 4332586126 ps
CPU time 7.72 seconds
Started Feb 08 01:21:57 PM UTC 25
Finished Feb 08 01:22:06 PM UTC 25
Peak memory 226224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174704457 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_timeout.4174704457
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/32.i2c_target_tx_stretch_ctrl.587242976
Short name T1159
Test name
Test status
Simulation time 246759008 ps
CPU time 3.44 seconds
Started Feb 08 01:22:09 PM UTC 25
Finished Feb 08 01:22:14 PM UTC 25
Peak memory 232568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587242976 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.587242976
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_alert_test.1580535003
Short name T1190
Test name
Test status
Simulation time 39999183 ps
CPU time 0.85 seconds
Started Feb 08 01:22:57 PM UTC 25
Finished Feb 08 01:22:59 PM UTC 25
Peak memory 214936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580535003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.1580535003
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_error_intr.3584995955
Short name T1168
Test name
Test status
Simulation time 940435764 ps
CPU time 3.95 seconds
Started Feb 08 01:22:19 PM UTC 25
Finished Feb 08 01:22:24 PM UTC 25
Peak memory 226536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584995955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_host_error_intr.3584995955
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_fmt_empty.3831415086
Short name T1173
Test name
Test status
Simulation time 473737731 ps
CPU time 23.75 seconds
Started Feb 08 01:22:16 PM UTC 25
Finished Feb 08 01:22:41 PM UTC 25
Peak memory 288256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831415086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empty.3831415086
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_full.56422023
Short name T1219
Test name
Test status
Simulation time 7713420386 ps
CPU time 90.28 seconds
Started Feb 08 01:22:17 PM UTC 25
Finished Feb 08 01:23:49 PM UTC 25
Peak memory 400612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56422023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ful
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 33.i2c_host_fifo_full.56422023
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_overflow.791344692
Short name T1210
Test name
Test status
Simulation time 2436744607 ps
CPU time 79.55 seconds
Started Feb 08 01:22:14 PM UTC 25
Finished Feb 08 01:23:36 PM UTC 25
Peak memory 816772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791344692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_host_fifo_overflow.791344692
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_fmt.1052808936
Short name T1164
Test name
Test status
Simulation time 605429259 ps
CPU time 1.48 seconds
Started Feb 08 01:22:15 PM UTC 25
Finished Feb 08 01:22:18 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052808936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fmt.1052808936
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_rx.1009662517
Short name T1169
Test name
Test status
Simulation time 148124812 ps
CPU time 9.12 seconds
Started Feb 08 01:22:16 PM UTC 25
Finished Feb 08 01:22:26 PM UTC 25
Peak memory 239248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009662517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.1009662517
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_watermark.2405906010
Short name T1243
Test name
Test status
Simulation time 4608386122 ps
CPU time 145.78 seconds
Started Feb 08 01:22:14 PM UTC 25
Finished Feb 08 01:24:43 PM UTC 25
Peak memory 1394176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405906010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 33.i2c_host_fifo_watermark.2405906010
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_may_nack.2998364527
Short name T1185
Test name
Test status
Simulation time 940223165 ps
CPU time 4.25 seconds
Started Feb 08 01:22:50 PM UTC 25
Finished Feb 08 01:22:56 PM UTC 25
Peak memory 215912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998364527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 33.i2c_host_may_nack.2998364527
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_override.3158648530
Short name T147
Test name
Test status
Simulation time 19633564 ps
CPU time 1.06 seconds
Started Feb 08 01:22:13 PM UTC 25
Finished Feb 08 01:22:16 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158648530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 33.i2c_host_override.3158648530
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_perf.111952589
Short name T1167
Test name
Test status
Simulation time 879631676 ps
CPU time 5.11 seconds
Started Feb 08 01:22:17 PM UTC 25
Finished Feb 08 01:22:23 PM UTC 25
Peak memory 242608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111952589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_host_perf.111952589
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_perf_precise.3210789532
Short name T1170
Test name
Test status
Simulation time 3364527258 ps
CPU time 12.4 seconds
Started Feb 08 01:22:17 PM UTC 25
Finished Feb 08 01:22:31 PM UTC 25
Peak memory 317136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210789532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_host_perf_precise.3210789532
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_smoke.1858068760
Short name T1181
Test name
Test status
Simulation time 2058167536 ps
CPU time 38.77 seconds
Started Feb 08 01:22:12 PM UTC 25
Finished Feb 08 01:22:53 PM UTC 25
Peak memory 417168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858068760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_host_smoke.1858068760
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_host_stretch_timeout.2294428336
Short name T1196
Test name
Test status
Simulation time 3890308312 ps
CPU time 42.56 seconds
Started Feb 08 01:22:19 PM UTC 25
Finished Feb 08 01:23:03 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294428336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.i2c_host_stretch_timeout.2294428336
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_bad_addr.2018446534
Short name T1182
Test name
Test status
Simulation time 2036318034 ps
CPU time 4.13 seconds
Started Feb 08 01:22:48 PM UTC 25
Finished Feb 08 01:22:53 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2018446534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.2018446534
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_acq.885642951
Short name T1178
Test name
Test status
Simulation time 1990142307 ps
CPU time 2.17 seconds
Started Feb 08 01:22:45 PM UTC 25
Finished Feb 08 01:22:48 PM UTC 25
Peak memory 215588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885642951 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_acq.885642951
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_tx.344460132
Short name T1176
Test name
Test status
Simulation time 200193309 ps
CPU time 1.28 seconds
Started Feb 08 01:22:45 PM UTC 25
Finished Feb 08 01:22:47 PM UTC 25
Peak memory 213476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344460132 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_tx.344460132
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_acq.4226186815
Short name T1184
Test name
Test status
Simulation time 4336421023 ps
CPU time 2.55 seconds
Started Feb 08 01:22:52 PM UTC 25
Finished Feb 08 01:22:55 PM UTC 25
Peak memory 215992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226186815 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.4226186815
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_tx.2668953718
Short name T1186
Test name
Test status
Simulation time 483846900 ps
CPU time 1.88 seconds
Started Feb 08 01:22:53 PM UTC 25
Finished Feb 08 01:22:56 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668953718 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.2668953718
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_hrst.2384623517
Short name T1179
Test name
Test status
Simulation time 220890824 ps
CPU time 2.38 seconds
Started Feb 08 01:22:48 PM UTC 25
Finished Feb 08 01:22:52 PM UTC 25
Peak memory 226264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384623517 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_hrst.2384623517
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_intr_smoke.3506853588
Short name T1175
Test name
Test status
Simulation time 1137282328 ps
CPU time 10.06 seconds
Started Feb 08 01:22:32 PM UTC 25
Finished Feb 08 01:22:44 PM UTC 25
Peak memory 233172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506853588 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_smoke.3506853588
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_intr_stress_wr.3341515815
Short name T1279
Test name
Test status
Simulation time 15729000835 ps
CPU time 169.83 seconds
Started Feb 08 01:22:38 PM UTC 25
Finished Feb 08 01:25:31 PM UTC 25
Peak memory 2023240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33415
15815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.3341515815
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull.3577522500
Short name T1188
Test name
Test status
Simulation time 1581221394 ps
CPU time 3.59 seconds
Started Feb 08 01:22:54 PM UTC 25
Finished Feb 08 01:22:59 PM UTC 25
Peak memory 226156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577522500 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_acqfull.3577522500
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull_addr.3371741167
Short name T1194
Test name
Test status
Simulation time 1805411756 ps
CPU time 3.91 seconds
Started Feb 08 01:22:56 PM UTC 25
Finished Feb 08 01:23:01 PM UTC 25
Peak memory 215996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371741167 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_acqfull_addr.3371741167
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_nack_txstretch.1884794430
Short name T1189
Test name
Test status
Simulation time 620538684 ps
CPU time 1.78 seconds
Started Feb 08 01:22:56 PM UTC 25
Finished Feb 08 01:22:59 PM UTC 25
Peak memory 231936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884794430 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_txstretch.1884794430
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_perf.733867772
Short name T1183
Test name
Test status
Simulation time 874161413 ps
CPU time 8.21 seconds
Started Feb 08 01:22:46 PM UTC 25
Finished Feb 08 01:22:55 PM UTC 25
Peak memory 232904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733867772 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_perf.733867772
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_smbus_maxlen.3454865015
Short name T1192
Test name
Test status
Simulation time 1024268185 ps
CPU time 4.48 seconds
Started Feb 08 01:22:54 PM UTC 25
Finished Feb 08 01:22:59 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454865015 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smbus_maxlen.3454865015
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_smoke.1200017220
Short name T86
Test name
Test status
Simulation time 4130631037 ps
CPU time 17.82 seconds
Started Feb 08 01:22:24 PM UTC 25
Finished Feb 08 01:22:43 PM UTC 25
Peak memory 226332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200017220 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smoke.1200017220
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_stress_all.1884571630
Short name T1225
Test name
Test status
Simulation time 41080245136 ps
CPU time 64 seconds
Started Feb 08 01:22:47 PM UTC 25
Finished Feb 08 01:23:53 PM UTC 25
Peak memory 308744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884571630 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_all.1884571630
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_stress_rd.53086433
Short name T1177
Test name
Test status
Simulation time 1815108527 ps
CPU time 18.72 seconds
Started Feb 08 01:22:27 PM UTC 25
Finished Feb 08 01:22:47 PM UTC 25
Peak memory 216152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53086433 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_rd.53086433
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_stress_wr.1511748909
Short name T1236
Test name
Test status
Simulation time 26900910280 ps
CPU time 117.78 seconds
Started Feb 08 01:22:25 PM UTC 25
Finished Feb 08 01:24:25 PM UTC 25
Peak memory 1844992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511748909 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_wr.1511748909
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_timeout.2450456372
Short name T1180
Test name
Test status
Simulation time 1182299634 ps
CPU time 9.48 seconds
Started Feb 08 01:22:41 PM UTC 25
Finished Feb 08 01:22:52 PM UTC 25
Peak memory 226220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450456372 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_timeout.2450456372
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/33.i2c_target_tx_stretch_ctrl.2471654243
Short name T1187
Test name
Test status
Simulation time 173324078 ps
CPU time 3.2 seconds
Started Feb 08 01:22:54 PM UTC 25
Finished Feb 08 01:22:58 PM UTC 25
Peak memory 215864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471654243 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.2471654243
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_alert_test.3009393867
Short name T1221
Test name
Test status
Simulation time 90433204 ps
CPU time 0.93 seconds
Started Feb 08 01:23:48 PM UTC 25
Finished Feb 08 01:23:51 PM UTC 25
Peak memory 214696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009393867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.3009393867
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_error_intr.4260568052
Short name T1198
Test name
Test status
Simulation time 131127301 ps
CPU time 3.08 seconds
Started Feb 08 01:23:04 PM UTC 25
Finished Feb 08 01:23:08 PM UTC 25
Peak memory 233192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260568052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_host_error_intr.4260568052
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_fmt_empty.3908187206
Short name T1202
Test name
Test status
Simulation time 1028603551 ps
CPU time 15.81 seconds
Started Feb 08 01:23:00 PM UTC 25
Finished Feb 08 01:23:18 PM UTC 25
Peak memory 267844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908187206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empty.3908187206
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_full.1245728812
Short name T1249
Test name
Test status
Simulation time 1741341763 ps
CPU time 109.16 seconds
Started Feb 08 01:23:00 PM UTC 25
Finished Feb 08 01:24:52 PM UTC 25
Peak memory 492960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245728812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 34.i2c_host_fifo_full.1245728812
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_overflow.548023378
Short name T1302
Test name
Test status
Simulation time 9244455276 ps
CPU time 178.97 seconds
Started Feb 08 01:22:59 PM UTC 25
Finished Feb 08 01:26:01 PM UTC 25
Peak memory 804004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548023378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_host_fifo_overflow.548023378
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_fmt.2439878037
Short name T1195
Test name
Test status
Simulation time 141012588 ps
CPU time 1.44 seconds
Started Feb 08 01:23:00 PM UTC 25
Finished Feb 08 01:23:03 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439878037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fmt.2439878037
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_rx.789919042
Short name T1199
Test name
Test status
Simulation time 245584817 ps
CPU time 7.48 seconds
Started Feb 08 01:23:00 PM UTC 25
Finished Feb 08 01:23:09 PM UTC 25
Peak memory 216032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789919042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.789919042
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_watermark.1152645452
Short name T1409
Test name
Test status
Simulation time 5052271669 ps
CPU time 321.14 seconds
Started Feb 08 01:22:59 PM UTC 25
Finished Feb 08 01:28:24 PM UTC 25
Peak memory 1535288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152645452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 34.i2c_host_fifo_watermark.1152645452
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_may_nack.566552113
Short name T1217
Test name
Test status
Simulation time 331527485 ps
CPU time 5.98 seconds
Started Feb 08 01:23:40 PM UTC 25
Finished Feb 08 01:23:48 PM UTC 25
Peak memory 216288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566552113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nac
k_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 34.i2c_host_may_nack.566552113
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_override.3414461555
Short name T1191
Test name
Test status
Simulation time 89833142 ps
CPU time 0.93 seconds
Started Feb 08 01:22:57 PM UTC 25
Finished Feb 08 01:22:59 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414461555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 34.i2c_host_override.3414461555
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_perf.3739121710
Short name T1204
Test name
Test status
Simulation time 1252414683 ps
CPU time 21.21 seconds
Started Feb 08 01:23:02 PM UTC 25
Finished Feb 08 01:23:24 PM UTC 25
Peak memory 296400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739121710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_host_perf.3739121710
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_perf_precise.115814917
Short name T1197
Test name
Test status
Simulation time 275820915 ps
CPU time 3.84 seconds
Started Feb 08 01:23:02 PM UTC 25
Finished Feb 08 01:23:07 PM UTC 25
Peak memory 215772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115814917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pr
ecise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_host_perf_precise.115814917
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_smoke.3561125697
Short name T1232
Test name
Test status
Simulation time 1305665657 ps
CPU time 69.83 seconds
Started Feb 08 01:22:57 PM UTC 25
Finished Feb 08 01:24:09 PM UTC 25
Peak memory 316916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561125697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_host_smoke.3561125697
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_host_stretch_timeout.4186658242
Short name T1201
Test name
Test status
Simulation time 950738764 ps
CPU time 12.48 seconds
Started Feb 08 01:23:04 PM UTC 25
Finished Feb 08 01:23:18 PM UTC 25
Peak memory 226092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186658242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.i2c_host_stretch_timeout.4186658242
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_bad_addr.3652470019
Short name T1213
Test name
Test status
Simulation time 2667574488 ps
CPU time 4.75 seconds
Started Feb 08 01:23:34 PM UTC 25
Finished Feb 08 01:23:40 PM UTC 25
Peak memory 226160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3652470019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.3652470019
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_acq.1559824178
Short name T1208
Test name
Test status
Simulation time 312428647 ps
CPU time 1.35 seconds
Started Feb 08 01:23:29 PM UTC 25
Finished Feb 08 01:23:32 PM UTC 25
Peak memory 214492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559824178 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_acq.1559824178
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_tx.688116360
Short name T1209
Test name
Test status
Simulation time 278747410 ps
CPU time 1.69 seconds
Started Feb 08 01:23:29 PM UTC 25
Finished Feb 08 01:23:33 PM UTC 25
Peak memory 214492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688116360 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_tx.688116360
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_acq.2891894573
Short name T1218
Test name
Test status
Simulation time 941670950 ps
CPU time 4.85 seconds
Started Feb 08 01:23:41 PM UTC 25
Finished Feb 08 01:23:48 PM UTC 25
Peak memory 215932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891894573 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.2891894573
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_tx.1543448197
Short name T1216
Test name
Test status
Simulation time 602955992 ps
CPU time 1.59 seconds
Started Feb 08 01:23:42 PM UTC 25
Finished Feb 08 01:23:45 PM UTC 25
Peak memory 213928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543448197 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.1543448197
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_hrst.334281893
Short name T1214
Test name
Test status
Simulation time 272357750 ps
CPU time 2.61 seconds
Started Feb 08 01:23:37 PM UTC 25
Finished Feb 08 01:23:41 PM UTC 25
Peak memory 226404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334281893 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_hrst.334281893
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_intr_smoke.1194991919
Short name T1207
Test name
Test status
Simulation time 1409600846 ps
CPU time 12.42 seconds
Started Feb 08 01:23:18 PM UTC 25
Finished Feb 08 01:23:32 PM UTC 25
Peak memory 230312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194991919 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_smoke.1194991919
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_intr_stress_wr.316359428
Short name T1376
Test name
Test status
Simulation time 27365428990 ps
CPU time 268.6 seconds
Started Feb 08 01:23:23 PM UTC 25
Finished Feb 08 01:27:55 PM UTC 25
Peak memory 3251780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31635
9428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.316359428
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull.379497732
Short name T1222
Test name
Test status
Simulation time 7585196840 ps
CPU time 4.34 seconds
Started Feb 08 01:23:45 PM UTC 25
Finished Feb 08 01:23:51 PM UTC 25
Peak memory 226220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379497732 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_acqfull.379497732
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull_addr.2475529241
Short name T1224
Test name
Test status
Simulation time 511471969 ps
CPU time 4.46 seconds
Started Feb 08 01:23:46 PM UTC 25
Finished Feb 08 01:23:52 PM UTC 25
Peak memory 215928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475529241 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_acqfull_addr.2475529241
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_nack_txstretch.3989547308
Short name T1223
Test name
Test status
Simulation time 506588218 ps
CPU time 1.79 seconds
Started Feb 08 01:23:48 PM UTC 25
Finished Feb 08 01:23:51 PM UTC 25
Peak memory 231716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989547308 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_txstretch.3989547308
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_perf.2615109377
Short name T1211
Test name
Test status
Simulation time 648807418 ps
CPU time 4.95 seconds
Started Feb 08 01:23:33 PM UTC 25
Finished Feb 08 01:23:39 PM UTC 25
Peak memory 219992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615109377 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_perf.2615109377
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_smbus_maxlen.275598268
Short name T1220
Test name
Test status
Simulation time 1223505119 ps
CPU time 3.96 seconds
Started Feb 08 01:23:44 PM UTC 25
Finished Feb 08 01:23:49 PM UTC 25
Peak memory 215640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275598268 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smbus_maxlen.275598268
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_smoke.2240983233
Short name T1203
Test name
Test status
Simulation time 3302373969 ps
CPU time 12.22 seconds
Started Feb 08 01:23:09 PM UTC 25
Finished Feb 08 01:23:22 PM UTC 25
Peak memory 232792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240983233 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smoke.2240983233
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_stress_all.2441516682
Short name T1245
Test name
Test status
Simulation time 8164711896 ps
CPU time 73.05 seconds
Started Feb 08 01:23:33 PM UTC 25
Finished Feb 08 01:24:48 PM UTC 25
Peak memory 249436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441516682 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_all.2441516682
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_stress_rd.3173532563
Short name T1215
Test name
Test status
Simulation time 2575504026 ps
CPU time 24.74 seconds
Started Feb 08 01:23:16 PM UTC 25
Finished Feb 08 01:23:42 PM UTC 25
Peak memory 237052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173532563 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_rd.3173532563
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_stress_wr.790208413
Short name T1358
Test name
Test status
Simulation time 31598210770 ps
CPU time 247.65 seconds
Started Feb 08 01:23:10 PM UTC 25
Finished Feb 08 01:27:21 PM UTC 25
Peak memory 3005960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790208413 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_wr.790208413
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_stretch.2175800533
Short name T1206
Test name
Test status
Simulation time 489584745 ps
CPU time 9.11 seconds
Started Feb 08 01:23:18 PM UTC 25
Finished Feb 08 01:23:28 PM UTC 25
Peak memory 286392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175800533 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stretch.2175800533
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_timeout.2686618612
Short name T1212
Test name
Test status
Simulation time 5427491365 ps
CPU time 12.3 seconds
Started Feb 08 01:23:25 PM UTC 25
Finished Feb 08 01:23:39 PM UTC 25
Peak memory 243272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686618612 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_timeout.2686618612
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/34.i2c_target_tx_stretch_ctrl.27102947
Short name T1227
Test name
Test status
Simulation time 515333283 ps
CPU time 9.17 seconds
Started Feb 08 01:23:43 PM UTC 25
Finished Feb 08 01:23:54 PM UTC 25
Peak memory 215924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27102947 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.27102947
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_alert_test.1397425673
Short name T1256
Test name
Test status
Simulation time 40145616 ps
CPU time 0.81 seconds
Started Feb 08 01:24:57 PM UTC 25
Finished Feb 08 01:25:00 PM UTC 25
Peak memory 213916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397425673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.1397425673
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_error_intr.1294251457
Short name T1233
Test name
Test status
Simulation time 519455063 ps
CPU time 11.65 seconds
Started Feb 08 01:24:00 PM UTC 25
Finished Feb 08 01:24:13 PM UTC 25
Peak memory 292692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294251457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_host_error_intr.1294251457
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_fmt_empty.3743488478
Short name T1230
Test name
Test status
Simulation time 806501094 ps
CPU time 4.89 seconds
Started Feb 08 01:23:53 PM UTC 25
Finished Feb 08 01:23:59 PM UTC 25
Peak memory 247476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743488478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empty.3743488478
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_full.2154512192
Short name T1265
Test name
Test status
Simulation time 1956472645 ps
CPU time 71.38 seconds
Started Feb 08 01:23:54 PM UTC 25
Finished Feb 08 01:25:07 PM UTC 25
Peak memory 484768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154512192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_host_fifo_full.2154512192
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_overflow.512512506
Short name T1292
Test name
Test status
Simulation time 4601630431 ps
CPU time 109.06 seconds
Started Feb 08 01:23:52 PM UTC 25
Finished Feb 08 01:25:43 PM UTC 25
Peak memory 779844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512512506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_host_fifo_overflow.512512506
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_fmt.2838911874
Short name T1228
Test name
Test status
Simulation time 143173957 ps
CPU time 1.63 seconds
Started Feb 08 01:23:53 PM UTC 25
Finished Feb 08 01:23:56 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838911874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fmt.2838911874
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_rx.2621513427
Short name T1231
Test name
Test status
Simulation time 734966019 ps
CPU time 9.02 seconds
Started Feb 08 01:23:54 PM UTC 25
Finished Feb 08 01:24:04 PM UTC 25
Peak memory 216064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621513427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx.2621513427
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_watermark.3337368642
Short name T1443
Test name
Test status
Simulation time 9241608684 ps
CPU time 315.83 seconds
Started Feb 08 01:23:52 PM UTC 25
Finished Feb 08 01:29:12 PM UTC 25
Peak memory 1392348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337368642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 35.i2c_host_fifo_watermark.3337368642
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_may_nack.1186426585
Short name T1263
Test name
Test status
Simulation time 409585867 ps
CPU time 15.32 seconds
Started Feb 08 01:24:49 PM UTC 25
Finished Feb 08 01:25:06 PM UTC 25
Peak memory 215964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186426585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 35.i2c_host_may_nack.1186426585
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_mode_toggle.2559140597
Short name T76
Test name
Test status
Simulation time 976383516 ps
CPU time 13.07 seconds
Started Feb 08 01:24:45 PM UTC 25
Finished Feb 08 01:24:59 PM UTC 25
Peak memory 263620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559140597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_t
oggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_host_mode_toggle.2559140597
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_override.3163211991
Short name T1226
Test name
Test status
Simulation time 31902806 ps
CPU time 1.01 seconds
Started Feb 08 01:23:51 PM UTC 25
Finished Feb 08 01:23:53 PM UTC 25
Peak memory 213920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163211991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 35.i2c_host_override.3163211991
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_perf.3430952226
Short name T1422
Test name
Test status
Simulation time 18281527862 ps
CPU time 276.03 seconds
Started Feb 08 01:23:55 PM UTC 25
Finished Feb 08 01:28:35 PM UTC 25
Peak memory 215956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430952226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_host_perf.3430952226
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_perf_precise.1411561797
Short name T1261
Test name
Test status
Simulation time 6274864927 ps
CPU time 65.07 seconds
Started Feb 08 01:23:56 PM UTC 25
Finished Feb 08 01:25:03 PM UTC 25
Peak memory 215968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411561797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_host_perf_precise.1411561797
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_smoke.2433844946
Short name T1237
Test name
Test status
Simulation time 1558407985 ps
CPU time 35.46 seconds
Started Feb 08 01:23:50 PM UTC 25
Finished Feb 08 01:24:27 PM UTC 25
Peak memory 386508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433844946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_host_smoke.2433844946
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_stress_all.764194383
Short name T1673
Test name
Test status
Simulation time 43703699486 ps
CPU time 941.93 seconds
Started Feb 08 01:24:05 PM UTC 25
Finished Feb 08 01:39:57 PM UTC 25
Peak memory 1644168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764194383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_host_stress_all.764194383
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_stretch_timeout.1029672591
Short name T1234
Test name
Test status
Simulation time 3482145749 ps
CPU time 21.19 seconds
Started Feb 08 01:23:59 PM UTC 25
Finished Feb 08 01:24:22 PM UTC 25
Peak memory 230252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029672591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_host_stretch_timeout.1029672591
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_bad_addr.35351458
Short name T1250
Test name
Test status
Simulation time 9456678052 ps
CPU time 7.77 seconds
Started Feb 08 01:24:43 PM UTC 25
Finished Feb 08 01:24:52 PM UTC 25
Peak memory 232672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=35351458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.35351458
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_acq.3559053833
Short name T1240
Test name
Test status
Simulation time 167106994 ps
CPU time 1.76 seconds
Started Feb 08 01:24:36 PM UTC 25
Finished Feb 08 01:24:39 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559053833 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_acq.3559053833
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_tx.2545074060
Short name T1241
Test name
Test status
Simulation time 641278408 ps
CPU time 1.99 seconds
Started Feb 08 01:24:37 PM UTC 25
Finished Feb 08 01:24:40 PM UTC 25
Peak memory 216160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545074060 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_tx.2545074060
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_acq.748596491
Short name T1252
Test name
Test status
Simulation time 1089790173 ps
CPU time 5.19 seconds
Started Feb 08 01:24:49 PM UTC 25
Finished Feb 08 01:24:55 PM UTC 25
Peak memory 216164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748596491 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.748596491
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_tx.3484929669
Short name T1251
Test name
Test status
Simulation time 299992721 ps
CPU time 1.9 seconds
Started Feb 08 01:24:52 PM UTC 25
Finished Feb 08 01:24:55 PM UTC 25
Peak memory 213928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484929669 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.3484929669
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_intr_smoke.1903915995
Short name T1238
Test name
Test status
Simulation time 3123900199 ps
CPU time 6.6 seconds
Started Feb 08 01:24:24 PM UTC 25
Finished Feb 08 01:24:32 PM UTC 25
Peak memory 230276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903915995 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_smoke.1903915995
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_intr_stress_wr.3511808833
Short name T1270
Test name
Test status
Simulation time 4652573278 ps
CPU time 52.52 seconds
Started Feb 08 01:24:26 PM UTC 25
Finished Feb 08 01:25:20 PM UTC 25
Peak memory 1244740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35118
08833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.3511808833
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull.4112512008
Short name T1255
Test name
Test status
Simulation time 488704173 ps
CPU time 3.69 seconds
Started Feb 08 01:24:53 PM UTC 25
Finished Feb 08 01:24:58 PM UTC 25
Peak memory 226412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112512008 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_acqfull.4112512008
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull_addr.2721757290
Short name T1259
Test name
Test status
Simulation time 4431519390 ps
CPU time 3.52 seconds
Started Feb 08 01:24:56 PM UTC 25
Finished Feb 08 01:25:01 PM UTC 25
Peak memory 215992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721757290 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_acqfull_addr.2721757290
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_nack_txstretch.1732379974
Short name T1257
Test name
Test status
Simulation time 129754318 ps
CPU time 2.18 seconds
Started Feb 08 01:24:56 PM UTC 25
Finished Feb 08 01:25:00 PM UTC 25
Peak memory 232976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732379974 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_txstretch.1732379974
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_perf.1750422273
Short name T1248
Test name
Test status
Simulation time 948600886 ps
CPU time 9.25 seconds
Started Feb 08 01:24:41 PM UTC 25
Finished Feb 08 01:24:51 PM UTC 25
Peak memory 230504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750422273 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_perf.1750422273
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_smbus_maxlen.3639277959
Short name T1254
Test name
Test status
Simulation time 379847836 ps
CPU time 2.71 seconds
Started Feb 08 01:24:53 PM UTC 25
Finished Feb 08 01:24:57 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639277959 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smbus_maxlen.3639277959
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_smoke.874014084
Short name T1235
Test name
Test status
Simulation time 1119276353 ps
CPU time 12.13 seconds
Started Feb 08 01:24:10 PM UTC 25
Finished Feb 08 01:24:23 PM UTC 25
Peak memory 226400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874014084 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smoke.874014084
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_stress_all.971983491
Short name T1751
Test name
Test status
Simulation time 73323292359 ps
CPU time 2105.16 seconds
Started Feb 08 01:24:41 PM UTC 25
Finished Feb 08 02:00:03 PM UTC 25
Peak memory 14741016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971983491 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_all.971983491
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_stress_rd.1124961322
Short name T1247
Test name
Test status
Simulation time 609616135 ps
CPU time 30.31 seconds
Started Feb 08 01:24:19 PM UTC 25
Finished Feb 08 01:24:51 PM UTC 25
Peak memory 226156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124961322 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_rd.1124961322
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_stress_wr.3660153702
Short name T1286
Test name
Test status
Simulation time 36686564860 ps
CPU time 84.81 seconds
Started Feb 08 01:24:15 PM UTC 25
Finished Feb 08 01:25:41 PM UTC 25
Peak memory 1132104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660153702 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_wr.3660153702
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_stretch.853628136
Short name T1242
Test name
Test status
Simulation time 3997311509 ps
CPU time 17.32 seconds
Started Feb 08 01:24:23 PM UTC 25
Finished Feb 08 01:24:42 PM UTC 25
Peak memory 360136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853628136 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stretch.853628136
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_timeout.2853119524
Short name T1239
Test name
Test status
Simulation time 1363466224 ps
CPU time 7.3 seconds
Started Feb 08 01:24:27 PM UTC 25
Finished Feb 08 01:24:36 PM UTC 25
Peak memory 232856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853119524 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_timeout.2853119524
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_tx_stretch_ctrl.3042262963
Short name T1253
Test name
Test status
Simulation time 135908648 ps
CPU time 2.94 seconds
Started Feb 08 01:24:52 PM UTC 25
Finished Feb 08 01:24:56 PM UTC 25
Peak memory 215864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042262963 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.3042262963
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_alert_test.1408727373
Short name T1294
Test name
Test status
Simulation time 15825807 ps
CPU time 0.98 seconds
Started Feb 08 01:25:41 PM UTC 25
Finished Feb 08 01:25:44 PM UTC 25
Peak memory 213916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408727373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.1408727373
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_fmt_empty.4282623522
Short name T1267
Test name
Test status
Simulation time 1373669060 ps
CPU time 7.39 seconds
Started Feb 08 01:25:02 PM UTC 25
Finished Feb 08 01:25:11 PM UTC 25
Peak memory 288252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282623522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empty.4282623522
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_full.745303831
Short name T1377
Test name
Test status
Simulation time 7186671091 ps
CPU time 169.44 seconds
Started Feb 08 01:25:03 PM UTC 25
Finished Feb 08 01:27:55 PM UTC 25
Peak memory 603980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745303831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fu
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 36.i2c_host_fifo_full.745303831
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_overflow.1697558785
Short name T1400
Test name
Test status
Simulation time 2520778213 ps
CPU time 184.92 seconds
Started Feb 08 01:25:01 PM UTC 25
Finished Feb 08 01:28:10 PM UTC 25
Peak memory 728844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697558785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_host_fifo_overflow.1697558785
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_fmt.4133207418
Short name T1262
Test name
Test status
Simulation time 208252601 ps
CPU time 1.37 seconds
Started Feb 08 01:25:01 PM UTC 25
Finished Feb 08 01:25:03 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133207418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fmt.4133207418
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_rx.1902826853
Short name T1266
Test name
Test status
Simulation time 404466675 ps
CPU time 4.86 seconds
Started Feb 08 01:25:02 PM UTC 25
Finished Feb 08 01:25:08 PM UTC 25
Peak memory 215972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902826853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.1902826853
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_watermark.549860661
Short name T1330
Test name
Test status
Simulation time 4226356183 ps
CPU time 90.94 seconds
Started Feb 08 01:25:00 PM UTC 25
Finished Feb 08 01:26:33 PM UTC 25
Peak memory 1185352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549860661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_wa
termark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_host_fifo_watermark.549860661
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_may_nack.948772491
Short name T1288
Test name
Test status
Simulation time 2555361479 ps
CPU time 9.62 seconds
Started Feb 08 01:25:31 PM UTC 25
Finished Feb 08 01:25:42 PM UTC 25
Peak memory 215904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948772491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nac
k_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 36.i2c_host_may_nack.948772491
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_override.2420411360
Short name T1258
Test name
Test status
Simulation time 23155418 ps
CPU time 0.97 seconds
Started Feb 08 01:24:59 PM UTC 25
Finished Feb 08 01:25:01 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420411360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 36.i2c_host_override.2420411360
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_perf.3110406671
Short name T1283
Test name
Test status
Simulation time 2685941735 ps
CPU time 31.63 seconds
Started Feb 08 01:25:04 PM UTC 25
Finished Feb 08 01:25:37 PM UTC 25
Peak memory 215984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110406671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_host_perf.3110406671
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_perf_precise.2154752990
Short name T1268
Test name
Test status
Simulation time 731573671 ps
CPU time 9.75 seconds
Started Feb 08 01:25:04 PM UTC 25
Finished Feb 08 01:25:15 PM UTC 25
Peak memory 215916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154752990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_host_perf_precise.2154752990
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_smoke.1882629571
Short name T1273
Test name
Test status
Simulation time 1159849125 ps
CPU time 26.81 seconds
Started Feb 08 01:24:58 PM UTC 25
Finished Feb 08 01:25:26 PM UTC 25
Peak memory 363988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882629571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_host_smoke.1882629571
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_host_stretch_timeout.4007980329
Short name T1278
Test name
Test status
Simulation time 3049067927 ps
CPU time 22.85 seconds
Started Feb 08 01:25:06 PM UTC 25
Finished Feb 08 01:25:30 PM UTC 25
Peak memory 232612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007980329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_host_stretch_timeout.4007980329
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_bad_addr.17288203
Short name T1285
Test name
Test status
Simulation time 4852642605 ps
CPU time 10.83 seconds
Started Feb 08 01:25:29 PM UTC 25
Finished Feb 08 01:25:41 PM UTC 25
Peak memory 233144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=17288203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.17288203
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_acq.2122249848
Short name T1275
Test name
Test status
Simulation time 175209261 ps
CPU time 1.22 seconds
Started Feb 08 01:25:25 PM UTC 25
Finished Feb 08 01:25:28 PM UTC 25
Peak memory 213928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122249848 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_acq.2122249848
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_tx.3897611327
Short name T1277
Test name
Test status
Simulation time 625285091 ps
CPU time 1.76 seconds
Started Feb 08 01:25:25 PM UTC 25
Finished Feb 08 01:25:28 PM UTC 25
Peak memory 216168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897611327 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_tx.3897611327
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_acq.538549526
Short name T1284
Test name
Test status
Simulation time 522071547 ps
CPU time 4.85 seconds
Started Feb 08 01:25:32 PM UTC 25
Finished Feb 08 01:25:38 PM UTC 25
Peak memory 215920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538549526 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.538549526
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_tx.2573860439
Short name T1281
Test name
Test status
Simulation time 160035086 ps
CPU time 2.3 seconds
Started Feb 08 01:25:32 PM UTC 25
Finished Feb 08 01:25:35 PM UTC 25
Peak memory 215712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573860439 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.2573860439
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_intr_smoke.2312208938
Short name T1272
Test name
Test status
Simulation time 945367977 ps
CPU time 6.75 seconds
Started Feb 08 01:25:16 PM UTC 25
Finished Feb 08 01:25:24 PM UTC 25
Peak memory 233020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312208938 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_smoke.2312208938
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_intr_stress_wr.3082522249
Short name T1487
Test name
Test status
Simulation time 15346105721 ps
CPU time 300.05 seconds
Started Feb 08 01:25:19 PM UTC 25
Finished Feb 08 01:30:23 PM UTC 25
Peak memory 3766020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30825
22249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.3082522249
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull.3563812262
Short name T1289
Test name
Test status
Simulation time 1852436265 ps
CPU time 4.13 seconds
Started Feb 08 01:25:37 PM UTC 25
Finished Feb 08 01:25:42 PM UTC 25
Peak memory 226412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563812262 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_acqfull.3563812262
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull_addr.1590558084
Short name T1291
Test name
Test status
Simulation time 3846716402 ps
CPU time 3.51 seconds
Started Feb 08 01:25:38 PM UTC 25
Finished Feb 08 01:25:43 PM UTC 25
Peak memory 215720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590558084 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_acqfull_addr.1590558084
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_perf.1870578231
Short name T1282
Test name
Test status
Simulation time 720817759 ps
CPU time 8.24 seconds
Started Feb 08 01:25:27 PM UTC 25
Finished Feb 08 01:25:36 PM UTC 25
Peak memory 226052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870578231 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_perf.1870578231
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_smbus_maxlen.2992236379
Short name T1287
Test name
Test status
Simulation time 2004265331 ps
CPU time 4.02 seconds
Started Feb 08 01:25:36 PM UTC 25
Finished Feb 08 01:25:41 PM UTC 25
Peak memory 215672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992236379 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smbus_maxlen.2992236379
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_smoke.2569805442
Short name T1274
Test name
Test status
Simulation time 554002392 ps
CPU time 15.39 seconds
Started Feb 08 01:25:09 PM UTC 25
Finished Feb 08 01:25:26 PM UTC 25
Peak memory 226200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569805442 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smoke.2569805442
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_stress_all.2316774058
Short name T1327
Test name
Test status
Simulation time 7460333799 ps
CPU time 60.42 seconds
Started Feb 08 01:25:27 PM UTC 25
Finished Feb 08 01:26:29 PM UTC 25
Peak memory 298452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316774058 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_all.2316774058
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_stress_rd.607390688
Short name T1295
Test name
Test status
Simulation time 3496832482 ps
CPU time 30.57 seconds
Started Feb 08 01:25:13 PM UTC 25
Finished Feb 08 01:25:44 PM UTC 25
Peak memory 243164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607390688 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_rd.607390688
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_stress_wr.4081928508
Short name T1317
Test name
Test status
Simulation time 22973315907 ps
CPU time 68.78 seconds
Started Feb 08 01:25:11 PM UTC 25
Finished Feb 08 01:26:22 PM UTC 25
Peak memory 952068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081928508 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_wr.4081928508
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_stretch.360485426
Short name T1300
Test name
Test status
Simulation time 4925187880 ps
CPU time 38.2 seconds
Started Feb 08 01:25:14 PM UTC 25
Finished Feb 08 01:25:54 PM UTC 25
Peak memory 1201728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360485426 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stretch.360485426
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_timeout.2361737089
Short name T1276
Test name
Test status
Simulation time 2205684485 ps
CPU time 6.63 seconds
Started Feb 08 01:25:20 PM UTC 25
Finished Feb 08 01:25:28 PM UTC 25
Peak memory 230244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361737089 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_timeout.2361737089
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/36.i2c_target_tx_stretch_ctrl.1426961995
Short name T1293
Test name
Test status
Simulation time 276535842 ps
CPU time 6.31 seconds
Started Feb 08 01:25:36 PM UTC 25
Finished Feb 08 01:25:44 PM UTC 25
Peak memory 215908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426961995 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.1426961995
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_alert_test.1957265660
Short name T1321
Test name
Test status
Simulation time 43276746 ps
CPU time 1.02 seconds
Started Feb 08 01:26:23 PM UTC 25
Finished Feb 08 01:26:25 PM UTC 25
Peak memory 214936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957265660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.1957265660
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_error_intr.551305513
Short name T1299
Test name
Test status
Simulation time 131105902 ps
CPU time 2.55 seconds
Started Feb 08 01:25:46 PM UTC 25
Finished Feb 08 01:25:50 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551305513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_host_error_intr.551305513
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_fmt_empty.1886584873
Short name T1303
Test name
Test status
Simulation time 330327645 ps
CPU time 15.93 seconds
Started Feb 08 01:25:44 PM UTC 25
Finished Feb 08 01:26:01 PM UTC 25
Peak memory 279708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886584873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empty.1886584873
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_full.112302967
Short name T1433
Test name
Test status
Simulation time 18964232759 ps
CPU time 188.82 seconds
Started Feb 08 01:25:45 PM UTC 25
Finished Feb 08 01:28:57 PM UTC 25
Peak memory 456480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112302967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fu
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 37.i2c_host_fifo_full.112302967
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_overflow.614976283
Short name T1336
Test name
Test status
Simulation time 9847972299 ps
CPU time 57.25 seconds
Started Feb 08 01:25:44 PM UTC 25
Finished Feb 08 01:26:43 PM UTC 25
Peak memory 593680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614976283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_host_fifo_overflow.614976283
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_fmt.3995915033
Short name T1297
Test name
Test status
Simulation time 76621577 ps
CPU time 1.23 seconds
Started Feb 08 01:25:44 PM UTC 25
Finished Feb 08 01:25:46 PM UTC 25
Peak memory 214144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995915033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fmt.3995915033
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_rx.2296893725
Short name T1301
Test name
Test status
Simulation time 320016006 ps
CPU time 12.02 seconds
Started Feb 08 01:25:44 PM UTC 25
Finished Feb 08 01:25:57 PM UTC 25
Peak memory 243392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296893725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.2296893725
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_watermark.1685316195
Short name T1470
Test name
Test status
Simulation time 3679441913 ps
CPU time 242.28 seconds
Started Feb 08 01:25:43 PM UTC 25
Finished Feb 08 01:29:49 PM UTC 25
Peak memory 1052428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685316195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 37.i2c_host_fifo_watermark.1685316195
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_may_nack.4107839692
Short name T1335
Test name
Test status
Simulation time 1051936664 ps
CPU time 23.9 seconds
Started Feb 08 01:26:15 PM UTC 25
Finished Feb 08 01:26:40 PM UTC 25
Peak memory 216212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107839692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 37.i2c_host_may_nack.4107839692
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_override.3533009474
Short name T1296
Test name
Test status
Simulation time 50982493 ps
CPU time 1.03 seconds
Started Feb 08 01:25:43 PM UTC 25
Finished Feb 08 01:25:45 PM UTC 25
Peak memory 214504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533009474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 37.i2c_host_override.3533009474
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_perf.1829343592
Short name T1363
Test name
Test status
Simulation time 2833032557 ps
CPU time 109.54 seconds
Started Feb 08 01:25:45 PM UTC 25
Finished Feb 08 01:27:37 PM UTC 25
Peak memory 265708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829343592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_host_perf.1829343592
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_perf_precise.460759671
Short name T1298
Test name
Test status
Simulation time 70555515 ps
CPU time 2.3 seconds
Started Feb 08 01:25:45 PM UTC 25
Finished Feb 08 01:25:49 PM UTC 25
Peak memory 230448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460759671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pr
ecise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_host_perf_precise.460759671
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_smoke.457927490
Short name T1318
Test name
Test status
Simulation time 9503681043 ps
CPU time 38.96 seconds
Started Feb 08 01:25:42 PM UTC 25
Finished Feb 08 01:26:23 PM UTC 25
Peak memory 353788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457927490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_host_smoke.457927490
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_stress_all.1124600307
Short name T129
Test name
Test status
Simulation time 71680312164 ps
CPU time 631.76 seconds
Started Feb 08 01:25:47 PM UTC 25
Finished Feb 08 01:36:26 PM UTC 25
Peak memory 1849100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124600307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_host_stress_all.1124600307
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_stretch_timeout.3243867713
Short name T1306
Test name
Test status
Simulation time 3176859120 ps
CPU time 15.61 seconds
Started Feb 08 01:25:46 PM UTC 25
Finished Feb 08 01:26:03 PM UTC 25
Peak memory 230316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243867713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.i2c_host_stretch_timeout.3243867713
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_bad_addr.3387630047
Short name T1314
Test name
Test status
Simulation time 8286631632 ps
CPU time 5.77 seconds
Started Feb 08 01:26:12 PM UTC 25
Finished Feb 08 01:26:19 PM UTC 25
Peak memory 226204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3387630047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.3387630047
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_acq.913423276
Short name T1307
Test name
Test status
Simulation time 509253060 ps
CPU time 2.76 seconds
Started Feb 08 01:26:04 PM UTC 25
Finished Feb 08 01:26:08 PM UTC 25
Peak memory 228460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913423276 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_acq.913423276
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_tx.2367842602
Short name T1308
Test name
Test status
Simulation time 291519113 ps
CPU time 2.72 seconds
Started Feb 08 01:26:07 PM UTC 25
Finished Feb 08 01:26:11 PM UTC 25
Peak memory 226156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367842602 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_tx.2367842602
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_acq.2205765893
Short name T1316
Test name
Test status
Simulation time 2505874092 ps
CPU time 3.72 seconds
Started Feb 08 01:26:17 PM UTC 25
Finished Feb 08 01:26:22 PM UTC 25
Peak memory 215996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205765893 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.2205765893
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_tx.3282129740
Short name T1315
Test name
Test status
Simulation time 109035301 ps
CPU time 1.78 seconds
Started Feb 08 01:26:18 PM UTC 25
Finished Feb 08 01:26:21 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282129740 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.3282129740
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_intr_smoke.1100527545
Short name T1310
Test name
Test status
Simulation time 4572498719 ps
CPU time 10 seconds
Started Feb 08 01:26:02 PM UTC 25
Finished Feb 08 01:26:13 PM UTC 25
Peak memory 230304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100527545 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_smoke.1100527545
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_intr_stress_wr.2077661802
Short name T1385
Test name
Test status
Simulation time 22412007668 ps
CPU time 114.81 seconds
Started Feb 08 01:26:03 PM UTC 25
Finished Feb 08 01:28:00 PM UTC 25
Peak memory 1375744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20776
61802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.2077661802
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull.2444182389
Short name T1324
Test name
Test status
Simulation time 1786605476 ps
CPU time 4.98 seconds
Started Feb 08 01:26:20 PM UTC 25
Finished Feb 08 01:26:26 PM UTC 25
Peak memory 225840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444182389 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_acqfull.2444182389
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull_addr.3157616337
Short name T1323
Test name
Test status
Simulation time 833588448 ps
CPU time 2.87 seconds
Started Feb 08 01:26:22 PM UTC 25
Finished Feb 08 01:26:26 PM UTC 25
Peak memory 215928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157616337 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_acqfull_addr.3157616337
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_perf.1796559665
Short name T1313
Test name
Test status
Simulation time 6876380721 ps
CPU time 8.8 seconds
Started Feb 08 01:26:09 PM UTC 25
Finished Feb 08 01:26:19 PM UTC 25
Peak memory 233044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796559665 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_perf.1796559665
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_smbus_maxlen.3505752064
Short name T1319
Test name
Test status
Simulation time 503814128 ps
CPU time 3.21 seconds
Started Feb 08 01:26:20 PM UTC 25
Finished Feb 08 01:26:24 PM UTC 25
Peak memory 215472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505752064 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smbus_maxlen.3505752064
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_smoke.1181523294
Short name T1305
Test name
Test status
Simulation time 676713047 ps
CPU time 11.62 seconds
Started Feb 08 01:25:49 PM UTC 25
Finished Feb 08 01:26:02 PM UTC 25
Peak memory 226212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181523294 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smoke.1181523294
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_stress_all.4151111611
Short name T270
Test name
Test status
Simulation time 41462056895 ps
CPU time 219.28 seconds
Started Feb 08 01:26:12 PM UTC 25
Finished Feb 08 01:29:55 PM UTC 25
Peak memory 1910524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151111611 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_all.4151111611
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_stress_rd.2966863126
Short name T1325
Test name
Test status
Simulation time 6664844986 ps
CPU time 30.9 seconds
Started Feb 08 01:25:54 PM UTC 25
Finished Feb 08 01:26:27 PM UTC 25
Peak memory 243244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966863126 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_rd.2966863126
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_stress_wr.3830774638
Short name T1368
Test name
Test status
Simulation time 38936639507 ps
CPU time 114.38 seconds
Started Feb 08 01:25:50 PM UTC 25
Finished Feb 08 01:27:47 PM UTC 25
Peak memory 1263104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830774638 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_wr.3830774638
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_stretch.3397362651
Short name T1361
Test name
Test status
Simulation time 4329951037 ps
CPU time 88.25 seconds
Started Feb 08 01:25:59 PM UTC 25
Finished Feb 08 01:27:29 PM UTC 25
Peak memory 1205764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397362651 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stretch.3397362651
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_timeout.3247618637
Short name T1309
Test name
Test status
Simulation time 12694743822 ps
CPU time 7.12 seconds
Started Feb 08 01:26:03 PM UTC 25
Finished Feb 08 01:26:11 PM UTC 25
Peak memory 243480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247618637 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_timeout.3247618637
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_target_tx_stretch_ctrl.3565773908
Short name T1320
Test name
Test status
Simulation time 213989687 ps
CPU time 4.97 seconds
Started Feb 08 01:26:19 PM UTC 25
Finished Feb 08 01:26:25 PM UTC 25
Peak memory 215864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565773908 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.3565773908
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_alert_test.1923095591
Short name T1351
Test name
Test status
Simulation time 18462988 ps
CPU time 0.94 seconds
Started Feb 08 01:27:05 PM UTC 25
Finished Feb 08 01:27:07 PM UTC 25
Peak memory 213916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923095591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1923095591
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_error_intr.1255276352
Short name T1334
Test name
Test status
Simulation time 185965918 ps
CPU time 4.09 seconds
Started Feb 08 01:26:33 PM UTC 25
Finished Feb 08 01:26:38 PM UTC 25
Peak memory 245608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255276352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_host_error_intr.1255276352
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_fmt_empty.1946329373
Short name T1333
Test name
Test status
Simulation time 1421410234 ps
CPU time 9.18 seconds
Started Feb 08 01:26:28 PM UTC 25
Finished Feb 08 01:26:38 PM UTC 25
Peak memory 288128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946329373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empty.1946329373
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_full.3653022859
Short name T1396
Test name
Test status
Simulation time 14867447281 ps
CPU time 95.67 seconds
Started Feb 08 01:26:28 PM UTC 25
Finished Feb 08 01:28:06 PM UTC 25
Peak memory 540168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653022859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_host_fifo_full.3653022859
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_overflow.1949274751
Short name T1371
Test name
Test status
Simulation time 10032360014 ps
CPU time 80.63 seconds
Started Feb 08 01:26:27 PM UTC 25
Finished Feb 08 01:27:49 PM UTC 25
Peak memory 831060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949274751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_host_fifo_overflow.1949274751
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_fmt.1982305080
Short name T1328
Test name
Test status
Simulation time 558984926 ps
CPU time 1.61 seconds
Started Feb 08 01:26:27 PM UTC 25
Finished Feb 08 01:26:29 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982305080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fmt.1982305080
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_rx.3084029450
Short name T1329
Test name
Test status
Simulation time 627996609 ps
CPU time 3.69 seconds
Started Feb 08 01:26:28 PM UTC 25
Finished Feb 08 01:26:33 PM UTC 25
Peak memory 215892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084029450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.3084029450
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_watermark.2615618097
Short name T1564
Test name
Test status
Simulation time 19870851997 ps
CPU time 368.49 seconds
Started Feb 08 01:26:27 PM UTC 25
Finished Feb 08 01:32:40 PM UTC 25
Peak memory 1402448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615618097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 38.i2c_host_fifo_watermark.2615618097
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_may_nack.3378872999
Short name T251
Test name
Test status
Simulation time 491162038 ps
CPU time 8.1 seconds
Started Feb 08 01:26:55 PM UTC 25
Finished Feb 08 01:27:05 PM UTC 25
Peak memory 215912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378872999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 38.i2c_host_may_nack.3378872999
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_override.1710175179
Short name T1326
Test name
Test status
Simulation time 16571934 ps
CPU time 0.98 seconds
Started Feb 08 01:26:25 PM UTC 25
Finished Feb 08 01:26:28 PM UTC 25
Peak memory 213920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710175179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 38.i2c_host_override.1710175179
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_perf.3675251256
Short name T1354
Test name
Test status
Simulation time 6801047836 ps
CPU time 38.58 seconds
Started Feb 08 01:26:29 PM UTC 25
Finished Feb 08 01:27:09 PM UTC 25
Peak memory 542260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675251256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_host_perf.3675251256
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_perf_precise.266516480
Short name T1331
Test name
Test status
Simulation time 123468720 ps
CPU time 2.08 seconds
Started Feb 08 01:26:30 PM UTC 25
Finished Feb 08 01:26:33 PM UTC 25
Peak memory 215912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266516480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pr
ecise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_host_perf_precise.266516480
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_smoke.253264432
Short name T1340
Test name
Test status
Simulation time 1133155750 ps
CPU time 23.51 seconds
Started Feb 08 01:26:24 PM UTC 25
Finished Feb 08 01:26:49 PM UTC 25
Peak memory 298696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253264432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_host_smoke.253264432
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_host_stretch_timeout.2414622960
Short name T1337
Test name
Test status
Simulation time 841271787 ps
CPU time 15.32 seconds
Started Feb 08 01:26:31 PM UTC 25
Finished Feb 08 01:26:48 PM UTC 25
Peak memory 232740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414622960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_host_stretch_timeout.2414622960
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_bad_addr.2055395620
Short name T1271
Test name
Test status
Simulation time 3803535543 ps
CPU time 6.16 seconds
Started Feb 08 01:26:53 PM UTC 25
Finished Feb 08 01:27:00 PM UTC 25
Peak memory 226176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2055395620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.2055395620
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_acq.3585927351
Short name T1342
Test name
Test status
Simulation time 202237457 ps
CPU time 1.05 seconds
Started Feb 08 01:26:50 PM UTC 25
Finished Feb 08 01:26:52 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585927351 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_acq.3585927351
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_tx.3823826357
Short name T1343
Test name
Test status
Simulation time 413235502 ps
CPU time 1.55 seconds
Started Feb 08 01:26:50 PM UTC 25
Finished Feb 08 01:26:53 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823826357 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_tx.3823826357
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_acq.933686092
Short name T1346
Test name
Test status
Simulation time 3283289389 ps
CPU time 5.18 seconds
Started Feb 08 01:26:56 PM UTC 25
Finished Feb 08 01:27:03 PM UTC 25
Peak memory 215964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933686092 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.933686092
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_tx.1625229225
Short name T1322
Test name
Test status
Simulation time 339283290 ps
CPU time 1.33 seconds
Started Feb 08 01:26:57 PM UTC 25
Finished Feb 08 01:27:00 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625229225 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.1625229225
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_hrst.3800136159
Short name T1345
Test name
Test status
Simulation time 1119007244 ps
CPU time 2.67 seconds
Started Feb 08 01:26:53 PM UTC 25
Finished Feb 08 01:26:57 PM UTC 25
Peak memory 215912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800136159 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_hrst.3800136159
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_intr_smoke.3146847291
Short name T1341
Test name
Test status
Simulation time 3212030172 ps
CPU time 8.88 seconds
Started Feb 08 01:26:40 PM UTC 25
Finished Feb 08 01:26:50 PM UTC 25
Peak memory 232988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146847291 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_smoke.3146847291
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_intr_stress_wr.95988465
Short name T1547
Test name
Test status
Simulation time 25644621646 ps
CPU time 339.01 seconds
Started Feb 08 01:26:41 PM UTC 25
Finished Feb 08 01:32:23 PM UTC 25
Peak memory 3257924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95988
465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.95988465
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull.1627106932
Short name T1350
Test name
Test status
Simulation time 1781252112 ps
CPU time 3.7 seconds
Started Feb 08 01:27:02 PM UTC 25
Finished Feb 08 01:27:07 PM UTC 25
Peak memory 226476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627106932 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_acqfull.1627106932
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull_addr.3746734752
Short name T1353
Test name
Test status
Simulation time 549065220 ps
CPU time 3.69 seconds
Started Feb 08 01:27:04 PM UTC 25
Finished Feb 08 01:27:09 PM UTC 25
Peak memory 215924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746734752 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_acqfull_addr.3746734752
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_perf.833680481
Short name T1290
Test name
Test status
Simulation time 1065282227 ps
CPU time 6.14 seconds
Started Feb 08 01:26:50 PM UTC 25
Finished Feb 08 01:26:57 PM UTC 25
Peak memory 232920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833680481 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_perf.833680481
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_smbus_maxlen.474748762
Short name T1349
Test name
Test status
Simulation time 1854372258 ps
CPU time 3.95 seconds
Started Feb 08 01:27:01 PM UTC 25
Finished Feb 08 01:27:06 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474748762 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smbus_maxlen.474748762
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_smoke.3877124816
Short name T1338
Test name
Test status
Simulation time 3096642797 ps
CPU time 13.48 seconds
Started Feb 08 01:26:34 PM UTC 25
Finished Feb 08 01:26:49 PM UTC 25
Peak memory 226192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877124816 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smoke.3877124816
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_stress_all.1869223888
Short name T1365
Test name
Test status
Simulation time 5883690286 ps
CPU time 45.21 seconds
Started Feb 08 01:26:51 PM UTC 25
Finished Feb 08 01:27:38 PM UTC 25
Peak memory 276060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869223888 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_all.1869223888
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_stress_rd.1303158685
Short name T1347
Test name
Test status
Simulation time 1104023630 ps
CPU time 22.43 seconds
Started Feb 08 01:26:39 PM UTC 25
Finished Feb 08 01:27:03 PM UTC 25
Peak memory 232852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303158685 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_rd.1303158685
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_stress_wr.2707995195
Short name T1381
Test name
Test status
Simulation time 21456665414 ps
CPU time 77.23 seconds
Started Feb 08 01:26:37 PM UTC 25
Finished Feb 08 01:27:56 PM UTC 25
Peak memory 437760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707995195 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_wr.2707995195
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_stretch.2572510874
Short name T1339
Test name
Test status
Simulation time 3300174314 ps
CPU time 8.41 seconds
Started Feb 08 01:26:39 PM UTC 25
Finished Feb 08 01:26:49 PM UTC 25
Peak memory 296720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572510874 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stretch.2572510874
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_timeout.4101964098
Short name T1344
Test name
Test status
Simulation time 1935899048 ps
CPU time 9.52 seconds
Started Feb 08 01:26:44 PM UTC 25
Finished Feb 08 01:26:54 PM UTC 25
Peak memory 226160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101964098 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_timeout.4101964098
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/38.i2c_target_tx_stretch_ctrl.3399486769
Short name T1348
Test name
Test status
Simulation time 258487945 ps
CPU time 4.59 seconds
Started Feb 08 01:26:58 PM UTC 25
Finished Feb 08 01:27:04 PM UTC 25
Peak memory 216120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399486769 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.3399486769
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_alert_test.2410658940
Short name T1393
Test name
Test status
Simulation time 19522815 ps
CPU time 0.98 seconds
Started Feb 08 01:28:00 PM UTC 25
Finished Feb 08 01:28:03 PM UTC 25
Peak memory 213916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410658940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.2410658940
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_error_intr.2522046407
Short name T1362
Test name
Test status
Simulation time 177314447 ps
CPU time 2.82 seconds
Started Feb 08 01:27:27 PM UTC 25
Finished Feb 08 01:27:31 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522046407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_host_error_intr.2522046407
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_fmt_empty.3497414201
Short name T1360
Test name
Test status
Simulation time 1109656244 ps
CPU time 15.08 seconds
Started Feb 08 01:27:09 PM UTC 25
Finished Feb 08 01:27:26 PM UTC 25
Peak memory 247292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497414201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empty.3497414201
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_full.1847890351
Short name T1448
Test name
Test status
Simulation time 2177088481 ps
CPU time 124.28 seconds
Started Feb 08 01:27:10 PM UTC 25
Finished Feb 08 01:29:17 PM UTC 25
Peak memory 478720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847890351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_host_fifo_full.1847890351
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_overflow.16349485
Short name T1438
Test name
Test status
Simulation time 17946032730 ps
CPU time 115.16 seconds
Started Feb 08 01:27:08 PM UTC 25
Finished Feb 08 01:29:06 PM UTC 25
Peak memory 628304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16349485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_host_fifo_overflow.16349485
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_fmt.3430474323
Short name T1356
Test name
Test status
Simulation time 1010919384 ps
CPU time 1.39 seconds
Started Feb 08 01:27:09 PM UTC 25
Finished Feb 08 01:27:12 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430474323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fmt.3430474323
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_rx.2153386878
Short name T1357
Test name
Test status
Simulation time 1587348008 ps
CPU time 5.95 seconds
Started Feb 08 01:27:10 PM UTC 25
Finished Feb 08 01:27:18 PM UTC 25
Peak memory 215960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153386878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.2153386878
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_watermark.324938044
Short name T1533
Test name
Test status
Simulation time 8278404376 ps
CPU time 273.94 seconds
Started Feb 08 01:27:08 PM UTC 25
Finished Feb 08 01:31:46 PM UTC 25
Peak memory 1156552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324938044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_wa
termark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_host_fifo_watermark.324938044
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_may_nack.617597015
Short name T1386
Test name
Test status
Simulation time 259473737 ps
CPU time 5.07 seconds
Started Feb 08 01:27:54 PM UTC 25
Finished Feb 08 01:28:00 PM UTC 25
Peak memory 215892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617597015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nac
k_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 39.i2c_host_may_nack.617597015
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_mode_toggle.416776300
Short name T1379
Test name
Test status
Simulation time 56904375 ps
CPU time 2.16 seconds
Started Feb 08 01:27:53 PM UTC 25
Finished Feb 08 01:27:56 PM UTC 25
Peak memory 226160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416776300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_to
ggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_host_mode_toggle.416776300
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_override.1128357991
Short name T1355
Test name
Test status
Simulation time 26096813 ps
CPU time 1.01 seconds
Started Feb 08 01:27:07 PM UTC 25
Finished Feb 08 01:27:10 PM UTC 25
Peak memory 213920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128357991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 39.i2c_host_override.1128357991
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_perf.3522319664
Short name T1369
Test name
Test status
Simulation time 2974155126 ps
CPU time 32.58 seconds
Started Feb 08 01:27:13 PM UTC 25
Finished Feb 08 01:27:47 PM UTC 25
Peak memory 241164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522319664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_host_perf.3522319664
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_perf_precise.308111096
Short name T1372
Test name
Test status
Simulation time 667276571 ps
CPU time 29.74 seconds
Started Feb 08 01:27:18 PM UTC 25
Finished Feb 08 01:27:50 PM UTC 25
Peak memory 215916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308111096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pr
ecise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_host_perf_precise.308111096
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_smoke.313548538
Short name T1364
Test name
Test status
Simulation time 25562792192 ps
CPU time 29.82 seconds
Started Feb 08 01:27:06 PM UTC 25
Finished Feb 08 01:27:37 PM UTC 25
Peak memory 345548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313548538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_host_smoke.313548538
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_host_stretch_timeout.1767633071
Short name T1367
Test name
Test status
Simulation time 1812227925 ps
CPU time 23.81 seconds
Started Feb 08 01:27:22 PM UTC 25
Finished Feb 08 01:27:47 PM UTC 25
Peak memory 226092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767633071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.i2c_host_stretch_timeout.1767633071
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_bad_addr.1078449447
Short name T1383
Test name
Test status
Simulation time 811500849 ps
CPU time 6.36 seconds
Started Feb 08 01:27:52 PM UTC 25
Finished Feb 08 01:27:59 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1078449447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1078449447
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_acq.2334812937
Short name T1374
Test name
Test status
Simulation time 201642076 ps
CPU time 2.15 seconds
Started Feb 08 01:27:48 PM UTC 25
Finished Feb 08 01:27:52 PM UTC 25
Peak memory 215900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334812937 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_acq.2334812937
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_tx.2343536209
Short name T1375
Test name
Test status
Simulation time 209606641 ps
CPU time 2.21 seconds
Started Feb 08 01:27:49 PM UTC 25
Finished Feb 08 01:27:53 PM UTC 25
Peak memory 216116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343536209 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_tx.2343536209
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_acq.1335612570
Short name T1387
Test name
Test status
Simulation time 1913695278 ps
CPU time 3.8 seconds
Started Feb 08 01:27:56 PM UTC 25
Finished Feb 08 01:28:01 PM UTC 25
Peak memory 215920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335612570 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.1335612570
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_tx.4000090708
Short name T1382
Test name
Test status
Simulation time 113523831 ps
CPU time 1.54 seconds
Started Feb 08 01:27:56 PM UTC 25
Finished Feb 08 01:27:59 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000090708 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.4000090708
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_hrst.3097892360
Short name T1380
Test name
Test status
Simulation time 959593774 ps
CPU time 2.42 seconds
Started Feb 08 01:27:53 PM UTC 25
Finished Feb 08 01:27:56 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097892360 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_hrst.3097892360
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_intr_smoke.2415413726
Short name T1370
Test name
Test status
Simulation time 781808110 ps
CPU time 7.67 seconds
Started Feb 08 01:27:39 PM UTC 25
Finished Feb 08 01:27:48 PM UTC 25
Peak memory 226088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415413726 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_smoke.2415413726
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_intr_stress_wr.3785737914
Short name T1384
Test name
Test status
Simulation time 3869782071 ps
CPU time 12.12 seconds
Started Feb 08 01:27:46 PM UTC 25
Finished Feb 08 01:28:00 PM UTC 25
Peak memory 215904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37857
37914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.3785737914
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull.3290483475
Short name T1391
Test name
Test status
Simulation time 2066837318 ps
CPU time 3.42 seconds
Started Feb 08 01:27:57 PM UTC 25
Finished Feb 08 01:28:02 PM UTC 25
Peak memory 226220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290483475 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_acqfull.3290483475
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull_addr.2664755731
Short name T1388
Test name
Test status
Simulation time 519862809 ps
CPU time 3.07 seconds
Started Feb 08 01:27:57 PM UTC 25
Finished Feb 08 01:28:01 PM UTC 25
Peak memory 215928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664755731 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_acqfull_addr.2664755731
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_nack_txstretch.2974551011
Short name T1392
Test name
Test status
Simulation time 511426835 ps
CPU time 1.83 seconds
Started Feb 08 01:27:59 PM UTC 25
Finished Feb 08 01:28:02 PM UTC 25
Peak memory 231916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974551011 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_txstretch.2974551011
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_perf.1486160114
Short name T1390
Test name
Test status
Simulation time 1794338697 ps
CPU time 9.89 seconds
Started Feb 08 01:27:50 PM UTC 25
Finished Feb 08 01:28:02 PM UTC 25
Peak memory 232944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486160114 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_perf.1486160114
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_smbus_maxlen.805653335
Short name T1389
Test name
Test status
Simulation time 1803977028 ps
CPU time 3.39 seconds
Started Feb 08 01:27:57 PM UTC 25
Finished Feb 08 01:28:02 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805653335 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smbus_maxlen.805653335
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_smoke.117808464
Short name T1366
Test name
Test status
Simulation time 3939986793 ps
CPU time 14.18 seconds
Started Feb 08 01:27:30 PM UTC 25
Finished Feb 08 01:27:46 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117808464 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smoke.117808464
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_stress_all.1537034002
Short name T1504
Test name
Test status
Simulation time 39587808233 ps
CPU time 190.74 seconds
Started Feb 08 01:27:51 PM UTC 25
Finished Feb 08 01:31:04 PM UTC 25
Peak memory 1521392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537034002 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_all.1537034002
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_stress_rd.2670343723
Short name T1426
Test name
Test status
Simulation time 2719611874 ps
CPU time 58.67 seconds
Started Feb 08 01:27:38 PM UTC 25
Finished Feb 08 01:28:38 PM UTC 25
Peak memory 226320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670343723 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_rd.2670343723
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_stress_wr.3791990362
Short name T1397
Test name
Test status
Simulation time 12066223144 ps
CPU time 33.71 seconds
Started Feb 08 01:27:32 PM UTC 25
Finished Feb 08 01:28:07 PM UTC 25
Peak memory 216168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791990362 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_wr.3791990362
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_timeout.1667972353
Short name T1378
Test name
Test status
Simulation time 7952873625 ps
CPU time 6.47 seconds
Started Feb 08 01:27:48 PM UTC 25
Finished Feb 08 01:27:56 PM UTC 25
Peak memory 245256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667972353 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_timeout.1667972353
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/39.i2c_target_tx_stretch_ctrl.4146156205
Short name T1399
Test name
Test status
Simulation time 767403139 ps
CPU time 10.6 seconds
Started Feb 08 01:27:57 PM UTC 25
Finished Feb 08 01:28:09 PM UTC 25
Peak memory 226104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146156205 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.4146156205
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_alert_test.1058357585
Short name T336
Test name
Test status
Simulation time 19500434 ps
CPU time 0.89 seconds
Started Feb 08 12:58:36 PM UTC 25
Finished Feb 08 12:58:39 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058357585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.1058357585
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_host_error_intr.2830182853
Short name T124
Test name
Test status
Simulation time 91618956 ps
CPU time 1.72 seconds
Started Feb 08 12:58:07 PM UTC 25
Finished Feb 08 12:58:10 PM UTC 25
Peak memory 226160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830182853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_host_error_intr.2830182853
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_fmt_empty.2199658484
Short name T122
Test name
Test status
Simulation time 588302624 ps
CPU time 4.81 seconds
Started Feb 08 12:58:02 PM UTC 25
Finished Feb 08 12:58:09 PM UTC 25
Peak memory 261624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199658484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty.2199658484
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_full.3185839459
Short name T341
Test name
Test status
Simulation time 8358580785 ps
CPU time 50.31 seconds
Started Feb 08 12:58:03 PM UTC 25
Finished Feb 08 12:58:55 PM UTC 25
Peak memory 480964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185839459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_host_fifo_full.3185839459
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_overflow.369069806
Short name T389
Test name
Test status
Simulation time 42801746705 ps
CPU time 172.7 seconds
Started Feb 08 12:58:01 PM UTC 25
Finished Feb 08 01:00:57 PM UTC 25
Peak memory 843472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369069806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ov
erflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_host_fifo_overflow.369069806
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_fmt.2467854038
Short name T119
Test name
Test status
Simulation time 154157686 ps
CPU time 1.78 seconds
Started Feb 08 12:58:02 PM UTC 25
Finished Feb 08 12:58:06 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467854038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt.2467854038
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_rx.1574383671
Short name T125
Test name
Test status
Simulation time 730347899 ps
CPU time 6.3 seconds
Started Feb 08 12:58:03 PM UTC 25
Finished Feb 08 12:58:10 PM UTC 25
Peak memory 216156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574383671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.1574383671
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_watermark.3315587260
Short name T473
Test name
Test status
Simulation time 5122528514 ps
CPU time 339.69 seconds
Started Feb 08 12:58:01 PM UTC 25
Finished Feb 08 01:03:45 PM UTC 25
Peak memory 1541572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315587260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.i2c_host_fifo_watermark.3315587260
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_host_override.891837422
Short name T321
Test name
Test status
Simulation time 44887607 ps
CPU time 1.02 seconds
Started Feb 08 12:58:01 PM UTC 25
Finished Feb 08 12:58:04 PM UTC 25
Peak memory 214516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891837422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overrid
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 4.i2c_host_override.891837422
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_host_perf.1077115698
Short name T1749
Test name
Test status
Simulation time 27678469518 ps
CPU time 3413.12 seconds
Started Feb 08 12:58:04 PM UTC 25
Finished Feb 08 01:55:28 PM UTC 25
Peak memory 4406836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077115698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_host_perf.1077115698
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_host_perf_precise.32451291
Short name T120
Test name
Test status
Simulation time 57033458 ps
CPU time 1.54 seconds
Started Feb 08 12:58:05 PM UTC 25
Finished Feb 08 12:58:07 PM UTC 25
Peak memory 234076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32451291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pre
cise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_host_perf_precise.32451291
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_host_smoke.3259361067
Short name T328
Test name
Test status
Simulation time 4457144966 ps
CPU time 27.89 seconds
Started Feb 08 12:57:59 PM UTC 25
Finished Feb 08 12:58:29 PM UTC 25
Peak memory 335380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259361067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_host_smoke.3259361067
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_host_stretch_timeout.929412937
Short name T286
Test name
Test status
Simulation time 860180690 ps
CPU time 16.35 seconds
Started Feb 08 12:58:06 PM UTC 25
Finished Feb 08 12:58:23 PM UTC 25
Peak memory 230232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929412937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch
_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.i2c_host_stretch_timeout.929412937
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_sec_cm.2643111117
Short name T188
Test name
Test status
Simulation time 645579952 ps
CPU time 1.31 seconds
Started Feb 08 12:58:35 PM UTC 25
Finished Feb 08 12:58:38 PM UTC 25
Peak memory 246448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643111117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM
_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2643111117
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_bad_addr.763907230
Short name T329
Test name
Test status
Simulation time 2741118322 ps
CPU time 5.04 seconds
Started Feb 08 12:58:24 PM UTC 25
Finished Feb 08 12:58:30 PM UTC 25
Peak memory 226460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=763907230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.763907230
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_acq.2413237155
Short name T323
Test name
Test status
Simulation time 1750132321 ps
CPU time 1.8 seconds
Started Feb 08 12:58:19 PM UTC 25
Finished Feb 08 12:58:22 PM UTC 25
Peak memory 214524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413237155 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_acq.2413237155
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_tx.426791000
Short name T325
Test name
Test status
Simulation time 169581085 ps
CPU time 1.38 seconds
Started Feb 08 12:58:20 PM UTC 25
Finished Feb 08 12:58:23 PM UTC 25
Peak memory 228196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426791000 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_tx.426791000
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_acq.2161142736
Short name T335
Test name
Test status
Simulation time 2049849082 ps
CPU time 4.96 seconds
Started Feb 08 12:58:30 PM UTC 25
Finished Feb 08 12:58:36 PM UTC 25
Peak memory 216184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161142736 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.2161142736
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_tx.1934929667
Short name T332
Test name
Test status
Simulation time 130818395 ps
CPU time 1.52 seconds
Started Feb 08 12:58:31 PM UTC 25
Finished Feb 08 12:58:34 PM UTC 25
Peak memory 214532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934929667 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.1934929667
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_hrst.3596009301
Short name T327
Test name
Test status
Simulation time 304925390 ps
CPU time 3.51 seconds
Started Feb 08 12:58:24 PM UTC 25
Finished Feb 08 12:58:29 PM UTC 25
Peak memory 226368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596009301 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_hrst.3596009301
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_intr_smoke.1217474355
Short name T322
Test name
Test status
Simulation time 1423105367 ps
CPU time 5.92 seconds
Started Feb 08 12:58:11 PM UTC 25
Finished Feb 08 12:58:18 PM UTC 25
Peak memory 228192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217474355 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_smoke.1217474355
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_intr_stress_wr.3705427577
Short name T210
Test name
Test status
Simulation time 22019949610 ps
CPU time 441.67 seconds
Started Feb 08 12:58:12 PM UTC 25
Finished Feb 08 01:05:39 PM UTC 25
Peak memory 3982852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37054
27577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.3705427577
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull.2786539953
Short name T337
Test name
Test status
Simulation time 1477219040 ps
CPU time 4.75 seconds
Started Feb 08 12:58:33 PM UTC 25
Finished Feb 08 12:58:39 PM UTC 25
Peak memory 226196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786539953 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_acqfull.2786539953
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull_addr.328490296
Short name T338
Test name
Test status
Simulation time 1542920038 ps
CPU time 3.52 seconds
Started Feb 08 12:58:34 PM UTC 25
Finished Feb 08 12:58:39 PM UTC 25
Peak memory 215864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328490296 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.328490296
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_nack_txstretch.3880225127
Short name T165
Test name
Test status
Simulation time 219604717 ps
CPU time 2.3 seconds
Started Feb 08 12:58:34 PM UTC 25
Finished Feb 08 12:58:38 PM UTC 25
Peak memory 233164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880225127 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_txstretch.3880225127
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_perf.3318291749
Short name T330
Test name
Test status
Simulation time 11764536145 ps
CPU time 7.78 seconds
Started Feb 08 12:58:22 PM UTC 25
Finished Feb 08 12:58:31 PM UTC 25
Peak memory 226160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318291749 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_perf.3318291749
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_smbus_maxlen.1088539635
Short name T334
Test name
Test status
Simulation time 1623201615 ps
CPU time 3.04 seconds
Started Feb 08 12:58:31 PM UTC 25
Finished Feb 08 12:58:36 PM UTC 25
Peak memory 215636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088539635 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smbus_maxlen.1088539635
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_smoke.2102825325
Short name T339
Test name
Test status
Simulation time 889413847 ps
CPU time 31.21 seconds
Started Feb 08 12:58:09 PM UTC 25
Finished Feb 08 12:58:42 PM UTC 25
Peak memory 226196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102825325 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smoke.2102825325
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_stress_all.3060274143
Short name T208
Test name
Test status
Simulation time 28023958449 ps
CPU time 160.32 seconds
Started Feb 08 12:58:24 PM UTC 25
Finished Feb 08 01:01:06 PM UTC 25
Peak memory 2205256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060274143 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_all.3060274143
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_stress_rd.3297294902
Short name T260
Test name
Test status
Simulation time 799107335 ps
CPU time 14.77 seconds
Started Feb 08 12:58:11 PM UTC 25
Finished Feb 08 12:58:27 PM UTC 25
Peak memory 220204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297294902 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_rd.3297294902
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_stress_wr.61830442
Short name T374
Test name
Test status
Simulation time 48907786220 ps
CPU time 148.06 seconds
Started Feb 08 12:58:09 PM UTC 25
Finished Feb 08 01:00:40 PM UTC 25
Peak memory 1922620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61830442 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_wr.61830442
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_stretch.2799133727
Short name T340
Test name
Test status
Simulation time 3082801697 ps
CPU time 29.81 seconds
Started Feb 08 12:58:11 PM UTC 25
Finished Feb 08 12:58:42 PM UTC 25
Peak memory 556544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799133727 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stretch.2799133727
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_timeout.1916712421
Short name T326
Test name
Test status
Simulation time 4894478001 ps
CPU time 10.19 seconds
Started Feb 08 12:58:15 PM UTC 25
Finished Feb 08 12:58:27 PM UTC 25
Peak memory 230556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916712421 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_timeout.1916712421
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_target_tx_stretch_ctrl.3384568803
Short name T333
Test name
Test status
Simulation time 90679056 ps
CPU time 2.25 seconds
Started Feb 08 12:58:31 PM UTC 25
Finished Feb 08 12:58:35 PM UTC 25
Peak memory 215864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384568803 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.3384568803
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_alert_test.175961372
Short name T1359
Test name
Test status
Simulation time 28812716 ps
CPU time 0.97 seconds
Started Feb 08 01:28:34 PM UTC 25
Finished Feb 08 01:28:36 PM UTC 25
Peak memory 213740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175961372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM
_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.175961372
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_error_intr.2339809095
Short name T1401
Test name
Test status
Simulation time 491202326 ps
CPU time 3.41 seconds
Started Feb 08 01:28:06 PM UTC 25
Finished Feb 08 01:28:11 PM UTC 25
Peak memory 233132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339809095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_host_error_intr.2339809095
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_fmt_empty.2947549552
Short name T1403
Test name
Test status
Simulation time 472464528 ps
CPU time 9.55 seconds
Started Feb 08 01:28:03 PM UTC 25
Finished Feb 08 01:28:13 PM UTC 25
Peak memory 318940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947549552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empty.2947549552
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_full.3652925038
Short name T1464
Test name
Test status
Simulation time 3028557055 ps
CPU time 86.34 seconds
Started Feb 08 01:28:03 PM UTC 25
Finished Feb 08 01:29:31 PM UTC 25
Peak memory 480856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652925038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_host_fifo_full.3652925038
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_overflow.1537563658
Short name T1446
Test name
Test status
Simulation time 4884992262 ps
CPU time 73.15 seconds
Started Feb 08 01:28:02 PM UTC 25
Finished Feb 08 01:29:17 PM UTC 25
Peak memory 648708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537563658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_host_fifo_overflow.1537563658
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_fmt.3879493810
Short name T1395
Test name
Test status
Simulation time 386745955 ps
CPU time 1.55 seconds
Started Feb 08 01:28:03 PM UTC 25
Finished Feb 08 01:28:05 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879493810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fmt.3879493810
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_rx.3931719139
Short name T1402
Test name
Test status
Simulation time 934184520 ps
CPU time 7.14 seconds
Started Feb 08 01:28:03 PM UTC 25
Finished Feb 08 01:28:11 PM UTC 25
Peak memory 261540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931719139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.3931719139
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_watermark.3590318027
Short name T1528
Test name
Test status
Simulation time 3064467201 ps
CPU time 212.04 seconds
Started Feb 08 01:28:01 PM UTC 25
Finished Feb 08 01:31:37 PM UTC 25
Peak memory 923152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590318027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 40.i2c_host_fifo_watermark.3590318027
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_may_nack.1118450807
Short name T1432
Test name
Test status
Simulation time 1708672027 ps
CPU time 20.07 seconds
Started Feb 08 01:28:27 PM UTC 25
Finished Feb 08 01:28:49 PM UTC 25
Peak memory 215964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118450807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 40.i2c_host_may_nack.1118450807
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_mode_toggle.3175457933
Short name T1416
Test name
Test status
Simulation time 336769093 ps
CPU time 1.82 seconds
Started Feb 08 01:28:26 PM UTC 25
Finished Feb 08 01:28:29 PM UTC 25
Peak memory 226156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175457933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_t
oggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_host_mode_toggle.3175457933
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_override.3674651433
Short name T1394
Test name
Test status
Simulation time 86363543 ps
CPU time 1.1 seconds
Started Feb 08 01:28:00 PM UTC 25
Finished Feb 08 01:28:03 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674651433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 40.i2c_host_override.3674651433
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_perf.2502830914
Short name T1436
Test name
Test status
Simulation time 25464022936 ps
CPU time 58.33 seconds
Started Feb 08 01:28:04 PM UTC 25
Finished Feb 08 01:29:04 PM UTC 25
Peak memory 237004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502830914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_host_perf.2502830914
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_perf_precise.2550904549
Short name T1398
Test name
Test status
Simulation time 66524397 ps
CPU time 3.73 seconds
Started Feb 08 01:28:04 PM UTC 25
Finished Feb 08 01:28:09 PM UTC 25
Peak memory 226268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550904549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_host_perf_precise.2550904549
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_smoke.815570134
Short name T1421
Test name
Test status
Simulation time 1655783432 ps
CPU time 32.61 seconds
Started Feb 08 01:28:00 PM UTC 25
Finished Feb 08 01:28:34 PM UTC 25
Peak memory 427460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815570134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_host_smoke.815570134
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_host_stretch_timeout.2380422825
Short name T1410
Test name
Test status
Simulation time 443176981 ps
CPU time 20.16 seconds
Started Feb 08 01:28:04 PM UTC 25
Finished Feb 08 01:28:26 PM UTC 25
Peak memory 226460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380422825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_host_stretch_timeout.2380422825
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_bad_addr.3161676157
Short name T1419
Test name
Test status
Simulation time 1968086802 ps
CPU time 7.35 seconds
Started Feb 08 01:28:24 PM UTC 25
Finished Feb 08 01:28:33 PM UTC 25
Peak memory 226220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3161676157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3161676157
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_acq.1749827319
Short name T1407
Test name
Test status
Simulation time 208336518 ps
CPU time 2.08 seconds
Started Feb 08 01:28:18 PM UTC 25
Finished Feb 08 01:28:21 PM UTC 25
Peak memory 215712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749827319 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_acq.1749827319
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_tx.2004075971
Short name T1408
Test name
Test status
Simulation time 153690277 ps
CPU time 1.88 seconds
Started Feb 08 01:28:20 PM UTC 25
Finished Feb 08 01:28:23 PM UTC 25
Peak memory 216172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004075971 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_tx.2004075971
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_acq.3279020974
Short name T1417
Test name
Test status
Simulation time 534921230 ps
CPU time 1.25 seconds
Started Feb 08 01:28:28 PM UTC 25
Finished Feb 08 01:28:31 PM UTC 25
Peak memory 214524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279020974 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.3279020974
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_tx.3377849347
Short name T1418
Test name
Test status
Simulation time 379250308 ps
CPU time 1.74 seconds
Started Feb 08 01:28:29 PM UTC 25
Finished Feb 08 01:28:32 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377849347 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.3377849347
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_hrst.4036889613
Short name T1415
Test name
Test status
Simulation time 4591115791 ps
CPU time 2.33 seconds
Started Feb 08 01:28:25 PM UTC 25
Finished Feb 08 01:28:29 PM UTC 25
Peak memory 226160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036889613 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_hrst.4036889613
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_intr_smoke.719198472
Short name T1405
Test name
Test status
Simulation time 1231794218 ps
CPU time 5.81 seconds
Started Feb 08 01:28:11 PM UTC 25
Finished Feb 08 01:28:19 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719198472 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_smoke.719198472
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_intr_stress_wr.1060251057
Short name T1420
Test name
Test status
Simulation time 10564163361 ps
CPU time 19.68 seconds
Started Feb 08 01:28:12 PM UTC 25
Finished Feb 08 01:28:33 PM UTC 25
Peak memory 411404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10602
51057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.1060251057
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull.833119265
Short name T1352
Test name
Test status
Simulation time 561756560 ps
CPU time 3.88 seconds
Started Feb 08 01:28:31 PM UTC 25
Finished Feb 08 01:28:36 PM UTC 25
Peak memory 226156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833119265 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_acqfull.833119265
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull_addr.2237548615
Short name T1423
Test name
Test status
Simulation time 918421150 ps
CPU time 3.85 seconds
Started Feb 08 01:28:32 PM UTC 25
Finished Feb 08 01:28:37 PM UTC 25
Peak memory 215924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237548615 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_acqfull_addr.2237548615
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_nack_txstretch.4122563072
Short name T1424
Test name
Test status
Simulation time 551805431 ps
CPU time 1.76 seconds
Started Feb 08 01:28:34 PM UTC 25
Finished Feb 08 01:28:37 PM UTC 25
Peak memory 232040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122563072 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_txstretch.4122563072
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_perf.1818228365
Short name T1412
Test name
Test status
Simulation time 4252300338 ps
CPU time 5.55 seconds
Started Feb 08 01:28:21 PM UTC 25
Finished Feb 08 01:28:28 PM UTC 25
Peak memory 226472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818228365 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_perf.1818228365
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_smbus_maxlen.2220030946
Short name T1373
Test name
Test status
Simulation time 585887889 ps
CPU time 3.89 seconds
Started Feb 08 01:28:29 PM UTC 25
Finished Feb 08 01:28:35 PM UTC 25
Peak memory 215640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220030946 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smbus_maxlen.2220030946
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_smoke.3666696623
Short name T1406
Test name
Test status
Simulation time 656134054 ps
CPU time 10.49 seconds
Started Feb 08 01:28:08 PM UTC 25
Finished Feb 08 01:28:20 PM UTC 25
Peak memory 232956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666696623 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smoke.3666696623
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_stress_all.1195429596
Short name T1548
Test name
Test status
Simulation time 69589923969 ps
CPU time 240.3 seconds
Started Feb 08 01:28:22 PM UTC 25
Finished Feb 08 01:32:25 PM UTC 25
Peak memory 1336888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195429596 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_all.1195429596
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_stress_rd.1073055773
Short name T1411
Test name
Test status
Simulation time 726313657 ps
CPU time 14.94 seconds
Started Feb 08 01:28:10 PM UTC 25
Finished Feb 08 01:28:27 PM UTC 25
Peak memory 220032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073055773 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_rd.1073055773
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_stress_wr.3118833350
Short name T1580
Test name
Test status
Simulation time 41691077657 ps
CPU time 304.89 seconds
Started Feb 08 01:28:09 PM UTC 25
Finished Feb 08 01:33:18 PM UTC 25
Peak memory 2911808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118833350 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_wr.3118833350
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_stretch.4197438189
Short name T1404
Test name
Test status
Simulation time 2857764527 ps
CPU time 2.38 seconds
Started Feb 08 01:28:10 PM UTC 25
Finished Feb 08 01:28:14 PM UTC 25
Peak memory 230352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197438189 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stretch.4197438189
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_timeout.123789772
Short name T1413
Test name
Test status
Simulation time 1456575491 ps
CPU time 12.09 seconds
Started Feb 08 01:28:15 PM UTC 25
Finished Feb 08 01:28:28 PM UTC 25
Peak memory 243472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123789772 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_timeout.123789772
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_tx_stretch_ctrl.3194931337
Short name T1428
Test name
Test status
Simulation time 404578669 ps
CPU time 10.91 seconds
Started Feb 08 01:28:29 PM UTC 25
Finished Feb 08 01:28:42 PM UTC 25
Peak memory 215864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194931337 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.3194931337
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_alert_test.1124463736
Short name T1456
Test name
Test status
Simulation time 38657155 ps
CPU time 0.85 seconds
Started Feb 08 01:29:21 PM UTC 25
Finished Feb 08 01:29:23 PM UTC 25
Peak memory 215416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124463736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.1124463736
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_error_intr.4165605118
Short name T1431
Test name
Test status
Simulation time 104368224 ps
CPU time 4.81 seconds
Started Feb 08 01:28:42 PM UTC 25
Finished Feb 08 01:28:48 PM UTC 25
Peak memory 232548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165605118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_host_error_intr.4165605118
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_fmt_empty.2236769784
Short name T1434
Test name
Test status
Simulation time 1205462814 ps
CPU time 18.68 seconds
Started Feb 08 01:28:37 PM UTC 25
Finished Feb 08 01:28:57 PM UTC 25
Peak memory 280052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236769784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empty.2236769784
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_full.3059458116
Short name T1500
Test name
Test status
Simulation time 2154094607 ps
CPU time 125.62 seconds
Started Feb 08 01:28:37 PM UTC 25
Finished Feb 08 01:30:45 PM UTC 25
Peak memory 419324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059458116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_host_fifo_full.3059458116
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_overflow.3555235667
Short name T1476
Test name
Test status
Simulation time 13613475325 ps
CPU time 87.79 seconds
Started Feb 08 01:28:36 PM UTC 25
Finished Feb 08 01:30:06 PM UTC 25
Peak memory 945876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555235667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_host_fifo_overflow.3555235667
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_fmt.718018643
Short name T1427
Test name
Test status
Simulation time 209834830 ps
CPU time 1.34 seconds
Started Feb 08 01:28:37 PM UTC 25
Finished Feb 08 01:28:40 PM UTC 25
Peak memory 214516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718018643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fmt.718018643
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_rx.1135798502
Short name T1430
Test name
Test status
Simulation time 453332641 ps
CPU time 7.66 seconds
Started Feb 08 01:28:37 PM UTC 25
Finished Feb 08 01:28:46 PM UTC 25
Peak memory 235076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135798502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.1135798502
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_watermark.3078910402
Short name T1502
Test name
Test status
Simulation time 22644064440 ps
CPU time 136.57 seconds
Started Feb 08 01:28:36 PM UTC 25
Finished Feb 08 01:30:55 PM UTC 25
Peak memory 1599052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078910402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 41.i2c_host_fifo_watermark.3078910402
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_may_nack.1814946923
Short name T1461
Test name
Test status
Simulation time 2175192385 ps
CPU time 9.25 seconds
Started Feb 08 01:29:16 PM UTC 25
Finished Feb 08 01:29:26 PM UTC 25
Peak memory 216044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814946923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 41.i2c_host_may_nack.1814946923
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_mode_toggle.3229771475
Short name T1451
Test name
Test status
Simulation time 133034934 ps
CPU time 5.44 seconds
Started Feb 08 01:29:13 PM UTC 25
Finished Feb 08 01:29:19 PM UTC 25
Peak memory 215916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229771475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_t
oggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_host_mode_toggle.3229771475
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_override.2771887029
Short name T1425
Test name
Test status
Simulation time 45239730 ps
CPU time 0.97 seconds
Started Feb 08 01:28:35 PM UTC 25
Finished Feb 08 01:28:37 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771887029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 41.i2c_host_override.2771887029
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_perf.906272036
Short name T1743
Test name
Test status
Simulation time 12557235669 ps
CPU time 978.76 seconds
Started Feb 08 01:28:38 PM UTC 25
Finished Feb 08 01:45:07 PM UTC 25
Peak memory 1695228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906272036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_host_perf.906272036
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_perf_precise.1784553802
Short name T1429
Test name
Test status
Simulation time 94574798 ps
CPU time 2.62 seconds
Started Feb 08 01:28:39 PM UTC 25
Finished Feb 08 01:28:43 PM UTC 25
Peak memory 236396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784553802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_host_perf_precise.1784553802
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_smoke.1578772353
Short name T1465
Test name
Test status
Simulation time 3993039534 ps
CPU time 58.82 seconds
Started Feb 08 01:28:34 PM UTC 25
Finished Feb 08 01:29:34 PM UTC 25
Peak memory 298320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578772353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_host_smoke.1578772353
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_stretch_timeout.2489600177
Short name T1435
Test name
Test status
Simulation time 3671893268 ps
CPU time 17.9 seconds
Started Feb 08 01:28:40 PM UTC 25
Finished Feb 08 01:29:00 PM UTC 25
Peak memory 232404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489600177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.i2c_host_stretch_timeout.2489600177
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_bad_addr.391200445
Short name T1450
Test name
Test status
Simulation time 2052903718 ps
CPU time 6.86 seconds
Started Feb 08 01:29:10 PM UTC 25
Finished Feb 08 01:29:18 PM UTC 25
Peak memory 232916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=391200445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.391200445
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_acq.1774213899
Short name T1441
Test name
Test status
Simulation time 578416967 ps
CPU time 1.49 seconds
Started Feb 08 01:29:07 PM UTC 25
Finished Feb 08 01:29:10 PM UTC 25
Peak memory 216240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774213899 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_acq.1774213899
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_tx.1233138130
Short name T1442
Test name
Test status
Simulation time 314011715 ps
CPU time 3.25 seconds
Started Feb 08 01:29:07 PM UTC 25
Finished Feb 08 01:29:12 PM UTC 25
Peak memory 215980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233138130 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_tx.1233138130
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_acq.158790450
Short name T1454
Test name
Test status
Simulation time 1133867220 ps
CPU time 2.6 seconds
Started Feb 08 01:29:18 PM UTC 25
Finished Feb 08 01:29:22 PM UTC 25
Peak memory 215900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158790450 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.158790450
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_tx.1819565444
Short name T1452
Test name
Test status
Simulation time 879760762 ps
CPU time 1.49 seconds
Started Feb 08 01:29:18 PM UTC 25
Finished Feb 08 01:29:20 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819565444 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.1819565444
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_hrst.2354087799
Short name T1447
Test name
Test status
Simulation time 1153811929 ps
CPU time 3.17 seconds
Started Feb 08 01:29:13 PM UTC 25
Finished Feb 08 01:29:17 PM UTC 25
Peak memory 226160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354087799 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_hrst.2354087799
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_intr_smoke.958465050
Short name T1440
Test name
Test status
Simulation time 970296040 ps
CPU time 7.78 seconds
Started Feb 08 01:28:58 PM UTC 25
Finished Feb 08 01:29:07 PM UTC 25
Peak memory 226212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958465050 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_smoke.958465050
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull.1710769359
Short name T1460
Test name
Test status
Simulation time 2280051750 ps
CPU time 5 seconds
Started Feb 08 01:29:19 PM UTC 25
Finished Feb 08 01:29:25 PM UTC 25
Peak memory 226272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710769359 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_acqfull.1710769359
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull_addr.853612765
Short name T1459
Test name
Test status
Simulation time 536586737 ps
CPU time 4.26 seconds
Started Feb 08 01:29:19 PM UTC 25
Finished Feb 08 01:29:24 PM UTC 25
Peak memory 215924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853612765 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_acqfull_addr.853612765
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_nack_txstretch.1011759398
Short name T1457
Test name
Test status
Simulation time 272223565 ps
CPU time 2.42 seconds
Started Feb 08 01:29:20 PM UTC 25
Finished Feb 08 01:29:24 PM UTC 25
Peak memory 233164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011759398 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_txstretch.1011759398
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_perf.3732289268
Short name T1444
Test name
Test status
Simulation time 856538074 ps
CPU time 5.45 seconds
Started Feb 08 01:29:08 PM UTC 25
Finished Feb 08 01:29:15 PM UTC 25
Peak memory 230300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732289268 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_perf.3732289268
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_smbus_maxlen.166144322
Short name T1455
Test name
Test status
Simulation time 743853885 ps
CPU time 2.99 seconds
Started Feb 08 01:29:18 PM UTC 25
Finished Feb 08 01:29:22 PM UTC 25
Peak memory 215640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166144322 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smbus_maxlen.166144322
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_smoke.2109429876
Short name T1449
Test name
Test status
Simulation time 3146636503 ps
CPU time 29.27 seconds
Started Feb 08 01:28:47 PM UTC 25
Finished Feb 08 01:29:17 PM UTC 25
Peak memory 226192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109429876 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smoke.2109429876
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_stress_all.1878198439
Short name T1733
Test name
Test status
Simulation time 85752089722 ps
CPU time 713.75 seconds
Started Feb 08 01:29:09 PM UTC 25
Finished Feb 08 01:41:10 PM UTC 25
Peak memory 3163644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878198439 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_all.1878198439
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_stress_rd.1531992105
Short name T1439
Test name
Test status
Simulation time 3680105536 ps
CPU time 15.47 seconds
Started Feb 08 01:28:50 PM UTC 25
Finished Feb 08 01:29:07 PM UTC 25
Peak memory 232908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531992105 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_rd.1531992105
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_stress_wr.3549795235
Short name T1437
Test name
Test status
Simulation time 16181062025 ps
CPU time 13.41 seconds
Started Feb 08 01:28:50 PM UTC 25
Finished Feb 08 01:29:05 PM UTC 25
Peak memory 216036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549795235 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_wr.3549795235
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_stretch.3525750616
Short name T1468
Test name
Test status
Simulation time 4283215488 ps
CPU time 39.33 seconds
Started Feb 08 01:28:58 PM UTC 25
Finished Feb 08 01:29:39 PM UTC 25
Peak memory 630476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525750616 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stretch.3525750616
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_timeout.827967995
Short name T1445
Test name
Test status
Simulation time 4845858265 ps
CPU time 10.22 seconds
Started Feb 08 01:29:05 PM UTC 25
Finished Feb 08 01:29:17 PM UTC 25
Peak memory 233172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827967995 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_timeout.827967995
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_tx_stretch_ctrl.602644084
Short name T1453
Test name
Test status
Simulation time 79105379 ps
CPU time 2.2 seconds
Started Feb 08 01:29:18 PM UTC 25
Finished Feb 08 01:29:21 PM UTC 25
Peak memory 216184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602644084 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.602644084
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_alert_test.2456776090
Short name T1491
Test name
Test status
Simulation time 20927940 ps
CPU time 0.97 seconds
Started Feb 08 01:30:26 PM UTC 25
Finished Feb 08 01:30:28 PM UTC 25
Peak memory 214936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456776090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.2456776090
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_error_intr.2991790564
Short name T1466
Test name
Test status
Simulation time 773796498 ps
CPU time 1.84 seconds
Started Feb 08 01:29:32 PM UTC 25
Finished Feb 08 01:29:35 PM UTC 25
Peak memory 216296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991790564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_host_error_intr.2991790564
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_fmt_empty.866993653
Short name T1467
Test name
Test status
Simulation time 908857320 ps
CPU time 9.15 seconds
Started Feb 08 01:29:26 PM UTC 25
Finished Feb 08 01:29:36 PM UTC 25
Peak memory 314888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866993653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empty.866993653
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_full.4028521584
Short name T1505
Test name
Test status
Simulation time 2446543005 ps
CPU time 100.95 seconds
Started Feb 08 01:29:26 PM UTC 25
Finished Feb 08 01:31:09 PM UTC 25
Peak memory 577096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028521584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_host_fifo_full.4028521584
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_overflow.2235784361
Short name T1536
Test name
Test status
Simulation time 1967079810 ps
CPU time 147.79 seconds
Started Feb 08 01:29:24 PM UTC 25
Finished Feb 08 01:31:55 PM UTC 25
Peak memory 714180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235784361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_host_fifo_overflow.2235784361
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_fmt.2933236710
Short name T1462
Test name
Test status
Simulation time 272974838 ps
CPU time 1.6 seconds
Started Feb 08 01:29:24 PM UTC 25
Finished Feb 08 01:29:27 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933236710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fmt.2933236710
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_rx.2183093289
Short name T1463
Test name
Test status
Simulation time 126856886 ps
CPU time 4.13 seconds
Started Feb 08 01:29:26 PM UTC 25
Finished Feb 08 01:29:31 PM UTC 25
Peak memory 215960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183093289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.2183093289
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.2176517846
Short name T1498
Test name
Test status
Simulation time 3661158646 ps
CPU time 77.34 seconds
Started Feb 08 01:29:23 PM UTC 25
Finished Feb 08 01:30:43 PM UTC 25
Peak memory 964104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176517846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 42.i2c_host_fifo_watermark.2176517846
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_may_nack.2339798442
Short name T1484
Test name
Test status
Simulation time 221288697 ps
CPU time 4.67 seconds
Started Feb 08 01:30:14 PM UTC 25
Finished Feb 08 01:30:20 PM UTC 25
Peak memory 216220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339798442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 42.i2c_host_may_nack.2339798442
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_mode_toggle.366158546
Short name T1482
Test name
Test status
Simulation time 711947203 ps
CPU time 4.45 seconds
Started Feb 08 01:30:13 PM UTC 25
Finished Feb 08 01:30:19 PM UTC 25
Peak memory 253448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366158546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_to
ggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_host_mode_toggle.366158546
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_override.674764286
Short name T1458
Test name
Test status
Simulation time 81640004 ps
CPU time 0.87 seconds
Started Feb 08 01:29:22 PM UTC 25
Finished Feb 08 01:29:24 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674764286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overrid
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 42.i2c_host_override.674764286
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_perf.2512539661
Short name T1736
Test name
Test status
Simulation time 27466634150 ps
CPU time 732 seconds
Started Feb 08 01:29:27 PM UTC 25
Finished Feb 08 01:41:46 PM UTC 25
Peak memory 2793272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512539661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_host_perf.2512539661
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_perf_precise.125703144
Short name T1585
Test name
Test status
Simulation time 5890727122 ps
CPU time 235.61 seconds
Started Feb 08 01:29:28 PM UTC 25
Finished Feb 08 01:33:27 PM UTC 25
Peak memory 215980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125703144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pr
ecise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_host_perf_precise.125703144
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_smoke.2640601525
Short name T1473
Test name
Test status
Simulation time 2124363370 ps
CPU time 36.18 seconds
Started Feb 08 01:29:22 PM UTC 25
Finished Feb 08 01:30:00 PM UTC 25
Peak memory 364228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640601525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_host_smoke.2640601525
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_stretch_timeout.1184081934
Short name T1469
Test name
Test status
Simulation time 9002139281 ps
CPU time 15.51 seconds
Started Feb 08 01:29:32 PM UTC 25
Finished Feb 08 01:29:49 PM UTC 25
Peak memory 243532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184081934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.i2c_host_stretch_timeout.1184081934
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_bad_addr.1998727796
Short name T1480
Test name
Test status
Simulation time 411694388 ps
CPU time 4.14 seconds
Started Feb 08 01:30:08 PM UTC 25
Finished Feb 08 01:30:13 PM UTC 25
Peak memory 230120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1998727796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.1998727796
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_acq.2884739840
Short name T1475
Test name
Test status
Simulation time 230605665 ps
CPU time 1.64 seconds
Started Feb 08 01:30:01 PM UTC 25
Finished Feb 08 01:30:03 PM UTC 25
Peak memory 226168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884739840 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_acq.2884739840
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_tx.3881062268
Short name T1477
Test name
Test status
Simulation time 235890153 ps
CPU time 1.74 seconds
Started Feb 08 01:30:04 PM UTC 25
Finished Feb 08 01:30:07 PM UTC 25
Peak memory 216172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881062268 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_tx.3881062268
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_acq.1294394131
Short name T1483
Test name
Test status
Simulation time 1328377226 ps
CPU time 3.45 seconds
Started Feb 08 01:30:15 PM UTC 25
Finished Feb 08 01:30:20 PM UTC 25
Peak memory 215712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294394131 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.1294394131
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_tx.2235653530
Short name T1488
Test name
Test status
Simulation time 489406263 ps
CPU time 2.47 seconds
Started Feb 08 01:30:19 PM UTC 25
Finished Feb 08 01:30:23 PM UTC 25
Peak memory 215716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235653530 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.2235653530
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_hrst.43825244
Short name T1479
Test name
Test status
Simulation time 561972852 ps
CPU time 3.28 seconds
Started Feb 08 01:30:08 PM UTC 25
Finished Feb 08 01:30:12 PM UTC 25
Peak memory 228264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43825244 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_hrst.43825244
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_intr_smoke.2119996611
Short name T1472
Test name
Test status
Simulation time 1066501298 ps
CPU time 8.8 seconds
Started Feb 08 01:29:49 PM UTC 25
Finished Feb 08 01:29:59 PM UTC 25
Peak memory 226344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119996611 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_smoke.2119996611
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_intr_stress_wr.153738261
Short name T1501
Test name
Test status
Simulation time 23386950648 ps
CPU time 57.13 seconds
Started Feb 08 01:29:53 PM UTC 25
Finished Feb 08 01:30:52 PM UTC 25
Peak memory 872008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15373
8261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.153738261
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull.2268407451
Short name T1493
Test name
Test status
Simulation time 2073090260 ps
CPU time 4.59 seconds
Started Feb 08 01:30:24 PM UTC 25
Finished Feb 08 01:30:29 PM UTC 25
Peak memory 225684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268407451 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_acqfull.2268407451
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull_addr.1724046480
Short name T1492
Test name
Test status
Simulation time 1601051892 ps
CPU time 3.65 seconds
Started Feb 08 01:30:24 PM UTC 25
Finished Feb 08 01:30:28 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724046480 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_acqfull_addr.1724046480
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_perf.3196951698
Short name T1481
Test name
Test status
Simulation time 730591150 ps
CPU time 8.76 seconds
Started Feb 08 01:30:05 PM UTC 25
Finished Feb 08 01:30:15 PM UTC 25
Peak memory 226276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196951698 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_perf.3196951698
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_smbus_maxlen.4035724931
Short name T1490
Test name
Test status
Simulation time 3028527236 ps
CPU time 4.13 seconds
Started Feb 08 01:30:20 PM UTC 25
Finished Feb 08 01:30:26 PM UTC 25
Peak memory 215768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035724931 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smbus_maxlen.4035724931
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_smoke.475888761
Short name T1486
Test name
Test status
Simulation time 18648448822 ps
CPU time 44.63 seconds
Started Feb 08 01:29:36 PM UTC 25
Finished Feb 08 01:30:22 PM UTC 25
Peak memory 226196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475888761 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smoke.475888761
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.321161026
Short name T1558
Test name
Test status
Simulation time 19869923963 ps
CPU time 144.44 seconds
Started Feb 08 01:30:07 PM UTC 25
Finished Feb 08 01:32:34 PM UTC 25
Peak memory 1369616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321161026 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_all.321161026
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_stress_rd.1527567590
Short name T1496
Test name
Test status
Simulation time 5289464564 ps
CPU time 54.63 seconds
Started Feb 08 01:29:39 PM UTC 25
Finished Feb 08 01:30:35 PM UTC 25
Peak memory 230364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527567590 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_rd.1527567590
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.274166838
Short name T1731
Test name
Test status
Simulation time 55132547547 ps
CPU time 653.17 seconds
Started Feb 08 01:29:37 PM UTC 25
Finished Feb 08 01:40:37 PM UTC 25
Peak memory 4507140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274166838 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_wr.274166838
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_stretch.2545578283
Short name T1471
Test name
Test status
Simulation time 208738520 ps
CPU time 2.06 seconds
Started Feb 08 01:29:49 PM UTC 25
Finished Feb 08 01:29:53 PM UTC 25
Peak memory 216216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545578283 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stretch.2545578283
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_timeout.3070990397
Short name T1478
Test name
Test status
Simulation time 5945135379 ps
CPU time 10.32 seconds
Started Feb 08 01:29:55 PM UTC 25
Finished Feb 08 01:30:07 PM UTC 25
Peak memory 233292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070990397 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_timeout.3070990397
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_tx_stretch_ctrl.309868562
Short name T1489
Test name
Test status
Simulation time 109898347 ps
CPU time 3.42 seconds
Started Feb 08 01:30:20 PM UTC 25
Finished Feb 08 01:30:25 PM UTC 25
Peak memory 215852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309868562 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.309868562
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_alert_test.1746142569
Short name T1525
Test name
Test status
Simulation time 43287698 ps
CPU time 0.88 seconds
Started Feb 08 01:31:31 PM UTC 25
Finished Feb 08 01:31:34 PM UTC 25
Peak memory 214936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746142569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1746142569
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_error_intr.4234144902
Short name T1485
Test name
Test status
Simulation time 2634473776 ps
CPU time 2.95 seconds
Started Feb 08 01:30:47 PM UTC 25
Finished Feb 08 01:30:51 PM UTC 25
Peak memory 243448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234144902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_host_error_intr.4234144902
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_fmt_empty.3358423902
Short name T1499
Test name
Test status
Simulation time 2417243385 ps
CPU time 10.29 seconds
Started Feb 08 01:30:31 PM UTC 25
Finished Feb 08 01:30:43 PM UTC 25
Peak memory 271940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358423902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empty.3358423902
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_full.2778412829
Short name T1563
Test name
Test status
Simulation time 1795089461 ps
CPU time 119.28 seconds
Started Feb 08 01:30:36 PM UTC 25
Finished Feb 08 01:32:38 PM UTC 25
Peak memory 515732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778412829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_host_fifo_full.2778412829
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_overflow.3746896644
Short name T1544
Test name
Test status
Simulation time 2755476070 ps
CPU time 105.74 seconds
Started Feb 08 01:30:29 PM UTC 25
Finished Feb 08 01:32:17 PM UTC 25
Peak memory 902720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746896644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_host_fifo_overflow.3746896644
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_fmt.1545404214
Short name T1495
Test name
Test status
Simulation time 285037863 ps
CPU time 1.36 seconds
Started Feb 08 01:30:30 PM UTC 25
Finished Feb 08 01:30:33 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545404214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fmt.1545404214
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_rx.3233906453
Short name T1497
Test name
Test status
Simulation time 738207105 ps
CPU time 5.47 seconds
Started Feb 08 01:30:33 PM UTC 25
Finished Feb 08 01:30:40 PM UTC 25
Peak memory 215916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233906453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.3233906453
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.3888784293
Short name T1648
Test name
Test status
Simulation time 6941563199 ps
CPU time 290.87 seconds
Started Feb 08 01:30:29 PM UTC 25
Finished Feb 08 01:35:24 PM UTC 25
Peak memory 1261128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888784293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 43.i2c_host_fifo_watermark.3888784293
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_may_nack.2978252035
Short name T1531
Test name
Test status
Simulation time 443191826 ps
CPU time 20.44 seconds
Started Feb 08 01:31:21 PM UTC 25
Finished Feb 08 01:31:43 PM UTC 25
Peak memory 216112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978252035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 43.i2c_host_may_nack.2978252035
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_mode_toggle.592708429
Short name T1517
Test name
Test status
Simulation time 966850932 ps
CPU time 3.04 seconds
Started Feb 08 01:31:20 PM UTC 25
Finished Feb 08 01:31:24 PM UTC 25
Peak memory 232888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592708429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_to
ggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_host_mode_toggle.592708429
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_override.3367534403
Short name T1494
Test name
Test status
Simulation time 29493416 ps
CPU time 0.95 seconds
Started Feb 08 01:30:28 PM UTC 25
Finished Feb 08 01:30:30 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367534403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 43.i2c_host_override.3367534403
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_perf.342540504
Short name T1515
Test name
Test status
Simulation time 3385515570 ps
CPU time 38.9 seconds
Started Feb 08 01:30:40 PM UTC 25
Finished Feb 08 01:31:21 PM UTC 25
Peak memory 226340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342540504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_host_perf.342540504
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_perf_precise.3184135190
Short name T1521
Test name
Test status
Simulation time 1755992452 ps
CPU time 42.46 seconds
Started Feb 08 01:30:43 PM UTC 25
Finished Feb 08 01:31:28 PM UTC 25
Peak memory 225992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184135190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_host_perf_precise.3184135190
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_smoke.3220832432
Short name T1474
Test name
Test status
Simulation time 1308243185 ps
CPU time 23.68 seconds
Started Feb 08 01:30:27 PM UTC 25
Finished Feb 08 01:30:52 PM UTC 25
Peak memory 347652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220832432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_host_smoke.3220832432
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_stretch_timeout.318978309
Short name T1506
Test name
Test status
Simulation time 1007271694 ps
CPU time 24.61 seconds
Started Feb 08 01:30:43 PM UTC 25
Finished Feb 08 01:31:10 PM UTC 25
Peak memory 226196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318978309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch
_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 43.i2c_host_stretch_timeout.318978309
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_bad_addr.2565676007
Short name T1516
Test name
Test status
Simulation time 528482191 ps
CPU time 3.5 seconds
Started Feb 08 01:31:18 PM UTC 25
Finished Feb 08 01:31:23 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2565676007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.2565676007
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_acq.2045790286
Short name T1510
Test name
Test status
Simulation time 223516159 ps
CPU time 1.89 seconds
Started Feb 08 01:31:13 PM UTC 25
Finished Feb 08 01:31:17 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045790286 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_acq.2045790286
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_tx.562134320
Short name T1513
Test name
Test status
Simulation time 525066229 ps
CPU time 1.92 seconds
Started Feb 08 01:31:15 PM UTC 25
Finished Feb 08 01:31:19 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562134320 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_tx.562134320
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_acq.3277611473
Short name T1519
Test name
Test status
Simulation time 414959744 ps
CPU time 3.39 seconds
Started Feb 08 01:31:22 PM UTC 25
Finished Feb 08 01:31:26 PM UTC 25
Peak memory 216220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277611473 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.3277611473
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_tx.1052048897
Short name T1520
Test name
Test status
Simulation time 124508714 ps
CPU time 1.57 seconds
Started Feb 08 01:31:24 PM UTC 25
Finished Feb 08 01:31:27 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052048897 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.1052048897
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_intr_smoke.1037381087
Short name T1508
Test name
Test status
Simulation time 1555365991 ps
CPU time 7.69 seconds
Started Feb 08 01:31:05 PM UTC 25
Finished Feb 08 01:31:14 PM UTC 25
Peak memory 230244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037381087 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_smoke.1037381087
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_intr_stress_wr.2456844601
Short name T1522
Test name
Test status
Simulation time 8233161506 ps
CPU time 19.01 seconds
Started Feb 08 01:31:10 PM UTC 25
Finished Feb 08 01:31:30 PM UTC 25
Peak memory 476736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24568
44601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2456844601
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull.2784120384
Short name T1524
Test name
Test status
Simulation time 2272106284 ps
CPU time 4.41 seconds
Started Feb 08 01:31:27 PM UTC 25
Finished Feb 08 01:31:33 PM UTC 25
Peak memory 226536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784120384 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_acqfull.2784120384
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull_addr.2641431996
Short name T1526
Test name
Test status
Simulation time 2113406682 ps
CPU time 5.13 seconds
Started Feb 08 01:31:27 PM UTC 25
Finished Feb 08 01:31:34 PM UTC 25
Peak memory 215940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641431996 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_acqfull_addr.2641431996
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_perf.1843070212
Short name T1518
Test name
Test status
Simulation time 617526836 ps
CPU time 6.38 seconds
Started Feb 08 01:31:17 PM UTC 25
Finished Feb 08 01:31:25 PM UTC 25
Peak memory 226108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843070212 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_perf.1843070212
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_smbus_maxlen.109654211
Short name T1523
Test name
Test status
Simulation time 494178080 ps
CPU time 3.21 seconds
Started Feb 08 01:31:26 PM UTC 25
Finished Feb 08 01:31:30 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109654211 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smbus_maxlen.109654211
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_smoke.2879137580
Short name T1503
Test name
Test status
Simulation time 4402613654 ps
CPU time 8.61 seconds
Started Feb 08 01:30:53 PM UTC 25
Finished Feb 08 01:31:02 PM UTC 25
Peak memory 226260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879137580 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smoke.2879137580
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.760459286
Short name T1569
Test name
Test status
Simulation time 22754878215 ps
CPU time 93.69 seconds
Started Feb 08 01:31:17 PM UTC 25
Finished Feb 08 01:32:53 PM UTC 25
Peak memory 1816120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760459286 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_all.760459286
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_stress_rd.2632458534
Short name T1507
Test name
Test status
Simulation time 2880662850 ps
CPU time 13.63 seconds
Started Feb 08 01:30:56 PM UTC 25
Finished Feb 08 01:31:11 PM UTC 25
Peak memory 224724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632458534 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_rd.2632458534
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.2640330118
Short name T1512
Test name
Test status
Simulation time 22263776963 ps
CPU time 22.85 seconds
Started Feb 08 01:30:54 PM UTC 25
Finished Feb 08 01:31:18 PM UTC 25
Peak memory 241156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640330118 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_wr.2640330118
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_timeout.2335220158
Short name T1514
Test name
Test status
Simulation time 2784064586 ps
CPU time 8.64 seconds
Started Feb 08 01:31:10 PM UTC 25
Finished Feb 08 01:31:20 PM UTC 25
Peak memory 226416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335220158 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_timeout.2335220158
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_target_tx_stretch_ctrl.3669686296
Short name T1530
Test name
Test status
Simulation time 617979691 ps
CPU time 11.53 seconds
Started Feb 08 01:31:25 PM UTC 25
Finished Feb 08 01:31:38 PM UTC 25
Peak memory 216116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669686296 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.3669686296
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_alert_test.884637134
Short name T1556
Test name
Test status
Simulation time 19286822 ps
CPU time 0.9 seconds
Started Feb 08 01:32:31 PM UTC 25
Finished Feb 08 01:32:33 PM UTC 25
Peak memory 215004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884637134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM
_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.884637134
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_error_intr.1391095099
Short name T1534
Test name
Test status
Simulation time 128821924 ps
CPU time 2.43 seconds
Started Feb 08 01:31:45 PM UTC 25
Finished Feb 08 01:31:49 PM UTC 25
Peak memory 226200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391095099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_host_error_intr.1391095099
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_fmt_empty.339163800
Short name T1535
Test name
Test status
Simulation time 971823869 ps
CPU time 12.51 seconds
Started Feb 08 01:31:36 PM UTC 25
Finished Feb 08 01:31:50 PM UTC 25
Peak memory 323280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339163800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empty.339163800
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.3395157238
Short name T1602
Test name
Test status
Simulation time 4080309909 ps
CPU time 140.6 seconds
Started Feb 08 01:31:38 PM UTC 25
Finished Feb 08 01:34:01 PM UTC 25
Peak memory 695792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395157238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 44.i2c_host_fifo_full.3395157238
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.2829401999
Short name T1578
Test name
Test status
Simulation time 2660602836 ps
CPU time 97.26 seconds
Started Feb 08 01:31:35 PM UTC 25
Finished Feb 08 01:33:14 PM UTC 25
Peak memory 828932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829401999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_host_fifo_overflow.2829401999
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_fmt.53026618
Short name T1529
Test name
Test status
Simulation time 80379961 ps
CPU time 1.3 seconds
Started Feb 08 01:31:35 PM UTC 25
Finished Feb 08 01:31:37 PM UTC 25
Peak memory 214516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53026618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fmt.53026618
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_rx.357312192
Short name T1532
Test name
Test status
Simulation time 199233267 ps
CPU time 5.2 seconds
Started Feb 08 01:31:38 PM UTC 25
Finished Feb 08 01:31:45 PM UTC 25
Peak memory 215868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357312192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.357312192
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.1109257487
Short name T1615
Test name
Test status
Simulation time 10544350506 ps
CPU time 172.27 seconds
Started Feb 08 01:31:33 PM UTC 25
Finished Feb 08 01:34:29 PM UTC 25
Peak memory 1541904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109257487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 44.i2c_host_fifo_watermark.1109257487
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_may_nack.1418207210
Short name T1554
Test name
Test status
Simulation time 2262027781 ps
CPU time 8.46 seconds
Started Feb 08 01:32:22 PM UTC 25
Finished Feb 08 01:32:32 PM UTC 25
Peak memory 216220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418207210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 44.i2c_host_may_nack.1418207210
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_override.3147535436
Short name T1527
Test name
Test status
Simulation time 21230407 ps
CPU time 0.9 seconds
Started Feb 08 01:31:32 PM UTC 25
Finished Feb 08 01:31:35 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147535436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 44.i2c_host_override.3147535436
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_perf.2004658693
Short name T1589
Test name
Test status
Simulation time 2555215198 ps
CPU time 109.24 seconds
Started Feb 08 01:31:39 PM UTC 25
Finished Feb 08 01:33:31 PM UTC 25
Peak memory 215904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004658693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_host_perf.2004658693
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_perf_precise.1370974348
Short name T1538
Test name
Test status
Simulation time 345205481 ps
CPU time 18.39 seconds
Started Feb 08 01:31:40 PM UTC 25
Finished Feb 08 01:32:00 PM UTC 25
Peak memory 215844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370974348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_host_perf_precise.1370974348
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_smoke.2685181976
Short name T1539
Test name
Test status
Simulation time 3858581710 ps
CPU time 31.53 seconds
Started Feb 08 01:31:31 PM UTC 25
Finished Feb 08 01:32:05 PM UTC 25
Peak memory 394764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685181976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_host_smoke.2685181976
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_stretch_timeout.2183756722
Short name T1537
Test name
Test status
Simulation time 643283745 ps
CPU time 13.95 seconds
Started Feb 08 01:31:44 PM UTC 25
Finished Feb 08 01:31:59 PM UTC 25
Peak memory 226204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183756722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.i2c_host_stretch_timeout.2183756722
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_bad_addr.1954404405
Short name T1549
Test name
Test status
Simulation time 3499056736 ps
CPU time 8.07 seconds
Started Feb 08 01:32:17 PM UTC 25
Finished Feb 08 01:32:26 PM UTC 25
Peak memory 230612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1954404405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.1954404405
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_acq.1476132796
Short name T1542
Test name
Test status
Simulation time 370225552 ps
CPU time 1.98 seconds
Started Feb 08 01:32:12 PM UTC 25
Finished Feb 08 01:32:15 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476132796 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_acq.1476132796
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_tx.3618543334
Short name T1543
Test name
Test status
Simulation time 164591911 ps
CPU time 2.04 seconds
Started Feb 08 01:32:13 PM UTC 25
Finished Feb 08 01:32:16 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618543334 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_tx.3618543334
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_acq.4002911271
Short name T1552
Test name
Test status
Simulation time 5014505752 ps
CPU time 4.42 seconds
Started Feb 08 01:32:24 PM UTC 25
Finished Feb 08 01:32:30 PM UTC 25
Peak memory 215864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002911271 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.4002911271
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_tx.2223403551
Short name T1550
Test name
Test status
Simulation time 145620515 ps
CPU time 1.87 seconds
Started Feb 08 01:32:24 PM UTC 25
Finished Feb 08 01:32:27 PM UTC 25
Peak memory 215800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223403551 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.2223403551
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_intr_smoke.2302193693
Short name T1541
Test name
Test status
Simulation time 2512205760 ps
CPU time 10.58 seconds
Started Feb 08 01:32:00 PM UTC 25
Finished Feb 08 01:32:12 PM UTC 25
Peak memory 226220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302193693 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_smoke.2302193693
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.3395764292
Short name T1735
Test name
Test status
Simulation time 22809677283 ps
CPU time 574.15 seconds
Started Feb 08 01:32:02 PM UTC 25
Finished Feb 08 01:41:42 PM UTC 25
Peak memory 5477964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33957
64292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.3395764292
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull.2665799482
Short name T1557
Test name
Test status
Simulation time 2026852355 ps
CPU time 3.65 seconds
Started Feb 08 01:32:29 PM UTC 25
Finished Feb 08 01:32:34 PM UTC 25
Peak memory 226208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665799482 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_acqfull.2665799482
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull_addr.4219695898
Short name T1560
Test name
Test status
Simulation time 467900235 ps
CPU time 3.64 seconds
Started Feb 08 01:32:30 PM UTC 25
Finished Feb 08 01:32:35 PM UTC 25
Peak memory 215996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219695898 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_acqfull_addr.4219695898
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_nack_txstretch.1626477752
Short name T1559
Test name
Test status
Simulation time 472484914 ps
CPU time 2.47 seconds
Started Feb 08 01:32:31 PM UTC 25
Finished Feb 08 01:32:35 PM UTC 25
Peak memory 232944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626477752 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_txstretch.1626477752
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_perf.492977577
Short name T1546
Test name
Test status
Simulation time 2640576224 ps
CPU time 5.89 seconds
Started Feb 08 01:32:14 PM UTC 25
Finished Feb 08 01:32:21 PM UTC 25
Peak memory 232300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492977577 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_perf.492977577
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_smbus_maxlen.2408128282
Short name T1555
Test name
Test status
Simulation time 791168273 ps
CPU time 3.32 seconds
Started Feb 08 01:32:28 PM UTC 25
Finished Feb 08 01:32:32 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408128282 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smbus_maxlen.2408128282
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_smoke.813450872
Short name T1551
Test name
Test status
Simulation time 973762393 ps
CPU time 38.02 seconds
Started Feb 08 01:31:49 PM UTC 25
Finished Feb 08 01:32:29 PM UTC 25
Peak memory 226080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813450872 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smoke.813450872
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.1725892360
Short name T1586
Test name
Test status
Simulation time 49683226912 ps
CPU time 70.9 seconds
Started Feb 08 01:32:16 PM UTC 25
Finished Feb 08 01:33:29 PM UTC 25
Peak memory 446240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725892360 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_all.1725892360
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_stress_rd.2277788644
Short name T1565
Test name
Test status
Simulation time 960536893 ps
CPU time 45.49 seconds
Started Feb 08 01:31:55 PM UTC 25
Finished Feb 08 01:32:43 PM UTC 25
Peak memory 226256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277788644 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_rd.2277788644
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.253550879
Short name T1734
Test name
Test status
Simulation time 38900006651 ps
CPU time 582.79 seconds
Started Feb 08 01:31:51 PM UTC 25
Finished Feb 08 01:41:40 PM UTC 25
Peak memory 4810508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253550879 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_wr.253550879
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_stretch.2300400801
Short name T1540
Test name
Test status
Simulation time 2703204332 ps
CPU time 9.25 seconds
Started Feb 08 01:32:00 PM UTC 25
Finished Feb 08 01:32:11 PM UTC 25
Peak memory 329164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300400801 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stretch.2300400801
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_timeout.3381938222
Short name T1545
Test name
Test status
Simulation time 15946870141 ps
CPU time 11.6 seconds
Started Feb 08 01:32:06 PM UTC 25
Finished Feb 08 01:32:18 PM UTC 25
Peak memory 232976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381938222 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_timeout.3381938222
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_tx_stretch_ctrl.2705660777
Short name T1553
Test name
Test status
Simulation time 138811048 ps
CPU time 3.75 seconds
Started Feb 08 01:32:27 PM UTC 25
Finished Feb 08 01:32:31 PM UTC 25
Peak memory 215864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705660777 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.2705660777
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_alert_test.1398047231
Short name T1592
Test name
Test status
Simulation time 42437662 ps
CPU time 0.92 seconds
Started Feb 08 01:33:30 PM UTC 25
Finished Feb 08 01:33:32 PM UTC 25
Peak memory 214936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398047231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1398047231
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_error_intr.975685883
Short name T1566
Test name
Test status
Simulation time 99833027 ps
CPU time 2.85 seconds
Started Feb 08 01:32:41 PM UTC 25
Finished Feb 08 01:32:45 PM UTC 25
Peak memory 233188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975685883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_host_error_intr.975685883
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_fmt_empty.3745466112
Short name T1567
Test name
Test status
Simulation time 738186904 ps
CPU time 13.07 seconds
Started Feb 08 01:32:34 PM UTC 25
Finished Feb 08 01:32:49 PM UTC 25
Peak memory 302772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745466112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empty.3745466112
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.3375251189
Short name T1603
Test name
Test status
Simulation time 2419834678 ps
CPU time 86.05 seconds
Started Feb 08 01:32:35 PM UTC 25
Finished Feb 08 01:34:03 PM UTC 25
Peak memory 661264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375251189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_host_fifo_full.3375251189
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.1017271392
Short name T1604
Test name
Test status
Simulation time 3915176007 ps
CPU time 88.69 seconds
Started Feb 08 01:32:34 PM UTC 25
Finished Feb 08 01:34:05 PM UTC 25
Peak memory 783884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017271392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_host_fifo_overflow.1017271392
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_fmt.2896342847
Short name T1562
Test name
Test status
Simulation time 1047035061 ps
CPU time 1.54 seconds
Started Feb 08 01:32:34 PM UTC 25
Finished Feb 08 01:32:37 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896342847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fmt.2896342847
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_rx.739154859
Short name T1570
Test name
Test status
Simulation time 581112626 ps
CPU time 16.65 seconds
Started Feb 08 01:32:35 PM UTC 25
Finished Feb 08 01:32:53 PM UTC 25
Peak memory 215892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739154859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.739154859
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.1178366836
Short name T1617
Test name
Test status
Simulation time 14824130103 ps
CPU time 114.62 seconds
Started Feb 08 01:32:33 PM UTC 25
Finished Feb 08 01:34:30 PM UTC 25
Peak memory 1165128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178366836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 45.i2c_host_fifo_watermark.1178366836
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.3080572316
Short name T248
Test name
Test status
Simulation time 737546207 ps
CPU time 20.83 seconds
Started Feb 08 01:33:19 PM UTC 25
Finished Feb 08 01:33:41 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080572316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 45.i2c_host_may_nack.3080572316
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_mode_toggle.2004930522
Short name T1509
Test name
Test status
Simulation time 77185135 ps
CPU time 2.23 seconds
Started Feb 08 01:33:17 PM UTC 25
Finished Feb 08 01:33:21 PM UTC 25
Peak memory 226160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004930522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_t
oggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_host_mode_toggle.2004930522
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_override.3104091708
Short name T1561
Test name
Test status
Simulation time 58520125 ps
CPU time 1.12 seconds
Started Feb 08 01:32:33 PM UTC 25
Finished Feb 08 01:32:35 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104091708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 45.i2c_host_override.3104091708
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_perf.3594040656
Short name T1722
Test name
Test status
Simulation time 29635804845 ps
CPU time 337.13 seconds
Started Feb 08 01:32:37 PM UTC 25
Finished Feb 08 01:38:18 PM UTC 25
Peak memory 511756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594040656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_host_perf.3594040656
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_perf_precise.241859183
Short name T1584
Test name
Test status
Simulation time 899385158 ps
CPU time 46.93 seconds
Started Feb 08 01:32:38 PM UTC 25
Finished Feb 08 01:33:26 PM UTC 25
Peak memory 341308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241859183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pr
ecise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_host_perf_precise.241859183
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.3375401050
Short name T1596
Test name
Test status
Simulation time 5442515706 ps
CPU time 68.73 seconds
Started Feb 08 01:32:32 PM UTC 25
Finished Feb 08 01:33:43 PM UTC 25
Peak memory 282120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375401050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_host_smoke.3375401050
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.1106618979
Short name T1568
Test name
Test status
Simulation time 2367786632 ps
CPU time 10.44 seconds
Started Feb 08 01:32:39 PM UTC 25
Finished Feb 08 01:32:50 PM UTC 25
Peak memory 226276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106618979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 45.i2c_host_stretch_timeout.1106618979
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.3439348131
Short name T1583
Test name
Test status
Simulation time 2208823716 ps
CPU time 10.51 seconds
Started Feb 08 01:33:13 PM UTC 25
Finished Feb 08 01:33:25 PM UTC 25
Peak memory 226252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=3439348131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.3439348131
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_acq.3372768578
Short name T1576
Test name
Test status
Simulation time 194779852 ps
CPU time 1.81 seconds
Started Feb 08 01:33:09 PM UTC 25
Finished Feb 08 01:33:12 PM UTC 25
Peak memory 213924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372768578 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_acq.3372768578
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_tx.1311878056
Short name T1577
Test name
Test status
Simulation time 233990919 ps
CPU time 1.68 seconds
Started Feb 08 01:33:10 PM UTC 25
Finished Feb 08 01:33:12 PM UTC 25
Peak memory 216172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311878056 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_tx.1311878056
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.69492636
Short name T1581
Test name
Test status
Simulation time 238943182 ps
CPU time 2.18 seconds
Started Feb 08 01:33:20 PM UTC 25
Finished Feb 08 01:33:23 PM UTC 25
Peak memory 215904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69492636 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.69492636
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.3033069605
Short name T1582
Test name
Test status
Simulation time 237060516 ps
CPU time 1.57 seconds
Started Feb 08 01:33:21 PM UTC 25
Finished Feb 08 01:33:24 PM UTC 25
Peak memory 213928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033069605 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.3033069605
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_intr_smoke.1771355854
Short name T1574
Test name
Test status
Simulation time 2037174857 ps
CPU time 12.85 seconds
Started Feb 08 01:32:54 PM UTC 25
Finished Feb 08 01:33:08 PM UTC 25
Peak memory 230468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771355854 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_smoke.1771355854
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.3129037963
Short name T1730
Test name
Test status
Simulation time 20041346007 ps
CPU time 442.43 seconds
Started Feb 08 01:32:56 PM UTC 25
Finished Feb 08 01:40:24 PM UTC 25
Peak memory 3354116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31290
37963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.3129037963
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.963076847
Short name T1591
Test name
Test status
Simulation time 2437935959 ps
CPU time 4.66 seconds
Started Feb 08 01:33:25 PM UTC 25
Finished Feb 08 01:33:31 PM UTC 25
Peak memory 226476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963076847 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_acqfull.963076847
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.2780230746
Short name T1593
Test name
Test status
Simulation time 540502045 ps
CPU time 3.15 seconds
Started Feb 08 01:33:27 PM UTC 25
Finished Feb 08 01:33:32 PM UTC 25
Peak memory 216156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780230746 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_acqfull_addr.2780230746
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_perf.1097520322
Short name T1575
Test name
Test status
Simulation time 2743992697 ps
CPU time 6.59 seconds
Started Feb 08 01:33:12 PM UTC 25
Finished Feb 08 01:33:20 PM UTC 25
Peak memory 226280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097520322 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_perf.1097520322
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.1989552730
Short name T1588
Test name
Test status
Simulation time 686371357 ps
CPU time 2.45 seconds
Started Feb 08 01:33:25 PM UTC 25
Finished Feb 08 01:33:29 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989552730 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smbus_maxlen.1989552730
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.4244346786
Short name T1571
Test name
Test status
Simulation time 1051408089 ps
CPU time 15.69 seconds
Started Feb 08 01:32:46 PM UTC 25
Finished Feb 08 01:33:03 PM UTC 25
Peak memory 232972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244346786 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smoke.4244346786
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.3188639974
Short name T1671
Test name
Test status
Simulation time 16422675639 ps
CPU time 191.02 seconds
Started Feb 08 01:33:13 PM UTC 25
Finished Feb 08 01:36:27 PM UTC 25
Peak memory 2326332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188639974 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_all.3188639974
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.2506828767
Short name T1572
Test name
Test status
Simulation time 780777059 ps
CPU time 15.06 seconds
Started Feb 08 01:32:51 PM UTC 25
Finished Feb 08 01:33:08 PM UTC 25
Peak memory 233160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506828767 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_rd.2506828767
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.2675454489
Short name T1737
Test name
Test status
Simulation time 38538151630 ps
CPU time 563.58 seconds
Started Feb 08 01:32:50 PM UTC 25
Finished Feb 08 01:42:19 PM UTC 25
Peak memory 4779524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675454489 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_wr.2675454489
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_stretch.291313719
Short name T1599
Test name
Test status
Simulation time 3267159272 ps
CPU time 50.53 seconds
Started Feb 08 01:32:54 PM UTC 25
Finished Feb 08 01:33:46 PM UTC 25
Peak memory 970500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291313719 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stretch.291313719
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.2349288212
Short name T1579
Test name
Test status
Simulation time 6090178521 ps
CPU time 11.46 seconds
Started Feb 08 01:33:03 PM UTC 25
Finished Feb 08 01:33:16 PM UTC 25
Peak memory 232424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349288212 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_timeout.2349288212
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.3274316932
Short name T1587
Test name
Test status
Simulation time 110517060 ps
CPU time 3.53 seconds
Started Feb 08 01:33:24 PM UTC 25
Finished Feb 08 01:33:29 PM UTC 25
Peak memory 215864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274316932 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.3274316932
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_alert_test.400665577
Short name T1622
Test name
Test status
Simulation time 50272627 ps
CPU time 0.96 seconds
Started Feb 08 01:34:31 PM UTC 25
Finished Feb 08 01:34:34 PM UTC 25
Peak memory 213924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400665577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM
_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.400665577
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.3634131293
Short name T1600
Test name
Test status
Simulation time 345225355 ps
CPU time 3.98 seconds
Started Feb 08 01:33:42 PM UTC 25
Finished Feb 08 01:33:48 PM UTC 25
Peak memory 247392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634131293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_host_error_intr.3634131293
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.4131399008
Short name T1597
Test name
Test status
Simulation time 1564282109 ps
CPU time 8.41 seconds
Started Feb 08 01:33:33 PM UTC 25
Finished Feb 08 01:33:43 PM UTC 25
Peak memory 263668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131399008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empty.4131399008
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.1994804710
Short name T1657
Test name
Test status
Simulation time 8258176782 ps
CPU time 127.66 seconds
Started Feb 08 01:33:33 PM UTC 25
Finished Feb 08 01:35:43 PM UTC 25
Peak memory 517704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994804710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 46.i2c_host_fifo_full.1994804710
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.3191512362
Short name T1678
Test name
Test status
Simulation time 2496404349 ps
CPU time 183.08 seconds
Started Feb 08 01:33:32 PM UTC 25
Finished Feb 08 01:36:38 PM UTC 25
Peak memory 820820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191512362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_host_fifo_overflow.3191512362
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.1703035354
Short name T1594
Test name
Test status
Simulation time 292901690 ps
CPU time 1.32 seconds
Started Feb 08 01:33:32 PM UTC 25
Finished Feb 08 01:33:34 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703035354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fmt.1703035354
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.2304921725
Short name T1595
Test name
Test status
Simulation time 151307777 ps
CPU time 5.22 seconds
Started Feb 08 01:33:33 PM UTC 25
Finished Feb 08 01:33:40 PM UTC 25
Peak memory 215960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304921725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.2304921725
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.1039616729
Short name T1692
Test name
Test status
Simulation time 3527583062 ps
CPU time 199.9 seconds
Started Feb 08 01:33:32 PM UTC 25
Finished Feb 08 01:36:55 PM UTC 25
Peak memory 1080832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039616729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 46.i2c_host_fifo_watermark.1039616729
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.2676658587
Short name T1630
Test name
Test status
Simulation time 457395472 ps
CPU time 21.24 seconds
Started Feb 08 01:34:22 PM UTC 25
Finished Feb 08 01:34:44 PM UTC 25
Peak memory 215964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676658587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 46.i2c_host_may_nack.2676658587
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_mode_toggle.1365560613
Short name T1612
Test name
Test status
Simulation time 360575578 ps
CPU time 1.62 seconds
Started Feb 08 01:34:21 PM UTC 25
Finished Feb 08 01:34:24 PM UTC 25
Peak memory 216056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365560613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_t
oggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_host_mode_toggle.1365560613
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_override.216759540
Short name T259
Test name
Test status
Simulation time 29484716 ps
CPU time 0.91 seconds
Started Feb 08 01:33:30 PM UTC 25
Finished Feb 08 01:33:32 PM UTC 25
Peak memory 213920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216759540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overrid
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 46.i2c_host_override.216759540
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_perf.2477389173
Short name T1626
Test name
Test status
Simulation time 4999622109 ps
CPU time 58.8 seconds
Started Feb 08 01:33:35 PM UTC 25
Finished Feb 08 01:34:36 PM UTC 25
Peak memory 360200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477389173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_host_perf.2477389173
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.1465746535
Short name T1598
Test name
Test status
Simulation time 428791299 ps
CPU time 3.63 seconds
Started Feb 08 01:33:38 PM UTC 25
Finished Feb 08 01:33:43 PM UTC 25
Peak memory 215788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465746535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_host_perf_precise.1465746535
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.1053978928
Short name T1621
Test name
Test status
Simulation time 1301971661 ps
CPU time 61.93 seconds
Started Feb 08 01:33:30 PM UTC 25
Finished Feb 08 01:34:33 PM UTC 25
Peak memory 364016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053978928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_host_smoke.1053978928
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.2774453216
Short name T1601
Test name
Test status
Simulation time 2604768854 ps
CPU time 15.95 seconds
Started Feb 08 01:33:40 PM UTC 25
Finished Feb 08 01:33:58 PM UTC 25
Peak memory 228460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774453216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_host_stretch_timeout.2774453216
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.1498617393
Short name T1611
Test name
Test status
Simulation time 796069975 ps
CPU time 6.33 seconds
Started Feb 08 01:34:14 PM UTC 25
Finished Feb 08 01:34:22 PM UTC 25
Peak memory 226204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1498617393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.1498617393
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.3703849785
Short name T1606
Test name
Test status
Simulation time 651943710 ps
CPU time 2.06 seconds
Started Feb 08 01:34:10 PM UTC 25
Finished Feb 08 01:34:14 PM UTC 25
Peak memory 215840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703849785 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_acq.3703849785
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.1643540521
Short name T1607
Test name
Test status
Simulation time 311385450 ps
CPU time 1.13 seconds
Started Feb 08 01:34:11 PM UTC 25
Finished Feb 08 01:34:14 PM UTC 25
Peak memory 213920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643540521 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_tx.1643540521
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.440639042
Short name T1613
Test name
Test status
Simulation time 410260017 ps
CPU time 2.54 seconds
Started Feb 08 01:34:23 PM UTC 25
Finished Feb 08 01:34:27 PM UTC 25
Peak memory 215708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440639042 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.440639042
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.2232823635
Short name T1616
Test name
Test status
Simulation time 562381599 ps
CPU time 2.23 seconds
Started Feb 08 01:34:26 PM UTC 25
Finished Feb 08 01:34:29 PM UTC 25
Peak memory 215908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232823635 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.2232823635
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.3386634961
Short name T1605
Test name
Test status
Simulation time 1040623490 ps
CPU time 9.23 seconds
Started Feb 08 01:33:59 PM UTC 25
Finished Feb 08 01:34:09 PM UTC 25
Peak memory 232348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386634961 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_smoke.3386634961
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.4269172957
Short name T1610
Test name
Test status
Simulation time 9231069633 ps
CPU time 17.61 seconds
Started Feb 08 01:34:02 PM UTC 25
Finished Feb 08 01:34:21 PM UTC 25
Peak memory 624388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42691
72957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.4269172957
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.2137353303
Short name T1623
Test name
Test status
Simulation time 2799362014 ps
CPU time 3.83 seconds
Started Feb 08 01:34:29 PM UTC 25
Finished Feb 08 01:34:34 PM UTC 25
Peak memory 226088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137353303 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_acqfull.2137353303
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.257126913
Short name T1624
Test name
Test status
Simulation time 1696471164 ps
CPU time 3.88 seconds
Started Feb 08 01:34:29 PM UTC 25
Finished Feb 08 01:34:34 PM UTC 25
Peak memory 215916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257126913 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_acqfull_addr.257126913
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_perf.1188460079
Short name T1609
Test name
Test status
Simulation time 2968259258 ps
CPU time 7.93 seconds
Started Feb 08 01:34:11 PM UTC 25
Finished Feb 08 01:34:21 PM UTC 25
Peak memory 232900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188460079 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_perf.1188460079
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.2472686183
Short name T1619
Test name
Test status
Simulation time 1662520800 ps
CPU time 2.74 seconds
Started Feb 08 01:34:28 PM UTC 25
Finished Feb 08 01:34:32 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472686183 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smbus_maxlen.2472686183
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.3115594865
Short name T1614
Test name
Test status
Simulation time 1156015650 ps
CPU time 42.15 seconds
Started Feb 08 01:33:43 PM UTC 25
Finished Feb 08 01:34:27 PM UTC 25
Peak memory 226268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115594865 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smoke.3115594865
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.3891452164
Short name T1740
Test name
Test status
Simulation time 67472537687 ps
CPU time 511.51 seconds
Started Feb 08 01:34:14 PM UTC 25
Finished Feb 08 01:42:51 PM UTC 25
Peak memory 2260752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891452164 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_all.3891452164
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.3130404308
Short name T1625
Test name
Test status
Simulation time 4361788144 ps
CPU time 46 seconds
Started Feb 08 01:33:48 PM UTC 25
Finished Feb 08 01:34:35 PM UTC 25
Peak memory 228260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130404308 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_rd.3130404308
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.3227495281
Short name T1720
Test name
Test status
Simulation time 42461751056 ps
CPU time 266.84 seconds
Started Feb 08 01:33:45 PM UTC 25
Finished Feb 08 01:38:15 PM UTC 25
Peak memory 2791172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227495281 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_wr.3227495281
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.1112239699
Short name T1608
Test name
Test status
Simulation time 6018031272 ps
CPU time 12.43 seconds
Started Feb 08 01:34:04 PM UTC 25
Finished Feb 08 01:34:18 PM UTC 25
Peak memory 243468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112239699 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_timeout.1112239699
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.3381340895
Short name T1618
Test name
Test status
Simulation time 64644357 ps
CPU time 2.53 seconds
Started Feb 08 01:34:28 PM UTC 25
Finished Feb 08 01:34:32 PM UTC 25
Peak memory 215928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381340895 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.3381340895
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_alert_test.2255472443
Short name T1590
Test name
Test status
Simulation time 16462803 ps
CPU time 0.84 seconds
Started Feb 08 01:35:30 PM UTC 25
Finished Feb 08 01:35:32 PM UTC 25
Peak memory 214996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255472443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.2255472443
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.2850763548
Short name T1631
Test name
Test status
Simulation time 373580716 ps
CPU time 6.63 seconds
Started Feb 08 01:34:39 PM UTC 25
Finished Feb 08 01:34:47 PM UTC 25
Peak memory 226404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850763548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_host_error_intr.2850763548
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.949752254
Short name T1635
Test name
Test status
Simulation time 450031513 ps
CPU time 26.92 seconds
Started Feb 08 01:34:35 PM UTC 25
Finished Feb 08 01:35:04 PM UTC 25
Peak memory 314872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949752254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empty.949752254
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.2917345994
Short name T1696
Test name
Test status
Simulation time 3921463297 ps
CPU time 161.47 seconds
Started Feb 08 01:34:36 PM UTC 25
Finished Feb 08 01:37:20 PM UTC 25
Peak memory 573140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917345994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_host_fifo_full.2917345994
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.40229609
Short name T1711
Test name
Test status
Simulation time 9018537988 ps
CPU time 193.12 seconds
Started Feb 08 01:34:34 PM UTC 25
Finished Feb 08 01:37:51 PM UTC 25
Peak memory 812788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40229609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_host_fifo_overflow.40229609
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.4082127712
Short name T1628
Test name
Test status
Simulation time 721250896 ps
CPU time 1.96 seconds
Started Feb 08 01:34:34 PM UTC 25
Finished Feb 08 01:34:38 PM UTC 25
Peak memory 214488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082127712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fmt.4082127712
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.3930697581
Short name T1629
Test name
Test status
Simulation time 595214253 ps
CPU time 5.05 seconds
Started Feb 08 01:34:36 PM UTC 25
Finished Feb 08 01:34:42 PM UTC 25
Peak memory 215960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930697581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.3930697581
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.3340593935
Short name T1725
Test name
Test status
Simulation time 4296153754 ps
CPU time 290.32 seconds
Started Feb 08 01:34:33 PM UTC 25
Finished Feb 08 01:39:28 PM UTC 25
Peak memory 1314392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340593935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 47.i2c_host_fifo_watermark.3340593935
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.4229225102
Short name T1656
Test name
Test status
Simulation time 462407549 ps
CPU time 20.27 seconds
Started Feb 08 01:35:18 PM UTC 25
Finished Feb 08 01:35:40 PM UTC 25
Peak memory 216228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229225102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 47.i2c_host_may_nack.4229225102
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_override.3289368137
Short name T1627
Test name
Test status
Simulation time 30691730 ps
CPU time 1.1 seconds
Started Feb 08 01:34:33 PM UTC 25
Finished Feb 08 01:34:36 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289368137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 47.i2c_host_override.3289368137
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_perf.3422578516
Short name T1634
Test name
Test status
Simulation time 3508769428 ps
CPU time 24.73 seconds
Started Feb 08 01:34:37 PM UTC 25
Finished Feb 08 01:35:03 PM UTC 25
Peak memory 226172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422578516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_host_perf.3422578516
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.685788341
Short name T1638
Test name
Test status
Simulation time 2563481788 ps
CPU time 32.08 seconds
Started Feb 08 01:34:37 PM UTC 25
Finished Feb 08 01:35:11 PM UTC 25
Peak memory 236552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685788341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pr
ecise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_host_perf_precise.685788341
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.1858123491
Short name T1668
Test name
Test status
Simulation time 4398893478 ps
CPU time 106.83 seconds
Started Feb 08 01:34:33 PM UTC 25
Finished Feb 08 01:36:23 PM UTC 25
Peak memory 386508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858123491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_host_smoke.1858123491
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_stress_all.2624965260
Short name T1742
Test name
Test status
Simulation time 90985063006 ps
CPU time 547.56 seconds
Started Feb 08 01:34:43 PM UTC 25
Finished Feb 08 01:43:56 PM UTC 25
Peak memory 1551948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624965260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_host_stress_all.2624965260
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.216716068
Short name T1636
Test name
Test status
Simulation time 6174906931 ps
CPU time 27.43 seconds
Started Feb 08 01:34:37 PM UTC 25
Finished Feb 08 01:35:06 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216716068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch
_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 47.i2c_host_stretch_timeout.216716068
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.4218148588
Short name T1645
Test name
Test status
Simulation time 3586947459 ps
CPU time 7.52 seconds
Started Feb 08 01:35:14 PM UTC 25
Finished Feb 08 01:35:23 PM UTC 25
Peak memory 232428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=4218148588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.4218148588
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.2673592610
Short name T1640
Test name
Test status
Simulation time 246896817 ps
CPU time 1.71 seconds
Started Feb 08 01:35:11 PM UTC 25
Finished Feb 08 01:35:14 PM UTC 25
Peak memory 214288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673592610 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_acq.2673592610
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.3391840309
Short name T1641
Test name
Test status
Simulation time 224551253 ps
CPU time 1.21 seconds
Started Feb 08 01:35:12 PM UTC 25
Finished Feb 08 01:35:14 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391840309 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_tx.3391840309
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.1171901330
Short name T1649
Test name
Test status
Simulation time 472707309 ps
CPU time 3.64 seconds
Started Feb 08 01:35:20 PM UTC 25
Finished Feb 08 01:35:25 PM UTC 25
Peak memory 215968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171901330 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.1171901330
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.3404739367
Short name T1647
Test name
Test status
Simulation time 482859000 ps
CPU time 1.83 seconds
Started Feb 08 01:35:21 PM UTC 25
Finished Feb 08 01:35:24 PM UTC 25
Peak memory 213928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404739367 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.3404739367
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_hrst.2382348342
Short name T1644
Test name
Test status
Simulation time 933430581 ps
CPU time 3.15 seconds
Started Feb 08 01:35:15 PM UTC 25
Finished Feb 08 01:35:19 PM UTC 25
Peak memory 230264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382348342 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_hrst.2382348342
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.548885062
Short name T1637
Test name
Test status
Simulation time 8207400303 ps
CPU time 4.81 seconds
Started Feb 08 01:35:04 PM UTC 25
Finished Feb 08 01:35:10 PM UTC 25
Peak memory 232996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548885062 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_smoke.548885062
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.1954129216
Short name T1639
Test name
Test status
Simulation time 5254131972 ps
CPU time 5.65 seconds
Started Feb 08 01:35:04 PM UTC 25
Finished Feb 08 01:35:11 PM UTC 25
Peak memory 269808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19541
29216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.1954129216
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.1692873098
Short name T1653
Test name
Test status
Simulation time 1056433913 ps
CPU time 3.97 seconds
Started Feb 08 01:35:26 PM UTC 25
Finished Feb 08 01:35:31 PM UTC 25
Peak memory 226280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692873098 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_acqfull.1692873098
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.3859600441
Short name T1652
Test name
Test status
Simulation time 7197557208 ps
CPU time 3.64 seconds
Started Feb 08 01:35:26 PM UTC 25
Finished Feb 08 01:35:30 PM UTC 25
Peak memory 216000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859600441 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_acqfull_addr.3859600441
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.3207247388
Short name T1650
Test name
Test status
Simulation time 505190285 ps
CPU time 1.87 seconds
Started Feb 08 01:35:26 PM UTC 25
Finished Feb 08 01:35:29 PM UTC 25
Peak memory 231876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207247388 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_txstretch.3207247388
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_perf.4166413575
Short name T1642
Test name
Test status
Simulation time 823109845 ps
CPU time 3.71 seconds
Started Feb 08 01:35:12 PM UTC 25
Finished Feb 08 01:35:17 PM UTC 25
Peak memory 226408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166413575 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_perf.4166413575
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.298692299
Short name T1651
Test name
Test status
Simulation time 1744853463 ps
CPU time 4.5 seconds
Started Feb 08 01:35:24 PM UTC 25
Finished Feb 08 01:35:30 PM UTC 25
Peak memory 215636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298692299 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smbus_maxlen.298692299
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.2765656305
Short name T1633
Test name
Test status
Simulation time 669143745 ps
CPU time 11.24 seconds
Started Feb 08 01:34:45 PM UTC 25
Finished Feb 08 01:34:58 PM UTC 25
Peak memory 228248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765656305 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smoke.2765656305
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.2761184762
Short name T1746
Test name
Test status
Simulation time 24430601083 ps
CPU time 659.26 seconds
Started Feb 08 01:35:12 PM UTC 25
Finished Feb 08 01:46:18 PM UTC 25
Peak memory 4179464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761184762 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_all.2761184762
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.2478397189
Short name T1646
Test name
Test status
Simulation time 2678005294 ps
CPU time 24.23 seconds
Started Feb 08 01:34:58 PM UTC 25
Finished Feb 08 01:35:24 PM UTC 25
Peak memory 245244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478397189 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_rd.2478397189
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.164849803
Short name T1632
Test name
Test status
Simulation time 10054151196 ps
CPU time 8.06 seconds
Started Feb 08 01:34:48 PM UTC 25
Finished Feb 08 01:34:57 PM UTC 25
Peak memory 215976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164849803 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_wr.164849803
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.4270077921
Short name T1660
Test name
Test status
Simulation time 5677960350 ps
CPU time 50.76 seconds
Started Feb 08 01:34:58 PM UTC 25
Finished Feb 08 01:35:51 PM UTC 25
Peak memory 503232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270077921 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stretch.4270077921
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.2894140438
Short name T1643
Test name
Test status
Simulation time 13535758688 ps
CPU time 11.06 seconds
Started Feb 08 01:35:05 PM UTC 25
Finished Feb 08 01:35:17 PM UTC 25
Peak memory 226284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894140438 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_timeout.2894140438
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.1402167283
Short name T1654
Test name
Test status
Simulation time 530015143 ps
CPU time 9.16 seconds
Started Feb 08 01:35:23 PM UTC 25
Finished Feb 08 01:35:34 PM UTC 25
Peak memory 226104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402167283 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.1402167283
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_alert_test.1270098676
Short name T1684
Test name
Test status
Simulation time 17156746 ps
CPU time 0.87 seconds
Started Feb 08 01:36:41 PM UTC 25
Finished Feb 08 01:36:43 PM UTC 25
Peak memory 213916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270098676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.1270098676
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.3078241237
Short name T1662
Test name
Test status
Simulation time 87945471 ps
CPU time 2 seconds
Started Feb 08 01:35:51 PM UTC 25
Finished Feb 08 01:35:55 PM UTC 25
Peak memory 226036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078241237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_host_error_intr.3078241237
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.2539885309
Short name T1658
Test name
Test status
Simulation time 479198842 ps
CPU time 9.05 seconds
Started Feb 08 01:35:35 PM UTC 25
Finished Feb 08 01:35:45 PM UTC 25
Peak memory 325116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539885309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empty.2539885309
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.1693300962
Short name T1726
Test name
Test status
Simulation time 47388529409 ps
CPU time 228.33 seconds
Started Feb 08 01:35:40 PM UTC 25
Finished Feb 08 01:39:32 PM UTC 25
Peak memory 837380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693300962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_host_fifo_full.1693300962
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.2139861927
Short name T1679
Test name
Test status
Simulation time 11537235162 ps
CPU time 64.67 seconds
Started Feb 08 01:35:33 PM UTC 25
Finished Feb 08 01:36:39 PM UTC 25
Peak memory 714312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139861927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_host_fifo_overflow.2139861927
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.3003814452
Short name T1655
Test name
Test status
Simulation time 501136183 ps
CPU time 1.62 seconds
Started Feb 08 01:35:34 PM UTC 25
Finished Feb 08 01:35:37 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003814452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fmt.3003814452
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.255233061
Short name T1661
Test name
Test status
Simulation time 471253529 ps
CPU time 13.13 seconds
Started Feb 08 01:35:37 PM UTC 25
Finished Feb 08 01:35:52 PM UTC 25
Peak memory 249540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255233061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.255233061
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.589043789
Short name T1723
Test name
Test status
Simulation time 9719435270 ps
CPU time 224.65 seconds
Started Feb 08 01:35:32 PM UTC 25
Finished Feb 08 01:39:20 PM UTC 25
Peak memory 1158596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589043789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_wa
termark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_host_fifo_watermark.589043789
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.1937853568
Short name T1680
Test name
Test status
Simulation time 1057364894 ps
CPU time 8.18 seconds
Started Feb 08 01:36:31 PM UTC 25
Finished Feb 08 01:36:40 PM UTC 25
Peak memory 215964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937853568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 48.i2c_host_may_nack.1937853568
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_mode_toggle.4127400646
Short name T77
Test name
Test status
Simulation time 108636488 ps
CPU time 2.78 seconds
Started Feb 08 01:36:31 PM UTC 25
Finished Feb 08 01:36:35 PM UTC 25
Peak memory 226224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127400646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_t
oggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_host_mode_toggle.4127400646
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_override.4001370721
Short name T1620
Test name
Test status
Simulation time 52964536 ps
CPU time 1.02 seconds
Started Feb 08 01:35:31 PM UTC 25
Finished Feb 08 01:35:33 PM UTC 25
Peak memory 213920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001370721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 48.i2c_host_override.4001370721
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_perf.576873587
Short name T1747
Test name
Test status
Simulation time 18898759616 ps
CPU time 817.57 seconds
Started Feb 08 01:35:44 PM UTC 25
Finished Feb 08 01:49:31 PM UTC 25
Peak memory 493124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576873587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_host_perf.576873587
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.266496065
Short name T1659
Test name
Test status
Simulation time 107484827 ps
CPU time 1.57 seconds
Started Feb 08 01:35:46 PM UTC 25
Finished Feb 08 01:35:49 PM UTC 25
Peak memory 236064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266496065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pr
ecise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_host_perf_precise.266496065
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.2851580272
Short name T1663
Test name
Test status
Simulation time 1757027917 ps
CPU time 26.54 seconds
Started Feb 08 01:35:31 PM UTC 25
Finished Feb 08 01:35:59 PM UTC 25
Peak memory 351688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851580272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_host_smoke.2851580272
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.3960134425
Short name T1664
Test name
Test status
Simulation time 2502191724 ps
CPU time 11.21 seconds
Started Feb 08 01:35:49 PM UTC 25
Finished Feb 08 01:36:02 PM UTC 25
Peak memory 232376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960134425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.i2c_host_stretch_timeout.3960134425
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.1868050992
Short name T1677
Test name
Test status
Simulation time 3623869215 ps
CPU time 8.61 seconds
Started Feb 08 01:36:28 PM UTC 25
Finished Feb 08 01:36:37 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1868050992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1868050992
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.555273634
Short name T1672
Test name
Test status
Simulation time 101583194 ps
CPU time 1.55 seconds
Started Feb 08 01:36:25 PM UTC 25
Finished Feb 08 01:36:28 PM UTC 25
Peak memory 226140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555273634 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_acq.555273634
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.1196120423
Short name T1674
Test name
Test status
Simulation time 180401945 ps
CPU time 1.34 seconds
Started Feb 08 01:36:27 PM UTC 25
Finished Feb 08 01:36:30 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196120423 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_tx.1196120423
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.362278499
Short name T1682
Test name
Test status
Simulation time 2930721151 ps
CPU time 3.85 seconds
Started Feb 08 01:36:36 PM UTC 25
Finished Feb 08 01:36:41 PM UTC 25
Peak memory 216244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362278499 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.362278499
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.1629909803
Short name T1681
Test name
Test status
Simulation time 169154658 ps
CPU time 2.02 seconds
Started Feb 08 01:36:37 PM UTC 25
Finished Feb 08 01:36:40 PM UTC 25
Peak memory 215908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629909803 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.1629909803
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.1136465081
Short name T1667
Test name
Test status
Simulation time 1142357872 ps
CPU time 9.29 seconds
Started Feb 08 01:36:12 PM UTC 25
Finished Feb 08 01:36:23 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136465081 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_smoke.1136465081
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.1586608712
Short name T1729
Test name
Test status
Simulation time 12412416845 ps
CPU time 227.49 seconds
Started Feb 08 01:36:14 PM UTC 25
Finished Feb 08 01:40:04 PM UTC 25
Peak memory 3102472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15866
08712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.1586608712
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.1550385252
Short name T1686
Test name
Test status
Simulation time 2794703034 ps
CPU time 3.92 seconds
Started Feb 08 01:36:39 PM UTC 25
Finished Feb 08 01:36:44 PM UTC 25
Peak memory 226160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550385252 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_acqfull.1550385252
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.1121194476
Short name T1689
Test name
Test status
Simulation time 7161375116 ps
CPU time 3.96 seconds
Started Feb 08 01:36:40 PM UTC 25
Finished Feb 08 01:36:45 PM UTC 25
Peak memory 215984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121194476 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_acqfull_addr.1121194476
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_nack_txstretch.2089212436
Short name T1687
Test name
Test status
Simulation time 614990853 ps
CPU time 2.03 seconds
Started Feb 08 01:36:41 PM UTC 25
Finished Feb 08 01:36:45 PM UTC 25
Peak memory 233172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089212436 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_txstretch.2089212436
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_perf.2364441872
Short name T1676
Test name
Test status
Simulation time 2466531766 ps
CPU time 8.03 seconds
Started Feb 08 01:36:27 PM UTC 25
Finished Feb 08 01:36:37 PM UTC 25
Peak memory 225988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364441872 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_perf.2364441872
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.3865042988
Short name T1683
Test name
Test status
Simulation time 506053298 ps
CPU time 3.55 seconds
Started Feb 08 01:36:38 PM UTC 25
Finished Feb 08 01:36:43 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865042988 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smbus_maxlen.3865042988
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.2845574223
Short name T1665
Test name
Test status
Simulation time 1045821152 ps
CPU time 14.32 seconds
Started Feb 08 01:35:56 PM UTC 25
Finished Feb 08 01:36:11 PM UTC 25
Peak memory 230364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845574223 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smoke.2845574223
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.3731426228
Short name T1670
Test name
Test status
Simulation time 3686612311 ps
CPU time 22 seconds
Started Feb 08 01:36:03 PM UTC 25
Finished Feb 08 01:36:26 PM UTC 25
Peak memory 226272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731426228 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_rd.3731426228
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.3540851835
Short name T1724
Test name
Test status
Simulation time 47791832718 ps
CPU time 204.27 seconds
Started Feb 08 01:36:00 PM UTC 25
Finished Feb 08 01:39:27 PM UTC 25
Peak memory 1842760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540851835 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_wr.3540851835
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.346186053
Short name T1669
Test name
Test status
Simulation time 1914474427 ps
CPU time 16.33 seconds
Started Feb 08 01:36:07 PM UTC 25
Finished Feb 08 01:36:24 PM UTC 25
Peak memory 282056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346186053 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stretch.346186053
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.664892759
Short name T1675
Test name
Test status
Simulation time 3451694286 ps
CPU time 11.21 seconds
Started Feb 08 01:36:23 PM UTC 25
Finished Feb 08 01:36:36 PM UTC 25
Peak memory 243280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664892759 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_timeout.664892759
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.1461912056
Short name T1685
Test name
Test status
Simulation time 239176749 ps
CPU time 4.33 seconds
Started Feb 08 01:36:38 PM UTC 25
Finished Feb 08 01:36:44 PM UTC 25
Peak memory 226100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461912056 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.1461912056
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_alert_test.1964588920
Short name T1714
Test name
Test status
Simulation time 27238085 ps
CPU time 1.04 seconds
Started Feb 08 01:37:53 PM UTC 25
Finished Feb 08 01:37:55 PM UTC 25
Peak memory 214936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964588920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.1964588920
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.4179180817
Short name T1693
Test name
Test status
Simulation time 606503170 ps
CPU time 7.61 seconds
Started Feb 08 01:36:53 PM UTC 25
Finished Feb 08 01:37:02 PM UTC 25
Peak memory 226268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179180817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_host_error_intr.4179180817
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.1030119700
Short name T1695
Test name
Test status
Simulation time 469991351 ps
CPU time 28.39 seconds
Started Feb 08 01:36:46 PM UTC 25
Finished Feb 08 01:37:16 PM UTC 25
Peak memory 321064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030119700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empty.1030119700
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.2399227915
Short name T1728
Test name
Test status
Simulation time 39474838706 ps
CPU time 185.15 seconds
Started Feb 08 01:36:46 PM UTC 25
Finished Feb 08 01:39:54 PM UTC 25
Peak memory 476880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399227915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 49.i2c_host_fifo_full.2399227915
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.3039735515
Short name T1727
Test name
Test status
Simulation time 6035083701 ps
CPU time 185.08 seconds
Started Feb 08 01:36:45 PM UTC 25
Finished Feb 08 01:39:53 PM UTC 25
Peak memory 777676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039735515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_host_fifo_overflow.3039735515
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.2620186040
Short name T1690
Test name
Test status
Simulation time 372130031 ps
CPU time 1.26 seconds
Started Feb 08 01:36:45 PM UTC 25
Finished Feb 08 01:36:47 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620186040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fmt.2620186040
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.3076438548
Short name T1691
Test name
Test status
Simulation time 134092079 ps
CPU time 4.71 seconds
Started Feb 08 01:36:46 PM UTC 25
Finished Feb 08 01:36:52 PM UTC 25
Peak memory 239172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076438548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.3076438548
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.3709982549
Short name T1738
Test name
Test status
Simulation time 4966991733 ps
CPU time 330.87 seconds
Started Feb 08 01:36:44 PM UTC 25
Finished Feb 08 01:42:19 PM UTC 25
Peak memory 1287764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709982549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 49.i2c_host_fifo_watermark.3709982549
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.681202178
Short name T1719
Test name
Test status
Simulation time 526632332 ps
CPU time 19.45 seconds
Started Feb 08 01:37:42 PM UTC 25
Finished Feb 08 01:38:02 PM UTC 25
Peak memory 216108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681202178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nac
k_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 49.i2c_host_may_nack.681202178
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_override.489541093
Short name T1688
Test name
Test status
Simulation time 33670373 ps
CPU time 0.99 seconds
Started Feb 08 01:36:43 PM UTC 25
Finished Feb 08 01:36:45 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489541093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overrid
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 49.i2c_host_override.489541093
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_perf.2104655902
Short name T1704
Test name
Test status
Simulation time 5013207929 ps
CPU time 52.8 seconds
Started Feb 08 01:36:46 PM UTC 25
Finished Feb 08 01:37:40 PM UTC 25
Peak memory 249428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104655902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_host_perf.2104655902
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.3022883037
Short name T1732
Test name
Test status
Simulation time 23275278417 ps
CPU time 241.34 seconds
Started Feb 08 01:36:48 PM UTC 25
Finished Feb 08 01:40:53 PM UTC 25
Peak memory 226088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022883037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_host_perf_precise.3022883037
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.2654357493
Short name T1705
Test name
Test status
Simulation time 4242419459 ps
CPU time 56.15 seconds
Started Feb 08 01:36:42 PM UTC 25
Finished Feb 08 01:37:41 PM UTC 25
Peak memory 307008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654357493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_host_smoke.2654357493
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.2312625393
Short name T1694
Test name
Test status
Simulation time 3885368804 ps
CPU time 21.93 seconds
Started Feb 08 01:36:49 PM UTC 25
Finished Feb 08 01:37:12 PM UTC 25
Peak memory 243348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312625393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.i2c_host_stretch_timeout.2312625393
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.425448392
Short name T1706
Test name
Test status
Simulation time 3216543123 ps
CPU time 7.91 seconds
Started Feb 08 01:37:33 PM UTC 25
Finished Feb 08 01:37:42 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=425448392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.425448392
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.3936087014
Short name T1701
Test name
Test status
Simulation time 439585704 ps
CPU time 1.02 seconds
Started Feb 08 01:37:29 PM UTC 25
Finished Feb 08 01:37:32 PM UTC 25
Peak memory 213928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936087014 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_acq.3936087014
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.3915411260
Short name T1709
Test name
Test status
Simulation time 835704835 ps
CPU time 3.67 seconds
Started Feb 08 01:37:44 PM UTC 25
Finished Feb 08 01:37:49 PM UTC 25
Peak memory 215980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915411260 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.3915411260
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.1806594704
Short name T1708
Test name
Test status
Simulation time 122490246 ps
CPU time 1.82 seconds
Started Feb 08 01:37:44 PM UTC 25
Finished Feb 08 01:37:47 PM UTC 25
Peak memory 214528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806594704 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.1806594704
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.1036724426
Short name T1702
Test name
Test status
Simulation time 2442633914 ps
CPU time 10.4 seconds
Started Feb 08 01:37:21 PM UTC 25
Finished Feb 08 01:37:33 PM UTC 25
Peak memory 226224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036724426 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_smoke.1036724426
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.521007035
Short name T1700
Test name
Test status
Simulation time 509329507 ps
CPU time 3.27 seconds
Started Feb 08 01:37:24 PM UTC 25
Finished Feb 08 01:37:28 PM UTC 25
Peak memory 215908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52100
7035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.521007035
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.1448501492
Short name T1715
Test name
Test status
Simulation time 2003265976 ps
CPU time 4.33 seconds
Started Feb 08 01:37:50 PM UTC 25
Finished Feb 08 01:37:56 PM UTC 25
Peak memory 226412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448501492 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_acqfull.1448501492
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.3627724747
Short name T1716
Test name
Test status
Simulation time 939141975 ps
CPU time 3.75 seconds
Started Feb 08 01:37:51 PM UTC 25
Finished Feb 08 01:37:56 PM UTC 25
Peak memory 215932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627724747 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_acqfull_addr.3627724747
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.368868732
Short name T1713
Test name
Test status
Simulation time 260718140 ps
CPU time 1.91 seconds
Started Feb 08 01:37:52 PM UTC 25
Finished Feb 08 01:37:55 PM UTC 25
Peak memory 231932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368868732 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_txstretch.368868732
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_perf.54045869
Short name T1707
Test name
Test status
Simulation time 1357448821 ps
CPU time 9.13 seconds
Started Feb 08 01:37:32 PM UTC 25
Finished Feb 08 01:37:43 PM UTC 25
Peak memory 243216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54045869 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_perf.54045869
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.2039053396
Short name T1712
Test name
Test status
Simulation time 874318470 ps
CPU time 3.15 seconds
Started Feb 08 01:37:48 PM UTC 25
Finished Feb 08 01:37:52 PM UTC 25
Peak memory 215636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039053396 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smbus_maxlen.2039053396
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.1563329413
Short name T1697
Test name
Test status
Simulation time 5012170167 ps
CPU time 18.46 seconds
Started Feb 08 01:37:03 PM UTC 25
Finished Feb 08 01:37:23 PM UTC 25
Peak memory 232928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563329413 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smoke.1563329413
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.1579040874
Short name T1741
Test name
Test status
Simulation time 20434360037 ps
CPU time 328.86 seconds
Started Feb 08 01:37:33 PM UTC 25
Finished Feb 08 01:43:07 PM UTC 25
Peak memory 2362972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579040874 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_all.1579040874
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.1407739691
Short name T1699
Test name
Test status
Simulation time 351750642 ps
CPU time 6.48 seconds
Started Feb 08 01:37:17 PM UTC 25
Finished Feb 08 01:37:24 PM UTC 25
Peak memory 215976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407739691 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_rd.1407739691
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.3683954534
Short name T1698
Test name
Test status
Simulation time 10041410759 ps
CPU time 8.5 seconds
Started Feb 08 01:37:14 PM UTC 25
Finished Feb 08 01:37:23 PM UTC 25
Peak memory 216036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683954534 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_wr.3683954534
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.2006646423
Short name T1721
Test name
Test status
Simulation time 4582998417 ps
CPU time 54.77 seconds
Started Feb 08 01:37:20 PM UTC 25
Finished Feb 08 01:38:16 PM UTC 25
Peak memory 755464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006646423 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stretch.2006646423
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.3750990141
Short name T1703
Test name
Test status
Simulation time 1198088451 ps
CPU time 9.7 seconds
Started Feb 08 01:37:24 PM UTC 25
Finished Feb 08 01:37:35 PM UTC 25
Peak memory 230504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750990141 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_timeout.3750990141
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.1151157803
Short name T1710
Test name
Test status
Simulation time 99264421 ps
CPU time 3.12 seconds
Started Feb 08 01:37:46 PM UTC 25
Finished Feb 08 01:37:50 PM UTC 25
Peak memory 216120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151157803 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.1151157803
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_alert_test.3335244019
Short name T357
Test name
Test status
Simulation time 26902387 ps
CPU time 0.91 seconds
Started Feb 08 12:59:23 PM UTC 25
Finished Feb 08 12:59:25 PM UTC 25
Peak memory 214932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335244019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3335244019
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_host_error_intr.3763200891
Short name T22
Test name
Test status
Simulation time 259856074 ps
CPU time 5.78 seconds
Started Feb 08 12:58:43 PM UTC 25
Finished Feb 08 12:58:50 PM UTC 25
Peak memory 226224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763200891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_host_error_intr.3763200891
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_fmt_empty.993203556
Short name T342
Test name
Test status
Simulation time 868779251 ps
CPU time 16.73 seconds
Started Feb 08 12:58:40 PM UTC 25
Finished Feb 08 12:58:58 PM UTC 25
Peak memory 291996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993203556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty.993203556
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_full.1274776690
Short name T404
Test name
Test status
Simulation time 5396506237 ps
CPU time 167.73 seconds
Started Feb 08 12:58:40 PM UTC 25
Finished Feb 08 01:01:31 PM UTC 25
Peak memory 687672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274776690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_host_fifo_full.1274776690
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_overflow.3392192505
Short name T90
Test name
Test status
Simulation time 9762921459 ps
CPU time 87.35 seconds
Started Feb 08 12:58:39 PM UTC 25
Finished Feb 08 01:00:08 PM UTC 25
Peak memory 837192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392192505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_host_fifo_overflow.3392192505
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_rx.3523204589
Short name T160
Test name
Test status
Simulation time 897526520 ps
CPU time 4.83 seconds
Started Feb 08 12:58:40 PM UTC 25
Finished Feb 08 12:58:46 PM UTC 25
Peak memory 215452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523204589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.3523204589
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_watermark.3722552641
Short name T452
Test name
Test status
Simulation time 4747180380 ps
CPU time 279.37 seconds
Started Feb 08 12:58:39 PM UTC 25
Finished Feb 08 01:03:22 PM UTC 25
Peak memory 1138180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722552641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 5.i2c_host_fifo_watermark.3722552641
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_host_may_nack.2500751753
Short name T353
Test name
Test status
Simulation time 567813233 ps
CPU time 6.79 seconds
Started Feb 08 12:59:12 PM UTC 25
Finished Feb 08 12:59:20 PM UTC 25
Peak memory 216128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500751753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 5.i2c_host_may_nack.2500751753
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_host_override.2476893487
Short name T139
Test name
Test status
Simulation time 27748612 ps
CPU time 0.96 seconds
Started Feb 08 12:58:38 PM UTC 25
Finished Feb 08 12:58:40 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476893487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 5.i2c_host_override.2476893487
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_host_perf.4272213219
Short name T17
Test name
Test status
Simulation time 25274870014 ps
CPU time 80.41 seconds
Started Feb 08 12:58:41 PM UTC 25
Finished Feb 08 01:00:03 PM UTC 25
Peak memory 263680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272213219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_host_perf.4272213219
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_host_perf_precise.3866710655
Short name T324
Test name
Test status
Simulation time 140806421 ps
CPU time 1.76 seconds
Started Feb 08 12:58:41 PM UTC 25
Finished Feb 08 12:58:44 PM UTC 25
Peak memory 236200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866710655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_host_perf_precise.3866710655
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_host_smoke.4292484744
Short name T287
Test name
Test status
Simulation time 4792378008 ps
CPU time 56.2 seconds
Started Feb 08 12:58:37 PM UTC 25
Finished Feb 08 12:59:35 PM UTC 25
Peak memory 401152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292484744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_host_smoke.4292484744
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_host_stretch_timeout.2096549794
Short name T351
Test name
Test status
Simulation time 2797479262 ps
CPU time 28.83 seconds
Started Feb 08 12:58:43 PM UTC 25
Finished Feb 08 12:59:14 PM UTC 25
Peak memory 226296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096549794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.i2c_host_stretch_timeout.2096549794
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_bad_addr.2311243059
Short name T349
Test name
Test status
Simulation time 6569404482 ps
CPU time 6.79 seconds
Started Feb 08 12:59:03 PM UTC 25
Finished Feb 08 12:59:11 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2311243059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2311243059
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_acq.1645997190
Short name T346
Test name
Test status
Simulation time 203304650 ps
CPU time 2.32 seconds
Started Feb 08 12:59:00 PM UTC 25
Finished Feb 08 12:59:03 PM UTC 25
Peak memory 215712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645997190 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_acq.1645997190
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_tx.1107109131
Short name T345
Test name
Test status
Simulation time 485932354 ps
CPU time 1.32 seconds
Started Feb 08 12:59:00 PM UTC 25
Finished Feb 08 12:59:02 PM UTC 25
Peak memory 226144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107109131 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_tx.1107109131
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_acq.3364799791
Short name T352
Test name
Test status
Simulation time 349212164 ps
CPU time 3.25 seconds
Started Feb 08 12:59:13 PM UTC 25
Finished Feb 08 12:59:17 PM UTC 25
Peak memory 215992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364799791 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.3364799791
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_tx.2902024604
Short name T288
Test name
Test status
Simulation time 1046924918 ps
CPU time 2.14 seconds
Started Feb 08 12:59:15 PM UTC 25
Finished Feb 08 12:59:18 PM UTC 25
Peak memory 215912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902024604 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.2902024604
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_intr_smoke.137787288
Short name T347
Test name
Test status
Simulation time 5381684309 ps
CPU time 8.35 seconds
Started Feb 08 12:58:55 PM UTC 25
Finished Feb 08 12:59:04 PM UTC 25
Peak memory 245532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137787288 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_smoke.137787288
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_intr_stress_wr.3963057697
Short name T363
Test name
Test status
Simulation time 11782249942 ps
CPU time 89.16 seconds
Started Feb 08 12:58:56 PM UTC 25
Finished Feb 08 01:00:27 PM UTC 25
Peak memory 1504836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39630
57697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3963057697
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull.2291949115
Short name T358
Test name
Test status
Simulation time 2079330431 ps
CPU time 5.73 seconds
Started Feb 08 12:59:18 PM UTC 25
Finished Feb 08 12:59:25 PM UTC 25
Peak memory 226076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291949115 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_acqfull.2291949115
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull_addr.2687659780
Short name T356
Test name
Test status
Simulation time 2039956886 ps
CPU time 4.13 seconds
Started Feb 08 12:59:19 PM UTC 25
Finished Feb 08 12:59:25 PM UTC 25
Peak memory 215920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687659780 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.2687659780
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_perf.2911675314
Short name T350
Test name
Test status
Simulation time 3477366065 ps
CPU time 8.59 seconds
Started Feb 08 12:59:02 PM UTC 25
Finished Feb 08 12:59:12 PM UTC 25
Peak memory 233300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911675314 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_perf.2911675314
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_smbus_maxlen.2232339222
Short name T354
Test name
Test status
Simulation time 682399620 ps
CPU time 4.17 seconds
Started Feb 08 12:59:17 PM UTC 25
Finished Feb 08 12:59:22 PM UTC 25
Peak memory 215704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232339222 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smbus_maxlen.2232339222
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_smoke.2419287475
Short name T84
Test name
Test status
Simulation time 1543310460 ps
CPU time 56.37 seconds
Started Feb 08 12:58:44 PM UTC 25
Finished Feb 08 12:59:43 PM UTC 25
Peak memory 226252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419287475 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smoke.2419287475
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_stress_all.3381984071
Short name T462
Test name
Test status
Simulation time 35179470324 ps
CPU time 270.67 seconds
Started Feb 08 12:59:03 PM UTC 25
Finished Feb 08 01:03:37 PM UTC 25
Peak memory 3219224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381984071 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_all.3381984071
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_stress_rd.3594977518
Short name T343
Test name
Test status
Simulation time 1068110374 ps
CPU time 10.97 seconds
Started Feb 08 12:58:46 PM UTC 25
Finished Feb 08 12:58:59 PM UTC 25
Peak memory 215892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594977518 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_rd.3594977518
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_stress_wr.146936531
Short name T624
Test name
Test status
Simulation time 39627057377 ps
CPU time 593.29 seconds
Started Feb 08 12:58:45 PM UTC 25
Finished Feb 08 01:08:46 PM UTC 25
Peak memory 5000704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146936531 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_wr.146936531
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_stretch.1744198286
Short name T344
Test name
Test status
Simulation time 2290194193 ps
CPU time 6.19 seconds
Started Feb 08 12:58:51 PM UTC 25
Finished Feb 08 12:58:59 PM UTC 25
Peak memory 242948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744198286 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stretch.1744198286
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_timeout.2953905588
Short name T348
Test name
Test status
Simulation time 1494437648 ps
CPU time 9.14 seconds
Started Feb 08 12:58:59 PM UTC 25
Finished Feb 08 12:59:09 PM UTC 25
Peak memory 233220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953905588 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_timeout.2953905588
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/5.i2c_target_tx_stretch_ctrl.1962282848
Short name T359
Test name
Test status
Simulation time 459966719 ps
CPU time 9.51 seconds
Started Feb 08 12:59:15 PM UTC 25
Finished Feb 08 12:59:25 PM UTC 25
Peak memory 232504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962282848 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.1962282848
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_alert_test.350726929
Short name T370
Test name
Test status
Simulation time 18264663 ps
CPU time 0.96 seconds
Started Feb 08 01:00:35 PM UTC 25
Finished Feb 08 01:00:37 PM UTC 25
Peak memory 214936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350726929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM
_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.350726929
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_host_error_intr.1476956109
Short name T32
Test name
Test status
Simulation time 317221141 ps
CPU time 4.43 seconds
Started Feb 08 12:59:38 PM UTC 25
Finished Feb 08 12:59:44 PM UTC 25
Peak memory 226224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476956109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_host_error_intr.1476956109
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_fmt_empty.1174689857
Short name T87
Test name
Test status
Simulation time 511025635 ps
CPU time 28.75 seconds
Started Feb 08 12:59:27 PM UTC 25
Finished Feb 08 12:59:57 PM UTC 25
Peak memory 316868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174689857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty.1174689857
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_full.2017940159
Short name T33
Test name
Test status
Simulation time 2416588648 ps
CPU time 115.42 seconds
Started Feb 08 12:59:31 PM UTC 25
Finished Feb 08 01:01:28 PM UTC 25
Peak memory 298120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017940159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_host_fifo_full.2017940159
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_overflow.2645571425
Short name T171
Test name
Test status
Simulation time 1366871867 ps
CPU time 49.59 seconds
Started Feb 08 12:59:26 PM UTC 25
Finished Feb 08 01:00:18 PM UTC 25
Peak memory 492944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645571425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_host_fifo_overflow.2645571425
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_fmt.2519266581
Short name T241
Test name
Test status
Simulation time 1281076644 ps
CPU time 1.38 seconds
Started Feb 08 12:59:27 PM UTC 25
Finished Feb 08 12:59:29 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519266581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt.2519266581
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_rx.2143409937
Short name T362
Test name
Test status
Simulation time 405722725 ps
CPU time 6.77 seconds
Started Feb 08 12:59:30 PM UTC 25
Finished Feb 08 12:59:38 PM UTC 25
Peak memory 257548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143409937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.2143409937
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_watermark.2413283031
Short name T172
Test name
Test status
Simulation time 11655511027 ps
CPU time 72.44 seconds
Started Feb 08 12:59:26 PM UTC 25
Finished Feb 08 01:00:41 PM UTC 25
Peak memory 931592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413283031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 6.i2c_host_fifo_watermark.2413283031
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_host_may_nack.3440239458
Short name T373
Test name
Test status
Simulation time 1469985925 ps
CPU time 9.24 seconds
Started Feb 08 01:00:27 PM UTC 25
Finished Feb 08 01:00:38 PM UTC 25
Peak memory 215856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440239458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 6.i2c_host_may_nack.3440239458
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_host_mode_toggle.2591559209
Short name T28
Test name
Test status
Simulation time 258737276 ps
CPU time 1.32 seconds
Started Feb 08 01:00:27 PM UTC 25
Finished Feb 08 01:00:30 PM UTC 25
Peak memory 226092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591559209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_t
oggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_host_mode_toggle.2591559209
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_host_override.1791143941
Short name T360
Test name
Test status
Simulation time 28211137 ps
CPU time 0.94 seconds
Started Feb 08 12:59:26 PM UTC 25
Finished Feb 08 12:59:29 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791143941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 6.i2c_host_override.1791143941
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_host_perf_precise.1045832867
Short name T361
Test name
Test status
Simulation time 368928363 ps
CPU time 1.91 seconds
Started Feb 08 12:59:34 PM UTC 25
Finished Feb 08 12:59:37 PM UTC 25
Peak memory 213864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045832867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_host_perf_precise.1045832867
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_host_smoke.2596187142
Short name T264
Test name
Test status
Simulation time 3464658792 ps
CPU time 44.48 seconds
Started Feb 08 12:59:25 PM UTC 25
Finished Feb 08 01:00:11 PM UTC 25
Peak memory 333316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596187142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_host_smoke.2596187142
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_host_stretch_timeout.1527181453
Short name T88
Test name
Test status
Simulation time 851499636 ps
CPU time 21.2 seconds
Started Feb 08 12:59:35 PM UTC 25
Finished Feb 08 12:59:58 PM UTC 25
Peak memory 228332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527181453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.i2c_host_stretch_timeout.1527181453
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_bad_addr.4166193472
Short name T375
Test name
Test status
Simulation time 4443738150 ps
CPU time 11.12 seconds
Started Feb 08 01:00:27 PM UTC 25
Finished Feb 08 01:00:40 PM UTC 25
Peak memory 228168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=4166193472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.4166193472
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_acq.2968271419
Short name T166
Test name
Test status
Simulation time 510770014 ps
CPU time 1.65 seconds
Started Feb 08 01:00:25 PM UTC 25
Finished Feb 08 01:00:30 PM UTC 25
Peak memory 216176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968271419 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_acq.2968271419
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_tx.2073255164
Short name T365
Test name
Test status
Simulation time 381821180 ps
CPU time 1.7 seconds
Started Feb 08 01:00:27 PM UTC 25
Finished Feb 08 01:00:31 PM UTC 25
Peak memory 216160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073255164 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_tx.2073255164
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_acq.3702941538
Short name T366
Test name
Test status
Simulation time 104195770 ps
CPU time 1.43 seconds
Started Feb 08 01:00:28 PM UTC 25
Finished Feb 08 01:00:31 PM UTC 25
Peak memory 214532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702941538 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.3702941538
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_tx.3400534269
Short name T367
Test name
Test status
Simulation time 256363121 ps
CPU time 1.86 seconds
Started Feb 08 01:00:30 PM UTC 25
Finished Feb 08 01:00:33 PM UTC 25
Peak memory 213932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400534269 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.3400534269
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_hrst.721134799
Short name T177
Test name
Test status
Simulation time 251597118 ps
CPU time 2.89 seconds
Started Feb 08 01:00:27 PM UTC 25
Finished Feb 08 01:00:32 PM UTC 25
Peak memory 225908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721134799 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_hrst.721134799
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_intr_smoke.2101486162
Short name T91
Test name
Test status
Simulation time 2853587545 ps
CPU time 7.76 seconds
Started Feb 08 01:00:00 PM UTC 25
Finished Feb 08 01:00:09 PM UTC 25
Peak memory 226456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101486162 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_smoke.2101486162
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_intr_stress_wr.1622762618
Short name T514
Test name
Test status
Simulation time 14950751750 ps
CPU time 287.61 seconds
Started Feb 08 01:00:03 PM UTC 25
Finished Feb 08 01:05:19 PM UTC 25
Peak memory 3614208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16227
62618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.1622762618
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull.1130470268
Short name T55
Test name
Test status
Simulation time 1351419731 ps
CPU time 4.07 seconds
Started Feb 08 01:00:31 PM UTC 25
Finished Feb 08 01:00:37 PM UTC 25
Peak memory 226220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130470268 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_acqfull.1130470268
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull_addr.1178232542
Short name T371
Test name
Test status
Simulation time 1087273149 ps
CPU time 3.24 seconds
Started Feb 08 01:00:32 PM UTC 25
Finished Feb 08 01:00:37 PM UTC 25
Peak memory 215988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178232542 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.1178232542
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_nack_txstretch.4152934
Short name T167
Test name
Test status
Simulation time 222468258 ps
CPU time 2.12 seconds
Started Feb 08 01:00:32 PM UTC 25
Finished Feb 08 01:00:36 PM UTC 25
Peak memory 233228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152934 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_txstretch.4152934
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_perf.1435964490
Short name T369
Test name
Test status
Simulation time 1521783485 ps
CPU time 7.57 seconds
Started Feb 08 01:00:27 PM UTC 25
Finished Feb 08 01:00:37 PM UTC 25
Peak memory 232548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435964490 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_perf.1435964490
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_smbus_maxlen.3842676348
Short name T368
Test name
Test status
Simulation time 1860343291 ps
CPU time 3.41 seconds
Started Feb 08 01:00:31 PM UTC 25
Finished Feb 08 01:00:36 PM UTC 25
Peak memory 215612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842676348 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smbus_maxlen.3842676348
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_smoke.1423194570
Short name T89
Test name
Test status
Simulation time 3730249463 ps
CPU time 16.74 seconds
Started Feb 08 12:59:43 PM UTC 25
Finished Feb 08 01:00:02 PM UTC 25
Peak memory 226332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423194570 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smoke.1423194570
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_stress_all.1150520949
Short name T290
Test name
Test status
Simulation time 79106387500 ps
CPU time 164.52 seconds
Started Feb 08 01:00:27 PM UTC 25
Finished Feb 08 01:03:15 PM UTC 25
Peak memory 1756696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150520949 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_all.1150520949
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_stress_rd.3324644108
Short name T92
Test name
Test status
Simulation time 910078358 ps
CPU time 10.09 seconds
Started Feb 08 12:59:58 PM UTC 25
Finished Feb 08 01:00:10 PM UTC 25
Peak memory 215848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324644108 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_rd.3324644108
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_stress_wr.3220195541
Short name T1573
Test name
Test status
Simulation time 59458857969 ps
CPU time 1985.98 seconds
Started Feb 08 12:59:44 PM UTC 25
Finished Feb 08 01:33:08 PM UTC 25
Peak memory 9963076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220195541 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_wr.3220195541
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_stretch.3105909971
Short name T93
Test name
Test status
Simulation time 3768698922 ps
CPU time 11.06 seconds
Started Feb 08 12:59:58 PM UTC 25
Finished Feb 08 01:00:11 PM UTC 25
Peak memory 331260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105909971 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stretch.3105909971
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_timeout.2732841359
Short name T377
Test name
Test status
Simulation time 1091096576 ps
CPU time 12.13 seconds
Started Feb 08 01:00:24 PM UTC 25
Finished Feb 08 01:00:41 PM UTC 25
Peak memory 233104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732841359 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_timeout.2732841359
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/6.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_alert_test.2661343110
Short name T355
Test name
Test status
Simulation time 139967013 ps
CPU time 0.89 seconds
Started Feb 08 01:01:04 PM UTC 25
Finished Feb 08 01:01:06 PM UTC 25
Peak memory 213912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661343110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2661343110
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_host_error_intr.511322217
Short name T380
Test name
Test status
Simulation time 2153100264 ps
CPU time 7.66 seconds
Started Feb 08 01:00:41 PM UTC 25
Finished Feb 08 01:00:50 PM UTC 25
Peak memory 232836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511322217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_host_error_intr.511322217
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_fmt_empty.3261405145
Short name T385
Test name
Test status
Simulation time 1168589886 ps
CPU time 13.82 seconds
Started Feb 08 01:00:38 PM UTC 25
Finished Feb 08 01:00:53 PM UTC 25
Peak memory 276024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261405145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty.3261405145
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_full.1392311168
Short name T425
Test name
Test status
Simulation time 7763667202 ps
CPU time 77.35 seconds
Started Feb 08 01:00:38 PM UTC 25
Finished Feb 08 01:01:58 PM UTC 25
Peak memory 511828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392311168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_host_fifo_full.1392311168
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_overflow.39717812
Short name T428
Test name
Test status
Simulation time 2709867910 ps
CPU time 87.01 seconds
Started Feb 08 01:00:37 PM UTC 25
Finished Feb 08 01:02:06 PM UTC 25
Peak memory 906840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39717812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_ove
rflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_host_fifo_overflow.39717812
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_fmt.2909395887
Short name T376
Test name
Test status
Simulation time 123466420 ps
CPU time 1.2 seconds
Started Feb 08 01:00:38 PM UTC 25
Finished Feb 08 01:00:40 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909395887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt.2909395887
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_rx.475013098
Short name T379
Test name
Test status
Simulation time 698722577 ps
CPU time 10.94 seconds
Started Feb 08 01:00:38 PM UTC 25
Finished Feb 08 01:00:50 PM UTC 25
Peak memory 247176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475013098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.475013098
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_host_may_nack.2629906118
Short name T254
Test name
Test status
Simulation time 737383850 ps
CPU time 33.57 seconds
Started Feb 08 01:00:58 PM UTC 25
Finished Feb 08 01:01:33 PM UTC 25
Peak memory 215852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629906118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 7.i2c_host_may_nack.2629906118
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_host_override.4230453733
Short name T372
Test name
Test status
Simulation time 89483747 ps
CPU time 0.98 seconds
Started Feb 08 01:00:35 PM UTC 25
Finished Feb 08 01:00:37 PM UTC 25
Peak memory 213920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230453733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 7.i2c_host_override.4230453733
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_host_perf.2304647543
Short name T382
Test name
Test status
Simulation time 4236935915 ps
CPU time 12.91 seconds
Started Feb 08 01:00:38 PM UTC 25
Finished Feb 08 01:00:53 PM UTC 25
Peak memory 331520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304647543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_host_perf.2304647543
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_host_perf_precise.729518991
Short name T378
Test name
Test status
Simulation time 207361405 ps
CPU time 2.07 seconds
Started Feb 08 01:00:39 PM UTC 25
Finished Feb 08 01:00:43 PM UTC 25
Peak memory 215976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729518991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pr
ecise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_host_perf_precise.729518991
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_host_smoke.3733459479
Short name T390
Test name
Test status
Simulation time 1068397573 ps
CPU time 21.08 seconds
Started Feb 08 01:00:35 PM UTC 25
Finished Feb 08 01:00:57 PM UTC 25
Peak memory 314900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733459479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_host_smoke.3733459479
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_host_stress_all.1826424151
Short name T111
Test name
Test status
Simulation time 8738662808 ps
CPU time 235.8 seconds
Started Feb 08 01:00:41 PM UTC 25
Finished Feb 08 01:04:41 PM UTC 25
Peak memory 1066560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826424151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_host_stress_all.1826424151
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_host_stretch_timeout.1451624353
Short name T381
Test name
Test status
Simulation time 536153868 ps
CPU time 10.63 seconds
Started Feb 08 01:00:40 PM UTC 25
Finished Feb 08 01:00:52 PM UTC 25
Peak memory 226212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451624353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.i2c_host_stretch_timeout.1451624353
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_bad_addr.1849002247
Short name T289
Test name
Test status
Simulation time 3286924433 ps
CPU time 4.79 seconds
Started Feb 08 01:00:54 PM UTC 25
Finished Feb 08 01:01:00 PM UTC 25
Peak memory 226216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=1849002247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.1849002247
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_acq.741574132
Short name T388
Test name
Test status
Simulation time 217581691 ps
CPU time 1.79 seconds
Started Feb 08 01:00:53 PM UTC 25
Finished Feb 08 01:00:56 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741574132 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_acq.741574132
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_tx.1685563551
Short name T387
Test name
Test status
Simulation time 140453627 ps
CPU time 1.73 seconds
Started Feb 08 01:00:53 PM UTC 25
Finished Feb 08 01:00:56 PM UTC 25
Peak memory 214524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685563551 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_tx.1685563551
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_acq.2994263387
Short name T395
Test name
Test status
Simulation time 1159197976 ps
CPU time 3.14 seconds
Started Feb 08 01:00:59 PM UTC 25
Finished Feb 08 01:01:03 PM UTC 25
Peak memory 215976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994263387 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.2994263387
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_tx.649839811
Short name T394
Test name
Test status
Simulation time 180774548 ps
CPU time 0.99 seconds
Started Feb 08 01:01:00 PM UTC 25
Finished Feb 08 01:01:02 PM UTC 25
Peak memory 213936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649839811 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.649839811
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_intr_smoke.1764258402
Short name T384
Test name
Test status
Simulation time 814375141 ps
CPU time 4.82 seconds
Started Feb 08 01:00:47 PM UTC 25
Finished Feb 08 01:00:53 PM UTC 25
Peak memory 226408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764258402 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_smoke.1764258402
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_intr_stress_wr.297729757
Short name T423
Test name
Test status
Simulation time 10265180747 ps
CPU time 59.93 seconds
Started Feb 08 01:00:51 PM UTC 25
Finished Feb 08 01:01:53 PM UTC 25
Peak memory 1050380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29772
9757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.297729757
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull.3344587643
Short name T397
Test name
Test status
Simulation time 456814190 ps
CPU time 3.96 seconds
Started Feb 08 01:01:02 PM UTC 25
Finished Feb 08 01:01:07 PM UTC 25
Peak memory 226412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344587643 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_acqfull.3344587643
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull_addr.30119952
Short name T50
Test name
Test status
Simulation time 5134608002 ps
CPU time 4.06 seconds
Started Feb 08 01:01:03 PM UTC 25
Finished Feb 08 01:01:08 PM UTC 25
Peak memory 216056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30119952 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.30119952
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_perf.4006947504
Short name T392
Test name
Test status
Simulation time 3358973594 ps
CPU time 6.24 seconds
Started Feb 08 01:00:53 PM UTC 25
Finished Feb 08 01:01:01 PM UTC 25
Peak memory 228200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006947504 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_perf.4006947504
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_smbus_maxlen.556318994
Short name T364
Test name
Test status
Simulation time 508845125 ps
CPU time 3.09 seconds
Started Feb 08 01:01:02 PM UTC 25
Finished Feb 08 01:01:06 PM UTC 25
Peak memory 215700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556318994 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smbus_maxlen.556318994
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_smoke.3363609379
Short name T391
Test name
Test status
Simulation time 3200680158 ps
CPU time 15.8 seconds
Started Feb 08 01:00:42 PM UTC 25
Finished Feb 08 01:00:59 PM UTC 25
Peak memory 226260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363609379 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smoke.3363609379
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_stress_all.1969402847
Short name T449
Test name
Test status
Simulation time 36667615543 ps
CPU time 125.32 seconds
Started Feb 08 01:00:54 PM UTC 25
Finished Feb 08 01:03:02 PM UTC 25
Peak memory 1029660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969402847 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_all.1969402847
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_stress_rd.3374213010
Short name T403
Test name
Test status
Simulation time 1087524483 ps
CPU time 45.46 seconds
Started Feb 08 01:00:43 PM UTC 25
Finished Feb 08 01:01:30 PM UTC 25
Peak memory 226420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374213010 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_rd.3374213010
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_stress_wr.314443299
Short name T271
Test name
Test status
Simulation time 9682400590 ps
CPU time 29.48 seconds
Started Feb 08 01:00:42 PM UTC 25
Finished Feb 08 01:01:13 PM UTC 25
Peak memory 216048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314443299 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_wr.314443299
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_stretch.4169267602
Short name T383
Test name
Test status
Simulation time 737476661 ps
CPU time 7.57 seconds
Started Feb 08 01:00:44 PM UTC 25
Finished Feb 08 01:00:53 PM UTC 25
Peak memory 232908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169267602 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stretch.4169267602
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_timeout.759446366
Short name T393
Test name
Test status
Simulation time 1276150888 ps
CPU time 9.44 seconds
Started Feb 08 01:00:51 PM UTC 25
Finished Feb 08 01:01:02 PM UTC 25
Peak memory 226348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759446366 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_timeout.759446366
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/7.i2c_target_tx_stretch_ctrl.1919339598
Short name T396
Test name
Test status
Simulation time 54588486 ps
CPU time 1.71 seconds
Started Feb 08 01:01:01 PM UTC 25
Finished Feb 08 01:01:04 PM UTC 25
Peak memory 214348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919339598 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.1919339598
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_alert_test.636834754
Short name T418
Test name
Test status
Simulation time 19865342 ps
CPU time 0.91 seconds
Started Feb 08 01:01:47 PM UTC 25
Finished Feb 08 01:01:49 PM UTC 25
Peak memory 214936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636834754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM
_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.636834754
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_host_error_intr.1197037296
Short name T34
Test name
Test status
Simulation time 52044818 ps
CPU time 1.72 seconds
Started Feb 08 01:01:13 PM UTC 25
Finished Feb 08 01:01:16 PM UTC 25
Peak memory 226032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197037296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_host_error_intr.1197037296
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_fmt_empty.3193968601
Short name T402
Test name
Test status
Simulation time 330906595 ps
CPU time 15.22 seconds
Started Feb 08 01:01:07 PM UTC 25
Finished Feb 08 01:01:24 PM UTC 25
Peak memory 270012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193968601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty.3193968601
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_full.2825795043
Short name T405
Test name
Test status
Simulation time 28745984388 ps
CPU time 139.17 seconds
Started Feb 08 01:01:10 PM UTC 25
Finished Feb 08 01:03:31 PM UTC 25
Peak memory 495008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825795043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 8.i2c_host_fifo_full.2825795043
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_overflow.2967910803
Short name T445
Test name
Test status
Simulation time 7564649890 ps
CPU time 108.44 seconds
Started Feb 08 01:01:07 PM UTC 25
Finished Feb 08 01:02:58 PM UTC 25
Peak memory 572932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967910803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_host_fifo_overflow.2967910803
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_fmt.3187252610
Short name T399
Test name
Test status
Simulation time 214367025 ps
CPU time 1.54 seconds
Started Feb 08 01:01:07 PM UTC 25
Finished Feb 08 01:01:10 PM UTC 25
Peak memory 214492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187252610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt.3187252610
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_rx.1341741171
Short name T235
Test name
Test status
Simulation time 375538359 ps
CPU time 5.04 seconds
Started Feb 08 01:01:08 PM UTC 25
Finished Feb 08 01:01:15 PM UTC 25
Peak memory 215964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341741171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.1341741171
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_watermark.3206500861
Short name T470
Test name
Test status
Simulation time 11630235956 ps
CPU time 153.9 seconds
Started Feb 08 01:01:07 PM UTC 25
Finished Feb 08 01:03:44 PM UTC 25
Peak memory 894536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206500861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 8.i2c_host_fifo_watermark.3206500861
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_host_may_nack.3036269259
Short name T252
Test name
Test status
Simulation time 418555876 ps
CPU time 17.57 seconds
Started Feb 08 01:01:34 PM UTC 25
Finished Feb 08 01:01:53 PM UTC 25
Peak memory 215912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036269259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 8.i2c_host_may_nack.3036269259
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_host_mode_toggle.3873626777
Short name T29
Test name
Test status
Simulation time 82634194 ps
CPU time 3.17 seconds
Started Feb 08 01:01:34 PM UTC 25
Finished Feb 08 01:01:38 PM UTC 25
Peak memory 226148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873626777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_t
oggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_host_mode_toggle.3873626777
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_host_override.1383653311
Short name T398
Test name
Test status
Simulation time 41713740 ps
CPU time 0.99 seconds
Started Feb 08 01:01:07 PM UTC 25
Finished Feb 08 01:01:09 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383653311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 8.i2c_host_override.1383653311
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_host_perf.277556278
Short name T18
Test name
Test status
Simulation time 7391442404 ps
CPU time 17 seconds
Started Feb 08 01:01:10 PM UTC 25
Finished Feb 08 01:01:28 PM UTC 25
Peak memory 363988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277556278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_host_perf.277556278
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_host_perf_precise.2438355043
Short name T232
Test name
Test status
Simulation time 1968786409 ps
CPU time 6.85 seconds
Started Feb 08 01:01:11 PM UTC 25
Finished Feb 08 01:01:19 PM UTC 25
Peak memory 215904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438355043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_p
recise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_host_perf_precise.2438355043
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_host_smoke.3935763955
Short name T409
Test name
Test status
Simulation time 6583914344 ps
CPU time 27.46 seconds
Started Feb 08 01:01:04 PM UTC 25
Finished Feb 08 01:01:33 PM UTC 25
Peak memory 360000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935763955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_host_smoke.3935763955
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_host_stress_all.4159487523
Short name T39
Test name
Test status
Simulation time 24847409693 ps
CPU time 699.6 seconds
Started Feb 08 01:01:14 PM UTC 25
Finished Feb 08 01:13:01 PM UTC 25
Peak memory 2160360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159487523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_host_stress_all.4159487523
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_host_stretch_timeout.2215329821
Short name T401
Test name
Test status
Simulation time 490854955 ps
CPU time 11.44 seconds
Started Feb 08 01:01:11 PM UTC 25
Finished Feb 08 01:01:23 PM UTC 25
Peak memory 228280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215329821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.i2c_host_stretch_timeout.2215329821
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_bad_addr.2489302597
Short name T414
Test name
Test status
Simulation time 5041321761 ps
CPU time 8.64 seconds
Started Feb 08 01:01:33 PM UTC 25
Finished Feb 08 01:01:43 PM UTC 25
Peak memory 226160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=2489302597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.2489302597
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_acq.4144190158
Short name T407
Test name
Test status
Simulation time 456257224 ps
CPU time 1.49 seconds
Started Feb 08 01:01:30 PM UTC 25
Finished Feb 08 01:01:32 PM UTC 25
Peak memory 214284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144190158 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_acq.4144190158
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_tx.534036386
Short name T408
Test name
Test status
Simulation time 187582121 ps
CPU time 2.01 seconds
Started Feb 08 01:01:30 PM UTC 25
Finished Feb 08 01:01:33 PM UTC 25
Peak memory 214532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534036386 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_tx.534036386
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_acq.1408950494
Short name T415
Test name
Test status
Simulation time 1110135830 ps
CPU time 4.17 seconds
Started Feb 08 01:01:38 PM UTC 25
Finished Feb 08 01:01:44 PM UTC 25
Peak memory 216048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408950494 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.1408950494
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_tx.1644227397
Short name T412
Test name
Test status
Simulation time 349687444 ps
CPU time 1.45 seconds
Started Feb 08 01:01:39 PM UTC 25
Finished Feb 08 01:01:42 PM UTC 25
Peak memory 213932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644227397 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.1644227397
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_intr_smoke.3728441278
Short name T406
Test name
Test status
Simulation time 3492832837 ps
CPU time 6.59 seconds
Started Feb 08 01:01:24 PM UTC 25
Finished Feb 08 01:01:32 PM UTC 25
Peak memory 226528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728441278 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_smoke.3728441278
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_intr_stress_wr.2148206733
Short name T568
Test name
Test status
Simulation time 16017275697 ps
CPU time 319.3 seconds
Started Feb 08 01:01:24 PM UTC 25
Finished Feb 08 01:06:48 PM UTC 25
Peak memory 3972680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21482
06733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.2148206733
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull.42350690
Short name T420
Test name
Test status
Simulation time 466898059 ps
CPU time 4.75 seconds
Started Feb 08 01:01:43 PM UTC 25
Finished Feb 08 01:01:49 PM UTC 25
Peak memory 226140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42350690 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_acqfull.42350690
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull_addr.1483507352
Short name T419
Test name
Test status
Simulation time 9323162719 ps
CPU time 4.1 seconds
Started Feb 08 01:01:44 PM UTC 25
Finished Feb 08 01:01:49 PM UTC 25
Peak memory 216044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483507352 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.1483507352
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_nack_txstretch.3207834623
Short name T168
Test name
Test status
Simulation time 136661260 ps
CPU time 2.54 seconds
Started Feb 08 01:01:45 PM UTC 25
Finished Feb 08 01:01:48 PM UTC 25
Peak memory 232972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207834623 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_txstretch.3207834623
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_perf.2876193803
Short name T411
Test name
Test status
Simulation time 4017516259 ps
CPU time 5.91 seconds
Started Feb 08 01:01:31 PM UTC 25
Finished Feb 08 01:01:38 PM UTC 25
Peak memory 228248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876193803 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_perf.2876193803
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_smbus_maxlen.2635827521
Short name T417
Test name
Test status
Simulation time 1738597054 ps
CPU time 3.82 seconds
Started Feb 08 01:01:42 PM UTC 25
Finished Feb 08 01:01:48 PM UTC 25
Peak memory 215636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635827521 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smbus_maxlen.2635827521
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_smoke.760230159
Short name T421
Test name
Test status
Simulation time 3008280240 ps
CPU time 31.86 seconds
Started Feb 08 01:01:16 PM UTC 25
Finished Feb 08 01:01:49 PM UTC 25
Peak memory 226264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760230159 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smoke.760230159
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_stress_all.522748577
Short name T268
Test name
Test status
Simulation time 20470651357 ps
CPU time 368.58 seconds
Started Feb 08 01:01:32 PM UTC 25
Finished Feb 08 01:07:45 PM UTC 25
Peak memory 2070024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522748577 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_all.522748577
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_stress_rd.2794878710
Short name T413
Test name
Test status
Simulation time 1061808656 ps
CPU time 24.99 seconds
Started Feb 08 01:01:16 PM UTC 25
Finished Feb 08 01:01:43 PM UTC 25
Peak memory 243144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794878710 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_rd.2794878710
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_stress_wr.4015110318
Short name T209
Test name
Test status
Simulation time 10496265398 ps
CPU time 8.42 seconds
Started Feb 08 01:01:16 PM UTC 25
Finished Feb 08 01:01:26 PM UTC 25
Peak memory 216024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015110318 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_wr.4015110318
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_timeout.593044732
Short name T410
Test name
Test status
Simulation time 1518890561 ps
CPU time 9.11 seconds
Started Feb 08 01:01:26 PM UTC 25
Finished Feb 08 01:01:37 PM UTC 25
Peak memory 243168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593044732 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_timeout.593044732
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/8.i2c_target_tx_stretch_ctrl.2907575058
Short name T416
Test name
Test status
Simulation time 139876830 ps
CPU time 5.06 seconds
Started Feb 08 01:01:39 PM UTC 25
Finished Feb 08 01:01:46 PM UTC 25
Peak memory 216120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907575058 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.2907575058
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_alert_test.3342084932
Short name T450
Test name
Test status
Simulation time 85592501 ps
CPU time 0.89 seconds
Started Feb 08 01:03:02 PM UTC 25
Finished Feb 08 01:03:04 PM UTC 25
Peak memory 213728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342084932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UV
M_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.3342084932
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_host_error_intr.3341736495
Short name T429
Test name
Test status
Simulation time 372377776 ps
CPU time 4.44 seconds
Started Feb 08 01:02:00 PM UTC 25
Finished Feb 08 01:02:06 PM UTC 25
Peak memory 226392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341736495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_host_error_intr.3341736495
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_fmt_empty.4144439447
Short name T426
Test name
Test status
Simulation time 1172693983 ps
CPU time 8.8 seconds
Started Feb 08 01:01:50 PM UTC 25
Finished Feb 08 01:02:00 PM UTC 25
Peak memory 279992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144439447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +
UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty.4144439447
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_full.2015723182
Short name T446
Test name
Test status
Simulation time 1789470530 ps
CPU time 64.86 seconds
Started Feb 08 01:01:53 PM UTC 25
Finished Feb 08 01:03:00 PM UTC 25
Peak memory 544212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015723182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_f
ull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_host_fifo_full.2015723182
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_overflow.1264634451
Short name T453
Test name
Test status
Simulation time 2590691600 ps
CPU time 91.88 seconds
Started Feb 08 01:01:50 PM UTC 25
Finished Feb 08 01:03:24 PM UTC 25
Peak memory 874064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264634451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_o
verflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_host_fifo_overflow.1264634451
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_fmt.347718280
Short name T424
Test name
Test status
Simulation time 301482620 ps
CPU time 1.48 seconds
Started Feb 08 01:01:50 PM UTC 25
Finished Feb 08 01:01:53 PM UTC 25
Peak memory 214512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347718280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt.347718280
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_rx.193500186
Short name T236
Test name
Test status
Simulation time 365990012 ps
CPU time 6.61 seconds
Started Feb 08 01:01:52 PM UTC 25
Finished Feb 08 01:02:00 PM UTC 25
Peak memory 251408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193500186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +U
VM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.193500186
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_watermark.1366375976
Short name T110
Test name
Test status
Simulation time 7605479693 ps
CPU time 77.77 seconds
Started Feb 08 01:01:50 PM UTC 25
Finished Feb 08 01:03:10 PM UTC 25
Peak memory 1003204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366375976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_w
atermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 9.i2c_host_fifo_watermark.1366375976
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_host_may_nack.1243791768
Short name T442
Test name
Test status
Simulation time 839250121 ps
CPU time 7.01 seconds
Started Feb 08 01:02:44 PM UTC 25
Finished Feb 08 01:02:52 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243791768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_na
ck_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 9.i2c_host_may_nack.1243791768
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_host_override.3355499952
Short name T422
Test name
Test status
Simulation time 26894434 ps
CPU time 0.96 seconds
Started Feb 08 01:01:49 PM UTC 25
Finished Feb 08 01:01:51 PM UTC 25
Peak memory 214520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355499952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_overri
de_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 9.i2c_host_override.3355499952
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_host_perf.1858957141
Short name T438
Test name
Test status
Simulation time 29808476296 ps
CPU time 40.01 seconds
Started Feb 08 01:01:53 PM UTC 25
Finished Feb 08 01:02:35 PM UTC 25
Peak memory 540176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858957141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_host_perf.1858957141
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_host_perf_precise.37058303
Short name T427
Test name
Test status
Simulation time 454653671 ps
CPU time 4.71 seconds
Started Feb 08 01:01:54 PM UTC 25
Finished Feb 08 01:02:00 PM UTC 25
Peak memory 243144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37058303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_pre
cise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_host_perf_precise.37058303
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_host_smoke.2843121639
Short name T455
Test name
Test status
Simulation time 1889886892 ps
CPU time 93.61 seconds
Started Feb 08 01:01:49 PM UTC 25
Finished Feb 08 01:03:25 PM UTC 25
Peak memory 261840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843121639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_host_smoke.2843121639
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_host_stretch_timeout.4284830011
Short name T432
Test name
Test status
Simulation time 3150762763 ps
CPU time 25.39 seconds
Started Feb 08 01:01:58 PM UTC 25
Finished Feb 08 01:02:25 PM UTC 25
Peak memory 226336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284830011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretc
h_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_host_stretch_timeout.4284830011
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_bad_addr.600831054
Short name T441
Test name
Test status
Simulation time 5382063727 ps
CPU time 10.66 seconds
Started Feb 08 01:02:35 PM UTC 25
Finished Feb 08 01:02:47 PM UTC 25
Peak memory 233160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct
=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se
ed=600831054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.600831054
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_acq.3133103
Short name T436
Test name
Test status
Simulation time 148796396 ps
CPU time 1.74 seconds
Started Feb 08 01:02:31 PM UTC 25
Finished Feb 08 01:02:34 PM UTC 25
Peak memory 214524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133103 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_acq.3133103
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_tx.2132290781
Short name T437
Test name
Test status
Simulation time 180363084 ps
CPU time 1.24 seconds
Started Feb 08 01:02:32 PM UTC 25
Finished Feb 08 01:02:35 PM UTC 25
Peak memory 213924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132290781 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_tx.2132290781
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_acq.2406567178
Short name T443
Test name
Test status
Simulation time 1287594946 ps
CPU time 3.26 seconds
Started Feb 08 01:02:48 PM UTC 25
Finished Feb 08 01:02:52 PM UTC 25
Peak memory 215908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406567178 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.2406567178
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_tx.381944338
Short name T444
Test name
Test status
Simulation time 136151394 ps
CPU time 1.66 seconds
Started Feb 08 01:02:53 PM UTC 25
Finished Feb 08 01:02:56 PM UTC 25
Peak memory 214536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381944338 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.381944338
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_intr_smoke.3477308345
Short name T433
Test name
Test status
Simulation time 4078428867 ps
CPU time 7.92 seconds
Started Feb 08 01:02:19 PM UTC 25
Finished Feb 08 01:02:28 PM UTC 25
Peak memory 235092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477308345 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_smoke.3477308345
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_intr_stress_wr.3016104930
Short name T525
Test name
Test status
Simulation time 10371559628 ps
CPU time 195.39 seconds
Started Feb 08 01:02:23 PM UTC 25
Finished Feb 08 01:05:41 PM UTC 25
Peak memory 2649672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30161
04930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.3016104930
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull.4201117221
Short name T56
Test name
Test status
Simulation time 1149588260 ps
CPU time 6.23 seconds
Started Feb 08 01:02:59 PM UTC 25
Finished Feb 08 01:03:07 PM UTC 25
Peak memory 226156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201117221 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_acqfull.4201117221
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull_addr.4099226062
Short name T51
Test name
Test status
Simulation time 1057892381 ps
CPU time 4.02 seconds
Started Feb 08 01:03:01 PM UTC 25
Finished Feb 08 01:03:06 PM UTC 25
Peak memory 215988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099226062 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.4099226062
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_nack_txstretch.3688122804
Short name T169
Test name
Test status
Simulation time 1309988518 ps
CPU time 2.33 seconds
Started Feb 08 01:03:01 PM UTC 25
Finished Feb 08 01:03:05 PM UTC 25
Peak memory 232884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688122804 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_txstretch.3688122804
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_perf.2774382017
Short name T440
Test name
Test status
Simulation time 841374012 ps
CPU time 4.4 seconds
Started Feb 08 01:02:33 PM UTC 25
Finished Feb 08 01:02:39 PM UTC 25
Peak memory 226152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774382017 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_perf.2774382017
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_smbus_maxlen.2163290855
Short name T448
Test name
Test status
Simulation time 1405445591 ps
CPU time 3.37 seconds
Started Feb 08 01:02:57 PM UTC 25
Finished Feb 08 01:03:02 PM UTC 25
Peak memory 215896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163290855 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smbus_maxlen.2163290855
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_smoke.2732143831
Short name T431
Test name
Test status
Simulation time 4309068396 ps
CPU time 14.63 seconds
Started Feb 08 01:02:02 PM UTC 25
Finished Feb 08 01:02:18 PM UTC 25
Peak memory 226400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732143831 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smoke.2732143831
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_stress_all.896579396
Short name T457
Test name
Test status
Simulation time 8486713367 ps
CPU time 51.61 seconds
Started Feb 08 01:02:35 PM UTC 25
Finished Feb 08 01:03:29 PM UTC 25
Peak memory 329036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896579396 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_all.896579396
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_stress_rd.2254694038
Short name T434
Test name
Test status
Simulation time 1395558027 ps
CPU time 22.49 seconds
Started Feb 08 01:02:07 PM UTC 25
Finished Feb 08 01:02:31 PM UTC 25
Peak memory 237256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254694038 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_rd.2254694038
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_stress_wr.3182669545
Short name T435
Test name
Test status
Simulation time 16907436549 ps
CPU time 23.76 seconds
Started Feb 08 01:02:07 PM UTC 25
Finished Feb 08 01:02:32 PM UTC 25
Peak memory 215972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182669545 -assert nopostproc +UVM_TE
STNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_wr.3182669545
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_stretch.282957155
Short name T456
Test name
Test status
Simulation time 2698407277 ps
CPU time 66.06 seconds
Started Feb 08 01:02:18 PM UTC 25
Finished Feb 08 01:03:26 PM UTC 25
Peak memory 507376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282957155 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stretch.282957155
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_timeout.2303172235
Short name T439
Test name
Test status
Simulation time 5602376091 ps
CPU time 9.4 seconds
Started Feb 08 01:02:26 PM UTC 25
Finished Feb 08 01:02:37 PM UTC 25
Peak memory 243280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303172235 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_timeout.2303172235
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/9.i2c_target_tx_stretch_ctrl.2959990920
Short name T447
Test name
Test status
Simulation time 173735241 ps
CPU time 5.82 seconds
Started Feb 08 01:02:53 PM UTC 25
Finished Feb 08 01:03:00 PM UTC 25
Peak memory 215928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959990920 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.2959990920
Directory /workspaces/repo/scratch/os_regression/i2c-sim-vcs/9.i2c_target_tx_stretch_ctrl/latest
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