Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.39 97.29 89.69 97.22 72.62 94.37 98.47 90.11


Total test records in report: 1839
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html
T212 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.2482855579 Oct 15 12:27:18 PM UTC 24 Oct 15 12:27:23 PM UTC 24 273230588 ps
T1762 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.3917805423 Oct 15 12:27:21 PM UTC 24 Oct 15 12:27:23 PM UTC 24 41461351 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.856824254 Oct 15 12:27:22 PM UTC 24 Oct 15 12:27:24 PM UTC 24 81072476 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.115308513 Oct 15 12:27:22 PM UTC 24 Oct 15 12:27:24 PM UTC 24 58814739 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.2945791539 Oct 15 12:27:21 PM UTC 24 Oct 15 12:27:24 PM UTC 24 173319148 ps
T1763 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2683385234 Oct 15 12:27:22 PM UTC 24 Oct 15 12:27:25 PM UTC 24 165888686 ps
T1764 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.2620260146 Oct 15 12:27:24 PM UTC 24 Oct 15 12:27:26 PM UTC 24 33855152 ps
T1765 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.4107321013 Oct 15 12:27:24 PM UTC 24 Oct 15 12:27:26 PM UTC 24 25152264 ps
T1766 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2123606281 Oct 15 12:27:23 PM UTC 24 Oct 15 12:27:26 PM UTC 24 23457722 ps
T1767 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1413435043 Oct 15 12:27:24 PM UTC 24 Oct 15 12:27:26 PM UTC 24 55648116 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.3707474795 Oct 15 12:27:23 PM UTC 24 Oct 15 12:27:26 PM UTC 24 90720428 ps
T1768 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1280427143 Oct 15 12:27:25 PM UTC 24 Oct 15 12:27:28 PM UTC 24 70701120 ps
T1769 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.1971593037 Oct 15 12:27:23 PM UTC 24 Oct 15 12:27:28 PM UTC 24 48597993 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.3787858964 Oct 15 12:27:25 PM UTC 24 Oct 15 12:27:28 PM UTC 24 106748713 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.1121249417 Oct 15 12:27:26 PM UTC 24 Oct 15 12:27:29 PM UTC 24 28674950 ps
T1770 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3131709954 Oct 15 12:27:26 PM UTC 24 Oct 15 12:27:29 PM UTC 24 25870470 ps
T1771 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.2898308951 Oct 15 12:27:25 PM UTC 24 Oct 15 12:27:29 PM UTC 24 34028397 ps
T1772 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3443674873 Oct 15 12:27:27 PM UTC 24 Oct 15 12:27:30 PM UTC 24 24357897 ps
T1773 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.1167795797 Oct 15 12:27:28 PM UTC 24 Oct 15 12:27:30 PM UTC 24 55088272 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.1344304595 Oct 15 12:27:28 PM UTC 24 Oct 15 12:27:30 PM UTC 24 175464950 ps
T1774 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.1342506853 Oct 15 12:27:29 PM UTC 24 Oct 15 12:27:31 PM UTC 24 42815799 ps
T1775 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.2619893260 Oct 15 12:27:27 PM UTC 24 Oct 15 12:27:32 PM UTC 24 169335878 ps
T1776 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.128851297 Oct 15 12:27:29 PM UTC 24 Oct 15 12:27:32 PM UTC 24 133705923 ps
T1777 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.595802610 Oct 15 12:27:29 PM UTC 24 Oct 15 12:27:32 PM UTC 24 26567293 ps
T1778 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.1340723069 Oct 15 12:27:29 PM UTC 24 Oct 15 12:27:32 PM UTC 24 216096614 ps
T1779 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.2715007410 Oct 15 12:27:30 PM UTC 24 Oct 15 12:27:33 PM UTC 24 103437270 ps
T1780 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.3746460733 Oct 15 12:27:30 PM UTC 24 Oct 15 12:27:34 PM UTC 24 17814703 ps
T1781 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.760783151 Oct 15 12:27:30 PM UTC 24 Oct 15 12:27:34 PM UTC 24 47167620 ps
T1782 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1555052629 Oct 15 12:27:31 PM UTC 24 Oct 15 12:27:35 PM UTC 24 51725799 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.3667592358 Oct 15 12:27:32 PM UTC 24 Oct 15 12:27:35 PM UTC 24 140039719 ps
T1783 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.3728199232 Oct 15 12:27:33 PM UTC 24 Oct 15 12:27:35 PM UTC 24 17038129 ps
T1784 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.1220788982 Oct 15 12:27:30 PM UTC 24 Oct 15 12:27:35 PM UTC 24 486894499 ps
T1785 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.4268516931 Oct 15 12:27:33 PM UTC 24 Oct 15 12:27:35 PM UTC 24 47652220 ps
T1786 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.1358398128 Oct 15 12:27:32 PM UTC 24 Oct 15 12:27:36 PM UTC 24 55086532 ps
T1787 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3673346975 Oct 15 12:27:33 PM UTC 24 Oct 15 12:27:36 PM UTC 24 37779511 ps
T1788 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.3776677438 Oct 15 12:27:33 PM UTC 24 Oct 15 12:27:37 PM UTC 24 257060861 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.1199093601 Oct 15 12:27:34 PM UTC 24 Oct 15 12:27:37 PM UTC 24 19764454 ps
T1789 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.4016078877 Oct 15 12:27:34 PM UTC 24 Oct 15 12:27:37 PM UTC 24 42845141 ps
T1790 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.3478155452 Oct 15 12:27:33 PM UTC 24 Oct 15 12:27:38 PM UTC 24 677129984 ps
T1791 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1694409552 Oct 15 12:27:35 PM UTC 24 Oct 15 12:27:38 PM UTC 24 127459398 ps
T1792 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1396046451 Oct 15 12:27:36 PM UTC 24 Oct 15 12:27:38 PM UTC 24 28127461 ps
T1793 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.1799321075 Oct 15 12:27:37 PM UTC 24 Oct 15 12:27:39 PM UTC 24 23828022 ps
T1794 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.248901487 Oct 15 12:27:37 PM UTC 24 Oct 15 12:27:39 PM UTC 24 18767770 ps
T1795 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1982189679 Oct 15 12:27:37 PM UTC 24 Oct 15 12:27:39 PM UTC 24 39340539 ps
T1796 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2520158157 Oct 15 12:27:37 PM UTC 24 Oct 15 12:27:40 PM UTC 24 40682344 ps
T1797 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.1908444060 Oct 15 12:27:37 PM UTC 24 Oct 15 12:27:40 PM UTC 24 57735098 ps
T1798 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.3364714953 Oct 15 12:27:38 PM UTC 24 Oct 15 12:27:40 PM UTC 24 121112970 ps
T1799 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.2385972135 Oct 15 12:27:38 PM UTC 24 Oct 15 12:27:41 PM UTC 24 20232082 ps
T1800 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.1314649937 Oct 15 12:27:37 PM UTC 24 Oct 15 12:27:41 PM UTC 24 316239134 ps
T1801 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1622984702 Oct 15 12:27:39 PM UTC 24 Oct 15 12:27:41 PM UTC 24 21859255 ps
T1802 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.892879648 Oct 15 12:27:39 PM UTC 24 Oct 15 12:27:41 PM UTC 24 140929520 ps
T1803 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.296094437 Oct 15 12:27:37 PM UTC 24 Oct 15 12:27:41 PM UTC 24 73890249 ps
T1804 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.2146332044 Oct 15 12:27:38 PM UTC 24 Oct 15 12:27:41 PM UTC 24 78418202 ps
T1805 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.2985362266 Oct 15 12:27:40 PM UTC 24 Oct 15 12:27:42 PM UTC 24 49282319 ps
T1806 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.1589851794 Oct 15 12:27:40 PM UTC 24 Oct 15 12:27:42 PM UTC 24 21575457 ps
T1807 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.2539026915 Oct 15 12:27:40 PM UTC 24 Oct 15 12:27:43 PM UTC 24 46073220 ps
T1808 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.463167733 Oct 15 12:27:41 PM UTC 24 Oct 15 12:27:43 PM UTC 24 47349143 ps
T1809 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.117197697 Oct 15 12:27:41 PM UTC 24 Oct 15 12:27:44 PM UTC 24 21261216 ps
T1810 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.1779498661 Oct 15 12:27:40 PM UTC 24 Oct 15 12:27:44 PM UTC 24 144146264 ps
T1811 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.1173068069 Oct 15 12:27:41 PM UTC 24 Oct 15 12:27:44 PM UTC 24 39053965 ps
T1812 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3121838201 Oct 15 12:27:41 PM UTC 24 Oct 15 12:27:44 PM UTC 24 50322124 ps
T1813 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.3451354387 Oct 15 12:27:43 PM UTC 24 Oct 15 12:27:45 PM UTC 24 33713172 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.3404542529 Oct 15 12:27:43 PM UTC 24 Oct 15 12:27:45 PM UTC 24 28442421 ps
T1814 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.3980893938 Oct 15 12:27:43 PM UTC 24 Oct 15 12:27:45 PM UTC 24 60656150 ps
T1815 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.4269472271 Oct 15 12:27:43 PM UTC 24 Oct 15 12:27:45 PM UTC 24 18358123 ps
T1816 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.3105957115 Oct 15 12:27:43 PM UTC 24 Oct 15 12:27:45 PM UTC 24 52239407 ps
T1817 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.1442417904 Oct 15 12:27:43 PM UTC 24 Oct 15 12:27:45 PM UTC 24 15568758 ps
T1818 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.4223406118 Oct 15 12:27:43 PM UTC 24 Oct 15 12:27:45 PM UTC 24 28588693 ps
T1819 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.4017792452 Oct 15 12:27:44 PM UTC 24 Oct 15 12:27:47 PM UTC 24 18234093 ps
T1820 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.3228625294 Oct 15 12:27:44 PM UTC 24 Oct 15 12:27:47 PM UTC 24 31324400 ps
T1821 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.2806235194 Oct 15 12:27:44 PM UTC 24 Oct 15 12:27:47 PM UTC 24 18262447 ps
T1822 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.4175941754 Oct 15 12:27:44 PM UTC 24 Oct 15 12:27:47 PM UTC 24 48169513 ps
T1823 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.4165733394 Oct 15 12:27:45 PM UTC 24 Oct 15 12:27:47 PM UTC 24 27007483 ps
T1824 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.783884737 Oct 15 12:27:45 PM UTC 24 Oct 15 12:27:47 PM UTC 24 44824362 ps
T1825 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.1155274587 Oct 15 12:27:46 PM UTC 24 Oct 15 12:27:48 PM UTC 24 21756590 ps
T1826 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.3208596832 Oct 15 12:27:46 PM UTC 24 Oct 15 12:27:48 PM UTC 24 23455193 ps
T1827 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.526784378 Oct 15 12:27:46 PM UTC 24 Oct 15 12:27:48 PM UTC 24 43450860 ps
T1828 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.1193400467 Oct 15 12:27:46 PM UTC 24 Oct 15 12:27:48 PM UTC 24 18255828 ps
T1829 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.990881884 Oct 15 12:27:46 PM UTC 24 Oct 15 12:27:48 PM UTC 24 54140623 ps
T1830 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.543860017 Oct 15 12:27:46 PM UTC 24 Oct 15 12:27:49 PM UTC 24 18199593 ps
T1831 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.1770086838 Oct 15 12:27:46 PM UTC 24 Oct 15 12:27:49 PM UTC 24 51183604 ps
T1832 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.1406202423 Oct 15 12:27:46 PM UTC 24 Oct 15 12:27:49 PM UTC 24 91506055 ps
T1833 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.1614130657 Oct 15 12:27:48 PM UTC 24 Oct 15 12:27:50 PM UTC 24 24537880 ps
T1834 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.617358592 Oct 15 12:27:48 PM UTC 24 Oct 15 12:27:50 PM UTC 24 46996441 ps
T1835 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.737365296 Oct 15 12:27:48 PM UTC 24 Oct 15 12:27:50 PM UTC 24 51326422 ps
T1836 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.3490186442 Oct 15 12:27:48 PM UTC 24 Oct 15 12:27:50 PM UTC 24 16766370 ps
T1837 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.98761957 Oct 15 12:27:48 PM UTC 24 Oct 15 12:27:50 PM UTC 24 45905194 ps
T1838 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.3793779966 Oct 15 12:27:48 PM UTC 24 Oct 15 12:27:50 PM UTC 24 20757812 ps
T1839 /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.302318401 Oct 15 12:27:49 PM UTC 24 Oct 15 12:27:52 PM UTC 24 14788934 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_perf_precise.2025503354
Short name T3
Test name
Test status
Simulation time 138497740 ps
CPU time 1.51 seconds
Started Oct 15 11:40:48 AM UTC 24
Finished Oct 15 11:40:54 AM UTC 24
Peak memory 215656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025503354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.2025503354
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_glitch.1506404869
Short name T53
Test name
Test status
Simulation time 4855090551 ps
CPU time 9.33 seconds
Started Oct 15 11:40:49 AM UTC 24
Finished Oct 15 11:41:01 AM UTC 24
Peak memory 226276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506404869 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.1506404869
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_stress_all.12951820
Short name T198
Test name
Test status
Simulation time 2125289040 ps
CPU time 124.72 seconds
Started Oct 15 11:44:24 AM UTC 24
Finished Oct 15 11:46:31 AM UTC 24
Peak memory 644036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12951820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.12951820
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_error_intr.4092283209
Short name T4
Test name
Test status
Simulation time 595527287 ps
CPU time 3.74 seconds
Started Oct 15 11:40:48 AM UTC 24
Finished Oct 15 11:40:56 AM UTC 24
Peak memory 228216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092283209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.4092283209
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_timeout.1723546635
Short name T46
Test name
Test status
Simulation time 4481483444 ps
CPU time 7.1 seconds
Started Oct 15 11:40:53 AM UTC 24
Finished Oct 15 11:41:03 AM UTC 24
Peak memory 232444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723546
635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_timeout.1723546635
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.2569427187
Short name T106
Test name
Test status
Simulation time 149057877 ps
CPU time 3.01 seconds
Started Oct 15 12:26:46 PM UTC 24
Finished Oct 15 12:26:50 PM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569427187 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2569427187
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_may_nack.3441460406
Short name T12
Test name
Test status
Simulation time 633819155 ps
CPU time 22.51 seconds
Started Oct 15 11:40:55 AM UTC 24
Finished Oct 15 11:41:19 AM UTC 24
Peak memory 215460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441460406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.3441460406
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_rx.2186082410
Short name T44
Test name
Test status
Simulation time 570355347 ps
CPU time 10.02 seconds
Started Oct 15 11:41:18 AM UTC 24
Finished Oct 15 11:41:29 AM UTC 24
Peak memory 236436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186082410 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.2186082410
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_nack_txstretch.2316046476
Short name T61
Test name
Test status
Simulation time 302247504 ps
CPU time 2.43 seconds
Started Oct 15 11:41:37 AM UTC 24
Finished Oct 15 11:41:40 AM UTC 24
Peak memory 232712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316046
476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_txstretch.2316046476
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_override.1810254942
Short name T141
Test name
Test status
Simulation time 157476104 ps
CPU time 0.99 seconds
Started Oct 15 11:42:12 AM UTC 24
Finished Oct 15 11:42:14 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810254942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.1810254942
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_watermark.2255401379
Short name T84
Test name
Test status
Simulation time 3161734599 ps
CPU time 59.34 seconds
Started Oct 15 11:40:48 AM UTC 24
Finished Oct 15 11:41:52 AM UTC 24
Peak memory 1022924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255401379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.2255401379
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull_addr.3567119003
Short name T50
Test name
Test status
Simulation time 1177141172 ps
CPU time 4.97 seconds
Started Oct 15 11:44:13 AM UTC 24
Finished Oct 15 11:44:19 AM UTC 24
Peak memory 215408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567119
003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.3567119003
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.955186105
Short name T170
Test name
Test status
Simulation time 33657516 ps
CPU time 1.26 seconds
Started Oct 15 11:40:59 AM UTC 24
Finished Oct 15 11:41:03 AM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955186105 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.955186105
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_host_stress_all.601186429
Short name T131
Test name
Test status
Simulation time 61845962090 ps
CPU time 712.45 seconds
Started Oct 15 12:03:40 PM UTC 24
Finished Oct 15 12:15:41 PM UTC 24
Peak memory 4007320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601186429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.601186429
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.1977106373
Short name T208
Test name
Test status
Simulation time 125052279 ps
CPU time 4.38 seconds
Started Oct 15 12:27:00 PM UTC 24
Finished Oct 15 12:27:06 PM UTC 24
Peak memory 225284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977106373 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.1977106373
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.17389158
Short name T228
Test name
Test status
Simulation time 52459281 ps
CPU time 1.17 seconds
Started Oct 15 12:26:48 PM UTC 24
Finished Oct 15 12:26:50 PM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17389158 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.17389158
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_stress_all.3100461525
Short name T59
Test name
Test status
Simulation time 19940897262 ps
CPU time 128.23 seconds
Started Oct 15 11:41:06 AM UTC 24
Finished Oct 15 11:43:16 AM UTC 24
Peak memory 1432588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310046
1525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_all.3100461525
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_stress_all.997631814
Short name T20
Test name
Test status
Simulation time 8942416407 ps
CPU time 259.33 seconds
Started Oct 15 11:47:14 AM UTC 24
Finished Oct 15 11:51:37 AM UTC 24
Peak memory 1596628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997631814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.997631814
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_bad_addr.405845637
Short name T67
Test name
Test status
Simulation time 4149802163 ps
CPU time 7.56 seconds
Started Oct 15 11:40:55 AM UTC 24
Finished Oct 15 11:41:04 AM UTC 24
Peak memory 229920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=405845637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.405845637
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull.3894521439
Short name T64
Test name
Test status
Simulation time 1783848063 ps
CPU time 2.76 seconds
Started Oct 15 11:40:57 AM UTC 24
Finished Oct 15 11:41:04 AM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894521
439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_acqfull.3894521439
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_perf_precise.4242820959
Short name T163
Test name
Test status
Simulation time 24404564455 ps
CPU time 100.15 seconds
Started Oct 15 11:41:02 AM UTC 24
Finished Oct 15 11:42:44 AM UTC 24
Peak memory 773060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242820959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.4242820959
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull.3498397955
Short name T57
Test name
Test status
Simulation time 842314999 ps
CPU time 5.81 seconds
Started Oct 15 11:58:46 AM UTC 24
Finished Oct 15 11:58:53 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498397
955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_acqfull.3498397955
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_stress_all.859645720
Short name T199
Test name
Test status
Simulation time 15195214756 ps
CPU time 432.91 seconds
Started Oct 15 11:42:16 AM UTC 24
Finished Oct 15 11:49:35 AM UTC 24
Peak memory 1149672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859645720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.859645720
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_fmt.3952303915
Short name T2
Test name
Test status
Simulation time 93003612 ps
CPU time 1.05 seconds
Started Oct 15 11:40:48 AM UTC 24
Finished Oct 15 11:40:53 AM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952303915 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt.3952303915
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_perf_precise.512881533
Short name T16
Test name
Test status
Simulation time 23393205034 ps
CPU time 149.87 seconds
Started Oct 15 11:45:52 AM UTC 24
Finished Oct 15 11:48:24 AM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512881533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.512881533
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_alert_test.3366734943
Short name T96
Test name
Test status
Simulation time 16046446 ps
CPU time 0.93 seconds
Started Oct 15 11:40:59 AM UTC 24
Finished Oct 15 11:41:02 AM UTC 24
Peak memory 213392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366734943 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.3366734943
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_host_may_nack.4126852497
Short name T263
Test name
Test status
Simulation time 1051196641 ps
CPU time 8.1 seconds
Started Oct 15 11:57:29 AM UTC 24
Finished Oct 15 11:57:39 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126852497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.4126852497
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_smoke.1547955173
Short name T89
Test name
Test status
Simulation time 2789620880 ps
CPU time 13.35 seconds
Started Oct 15 12:14:59 PM UTC 24
Finished Oct 15 12:15:13 PM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547955173 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smoke.1547955173
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.3728199232
Short name T1783
Test name
Test status
Simulation time 17038129 ps
CPU time 0.94 seconds
Started Oct 15 12:27:33 PM UTC 24
Finished Oct 15 12:27:35 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728199232 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3728199232
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_stress_rd.2790303216
Short name T225
Test name
Test status
Simulation time 3923535926 ps
CPU time 18.99 seconds
Started Oct 15 11:41:22 AM UTC 24
Finished Oct 15 11:41:42 AM UTC 24
Peak memory 232508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790303216 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_rd.2790303216
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_may_nack.4088094416
Short name T255
Test name
Test status
Simulation time 371015098 ps
CPU time 7.61 seconds
Started Oct 15 11:44:06 AM UTC 24
Finished Oct 15 11:44:15 AM UTC 24
Peak memory 215780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088094416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.4088094416
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_mode_toggle.3891086339
Short name T18
Test name
Test status
Simulation time 74858331 ps
CPU time 2.91 seconds
Started Oct 15 11:41:08 AM UTC 24
Finished Oct 15 11:41:12 AM UTC 24
Peak memory 232240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891086339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.3891086339
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_fmt.1204622509
Short name T251
Test name
Test status
Simulation time 301798793 ps
CPU time 1.95 seconds
Started Oct 15 11:46:54 AM UTC 24
Finished Oct 15 11:46:58 AM UTC 24
Peak memory 215712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204622509 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fmt.1204622509
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_fmt.875602097
Short name T252
Test name
Test status
Simulation time 262757273 ps
CPU time 1.6 seconds
Started Oct 15 11:53:36 AM UTC 24
Finished Oct 15 11:53:39 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875602097 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fmt.875602097
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_stress_all.4220698319
Short name T223
Test name
Test status
Simulation time 33719955360 ps
CPU time 69.73 seconds
Started Oct 15 11:54:09 AM UTC 24
Finished Oct 15 11:55:21 AM UTC 24
Peak memory 248772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422069
8319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_all.4220698319
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_stress_all.780374899
Short name T596
Test name
Test status
Simulation time 17089088998 ps
CPU time 603.09 seconds
Started Oct 15 11:41:20 AM UTC 24
Finished Oct 15 11:51:30 AM UTC 24
Peak memory 1445120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780374899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.780374899
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_acq.3413998136
Short name T248
Test name
Test status
Simulation time 209700140 ps
CPU time 2.58 seconds
Started Oct 15 12:08:03 PM UTC 24
Finished Oct 15 12:08:07 PM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413998
136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_acq.3413998136
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.3787858964
Short name T210
Test name
Test status
Simulation time 106748713 ps
CPU time 1.95 seconds
Started Oct 15 12:27:25 PM UTC 24
Finished Oct 15 12:27:28 PM UTC 24
Peak memory 213592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787858964 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.3787858964
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_perf.2788030808
Short name T8
Test name
Test status
Simulation time 6038888446 ps
CPU time 10.54 seconds
Started Oct 15 11:41:19 AM UTC 24
Finished Oct 15 11:41:30 AM UTC 24
Peak memory 245004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788030808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.2788030808
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.2482855579
Short name T212
Test name
Test status
Simulation time 273230588 ps
CPU time 3.42 seconds
Started Oct 15 12:27:18 PM UTC 24
Finished Oct 15 12:27:23 PM UTC 24
Peak memory 214984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482855579 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2482855579
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_tx.422928824
Short name T158
Test name
Test status
Simulation time 244479758 ps
CPU time 1.29 seconds
Started Oct 15 12:20:09 PM UTC 24
Finished Oct 15 12:20:11 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229288
24 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_tx.422928824
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.1199093601
Short name T287
Test name
Test status
Simulation time 19764454 ps
CPU time 1.2 seconds
Started Oct 15 12:27:34 PM UTC 24
Finished Oct 15 12:27:37 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199093601 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1199093601
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_acq.1934524997
Short name T49
Test name
Test status
Simulation time 993030284 ps
CPU time 4.32 seconds
Started Oct 15 11:40:55 AM UTC 24
Finished Oct 15 11:41:01 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934524
997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_watermark
s_acq.1934524997
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_tx_stretch_ctrl.38226376
Short name T73
Test name
Test status
Simulation time 236024410 ps
CPU time 4.13 seconds
Started Oct 15 11:40:56 AM UTC 24
Finished Oct 15 11:41:01 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822637
6 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.38226376
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_may_nack.715546791
Short name T11
Test name
Test status
Simulation time 400874392 ps
CPU time 6.87 seconds
Started Oct 15 11:41:09 AM UTC 24
Finished Oct 15 11:41:17 AM UTC 24
Peak memory 215520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715546791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.715546791
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_may_nack.3071687208
Short name T270
Test name
Test status
Simulation time 1282905506 ps
CPU time 8.05 seconds
Started Oct 15 11:47:48 AM UTC 24
Finished Oct 15 11:47:57 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071687208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.3071687208
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_tx.1733551462
Short name T463
Test name
Test status
Simulation time 210706919 ps
CPU time 2.73 seconds
Started Oct 15 11:47:38 AM UTC 24
Finished Oct 15 11:47:41 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733551
462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_tx.1733551462
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_acq.988095955
Short name T296
Test name
Test status
Simulation time 313913886 ps
CPU time 3.62 seconds
Started Oct 15 11:51:18 AM UTC 24
Finished Oct 15 11:51:22 AM UTC 24
Peak memory 217520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9880959
55 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_acq.988095955
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_host_may_nack.3730575023
Short name T264
Test name
Test status
Simulation time 450981074 ps
CPU time 8.02 seconds
Started Oct 15 11:55:23 AM UTC 24
Finished Oct 15 11:55:32 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730575023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.3730575023
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.3175916859
Short name T205
Test name
Test status
Simulation time 87115026 ps
CPU time 3.14 seconds
Started Oct 15 12:26:50 PM UTC 24
Finished Oct 15 12:26:55 PM UTC 24
Peak memory 214984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175916859 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3175916859
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_error_intr.1546875551
Short name T21
Test name
Test status
Simulation time 402007520 ps
CPU time 4.56 seconds
Started Oct 15 11:48:51 AM UTC 24
Finished Oct 15 11:48:57 AM UTC 24
Peak memory 225920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546875551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.1546875551
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.2945791539
Short name T213
Test name
Test status
Simulation time 173319148 ps
CPU time 2.36 seconds
Started Oct 15 12:27:21 PM UTC 24
Finished Oct 15 12:27:24 PM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945791539 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.2945791539
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.1344304595
Short name T211
Test name
Test status
Simulation time 175464950 ps
CPU time 1.74 seconds
Started Oct 15 12:27:28 PM UTC 24
Finished Oct 15 12:27:30 PM UTC 24
Peak memory 214212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344304595 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.1344304595
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_hrst.2001325135
Short name T195
Test name
Test status
Simulation time 1043772516 ps
CPU time 3.46 seconds
Started Oct 15 11:41:08 AM UTC 24
Finished Oct 15 11:41:12 AM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001325
135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_hrst.2001325135
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_mode_toggle.2994868001
Short name T81
Test name
Test status
Simulation time 74750607 ps
CPU time 1.81 seconds
Started Oct 15 11:48:32 AM UTC 24
Finished Oct 15 11:48:35 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994868001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.2994868001
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.2413817456
Short name T104
Test name
Test status
Simulation time 113710454 ps
CPU time 2.55 seconds
Started Oct 15 12:26:45 PM UTC 24
Finished Oct 15 12:26:48 PM UTC 24
Peak memory 214916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413817456 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2413817456
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.2060155456
Short name T1734
Test name
Test status
Simulation time 65323019 ps
CPU time 3.71 seconds
Started Oct 15 12:26:43 PM UTC 24
Finished Oct 15 12:26:48 PM UTC 24
Peak memory 214924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060155456 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.2060155456
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.2971716994
Short name T217
Test name
Test status
Simulation time 28518300 ps
CPU time 1.25 seconds
Started Oct 15 12:26:42 PM UTC 24
Finished Oct 15 12:26:45 PM UTC 24
Peak memory 214196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971716994 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2971716994
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1965741192
Short name T103
Test name
Test status
Simulation time 110553790 ps
CPU time 1.48 seconds
Started Oct 15 12:26:45 PM UTC 24
Finished Oct 15 12:26:47 PM UTC 24
Peak memory 214200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1965741192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1965741192
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.3414218122
Short name T218
Test name
Test status
Simulation time 18711263 ps
CPU time 1.21 seconds
Started Oct 15 12:26:43 PM UTC 24
Finished Oct 15 12:26:46 PM UTC 24
Peak memory 214256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414218122 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.3414218122
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.2422481220
Short name T279
Test name
Test status
Simulation time 37615920 ps
CPU time 1.06 seconds
Started Oct 15 12:26:42 PM UTC 24
Finished Oct 15 12:26:44 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422481220 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.2422481220
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1735528927
Short name T102
Test name
Test status
Simulation time 74682713 ps
CPU time 1.12 seconds
Started Oct 15 12:26:45 PM UTC 24
Finished Oct 15 12:26:47 PM UTC 24
Peak memory 214328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735528927 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_outstanding.1735528927
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.256885338
Short name T200
Test name
Test status
Simulation time 153484745 ps
CPU time 3.06 seconds
Started Oct 15 12:26:40 PM UTC 24
Finished Oct 15 12:26:44 PM UTC 24
Peak memory 215176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256885338 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.256885338
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.573700737
Short name T201
Test name
Test status
Simulation time 69259625 ps
CPU time 1.9 seconds
Started Oct 15 12:26:41 PM UTC 24
Finished Oct 15 12:26:44 PM UTC 24
Peak memory 214448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573700737 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.573700737
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.882843018
Short name T229
Test name
Test status
Simulation time 48757230 ps
CPU time 1.86 seconds
Started Oct 15 12:26:49 PM UTC 24
Finished Oct 15 12:26:52 PM UTC 24
Peak memory 214276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882843018 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i
2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.882843018
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.519266616
Short name T108
Test name
Test status
Simulation time 535092674 ps
CPU time 4.45 seconds
Started Oct 15 12:26:49 PM UTC 24
Finished Oct 15 12:26:55 PM UTC 24
Peak memory 215176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519266616 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i
2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.519266616
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.1969155057
Short name T227
Test name
Test status
Simulation time 184389212 ps
CPU time 1.01 seconds
Started Oct 15 12:26:48 PM UTC 24
Finished Oct 15 12:26:50 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969155057 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1969155057
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.730271134
Short name T224
Test name
Test status
Simulation time 88449173 ps
CPU time 1.18 seconds
Started Oct 15 12:26:50 PM UTC 24
Finished Oct 15 12:26:53 PM UTC 24
Peak memory 214296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=730271134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.730271134
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.1544717526
Short name T277
Test name
Test status
Simulation time 99643863 ps
CPU time 1.11 seconds
Started Oct 15 12:26:47 PM UTC 24
Finished Oct 15 12:26:49 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544717526 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1544717526
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1456074352
Short name T237
Test name
Test status
Simulation time 90762012 ps
CPU time 1.53 seconds
Started Oct 15 12:26:49 PM UTC 24
Finished Oct 15 12:26:52 PM UTC 24
Peak memory 214340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456074352 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_outstanding.1456074352
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.1541535698
Short name T105
Test name
Test status
Simulation time 563911712 ps
CPU time 1.92 seconds
Started Oct 15 12:26:46 PM UTC 24
Finished Oct 15 12:26:49 PM UTC 24
Peak memory 214144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541535698 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.1541535698
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2123606281
Short name T1766
Test name
Test status
Simulation time 23457722 ps
CPU time 1.25 seconds
Started Oct 15 12:27:23 PM UTC 24
Finished Oct 15 12:27:26 PM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2123606281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.2123606281
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.856824254
Short name T235
Test name
Test status
Simulation time 81072476 ps
CPU time 1.04 seconds
Started Oct 15 12:27:22 PM UTC 24
Finished Oct 15 12:27:24 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856824254 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.856824254
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.115308513
Short name T286
Test name
Test status
Simulation time 58814739 ps
CPU time 1.1 seconds
Started Oct 15 12:27:22 PM UTC 24
Finished Oct 15 12:27:24 PM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115308513 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.115308513
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2683385234
Short name T1763
Test name
Test status
Simulation time 165888686 ps
CPU time 1.52 seconds
Started Oct 15 12:27:22 PM UTC 24
Finished Oct 15 12:27:25 PM UTC 24
Peak memory 214212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683385234 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_outstanding.2683385234
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.3917805423
Short name T1762
Test name
Test status
Simulation time 41461351 ps
CPU time 1.68 seconds
Started Oct 15 12:27:21 PM UTC 24
Finished Oct 15 12:27:23 PM UTC 24
Peak memory 214144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917805423 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.3917805423
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1280427143
Short name T1768
Test name
Test status
Simulation time 70701120 ps
CPU time 1.25 seconds
Started Oct 15 12:27:25 PM UTC 24
Finished Oct 15 12:27:28 PM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1280427143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.1280427143
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.2620260146
Short name T1764
Test name
Test status
Simulation time 33855152 ps
CPU time 0.95 seconds
Started Oct 15 12:27:24 PM UTC 24
Finished Oct 15 12:27:26 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620260146 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2620260146
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.4107321013
Short name T1765
Test name
Test status
Simulation time 25152264 ps
CPU time 1.02 seconds
Started Oct 15 12:27:24 PM UTC 24
Finished Oct 15 12:27:26 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107321013 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.4107321013
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1413435043
Short name T1767
Test name
Test status
Simulation time 55648116 ps
CPU time 1.22 seconds
Started Oct 15 12:27:24 PM UTC 24
Finished Oct 15 12:27:26 PM UTC 24
Peak memory 214268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413435043 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_outstanding.1413435043
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.1971593037
Short name T1769
Test name
Test status
Simulation time 48597993 ps
CPU time 3.7 seconds
Started Oct 15 12:27:23 PM UTC 24
Finished Oct 15 12:27:28 PM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971593037 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1971593037
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.3707474795
Short name T209
Test name
Test status
Simulation time 90720428 ps
CPU time 1.94 seconds
Started Oct 15 12:27:23 PM UTC 24
Finished Oct 15 12:27:26 PM UTC 24
Peak memory 214144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707474795 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.3707474795
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3443674873
Short name T1772
Test name
Test status
Simulation time 24357897 ps
CPU time 1.26 seconds
Started Oct 15 12:27:27 PM UTC 24
Finished Oct 15 12:27:30 PM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3443674873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3443674873
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.1121249417
Short name T236
Test name
Test status
Simulation time 28674950 ps
CPU time 1.23 seconds
Started Oct 15 12:27:26 PM UTC 24
Finished Oct 15 12:27:29 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121249417 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1121249417
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.2034531862
Short name T280
Test name
Test status
Simulation time 18142243 ps
CPU time 1.04 seconds
Started Oct 15 12:27:25 PM UTC 24
Finished Oct 15 12:27:28 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034531862 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2034531862
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3131709954
Short name T1770
Test name
Test status
Simulation time 25870470 ps
CPU time 1.24 seconds
Started Oct 15 12:27:26 PM UTC 24
Finished Oct 15 12:27:29 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131709954 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_outstanding.3131709954
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.2898308951
Short name T1771
Test name
Test status
Simulation time 34028397 ps
CPU time 2.35 seconds
Started Oct 15 12:27:25 PM UTC 24
Finished Oct 15 12:27:29 PM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898308951 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2898308951
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.128851297
Short name T1776
Test name
Test status
Simulation time 133705923 ps
CPU time 1.24 seconds
Started Oct 15 12:27:29 PM UTC 24
Finished Oct 15 12:27:32 PM UTC 24
Peak memory 214204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=128851297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.128851297
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.1342506853
Short name T1774
Test name
Test status
Simulation time 42815799 ps
CPU time 1.01 seconds
Started Oct 15 12:27:29 PM UTC 24
Finished Oct 15 12:27:31 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342506853 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1342506853
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.1167795797
Short name T1773
Test name
Test status
Simulation time 55088272 ps
CPU time 0.98 seconds
Started Oct 15 12:27:28 PM UTC 24
Finished Oct 15 12:27:30 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167795797 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1167795797
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.595802610
Short name T1777
Test name
Test status
Simulation time 26567293 ps
CPU time 1.35 seconds
Started Oct 15 12:27:29 PM UTC 24
Finished Oct 15 12:27:32 PM UTC 24
Peak memory 214276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595802610 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_outstanding.595802610
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.2619893260
Short name T1775
Test name
Test status
Simulation time 169335878 ps
CPU time 3.45 seconds
Started Oct 15 12:27:27 PM UTC 24
Finished Oct 15 12:27:32 PM UTC 24
Peak memory 225352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619893260 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2619893260
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1555052629
Short name T1782
Test name
Test status
Simulation time 51725799 ps
CPU time 1.42 seconds
Started Oct 15 12:27:31 PM UTC 24
Finished Oct 15 12:27:35 PM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1555052629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1555052629
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.3746460733
Short name T1780
Test name
Test status
Simulation time 17814703 ps
CPU time 1.22 seconds
Started Oct 15 12:27:30 PM UTC 24
Finished Oct 15 12:27:34 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746460733 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.3746460733
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.2715007410
Short name T1779
Test name
Test status
Simulation time 103437270 ps
CPU time 1.06 seconds
Started Oct 15 12:27:30 PM UTC 24
Finished Oct 15 12:27:33 PM UTC 24
Peak memory 213988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715007410 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.2715007410
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.760783151
Short name T1781
Test name
Test status
Simulation time 47167620 ps
CPU time 1.59 seconds
Started Oct 15 12:27:30 PM UTC 24
Finished Oct 15 12:27:34 PM UTC 24
Peak memory 214276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760783151 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_outstanding.760783151
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.1340723069
Short name T1778
Test name
Test status
Simulation time 216096614 ps
CPU time 1.61 seconds
Started Oct 15 12:27:29 PM UTC 24
Finished Oct 15 12:27:32 PM UTC 24
Peak memory 214204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340723069 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1340723069
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.1220788982
Short name T1784
Test name
Test status
Simulation time 486894499 ps
CPU time 3.44 seconds
Started Oct 15 12:27:30 PM UTC 24
Finished Oct 15 12:27:35 PM UTC 24
Peak memory 215048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220788982 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1220788982
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3673346975
Short name T1787
Test name
Test status
Simulation time 37779511 ps
CPU time 1.65 seconds
Started Oct 15 12:27:33 PM UTC 24
Finished Oct 15 12:27:36 PM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3673346975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3673346975
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.4268516931
Short name T1785
Test name
Test status
Simulation time 47652220 ps
CPU time 1.08 seconds
Started Oct 15 12:27:33 PM UTC 24
Finished Oct 15 12:27:35 PM UTC 24
Peak memory 213584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268516931 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.4268516931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.1358398128
Short name T1786
Test name
Test status
Simulation time 55086532 ps
CPU time 2.5 seconds
Started Oct 15 12:27:32 PM UTC 24
Finished Oct 15 12:27:36 PM UTC 24
Peak memory 215368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358398128 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.1358398128
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.3667592358
Short name T215
Test name
Test status
Simulation time 140039719 ps
CPU time 1.88 seconds
Started Oct 15 12:27:32 PM UTC 24
Finished Oct 15 12:27:35 PM UTC 24
Peak memory 214212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667592358 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3667592358
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1396046451
Short name T1792
Test name
Test status
Simulation time 28127461 ps
CPU time 1.36 seconds
Started Oct 15 12:27:36 PM UTC 24
Finished Oct 15 12:27:38 PM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1396046451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1396046451
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.4016078877
Short name T1789
Test name
Test status
Simulation time 42845141 ps
CPU time 1.03 seconds
Started Oct 15 12:27:34 PM UTC 24
Finished Oct 15 12:27:37 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016078877 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.4016078877
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1694409552
Short name T1791
Test name
Test status
Simulation time 127459398 ps
CPU time 1.29 seconds
Started Oct 15 12:27:35 PM UTC 24
Finished Oct 15 12:27:38 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694409552 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_outstanding.1694409552
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.3478155452
Short name T1790
Test name
Test status
Simulation time 677129984 ps
CPU time 3.4 seconds
Started Oct 15 12:27:33 PM UTC 24
Finished Oct 15 12:27:38 PM UTC 24
Peak memory 215304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478155452 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.3478155452
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.3776677438
Short name T1788
Test name
Test status
Simulation time 257060861 ps
CPU time 2.05 seconds
Started Oct 15 12:27:33 PM UTC 24
Finished Oct 15 12:27:37 PM UTC 24
Peak memory 215048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776677438 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.3776677438
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2520158157
Short name T1796
Test name
Test status
Simulation time 40682344 ps
CPU time 1.62 seconds
Started Oct 15 12:27:37 PM UTC 24
Finished Oct 15 12:27:40 PM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2520158157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.2520158157
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.1799321075
Short name T1793
Test name
Test status
Simulation time 23828022 ps
CPU time 1.01 seconds
Started Oct 15 12:27:37 PM UTC 24
Finished Oct 15 12:27:39 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799321075 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1799321075
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.248901487
Short name T1794
Test name
Test status
Simulation time 18767770 ps
CPU time 1.07 seconds
Started Oct 15 12:27:37 PM UTC 24
Finished Oct 15 12:27:39 PM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248901487 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.248901487
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1982189679
Short name T1795
Test name
Test status
Simulation time 39340539 ps
CPU time 1.25 seconds
Started Oct 15 12:27:37 PM UTC 24
Finished Oct 15 12:27:39 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982189679 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_outstanding.1982189679
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.1908444060
Short name T1797
Test name
Test status
Simulation time 57735098 ps
CPU time 2.23 seconds
Started Oct 15 12:27:37 PM UTC 24
Finished Oct 15 12:27:40 PM UTC 24
Peak memory 215112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908444060 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1908444060
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.1314649937
Short name T1800
Test name
Test status
Simulation time 316239134 ps
CPU time 2.88 seconds
Started Oct 15 12:27:37 PM UTC 24
Finished Oct 15 12:27:41 PM UTC 24
Peak memory 214984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314649937 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1314649937
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.892879648
Short name T1802
Test name
Test status
Simulation time 140929520 ps
CPU time 1.32 seconds
Started Oct 15 12:27:39 PM UTC 24
Finished Oct 15 12:27:41 PM UTC 24
Peak memory 214204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=892879648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.892879648
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.2385972135
Short name T1799
Test name
Test status
Simulation time 20232082 ps
CPU time 1.25 seconds
Started Oct 15 12:27:38 PM UTC 24
Finished Oct 15 12:27:41 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385972135 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2385972135
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.3364714953
Short name T1798
Test name
Test status
Simulation time 121112970 ps
CPU time 1.08 seconds
Started Oct 15 12:27:38 PM UTC 24
Finished Oct 15 12:27:40 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364714953 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3364714953
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1622984702
Short name T1801
Test name
Test status
Simulation time 21859255 ps
CPU time 1.29 seconds
Started Oct 15 12:27:39 PM UTC 24
Finished Oct 15 12:27:41 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622984702 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_outstanding.1622984702
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.296094437
Short name T1803
Test name
Test status
Simulation time 73890249 ps
CPU time 2.8 seconds
Started Oct 15 12:27:37 PM UTC 24
Finished Oct 15 12:27:41 PM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296094437 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.296094437
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.2146332044
Short name T1804
Test name
Test status
Simulation time 78418202 ps
CPU time 2.05 seconds
Started Oct 15 12:27:38 PM UTC 24
Finished Oct 15 12:27:41 PM UTC 24
Peak memory 215048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146332044 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2146332044
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3121838201
Short name T1812
Test name
Test status
Simulation time 50322124 ps
CPU time 1.35 seconds
Started Oct 15 12:27:41 PM UTC 24
Finished Oct 15 12:27:44 PM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3121838201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3121838201
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.1589851794
Short name T1806
Test name
Test status
Simulation time 21575457 ps
CPU time 1.19 seconds
Started Oct 15 12:27:40 PM UTC 24
Finished Oct 15 12:27:42 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589851794 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.1589851794
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.2985362266
Short name T1805
Test name
Test status
Simulation time 49282319 ps
CPU time 1.1 seconds
Started Oct 15 12:27:40 PM UTC 24
Finished Oct 15 12:27:42 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985362266 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2985362266
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.117197697
Short name T1809
Test name
Test status
Simulation time 21261216 ps
CPU time 1.34 seconds
Started Oct 15 12:27:41 PM UTC 24
Finished Oct 15 12:27:44 PM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117197697 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_outstanding.117197697
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.1779498661
Short name T1810
Test name
Test status
Simulation time 144146264 ps
CPU time 2.79 seconds
Started Oct 15 12:27:40 PM UTC 24
Finished Oct 15 12:27:44 PM UTC 24
Peak memory 215304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779498661 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.1779498661
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.2539026915
Short name T1807
Test name
Test status
Simulation time 46073220 ps
CPU time 2.1 seconds
Started Oct 15 12:27:40 PM UTC 24
Finished Oct 15 12:27:43 PM UTC 24
Peak memory 215236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539026915 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2539026915
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.1350665714
Short name T230
Test name
Test status
Simulation time 96781312 ps
CPU time 2.65 seconds
Started Oct 15 12:26:55 PM UTC 24
Finished Oct 15 12:26:59 PM UTC 24
Peak memory 214712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350665714 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.1350665714
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.2829160293
Short name T111
Test name
Test status
Simulation time 525598664 ps
CPU time 6.67 seconds
Started Oct 15 12:26:54 PM UTC 24
Finished Oct 15 12:27:02 PM UTC 24
Peak memory 214980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829160293 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2829160293
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.1532885307
Short name T1736
Test name
Test status
Simulation time 54888341 ps
CPU time 1.19 seconds
Started Oct 15 12:26:53 PM UTC 24
Finished Oct 15 12:26:55 PM UTC 24
Peak memory 214196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532885307 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1532885307
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3512756145
Short name T109
Test name
Test status
Simulation time 276594499 ps
CPU time 1.48 seconds
Started Oct 15 12:26:56 PM UTC 24
Finished Oct 15 12:26:59 PM UTC 24
Peak memory 214200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3512756145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3512756145
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.2493199998
Short name T1735
Test name
Test status
Simulation time 82450164 ps
CPU time 1.07 seconds
Started Oct 15 12:26:53 PM UTC 24
Finished Oct 15 12:26:55 PM UTC 24
Peak memory 214256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493199998 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2493199998
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.1350176153
Short name T281
Test name
Test status
Simulation time 17938054 ps
CPU time 1.08 seconds
Started Oct 15 12:26:52 PM UTC 24
Finished Oct 15 12:26:54 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350176153 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1350176153
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2299358982
Short name T238
Test name
Test status
Simulation time 53007986 ps
CPU time 1.87 seconds
Started Oct 15 12:26:55 PM UTC 24
Finished Oct 15 12:26:58 PM UTC 24
Peak memory 214348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299358982 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_outstanding.2299358982
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.1999352304
Short name T107
Test name
Test status
Simulation time 332661022 ps
CPU time 2.94 seconds
Started Oct 15 12:26:50 PM UTC 24
Finished Oct 15 12:26:54 PM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999352304 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1999352304
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.463167733
Short name T1808
Test name
Test status
Simulation time 47349143 ps
CPU time 0.96 seconds
Started Oct 15 12:27:41 PM UTC 24
Finished Oct 15 12:27:43 PM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463167733 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.463167733
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.1173068069
Short name T1811
Test name
Test status
Simulation time 39053965 ps
CPU time 1.16 seconds
Started Oct 15 12:27:41 PM UTC 24
Finished Oct 15 12:27:44 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173068069 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1173068069
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.3451354387
Short name T1813
Test name
Test status
Simulation time 33713172 ps
CPU time 1.07 seconds
Started Oct 15 12:27:43 PM UTC 24
Finished Oct 15 12:27:45 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451354387 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3451354387
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.3980893938
Short name T1814
Test name
Test status
Simulation time 60656150 ps
CPU time 1.1 seconds
Started Oct 15 12:27:43 PM UTC 24
Finished Oct 15 12:27:45 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980893938 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3980893938
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.4269472271
Short name T1815
Test name
Test status
Simulation time 18358123 ps
CPU time 1.11 seconds
Started Oct 15 12:27:43 PM UTC 24
Finished Oct 15 12:27:45 PM UTC 24
Peak memory 214132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269472271 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.4269472271
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.3404542529
Short name T288
Test name
Test status
Simulation time 28442421 ps
CPU time 1.01 seconds
Started Oct 15 12:27:43 PM UTC 24
Finished Oct 15 12:27:45 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404542529 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3404542529
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.1442417904
Short name T1817
Test name
Test status
Simulation time 15568758 ps
CPU time 1.09 seconds
Started Oct 15 12:27:43 PM UTC 24
Finished Oct 15 12:27:45 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442417904 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1442417904
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.3105957115
Short name T1816
Test name
Test status
Simulation time 52239407 ps
CPU time 1.11 seconds
Started Oct 15 12:27:43 PM UTC 24
Finished Oct 15 12:27:45 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105957115 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.3105957115
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.4223406118
Short name T1818
Test name
Test status
Simulation time 28588693 ps
CPU time 1.1 seconds
Started Oct 15 12:27:43 PM UTC 24
Finished Oct 15 12:27:45 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223406118 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.4223406118
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.2806235194
Short name T1821
Test name
Test status
Simulation time 18262447 ps
CPU time 1.13 seconds
Started Oct 15 12:27:44 PM UTC 24
Finished Oct 15 12:27:47 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806235194 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2806235194
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.3895671526
Short name T231
Test name
Test status
Simulation time 85186894 ps
CPU time 1.78 seconds
Started Oct 15 12:27:00 PM UTC 24
Finished Oct 15 12:27:03 PM UTC 24
Peak memory 214272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895671526 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3895671526
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.2409385049
Short name T233
Test name
Test status
Simulation time 4327213188 ps
CPU time 7.3 seconds
Started Oct 15 12:27:00 PM UTC 24
Finished Oct 15 12:27:08 PM UTC 24
Peak memory 214988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409385049 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.2409385049
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.3845650587
Short name T1737
Test name
Test status
Simulation time 35293433 ps
CPU time 1.26 seconds
Started Oct 15 12:26:57 PM UTC 24
Finished Oct 15 12:27:00 PM UTC 24
Peak memory 214196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845650587 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3845650587
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2245239874
Short name T129
Test name
Test status
Simulation time 88798473 ps
CPU time 1.28 seconds
Started Oct 15 12:27:00 PM UTC 24
Finished Oct 15 12:27:02 PM UTC 24
Peak memory 214200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2245239874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.2245239874
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.395641531
Short name T110
Test name
Test status
Simulation time 96666248 ps
CPU time 1.16 seconds
Started Oct 15 12:26:59 PM UTC 24
Finished Oct 15 12:27:01 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395641531 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.395641531
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.3079838533
Short name T282
Test name
Test status
Simulation time 18479397 ps
CPU time 1.08 seconds
Started Oct 15 12:26:56 PM UTC 24
Finished Oct 15 12:26:58 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079838533 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.3079838533
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.107669172
Short name T239
Test name
Test status
Simulation time 40834975 ps
CPU time 1.47 seconds
Started Oct 15 12:27:00 PM UTC 24
Finished Oct 15 12:27:02 PM UTC 24
Peak memory 214216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107669172 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_outstanding.107669172
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.2743332648
Short name T207
Test name
Test status
Simulation time 47011905 ps
CPU time 1.65 seconds
Started Oct 15 12:26:56 PM UTC 24
Finished Oct 15 12:26:59 PM UTC 24
Peak memory 214144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743332648 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2743332648
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.974798880
Short name T219
Test name
Test status
Simulation time 150297178 ps
CPU time 1.93 seconds
Started Oct 15 12:26:56 PM UTC 24
Finished Oct 15 12:26:59 PM UTC 24
Peak memory 214208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974798880 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.974798880
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.3228625294
Short name T1820
Test name
Test status
Simulation time 31324400 ps
CPU time 1.11 seconds
Started Oct 15 12:27:44 PM UTC 24
Finished Oct 15 12:27:47 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228625294 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3228625294
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.4017792452
Short name T1819
Test name
Test status
Simulation time 18234093 ps
CPU time 1.03 seconds
Started Oct 15 12:27:44 PM UTC 24
Finished Oct 15 12:27:47 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017792452 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.4017792452
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.4175941754
Short name T1822
Test name
Test status
Simulation time 48169513 ps
CPU time 1.1 seconds
Started Oct 15 12:27:44 PM UTC 24
Finished Oct 15 12:27:47 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175941754 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.4175941754
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.783884737
Short name T1824
Test name
Test status
Simulation time 44824362 ps
CPU time 1.14 seconds
Started Oct 15 12:27:45 PM UTC 24
Finished Oct 15 12:27:47 PM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783884737 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.783884737
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.4165733394
Short name T1823
Test name
Test status
Simulation time 27007483 ps
CPU time 1.06 seconds
Started Oct 15 12:27:45 PM UTC 24
Finished Oct 15 12:27:47 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165733394 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.4165733394
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.3208596832
Short name T1826
Test name
Test status
Simulation time 23455193 ps
CPU time 1.17 seconds
Started Oct 15 12:27:46 PM UTC 24
Finished Oct 15 12:27:48 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208596832 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3208596832
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.1155274587
Short name T1825
Test name
Test status
Simulation time 21756590 ps
CPU time 1 seconds
Started Oct 15 12:27:46 PM UTC 24
Finished Oct 15 12:27:48 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155274587 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1155274587
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.1193400467
Short name T1828
Test name
Test status
Simulation time 18255828 ps
CPU time 1.04 seconds
Started Oct 15 12:27:46 PM UTC 24
Finished Oct 15 12:27:48 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193400467 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1193400467
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.990881884
Short name T1829
Test name
Test status
Simulation time 54140623 ps
CPU time 1 seconds
Started Oct 15 12:27:46 PM UTC 24
Finished Oct 15 12:27:48 PM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990881884 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.990881884
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.1406202423
Short name T1832
Test name
Test status
Simulation time 91506055 ps
CPU time 0.98 seconds
Started Oct 15 12:27:46 PM UTC 24
Finished Oct 15 12:27:49 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406202423 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1406202423
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.3791835152
Short name T1739
Test name
Test status
Simulation time 277167897 ps
CPU time 2.13 seconds
Started Oct 15 12:27:04 PM UTC 24
Finished Oct 15 12:27:07 PM UTC 24
Peak memory 214916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791835152 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3791835152
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.51645704
Short name T1746
Test name
Test status
Simulation time 1463602668 ps
CPU time 6.55 seconds
Started Oct 15 12:27:04 PM UTC 24
Finished Oct 15 12:27:11 PM UTC 24
Peak memory 214860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51645704 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.51645704
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.3857432271
Short name T232
Test name
Test status
Simulation time 37082465 ps
CPU time 1.09 seconds
Started Oct 15 12:27:02 PM UTC 24
Finished Oct 15 12:27:04 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857432271 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3857432271
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.996956636
Short name T1740
Test name
Test status
Simulation time 100850686 ps
CPU time 2.16 seconds
Started Oct 15 12:27:05 PM UTC 24
Finished Oct 15 12:27:08 PM UTC 24
Peak memory 225364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=996956636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.996956636
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.2708230125
Short name T240
Test name
Test status
Simulation time 33736979 ps
CPU time 1.03 seconds
Started Oct 15 12:27:03 PM UTC 24
Finished Oct 15 12:27:05 PM UTC 24
Peak memory 214256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708230125 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2708230125
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.2927681486
Short name T1738
Test name
Test status
Simulation time 15255429 ps
CPU time 1.04 seconds
Started Oct 15 12:27:01 PM UTC 24
Finished Oct 15 12:27:03 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927681486 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.2927681486
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.332501070
Short name T241
Test name
Test status
Simulation time 34552670 ps
CPU time 1.27 seconds
Started Oct 15 12:27:04 PM UTC 24
Finished Oct 15 12:27:06 PM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332501070 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_outstanding.332501070
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.3467133483
Short name T206
Test name
Test status
Simulation time 81722224 ps
CPU time 2.05 seconds
Started Oct 15 12:27:01 PM UTC 24
Finished Oct 15 12:27:04 PM UTC 24
Peak memory 215188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467133483 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3467133483
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.526784378
Short name T1827
Test name
Test status
Simulation time 43450860 ps
CPU time 0.92 seconds
Started Oct 15 12:27:46 PM UTC 24
Finished Oct 15 12:27:48 PM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526784378 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.526784378
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.1770086838
Short name T1831
Test name
Test status
Simulation time 51183604 ps
CPU time 1.1 seconds
Started Oct 15 12:27:46 PM UTC 24
Finished Oct 15 12:27:49 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770086838 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1770086838
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.543860017
Short name T1830
Test name
Test status
Simulation time 18199593 ps
CPU time 0.98 seconds
Started Oct 15 12:27:46 PM UTC 24
Finished Oct 15 12:27:49 PM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543860017 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.543860017
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.1614130657
Short name T1833
Test name
Test status
Simulation time 24537880 ps
CPU time 1.03 seconds
Started Oct 15 12:27:48 PM UTC 24
Finished Oct 15 12:27:50 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614130657 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1614130657
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.3490186442
Short name T1836
Test name
Test status
Simulation time 16766370 ps
CPU time 1.02 seconds
Started Oct 15 12:27:48 PM UTC 24
Finished Oct 15 12:27:50 PM UTC 24
Peak memory 214040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490186442 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.3490186442
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.98761957
Short name T1837
Test name
Test status
Simulation time 45905194 ps
CPU time 1.04 seconds
Started Oct 15 12:27:48 PM UTC 24
Finished Oct 15 12:27:50 PM UTC 24
Peak memory 214076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98761957 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.98761957
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.617358592
Short name T1834
Test name
Test status
Simulation time 46996441 ps
CPU time 1.05 seconds
Started Oct 15 12:27:48 PM UTC 24
Finished Oct 15 12:27:50 PM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617358592 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.617358592
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.3793779966
Short name T1838
Test name
Test status
Simulation time 20757812 ps
CPU time 1.05 seconds
Started Oct 15 12:27:48 PM UTC 24
Finished Oct 15 12:27:50 PM UTC 24
Peak memory 214016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793779966 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3793779966
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.737365296
Short name T1835
Test name
Test status
Simulation time 51326422 ps
CPU time 1.04 seconds
Started Oct 15 12:27:48 PM UTC 24
Finished Oct 15 12:27:50 PM UTC 24
Peak memory 214060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737365296 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.737365296
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.302318401
Short name T1839
Test name
Test status
Simulation time 14788934 ps
CPU time 1.04 seconds
Started Oct 15 12:27:49 PM UTC 24
Finished Oct 15 12:27:52 PM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302318401 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.302318401
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2331663188
Short name T1745
Test name
Test status
Simulation time 63657827 ps
CPU time 1.51 seconds
Started Oct 15 12:27:08 PM UTC 24
Finished Oct 15 12:27:11 PM UTC 24
Peak memory 214200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2331663188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2331663188
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.3615019560
Short name T1743
Test name
Test status
Simulation time 18162708 ps
CPU time 1.16 seconds
Started Oct 15 12:27:07 PM UTC 24
Finished Oct 15 12:27:09 PM UTC 24
Peak memory 214256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615019560 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3615019560
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.3813385736
Short name T1741
Test name
Test status
Simulation time 26052802 ps
CPU time 1.05 seconds
Started Oct 15 12:27:06 PM UTC 24
Finished Oct 15 12:27:08 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813385736 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3813385736
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.650464579
Short name T242
Test name
Test status
Simulation time 65955612 ps
CPU time 1.75 seconds
Started Oct 15 12:27:07 PM UTC 24
Finished Oct 15 12:27:10 PM UTC 24
Peak memory 214216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650464579 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_outstanding.650464579
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.4294950014
Short name T214
Test name
Test status
Simulation time 76930211 ps
CPU time 2.31 seconds
Started Oct 15 12:27:05 PM UTC 24
Finished Oct 15 12:27:08 PM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294950014 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.4294950014
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.2595763663
Short name T1742
Test name
Test status
Simulation time 55456866 ps
CPU time 2.07 seconds
Started Oct 15 12:27:06 PM UTC 24
Finished Oct 15 12:27:09 PM UTC 24
Peak memory 215052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595763663 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.2595763663
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2537128605
Short name T1748
Test name
Test status
Simulation time 24407686 ps
CPU time 1.29 seconds
Started Oct 15 12:27:11 PM UTC 24
Finished Oct 15 12:27:13 PM UTC 24
Peak memory 214200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2537128605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.2537128605
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.319710187
Short name T1747
Test name
Test status
Simulation time 63989882 ps
CPU time 0.98 seconds
Started Oct 15 12:27:10 PM UTC 24
Finished Oct 15 12:27:12 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319710187 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.319710187
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.950474885
Short name T284
Test name
Test status
Simulation time 16879230 ps
CPU time 1.07 seconds
Started Oct 15 12:27:10 PM UTC 24
Finished Oct 15 12:27:12 PM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950474885 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.950474885
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3719417216
Short name T1749
Test name
Test status
Simulation time 31928257 ps
CPU time 1.35 seconds
Started Oct 15 12:27:11 PM UTC 24
Finished Oct 15 12:27:13 PM UTC 24
Peak memory 214328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719417216 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_outstanding.3719417216
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.852166784
Short name T1750
Test name
Test status
Simulation time 226231290 ps
CPU time 3.12 seconds
Started Oct 15 12:27:10 PM UTC 24
Finished Oct 15 12:27:14 PM UTC 24
Peak memory 215048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852166784 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.852166784
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.2368357038
Short name T216
Test name
Test status
Simulation time 147973660 ps
CPU time 3.74 seconds
Started Oct 15 12:27:10 PM UTC 24
Finished Oct 15 12:27:14 PM UTC 24
Peak memory 214984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368357038 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2368357038
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1921847824
Short name T1753
Test name
Test status
Simulation time 40105994 ps
CPU time 1.57 seconds
Started Oct 15 12:27:14 PM UTC 24
Finished Oct 15 12:27:17 PM UTC 24
Peak memory 214204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1921847824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1921847824
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.4127278485
Short name T1751
Test name
Test status
Simulation time 19959131 ps
CPU time 1.16 seconds
Started Oct 15 12:27:13 PM UTC 24
Finished Oct 15 12:27:15 PM UTC 24
Peak memory 214256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127278485 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.4127278485
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.3059171232
Short name T285
Test name
Test status
Simulation time 50143581 ps
CPU time 1.11 seconds
Started Oct 15 12:27:12 PM UTC 24
Finished Oct 15 12:27:14 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059171232 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.3059171232
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2958928124
Short name T1752
Test name
Test status
Simulation time 23210888 ps
CPU time 1.21 seconds
Started Oct 15 12:27:14 PM UTC 24
Finished Oct 15 12:27:17 PM UTC 24
Peak memory 214328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958928124 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_outstanding.2958928124
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.2328340522
Short name T1754
Test name
Test status
Simulation time 134361865 ps
CPU time 3.87 seconds
Started Oct 15 12:27:12 PM UTC 24
Finished Oct 15 12:27:17 PM UTC 24
Peak memory 225412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328340522 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.2328340522
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.115049356
Short name T273
Test name
Test status
Simulation time 784820018 ps
CPU time 1.7 seconds
Started Oct 15 12:27:12 PM UTC 24
Finished Oct 15 12:27:15 PM UTC 24
Peak memory 214216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115049356 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.115049356
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1664204168
Short name T1759
Test name
Test status
Simulation time 26796203 ps
CPU time 1.85 seconds
Started Oct 15 12:27:18 PM UTC 24
Finished Oct 15 12:27:21 PM UTC 24
Peak memory 214152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1664204168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1664204168
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.1733053720
Short name T1755
Test name
Test status
Simulation time 68791250 ps
CPU time 1.06 seconds
Started Oct 15 12:27:16 PM UTC 24
Finished Oct 15 12:27:18 PM UTC 24
Peak memory 214256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733053720 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1733053720
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.2320572975
Short name T283
Test name
Test status
Simulation time 47671513 ps
CPU time 1.02 seconds
Started Oct 15 12:27:16 PM UTC 24
Finished Oct 15 12:27:18 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320572975 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.2320572975
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1589855426
Short name T1757
Test name
Test status
Simulation time 200748512 ps
CPU time 1.18 seconds
Started Oct 15 12:27:17 PM UTC 24
Finished Oct 15 12:27:19 PM UTC 24
Peak memory 214328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589855426 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_outstanding.1589855426
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.145465505
Short name T1756
Test name
Test status
Simulation time 194304578 ps
CPU time 2.71 seconds
Started Oct 15 12:27:15 PM UTC 24
Finished Oct 15 12:27:18 PM UTC 24
Peak memory 215304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145465505 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.145465505
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.300290402
Short name T220
Test name
Test status
Simulation time 553085564 ps
CPU time 3.21 seconds
Started Oct 15 12:27:16 PM UTC 24
Finished Oct 15 12:27:20 PM UTC 24
Peak memory 214924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300290402 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.300290402
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2736234168
Short name T1760
Test name
Test status
Simulation time 21513198 ps
CPU time 1.36 seconds
Started Oct 15 12:27:20 PM UTC 24
Finished Oct 15 12:27:22 PM UTC 24
Peak memory 214200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2736234168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2736234168
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.4042219586
Short name T234
Test name
Test status
Simulation time 20486202 ps
CPU time 1.07 seconds
Started Oct 15 12:27:18 PM UTC 24
Finished Oct 15 12:27:20 PM UTC 24
Peak memory 214256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042219586 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.4042219586
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.1462789185
Short name T1758
Test name
Test status
Simulation time 48421809 ps
CPU time 1.17 seconds
Started Oct 15 12:27:18 PM UTC 24
Finished Oct 15 12:27:21 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462789185 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1462789185
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1810523338
Short name T1761
Test name
Test status
Simulation time 30174425 ps
CPU time 1.67 seconds
Started Oct 15 12:27:20 PM UTC 24
Finished Oct 15 12:27:22 PM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810523338 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_outstanding.1810523338
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.2881465282
Short name T1744
Test name
Test status
Simulation time 71366447 ps
CPU time 2.72 seconds
Started Oct 15 12:27:18 PM UTC 24
Finished Oct 15 12:27:22 PM UTC 24
Peak memory 215044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881465282 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2881465282
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_fmt_empty.756645858
Short name T9
Test name
Test status
Simulation time 319534532 ps
CPU time 5.83 seconds
Started Oct 15 11:40:48 AM UTC 24
Finished Oct 15 11:40:58 AM UTC 24
Peak memory 281476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756645858 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty.756645858
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_full.3517014847
Short name T164
Test name
Test status
Simulation time 2485406974 ps
CPU time 119.3 seconds
Started Oct 15 11:40:48 AM UTC 24
Finished Oct 15 11:42:53 AM UTC 24
Peak memory 394248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517014847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3517014847
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_overflow.501591977
Short name T190
Test name
Test status
Simulation time 8078564621 ps
CPU time 123.02 seconds
Started Oct 15 11:40:48 AM UTC 24
Finished Oct 15 11:42:56 AM UTC 24
Peak memory 711748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501591977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.501591977
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_rx.2126370388
Short name T33
Test name
Test status
Simulation time 194684416 ps
CPU time 7.06 seconds
Started Oct 15 11:40:48 AM UTC 24
Finished Oct 15 11:40:59 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126370388 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.2126370388
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_override.1983701194
Short name T1
Test name
Test status
Simulation time 53043128 ps
CPU time 0.71 seconds
Started Oct 15 11:40:48 AM UTC 24
Finished Oct 15 11:40:53 AM UTC 24
Peak memory 214592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983701194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.1983701194
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_perf.3921475636
Short name T24
Test name
Test status
Simulation time 1614762038 ps
CPU time 8.04 seconds
Started Oct 15 11:40:48 AM UTC 24
Finished Oct 15 11:41:00 AM UTC 24
Peak memory 281540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921475636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3921475636
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_smoke.2769870778
Short name T31
Test name
Test status
Simulation time 7359236912 ps
CPU time 21.38 seconds
Started Oct 15 11:40:48 AM UTC 24
Finished Oct 15 11:41:14 AM UTC 24
Peak memory 381900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769870778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.2769870778
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_host_stretch_timeout.2649692011
Short name T34
Test name
Test status
Simulation time 9399894110 ps
CPU time 8.47 seconds
Started Oct 15 11:40:48 AM UTC 24
Finished Oct 15 11:41:01 AM UTC 24
Peak memory 227952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649692011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.2649692011
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_acq.2320286116
Short name T5
Test name
Test status
Simulation time 147360022 ps
CPU time 0.9 seconds
Started Oct 15 11:40:53 AM UTC 24
Finished Oct 15 11:40:57 AM UTC 24
Peak memory 225432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320286
116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_acq.2320286116
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_tx.3142857665
Short name T10
Test name
Test status
Simulation time 592937234 ps
CPU time 2.11 seconds
Started Oct 15 11:40:54 AM UTC 24
Finished Oct 15 11:40:58 AM UTC 24
Peak memory 217512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142857
665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_tx.3142857665
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_tx.2697852382
Short name T6
Test name
Test status
Simulation time 300635615 ps
CPU time 1.4 seconds
Started Oct 15 11:40:55 AM UTC 24
Finished Oct 15 11:40:58 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697852
382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_watermarks
_tx.2697852382
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_intr_smoke.3376128517
Short name T72
Test name
Test status
Simulation time 733887074 ps
CPU time 5.27 seconds
Started Oct 15 11:40:53 AM UTC 24
Finished Oct 15 11:41:01 AM UTC 24
Peak memory 232104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337612
8517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_smoke.3376128517
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_intr_stress_wr.2783320333
Short name T7
Test name
Test status
Simulation time 317399568 ps
CPU time 1.91 seconds
Started Oct 15 11:40:53 AM UTC 24
Finished Oct 15 11:40:58 AM UTC 24
Peak memory 225420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2783320333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_stress
_wr.2783320333
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull_addr.2840012679
Short name T65
Test name
Test status
Simulation time 2132395457 ps
CPU time 4.7 seconds
Started Oct 15 11:40:58 AM UTC 24
Finished Oct 15 11:41:07 AM UTC 24
Peak memory 215484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840012
679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.2840012679
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_perf.3720225874
Short name T75
Test name
Test status
Simulation time 833396560 ps
CPU time 5.61 seconds
Started Oct 15 11:40:55 AM UTC 24
Finished Oct 15 11:41:02 AM UTC 24
Peak memory 232336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720225
874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_perf.3720225874
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_smbus_maxlen.3539450972
Short name T171
Test name
Test status
Simulation time 923153991 ps
CPU time 2.26 seconds
Started Oct 15 11:40:57 AM UTC 24
Finished Oct 15 11:41:03 AM UTC 24
Peak memory 215240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539450
972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smbus_maxlen.3539450972
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_smoke.1770228963
Short name T77
Test name
Test status
Simulation time 3102016076 ps
CPU time 9.35 seconds
Started Oct 15 11:40:53 AM UTC 24
Finished Oct 15 11:41:05 AM UTC 24
Peak memory 225676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770228963 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smoke.1770228963
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_stress_all.3797185624
Short name T127
Test name
Test status
Simulation time 46197643381 ps
CPU time 62 seconds
Started Oct 15 11:40:55 AM UTC 24
Finished Oct 15 11:42:00 AM UTC 24
Peak memory 259468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379718
5624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_all.3797185624
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_stress_rd.84412537
Short name T76
Test name
Test status
Simulation time 2140711055 ps
CPU time 8.36 seconds
Started Oct 15 11:40:53 AM UTC 24
Finished Oct 15 11:41:04 AM UTC 24
Peak memory 229944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84412537 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_rd.84412537
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_stress_wr.779446731
Short name T295
Test name
Test status
Simulation time 24534434934 ps
CPU time 16.95 seconds
Started Oct 15 11:40:53 AM UTC 24
Finished Oct 15 11:41:13 AM UTC 24
Peak memory 359372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779446731 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_wr.779446731
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/0.i2c_target_stretch.2557224462
Short name T48
Test name
Test status
Simulation time 3081221868 ps
CPU time 4.19 seconds
Started Oct 15 11:40:53 AM UTC 24
Finished Oct 15 11:41:00 AM UTC 24
Peak memory 314308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557224462 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stretch.2557224462
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/0.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_alert_test.913194762
Short name T97
Test name
Test status
Simulation time 14724561 ps
CPU time 0.95 seconds
Started Oct 15 11:41:14 AM UTC 24
Finished Oct 15 11:41:16 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913194762 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.913194762
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_error_intr.1060998766
Short name T17
Test name
Test status
Simulation time 244691309 ps
CPU time 3.96 seconds
Started Oct 15 11:41:02 AM UTC 24
Finished Oct 15 11:41:07 AM UTC 24
Peak memory 225844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060998766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.1060998766
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_fmt_empty.2542771279
Short name T43
Test name
Test status
Simulation time 3783675737 ps
CPU time 9.24 seconds
Started Oct 15 11:41:01 AM UTC 24
Finished Oct 15 11:41:11 AM UTC 24
Peak memory 297848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542771279 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty.2542771279
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_full.1969494846
Short name T160
Test name
Test status
Simulation time 8487286233 ps
CPU time 63.35 seconds
Started Oct 15 11:41:01 AM UTC 24
Finished Oct 15 11:42:06 AM UTC 24
Peak memory 640000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969494846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.1969494846
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_overflow.2431903058
Short name T37
Test name
Test status
Simulation time 5600905781 ps
CPU time 86.94 seconds
Started Oct 15 11:41:01 AM UTC 24
Finished Oct 15 11:42:29 AM UTC 24
Peak memory 574396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431903058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2431903058
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_fmt.3837845461
Short name T38
Test name
Test status
Simulation time 210514916 ps
CPU time 1.35 seconds
Started Oct 15 11:41:01 AM UTC 24
Finished Oct 15 11:41:03 AM UTC 24
Peak memory 215716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837845461 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt.3837845461
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_rx.2393115932
Short name T35
Test name
Test status
Simulation time 154173602 ps
CPU time 6.78 seconds
Started Oct 15 11:41:01 AM UTC 24
Finished Oct 15 11:41:09 AM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393115932 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.2393115932
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_watermark.726843996
Short name T85
Test name
Test status
Simulation time 11038616954 ps
CPU time 129.87 seconds
Started Oct 15 11:40:59 AM UTC 24
Finished Oct 15 11:43:13 AM UTC 24
Peak memory 891964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726843996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.726843996
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_override.1756529895
Short name T98
Test name
Test status
Simulation time 29981960 ps
CPU time 1.06 seconds
Started Oct 15 11:40:59 AM UTC 24
Finished Oct 15 11:41:02 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756529895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1756529895
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_perf.725859625
Short name T14
Test name
Test status
Simulation time 6177617592 ps
CPU time 39.33 seconds
Started Oct 15 11:41:01 AM UTC 24
Finished Oct 15 11:41:42 AM UTC 24
Peak memory 215824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725859625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.725859625
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_smoke.3298728298
Short name T308
Test name
Test status
Simulation time 5503256279 ps
CPU time 62.21 seconds
Started Oct 15 11:40:59 AM UTC 24
Finished Oct 15 11:42:04 AM UTC 24
Peak memory 330676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298728298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.3298728298
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_host_stretch_timeout.2072419560
Short name T36
Test name
Test status
Simulation time 3878502959 ps
CPU time 18.96 seconds
Started Oct 15 11:41:02 AM UTC 24
Finished Oct 15 11:41:22 AM UTC 24
Peak memory 242664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072419560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2072419560
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_sec_cm.3942826083
Short name T202
Test name
Test status
Simulation time 163285535 ps
CPU time 1.49 seconds
Started Oct 15 11:41:14 AM UTC 24
Finished Oct 15 11:41:17 AM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942826083 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.3942826083
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_bad_addr.2736645581
Short name T68
Test name
Test status
Simulation time 1377217103 ps
CPU time 4.02 seconds
Started Oct 15 11:41:07 AM UTC 24
Finished Oct 15 11:41:12 AM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2736645581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.2736645581
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_acq.4176923899
Short name T47
Test name
Test status
Simulation time 365234933 ps
CPU time 1.2 seconds
Started Oct 15 11:41:05 AM UTC 24
Finished Oct 15 11:41:07 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176923
899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_acq.4176923899
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_tx.1941877923
Short name T193
Test name
Test status
Simulation time 139881145 ps
CPU time 1.4 seconds
Started Oct 15 11:41:06 AM UTC 24
Finished Oct 15 11:41:08 AM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941877
923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_tx.1941877923
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_acq.4258558468
Short name T276
Test name
Test status
Simulation time 1746158578 ps
CPU time 2.85 seconds
Started Oct 15 11:41:09 AM UTC 24
Finished Oct 15 11:41:13 AM UTC 24
Peak memory 215176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258558
468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_watermark
s_acq.4258558468
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_tx.1348992602
Short name T299
Test name
Test status
Simulation time 425322239 ps
CPU time 1.68 seconds
Started Oct 15 11:41:12 AM UTC 24
Finished Oct 15 11:41:15 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348992
602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_watermarks
_tx.1348992602
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_glitch.2585754105
Short name T54
Test name
Test status
Simulation time 3530398411 ps
CPU time 17.88 seconds
Started Oct 15 11:41:02 AM UTC 24
Finished Oct 15 11:41:21 AM UTC 24
Peak memory 226532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585754105 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.2585754105
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_intr_smoke.1011440707
Short name T301
Test name
Test status
Simulation time 1296291391 ps
CPU time 11.15 seconds
Started Oct 15 11:41:04 AM UTC 24
Finished Oct 15 11:41:18 AM UTC 24
Peak memory 232280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101144
0707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_smoke.1011440707
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_intr_stress_wr.2557909720
Short name T312
Test name
Test status
Simulation time 8711186144 ps
CPU time 82.46 seconds
Started Oct 15 11:41:04 AM UTC 24
Finished Oct 15 11:42:30 AM UTC 24
Peak memory 2335944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2557909720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_stress
_wr.2557909720
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull.4080667617
Short name T66
Test name
Test status
Simulation time 1258780994 ps
CPU time 3.41 seconds
Started Oct 15 11:41:13 AM UTC 24
Finished Oct 15 11:41:17 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080667
617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_acqfull.4080667617
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull_addr.4222429215
Short name T70
Test name
Test status
Simulation time 500578830 ps
CPU time 4.56 seconds
Started Oct 15 11:41:13 AM UTC 24
Finished Oct 15 11:41:19 AM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222429
215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.4222429215
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_perf.2152151455
Short name T298
Test name
Test status
Simulation time 751284356 ps
CPU time 7.01 seconds
Started Oct 15 11:41:06 AM UTC 24
Finished Oct 15 11:41:14 AM UTC 24
Peak memory 232696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152151
455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_perf.2152151455
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_smbus_maxlen.1883307217
Short name T300
Test name
Test status
Simulation time 504984846 ps
CPU time 3.44 seconds
Started Oct 15 11:41:13 AM UTC 24
Finished Oct 15 11:41:17 AM UTC 24
Peak memory 215236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883307
217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smbus_maxlen.1883307217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_smoke.711426619
Short name T304
Test name
Test status
Simulation time 2510942982 ps
CPU time 19.5 seconds
Started Oct 15 11:41:03 AM UTC 24
Finished Oct 15 11:41:25 AM UTC 24
Peak memory 227796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711426619 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smoke.711426619
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_stress_rd.2790291625
Short name T128
Test name
Test status
Simulation time 4774521524 ps
CPU time 53.93 seconds
Started Oct 15 11:41:03 AM UTC 24
Finished Oct 15 11:42:00 AM UTC 24
Peak memory 225672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790291625 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_rd.2790291625
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_stress_wr.22055875
Short name T303
Test name
Test status
Simulation time 13241213743 ps
CPU time 16.08 seconds
Started Oct 15 11:41:03 AM UTC 24
Finished Oct 15 11:41:21 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22055875 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_wr.22055875
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_stretch.3538258765
Short name T204
Test name
Test status
Simulation time 193811979 ps
CPU time 1.59 seconds
Started Oct 15 11:41:03 AM UTC 24
Finished Oct 15 11:41:06 AM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538258765 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stretch.3538258765
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_timeout.2838288290
Short name T78
Test name
Test status
Simulation time 1211869057 ps
CPU time 6.95 seconds
Started Oct 15 11:41:04 AM UTC 24
Finished Oct 15 11:41:13 AM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838288
290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_timeout.2838288290
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/1.i2c_target_tx_stretch_ctrl.1008602601
Short name T74
Test name
Test status
Simulation time 620083203 ps
CPU time 11.74 seconds
Started Oct 15 11:41:12 AM UTC 24
Finished Oct 15 11:41:25 AM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008602
601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.1008602601
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_alert_test.1211168886
Short name T479
Test name
Test status
Simulation time 25451926 ps
CPU time 1 seconds
Started Oct 15 11:47:52 AM UTC 24
Finished Oct 15 11:47:54 AM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211168886 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.1211168886
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_error_intr.382170825
Short name T457
Test name
Test status
Simulation time 168259609 ps
CPU time 2.61 seconds
Started Oct 15 11:47:12 AM UTC 24
Finished Oct 15 11:47:16 AM UTC 24
Peak memory 225788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382170825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.382170825
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_fmt_empty.2346729733
Short name T456
Test name
Test status
Simulation time 1105835088 ps
CPU time 15.39 seconds
Started Oct 15 11:46:56 AM UTC 24
Finished Oct 15 11:47:13 AM UTC 24
Peak memory 275332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346729733 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empty.2346729733
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_full.3750998727
Short name T522
Test name
Test status
Simulation time 13479493359 ps
CPU time 125.25 seconds
Started Oct 15 11:47:01 AM UTC 24
Finished Oct 15 11:49:09 AM UTC 24
Peak memory 781572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750998727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.3750998727
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_overflow.3007503495
Short name T490
Test name
Test status
Simulation time 5716769943 ps
CPU time 75.76 seconds
Started Oct 15 11:46:54 AM UTC 24
Finished Oct 15 11:48:12 AM UTC 24
Peak memory 533444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007503495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.3007503495
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_rx.2797552799
Short name T454
Test name
Test status
Simulation time 279980631 ps
CPU time 6.79 seconds
Started Oct 15 11:46:58 AM UTC 24
Finished Oct 15 11:47:06 AM UTC 24
Peak memory 236416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797552799 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.2797552799
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_watermark.3252890085
Short name T113
Test name
Test status
Simulation time 19534833695 ps
CPU time 94.29 seconds
Started Oct 15 11:46:53 AM UTC 24
Finished Oct 15 11:48:30 AM UTC 24
Peak memory 1496324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252890085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.3252890085
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_override.1718718087
Short name T451
Test name
Test status
Simulation time 26667253 ps
CPU time 1.04 seconds
Started Oct 15 11:46:53 AM UTC 24
Finished Oct 15 11:46:56 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718718087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.1718718087
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_perf.780056892
Short name T247
Test name
Test status
Simulation time 709837488 ps
CPU time 12.74 seconds
Started Oct 15 11:47:03 AM UTC 24
Finished Oct 15 11:47:17 AM UTC 24
Peak memory 215848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780056892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.780056892
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_perf_precise.532552473
Short name T455
Test name
Test status
Simulation time 70860861 ps
CPU time 2.18 seconds
Started Oct 15 11:47:08 AM UTC 24
Finished Oct 15 11:47:11 AM UTC 24
Peak memory 227624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532552473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.532552473
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_smoke.3420691188
Short name T462
Test name
Test status
Simulation time 1076881190 ps
CPU time 46.24 seconds
Started Oct 15 11:46:52 AM UTC 24
Finished Oct 15 11:47:40 AM UTC 24
Peak memory 304380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420691188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.3420691188
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_host_stretch_timeout.3237366684
Short name T472
Test name
Test status
Simulation time 730293054 ps
CPU time 37.27 seconds
Started Oct 15 11:47:11 AM UTC 24
Finished Oct 15 11:47:50 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237366684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.3237366684
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_bad_addr.3505016759
Short name T474
Test name
Test status
Simulation time 2056763468 ps
CPU time 8.98 seconds
Started Oct 15 11:47:41 AM UTC 24
Finished Oct 15 11:47:51 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3505016759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_ad
dr.3505016759
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_acq.2654783280
Short name T461
Test name
Test status
Simulation time 713477707 ps
CPU time 1.26 seconds
Started Oct 15 11:47:38 AM UTC 24
Finished Oct 15 11:47:40 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654783
280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_acq.2654783280
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_acq.215618716
Short name T477
Test name
Test status
Simulation time 566111615 ps
CPU time 3.69 seconds
Started Oct 15 11:47:48 AM UTC 24
Finished Oct 15 11:47:53 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156187
16 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_watermark
s_acq.215618716
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_tx.1122251382
Short name T475
Test name
Test status
Simulation time 150766539 ps
CPU time 2.26 seconds
Started Oct 15 11:47:48 AM UTC 24
Finished Oct 15 11:47:52 AM UTC 24
Peak memory 215168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122251
382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_watermark
s_tx.1122251382
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_hrst.3573790318
Short name T466
Test name
Test status
Simulation time 300513377 ps
CPU time 4.19 seconds
Started Oct 15 11:47:42 AM UTC 24
Finished Oct 15 11:47:47 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573790
318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_hrst.3573790318
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_intr_smoke.1127170118
Short name T458
Test name
Test status
Simulation time 2067961676 ps
CPU time 10.23 seconds
Started Oct 15 11:47:20 AM UTC 24
Finished Oct 15 11:47:32 AM UTC 24
Peak memory 226016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112717
0118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_smoke.1127170118
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_intr_stress_wr.1804737663
Short name T468
Test name
Test status
Simulation time 11632925471 ps
CPU time 17.39 seconds
Started Oct 15 11:47:29 AM UTC 24
Finished Oct 15 11:47:48 AM UTC 24
Peak memory 484556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1804737663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_stres
s_wr.1804737663
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull.161214760
Short name T482
Test name
Test status
Simulation time 1261326865 ps
CPU time 4.23 seconds
Started Oct 15 11:47:49 AM UTC 24
Finished Oct 15 11:47:55 AM UTC 24
Peak memory 226080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612147
60 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_acqfull.161214760
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull_addr.3328359533
Short name T480
Test name
Test status
Simulation time 465666146 ps
CPU time 3.26 seconds
Started Oct 15 11:47:50 AM UTC 24
Finished Oct 15 11:47:54 AM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328359
533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_acqfull_ad
dr.3328359533
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_nack_txstretch.4148067461
Short name T185
Test name
Test status
Simulation time 170994443 ps
CPU time 2.27 seconds
Started Oct 15 11:47:51 AM UTC 24
Finished Oct 15 11:47:54 AM UTC 24
Peak memory 232460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148067
461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_txstretch.4148067461
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_perf.3797207263
Short name T470
Test name
Test status
Simulation time 3870507139 ps
CPU time 8.92 seconds
Started Oct 15 11:47:39 AM UTC 24
Finished Oct 15 11:47:49 AM UTC 24
Peak memory 225960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797207
263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_perf.3797207263
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_smbus_maxlen.1686251762
Short name T476
Test name
Test status
Simulation time 2066504746 ps
CPU time 2.37 seconds
Started Oct 15 11:47:49 AM UTC 24
Finished Oct 15 11:47:53 AM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686251
762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smbus_maxlen.1686251762
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_smoke.2931824646
Short name T460
Test name
Test status
Simulation time 2162856471 ps
CPU time 21.83 seconds
Started Oct 15 11:47:15 AM UTC 24
Finished Oct 15 11:47:38 AM UTC 24
Peak memory 232584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931824646 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smoke.2931824646
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_stress_all.3495031165
Short name T556
Test name
Test status
Simulation time 34101049465 ps
CPU time 174.66 seconds
Started Oct 15 11:47:41 AM UTC 24
Finished Oct 15 11:50:38 AM UTC 24
Peak memory 2899204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349503
1165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_all.3495031165
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_stress_rd.2658979329
Short name T485
Test name
Test status
Simulation time 1514046001 ps
CPU time 39.75 seconds
Started Oct 15 11:47:16 AM UTC 24
Finished Oct 15 11:47:57 AM UTC 24
Peak memory 243068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658979329 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_rd.2658979329
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_stress_wr.4011131343
Short name T481
Test name
Test status
Simulation time 71600151103 ps
CPU time 38.1 seconds
Started Oct 15 11:47:15 AM UTC 24
Finished Oct 15 11:47:54 AM UTC 24
Peak memory 719796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011131343 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_wr.4011131343
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_stretch.3851597778
Short name T459
Test name
Test status
Simulation time 1506438527 ps
CPU time 18.72 seconds
Started Oct 15 11:47:17 AM UTC 24
Finished Oct 15 11:47:37 AM UTC 24
Peak memory 527680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851597778 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stretch.3851597778
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_timeout.1737363009
Short name T469
Test name
Test status
Simulation time 5640532070 ps
CPU time 14.52 seconds
Started Oct 15 11:47:32 AM UTC 24
Finished Oct 15 11:47:48 AM UTC 24
Peak memory 242748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737363
009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_timeout.1737363009
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/10.i2c_target_tx_stretch_ctrl.1669036545
Short name T478
Test name
Test status
Simulation time 103770461 ps
CPU time 2.55 seconds
Started Oct 15 11:47:49 AM UTC 24
Finished Oct 15 11:47:53 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669036
545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.1669036545
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_alert_test.1833680392
Short name T511
Test name
Test status
Simulation time 24563758 ps
CPU time 0.98 seconds
Started Oct 15 11:48:40 AM UTC 24
Finished Oct 15 11:48:43 AM UTC 24
Peak memory 213376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833680392 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.1833680392
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_error_intr.310971303
Short name T487
Test name
Test status
Simulation time 279798351 ps
CPU time 2.29 seconds
Started Oct 15 11:47:57 AM UTC 24
Finished Oct 15 11:48:01 AM UTC 24
Peak memory 225788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310971303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.310971303
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_fmt_empty.3757235913
Short name T489
Test name
Test status
Simulation time 534036321 ps
CPU time 7.3 seconds
Started Oct 15 11:47:55 AM UTC 24
Finished Oct 15 11:48:03 AM UTC 24
Peak memory 252788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757235913 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empty.3757235913
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_full.3267997129
Short name T543
Test name
Test status
Simulation time 7154502824 ps
CPU time 115.44 seconds
Started Oct 15 11:47:55 AM UTC 24
Finished Oct 15 11:49:53 AM UTC 24
Peak memory 359680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267997129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.3267997129
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_overflow.3700038338
Short name T520
Test name
Test status
Simulation time 4610701779 ps
CPU time 54.77 seconds
Started Oct 15 11:47:54 AM UTC 24
Finished Oct 15 11:48:50 AM UTC 24
Peak memory 570376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700038338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.3700038338
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_fmt.3071461461
Short name T484
Test name
Test status
Simulation time 73156756 ps
CPU time 1.32 seconds
Started Oct 15 11:47:54 AM UTC 24
Finished Oct 15 11:47:56 AM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071461461 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fmt.3071461461
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_rx.4241377181
Short name T488
Test name
Test status
Simulation time 517395909 ps
CPU time 5.74 seconds
Started Oct 15 11:47:55 AM UTC 24
Finished Oct 15 11:48:02 AM UTC 24
Peak memory 215720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241377181 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.4241377181
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_watermark.3902867597
Short name T606
Test name
Test status
Simulation time 8801658660 ps
CPU time 238.31 seconds
Started Oct 15 11:47:54 AM UTC 24
Finished Oct 15 11:51:56 AM UTC 24
Peak memory 1352912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902867597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.3902867597
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_may_nack.2358543358
Short name T260
Test name
Test status
Simulation time 602206713 ps
CPU time 18.88 seconds
Started Oct 15 11:48:33 AM UTC 24
Finished Oct 15 11:48:53 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358543358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.2358543358
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_override.2841785572
Short name T483
Test name
Test status
Simulation time 17932007 ps
CPU time 1.03 seconds
Started Oct 15 11:47:53 AM UTC 24
Finished Oct 15 11:47:55 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841785572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.2841785572
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_perf.299563872
Short name T509
Test name
Test status
Simulation time 5679357334 ps
CPU time 43.33 seconds
Started Oct 15 11:47:55 AM UTC 24
Finished Oct 15 11:48:40 AM UTC 24
Peak memory 236004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299563872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.299563872
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_perf_precise.587303861
Short name T486
Test name
Test status
Simulation time 162614750 ps
CPU time 2.54 seconds
Started Oct 15 11:47:56 AM UTC 24
Finished Oct 15 11:48:00 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587303861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.587303861
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_smoke.1632001287
Short name T499
Test name
Test status
Simulation time 10120598547 ps
CPU time 38.09 seconds
Started Oct 15 11:47:52 AM UTC 24
Finished Oct 15 11:48:31 AM UTC 24
Peak memory 418684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632001287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.1632001287
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_stress_all.1462527000
Short name T278
Test name
Test status
Simulation time 59105011062 ps
CPU time 2913.27 seconds
Started Oct 15 11:47:59 AM UTC 24
Finished Oct 15 12:37:01 PM UTC 24
Peak memory 1133776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462527000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.1462527000
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_stretch_timeout.2424190494
Short name T510
Test name
Test status
Simulation time 3263321722 ps
CPU time 43.7 seconds
Started Oct 15 11:47:56 AM UTC 24
Finished Oct 15 11:48:41 AM UTC 24
Peak memory 226032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424190494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.2424190494
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_bad_addr.3077936118
Short name T503
Test name
Test status
Simulation time 2359662641 ps
CPU time 5.79 seconds
Started Oct 15 11:48:31 AM UTC 24
Finished Oct 15 11:48:38 AM UTC 24
Peak memory 232280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3077936118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_bad_ad
dr.3077936118
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_acq.4294331732
Short name T493
Test name
Test status
Simulation time 179587745 ps
CPU time 1.49 seconds
Started Oct 15 11:48:24 AM UTC 24
Finished Oct 15 11:48:27 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294331
732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_acq.4294331732
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_tx.3545221917
Short name T494
Test name
Test status
Simulation time 338860024 ps
CPU time 1.38 seconds
Started Oct 15 11:48:25 AM UTC 24
Finished Oct 15 11:48:28 AM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545221
917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_tx.3545221917
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_acq.2375711784
Short name T504
Test name
Test status
Simulation time 1141715311 ps
CPU time 2.01 seconds
Started Oct 15 11:48:36 AM UTC 24
Finished Oct 15 11:48:39 AM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375711
784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_watermar
ks_acq.2375711784
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_tx.579583160
Short name T505
Test name
Test status
Simulation time 59487839 ps
CPU time 1.46 seconds
Started Oct 15 11:48:37 AM UTC 24
Finished Oct 15 11:48:39 AM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5795831
60 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_watermarks
_tx.579583160
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_intr_smoke.3710110408
Short name T491
Test name
Test status
Simulation time 1132029894 ps
CPU time 12.25 seconds
Started Oct 15 11:48:04 AM UTC 24
Finished Oct 15 11:48:17 AM UTC 24
Peak memory 230060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371011
0408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_smoke.3710110408
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_intr_stress_wr.3685704244
Short name T135
Test name
Test status
Simulation time 25270181655 ps
CPU time 201.39 seconds
Started Oct 15 11:48:13 AM UTC 24
Finished Oct 15 11:51:38 AM UTC 24
Peak memory 3083208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3685704244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_stres
s_wr.3685704244
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull.4255379177
Short name T512
Test name
Test status
Simulation time 4077334197 ps
CPU time 3.86 seconds
Started Oct 15 11:48:38 AM UTC 24
Finished Oct 15 11:48:43 AM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255379
177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_acqfull.4255379177
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull_addr.1327173950
Short name T518
Test name
Test status
Simulation time 548477200 ps
CPU time 4.98 seconds
Started Oct 15 11:48:40 AM UTC 24
Finished Oct 15 11:48:47 AM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327173
950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_acqfull_ad
dr.1327173950
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_perf.470095430
Short name T506
Test name
Test status
Simulation time 911117344 ps
CPU time 10.08 seconds
Started Oct 15 11:48:28 AM UTC 24
Finished Oct 15 11:48:40 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4700954
30 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_perf.470095430
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_smbus_maxlen.1852944656
Short name T514
Test name
Test status
Simulation time 2127903619 ps
CPU time 4.17 seconds
Started Oct 15 11:48:38 AM UTC 24
Finished Oct 15 11:48:44 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852944
656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smbus_maxlen.1852944656
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_smoke.282296828
Short name T492
Test name
Test status
Simulation time 1960111137 ps
CPU time 18.67 seconds
Started Oct 15 11:47:59 AM UTC 24
Finished Oct 15 11:48:18 AM UTC 24
Peak memory 232396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282296828 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smoke.282296828
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_stress_all.1776488140
Short name T541
Test name
Test status
Simulation time 9254092397 ps
CPU time 79.62 seconds
Started Oct 15 11:48:29 AM UTC 24
Finished Oct 15 11:49:51 AM UTC 24
Peak memory 324556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177648
8140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_all.1776488140
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_stress_rd.120200949
Short name T496
Test name
Test status
Simulation time 1217410246 ps
CPU time 27.08 seconds
Started Oct 15 11:48:02 AM UTC 24
Finished Oct 15 11:48:30 AM UTC 24
Peak memory 232448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120200949 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_rd.120200949
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_stress_wr.536175134
Short name T516
Test name
Test status
Simulation time 20367754042 ps
CPU time 44.14 seconds
Started Oct 15 11:48:01 AM UTC 24
Finished Oct 15 11:48:46 AM UTC 24
Peak memory 215908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536175134 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_wr.536175134
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_stretch.1409343427
Short name T513
Test name
Test status
Simulation time 4032702838 ps
CPU time 88.08 seconds
Started Oct 15 11:48:03 AM UTC 24
Finished Oct 15 11:49:33 AM UTC 24
Peak memory 635784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409343427 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stretch.1409343427
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_timeout.1072017156
Short name T497
Test name
Test status
Simulation time 4700058692 ps
CPU time 11.76 seconds
Started Oct 15 11:48:18 AM UTC 24
Finished Oct 15 11:48:31 AM UTC 24
Peak memory 231972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072017
156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_timeout.1072017156
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_target_tx_stretch_ctrl.2224657206
Short name T507
Test name
Test status
Simulation time 61829087 ps
CPU time 1.84 seconds
Started Oct 15 11:48:37 AM UTC 24
Finished Oct 15 11:48:40 AM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224657
206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.2224657206
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_alert_test.1883624538
Short name T495
Test name
Test status
Simulation time 101443760 ps
CPU time 0.95 seconds
Started Oct 15 11:49:44 AM UTC 24
Finished Oct 15 11:49:46 AM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883624538 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.1883624538
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_fmt_empty.2579324178
Short name T521
Test name
Test status
Simulation time 443326084 ps
CPU time 8.79 seconds
Started Oct 15 11:48:45 AM UTC 24
Finished Oct 15 11:48:55 AM UTC 24
Peak memory 249028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579324178 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empty.2579324178
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_full.2405253948
Short name T549
Test name
Test status
Simulation time 12190287555 ps
CPU time 93.41 seconds
Started Oct 15 11:48:45 AM UTC 24
Finished Oct 15 11:50:21 AM UTC 24
Peak memory 556048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405253948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.2405253948
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_overflow.806627399
Short name T585
Test name
Test status
Simulation time 9162389084 ps
CPU time 150.31 seconds
Started Oct 15 11:48:44 AM UTC 24
Finished Oct 15 11:51:17 AM UTC 24
Peak memory 779136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806627399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.806627399
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_fmt.2151120021
Short name T517
Test name
Test status
Simulation time 116790795 ps
CPU time 1.43 seconds
Started Oct 15 11:48:44 AM UTC 24
Finished Oct 15 11:48:46 AM UTC 24
Peak memory 215712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151120021 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fmt.2151120021
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_rx.2198754248
Short name T519
Test name
Test status
Simulation time 834169711 ps
CPU time 3.84 seconds
Started Oct 15 11:48:45 AM UTC 24
Finished Oct 15 11:48:50 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198754248 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.2198754248
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_watermark.1870407634
Short name T696
Test name
Test status
Simulation time 5006949653 ps
CPU time 312.16 seconds
Started Oct 15 11:48:42 AM UTC 24
Finished Oct 15 11:53:59 AM UTC 24
Peak memory 1381380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870407634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1870407634
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_may_nack.2688490147
Short name T535
Test name
Test status
Simulation time 475668292 ps
CPU time 7.17 seconds
Started Oct 15 11:49:36 AM UTC 24
Finished Oct 15 11:49:44 AM UTC 24
Peak memory 215844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688490147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.2688490147
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_override.1798083332
Short name T515
Test name
Test status
Simulation time 95292354 ps
CPU time 1.06 seconds
Started Oct 15 11:48:41 AM UTC 24
Finished Oct 15 11:48:44 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798083332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.1798083332
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_perf.2119439949
Short name T636
Test name
Test status
Simulation time 12126305977 ps
CPU time 225.08 seconds
Started Oct 15 11:48:47 AM UTC 24
Finished Oct 15 11:52:35 AM UTC 24
Peak memory 1557432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119439949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2119439949
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_perf_precise.721863161
Short name T634
Test name
Test status
Simulation time 24676839175 ps
CPU time 220.91 seconds
Started Oct 15 11:48:47 AM UTC 24
Finished Oct 15 11:52:31 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721863161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.721863161
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_smoke.2819644086
Short name T527
Test name
Test status
Simulation time 4490665900 ps
CPU time 45.88 seconds
Started Oct 15 11:48:40 AM UTC 24
Finished Oct 15 11:49:28 AM UTC 24
Peak memory 248704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819644086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.2819644086
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_host_stretch_timeout.1881859573
Short name T523
Test name
Test status
Simulation time 2002714227 ps
CPU time 23.74 seconds
Started Oct 15 11:48:47 AM UTC 24
Finished Oct 15 11:49:12 AM UTC 24
Peak memory 226096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881859573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.1881859573
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_bad_addr.3198615336
Short name T534
Test name
Test status
Simulation time 1251586539 ps
CPU time 7.64 seconds
Started Oct 15 11:49:34 AM UTC 24
Finished Oct 15 11:49:43 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3198615336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_ad
dr.3198615336
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_acq.1978816459
Short name T528
Test name
Test status
Simulation time 453973567 ps
CPU time 2.13 seconds
Started Oct 15 11:49:29 AM UTC 24
Finished Oct 15 11:49:32 AM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978816
459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_acq.1978816459
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_tx.1780217322
Short name T508
Test name
Test status
Simulation time 225537352 ps
CPU time 1.49 seconds
Started Oct 15 11:49:31 AM UTC 24
Finished Oct 15 11:49:34 AM UTC 24
Peak memory 225556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780217
322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_tx.1780217322
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_acq.3642873450
Short name T532
Test name
Test status
Simulation time 1762969844 ps
CPU time 5 seconds
Started Oct 15 11:49:37 AM UTC 24
Finished Oct 15 11:49:43 AM UTC 24
Peak memory 215444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642873
450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_watermar
ks_acq.3642873450
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_tx.4187481974
Short name T531
Test name
Test status
Simulation time 1813557943 ps
CPU time 2.54 seconds
Started Oct 15 11:49:38 AM UTC 24
Finished Oct 15 11:49:41 AM UTC 24
Peak memory 215176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187481
974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_watermark
s_tx.4187481974
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_hrst.2287555889
Short name T498
Test name
Test status
Simulation time 620959599 ps
CPU time 1.68 seconds
Started Oct 15 11:49:34 AM UTC 24
Finished Oct 15 11:49:37 AM UTC 24
Peak memory 231312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287555
889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_hrst.2287555889
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_intr_smoke.78785080
Short name T526
Test name
Test status
Simulation time 2031680491 ps
CPU time 12.16 seconds
Started Oct 15 11:49:13 AM UTC 24
Finished Oct 15 11:49:26 AM UTC 24
Peak memory 231780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787850
80 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_smoke.78785080
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_intr_stress_wr.4012496011
Short name T581
Test name
Test status
Simulation time 20356502616 ps
CPU time 108.79 seconds
Started Oct 15 11:49:15 AM UTC 24
Finished Oct 15 11:51:06 AM UTC 24
Peak memory 1576136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4012496011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_stres
s_wr.4012496011
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull.4090056223
Short name T537
Test name
Test status
Simulation time 598422338 ps
CPU time 3.69 seconds
Started Oct 15 11:49:42 AM UTC 24
Finished Oct 15 11:49:47 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090056
223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_acqfull.4090056223
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull_addr.4289421832
Short name T538
Test name
Test status
Simulation time 496729612 ps
CPU time 5.22 seconds
Started Oct 15 11:49:43 AM UTC 24
Finished Oct 15 11:49:49 AM UTC 24
Peak memory 215744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289421
832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_acqfull_ad
dr.4289421832
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_perf.2341741341
Short name T530
Test name
Test status
Simulation time 559426785 ps
CPU time 7.09 seconds
Started Oct 15 11:49:32 AM UTC 24
Finished Oct 15 11:49:40 AM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341741
341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_perf.2341741341
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_smbus_maxlen.666142928
Short name T536
Test name
Test status
Simulation time 3898687484 ps
CPU time 4.41 seconds
Started Oct 15 11:49:41 AM UTC 24
Finished Oct 15 11:49:46 AM UTC 24
Peak memory 215236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6661429
28 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smbus_maxlen.666142928
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_smoke.1520374696
Short name T524
Test name
Test status
Simulation time 1790896914 ps
CPU time 18.81 seconds
Started Oct 15 11:48:54 AM UTC 24
Finished Oct 15 11:49:14 AM UTC 24
Peak memory 232452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520374696 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smoke.1520374696
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_stress_all.1417473647
Short name T222
Test name
Test status
Simulation time 24253014775 ps
CPU time 243.91 seconds
Started Oct 15 11:49:33 AM UTC 24
Finished Oct 15 11:53:40 AM UTC 24
Peak memory 3230676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141747
3647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_all.1417473647
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_stress_rd.1592967178
Short name T525
Test name
Test status
Simulation time 1443356006 ps
CPU time 21.83 seconds
Started Oct 15 11:48:57 AM UTC 24
Finished Oct 15 11:49:21 AM UTC 24
Peak memory 215584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592967178 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_rd.1592967178
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_stress_wr.1144828947
Short name T465
Test name
Test status
Simulation time 22512208886 ps
CPU time 37.55 seconds
Started Oct 15 11:48:55 AM UTC 24
Finished Oct 15 11:49:34 AM UTC 24
Peak memory 428996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144828947 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_wr.1144828947
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_stretch.3275253582
Short name T564
Test name
Test status
Simulation time 2026945387 ps
CPU time 93.03 seconds
Started Oct 15 11:49:11 AM UTC 24
Finished Oct 15 11:50:46 AM UTC 24
Peak memory 679108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275253582 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stretch.3275253582
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/12.i2c_target_timeout.713049760
Short name T502
Test name
Test status
Simulation time 10215214867 ps
CPU time 12.79 seconds
Started Oct 15 11:49:22 AM UTC 24
Finished Oct 15 11:49:36 AM UTC 24
Peak memory 242648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7130497
60 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_timeout.713049760
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/12.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_alert_test.1893388754
Short name T567
Test name
Test status
Simulation time 22975500 ps
CPU time 1.04 seconds
Started Oct 15 11:50:48 AM UTC 24
Finished Oct 15 11:50:50 AM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893388754 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.1893388754
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_error_intr.3441614368
Short name T32
Test name
Test status
Simulation time 623026669 ps
CPU time 8.14 seconds
Started Oct 15 11:49:58 AM UTC 24
Finished Oct 15 11:50:07 AM UTC 24
Peak memory 247064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441614368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.3441614368
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_fmt_empty.3814781491
Short name T546
Test name
Test status
Simulation time 1255898109 ps
CPU time 15.35 seconds
Started Oct 15 11:49:50 AM UTC 24
Finished Oct 15 11:50:06 AM UTC 24
Peak memory 255164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814781491 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empty.3814781491
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_full.1147822550
Short name T582
Test name
Test status
Simulation time 13371304590 ps
CPU time 72.2 seconds
Started Oct 15 11:49:52 AM UTC 24
Finished Oct 15 11:51:06 AM UTC 24
Peak memory 490452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147822550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1147822550
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_overflow.2833245222
Short name T575
Test name
Test status
Simulation time 2039345933 ps
CPU time 65.69 seconds
Started Oct 15 11:49:47 AM UTC 24
Finished Oct 15 11:50:55 AM UTC 24
Peak memory 711500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833245222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.2833245222
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_fmt.3166894088
Short name T540
Test name
Test status
Simulation time 83369532 ps
CPU time 1.54 seconds
Started Oct 15 11:49:49 AM UTC 24
Finished Oct 15 11:49:51 AM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166894088 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_fmt.3166894088
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_rx.2804627133
Short name T545
Test name
Test status
Simulation time 316169096 ps
CPU time 12.35 seconds
Started Oct 15 11:49:51 AM UTC 24
Finished Oct 15 11:50:04 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804627133 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.2804627133
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_watermark.4136213374
Short name T114
Test name
Test status
Simulation time 13928868156 ps
CPU time 72.33 seconds
Started Oct 15 11:49:47 AM UTC 24
Finished Oct 15 11:51:01 AM UTC 24
Peak memory 1104768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136213374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.4136213374
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_may_nack.3943980105
Short name T269
Test name
Test status
Simulation time 590822301 ps
CPU time 22.3 seconds
Started Oct 15 11:50:40 AM UTC 24
Finished Oct 15 11:51:04 AM UTC 24
Peak memory 215520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943980105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.3943980105
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_mode_toggle.1383235162
Short name T560
Test name
Test status
Simulation time 787837771 ps
CPU time 2.57 seconds
Started Oct 15 11:50:39 AM UTC 24
Finished Oct 15 11:50:43 AM UTC 24
Peak memory 230064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383235162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.1383235162
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_override.3203238182
Short name T539
Test name
Test status
Simulation time 29647033 ps
CPU time 1.08 seconds
Started Oct 15 11:49:47 AM UTC 24
Finished Oct 15 11:49:49 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203238182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.3203238182
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_perf.2107314295
Short name T553
Test name
Test status
Simulation time 52264456594 ps
CPU time 39.49 seconds
Started Oct 15 11:49:52 AM UTC 24
Finished Oct 15 11:50:33 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107314295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.2107314295
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_perf_precise.3863794130
Short name T544
Test name
Test status
Simulation time 257713738 ps
CPU time 3.54 seconds
Started Oct 15 11:49:53 AM UTC 24
Finished Oct 15 11:49:58 AM UTC 24
Peak memory 215776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863794130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.3863794130
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_smoke.3768525672
Short name T577
Test name
Test status
Simulation time 6594226127 ps
CPU time 71.27 seconds
Started Oct 15 11:49:44 AM UTC 24
Finished Oct 15 11:50:57 AM UTC 24
Peak memory 314248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768525672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.3768525672
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_host_stretch_timeout.1676275082
Short name T547
Test name
Test status
Simulation time 1244443475 ps
CPU time 11.02 seconds
Started Oct 15 11:49:54 AM UTC 24
Finished Oct 15 11:50:06 AM UTC 24
Peak memory 232096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676275082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.1676275082
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_bad_addr.24673457
Short name T565
Test name
Test status
Simulation time 3553011015 ps
CPU time 5.73 seconds
Started Oct 15 11:50:39 AM UTC 24
Finished Oct 15 11:50:46 AM UTC 24
Peak memory 229988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=24673457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.24673457
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_acq.818183539
Short name T555
Test name
Test status
Simulation time 384201765 ps
CPU time 2.91 seconds
Started Oct 15 11:50:34 AM UTC 24
Finished Oct 15 11:50:38 AM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8181835
39 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_acq.818183539
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_tx.3547271832
Short name T557
Test name
Test status
Simulation time 361937572 ps
CPU time 2.69 seconds
Started Oct 15 11:50:35 AM UTC 24
Finished Oct 15 11:50:39 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547271
832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_tx.3547271832
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_acq.334192247
Short name T566
Test name
Test status
Simulation time 543442713 ps
CPU time 1.99 seconds
Started Oct 15 11:50:43 AM UTC 24
Finished Oct 15 11:50:46 AM UTC 24
Peak memory 215428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341922
47 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_watermark
s_acq.334192247
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_tx.1426755128
Short name T563
Test name
Test status
Simulation time 183137155 ps
CPU time 1.16 seconds
Started Oct 15 11:50:44 AM UTC 24
Finished Oct 15 11:50:46 AM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426755
128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_watermark
s_tx.1426755128
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_hrst.2737574112
Short name T561
Test name
Test status
Simulation time 1405640755 ps
CPU time 3.78 seconds
Started Oct 15 11:50:39 AM UTC 24
Finished Oct 15 11:50:44 AM UTC 24
Peak memory 225608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737574
112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_hrst.2737574112
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_intr_smoke.3553720062
Short name T554
Test name
Test status
Simulation time 1951315946 ps
CPU time 12.63 seconds
Started Oct 15 11:50:22 AM UTC 24
Finished Oct 15 11:50:35 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355372
0062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_smoke.3553720062
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_intr_stress_wr.3756757833
Short name T579
Test name
Test status
Simulation time 16765426732 ps
CPU time 34.97 seconds
Started Oct 15 11:50:25 AM UTC 24
Finished Oct 15 11:51:01 AM UTC 24
Peak memory 615300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3756757833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_stres
s_wr.3756757833
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull.376070202
Short name T573
Test name
Test status
Simulation time 584840429 ps
CPU time 5.42 seconds
Started Oct 15 11:50:47 AM UTC 24
Finished Oct 15 11:50:53 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760702
02 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_acqfull.376070202
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull_addr.2773413948
Short name T571
Test name
Test status
Simulation time 1780056529 ps
CPU time 4.92 seconds
Started Oct 15 11:50:47 AM UTC 24
Finished Oct 15 11:50:53 AM UTC 24
Peak memory 215480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773413
948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_acqfull_ad
dr.2773413948
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_perf.2304394659
Short name T559
Test name
Test status
Simulation time 494655119 ps
CPU time 5.13 seconds
Started Oct 15 11:50:36 AM UTC 24
Finished Oct 15 11:50:42 AM UTC 24
Peak memory 231776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304394
659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_perf.2304394659
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_smbus_maxlen.3734666093
Short name T570
Test name
Test status
Simulation time 1875719501 ps
CPU time 4.35 seconds
Started Oct 15 11:50:46 AM UTC 24
Finished Oct 15 11:50:51 AM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734666
093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smbus_maxlen.3734666093
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_smoke.2326453249
Short name T550
Test name
Test status
Simulation time 699726017 ps
CPU time 15.53 seconds
Started Oct 15 11:50:07 AM UTC 24
Finished Oct 15 11:50:24 AM UTC 24
Peak memory 225820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326453249 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smoke.2326453249
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_stress_all.2721801878
Short name T589
Test name
Test status
Simulation time 20456562186 ps
CPU time 42.1 seconds
Started Oct 15 11:50:36 AM UTC 24
Finished Oct 15 11:51:20 AM UTC 24
Peak memory 291724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272180
1878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_all.2721801878
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_stress_rd.1704519326
Short name T568
Test name
Test status
Simulation time 3965151511 ps
CPU time 40.32 seconds
Started Oct 15 11:50:08 AM UTC 24
Finished Oct 15 11:50:50 AM UTC 24
Peak memory 227804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704519326 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_rd.1704519326
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_stress_wr.4124956639
Short name T774
Test name
Test status
Simulation time 61274624306 ps
CPU time 391.6 seconds
Started Oct 15 11:50:07 AM UTC 24
Finished Oct 15 11:56:43 AM UTC 24
Peak memory 5149896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124956639 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_wr.4124956639
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_stretch.909795166
Short name T551
Test name
Test status
Simulation time 1499932908 ps
CPU time 13.76 seconds
Started Oct 15 11:50:11 AM UTC 24
Finished Oct 15 11:50:25 AM UTC 24
Peak memory 363712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909795166 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stretch.909795166
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_timeout.1003915200
Short name T558
Test name
Test status
Simulation time 1164195524 ps
CPU time 11.8 seconds
Started Oct 15 11:50:27 AM UTC 24
Finished Oct 15 11:50:40 AM UTC 24
Peak memory 232580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003915
200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_timeout.1003915200
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/13.i2c_target_tx_stretch_ctrl.3976548431
Short name T574
Test name
Test status
Simulation time 326539168 ps
CPU time 8.7 seconds
Started Oct 15 11:50:45 AM UTC 24
Finished Oct 15 11:50:54 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976548
431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.3976548431
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_alert_test.760318781
Short name T599
Test name
Test status
Simulation time 16592970 ps
CPU time 1.02 seconds
Started Oct 15 11:51:32 AM UTC 24
Finished Oct 15 11:51:34 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760318781 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.760318781
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_error_intr.1224822204
Short name T580
Test name
Test status
Simulation time 216746142 ps
CPU time 2.55 seconds
Started Oct 15 11:50:58 AM UTC 24
Finished Oct 15 11:51:02 AM UTC 24
Peak memory 226048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224822204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.1224822204
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_fmt_empty.949053573
Short name T586
Test name
Test status
Simulation time 2517730326 ps
CPU time 23.17 seconds
Started Oct 15 11:50:53 AM UTC 24
Finished Oct 15 11:51:18 AM UTC 24
Peak memory 308552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949053573 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empty.949053573
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_full.2702655395
Short name T605
Test name
Test status
Simulation time 2078087585 ps
CPU time 58.28 seconds
Started Oct 15 11:50:55 AM UTC 24
Finished Oct 15 11:51:54 AM UTC 24
Peak memory 533696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702655395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.2702655395
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_overflow.3158034071
Short name T139
Test name
Test status
Simulation time 1739072225 ps
CPU time 53.37 seconds
Started Oct 15 11:50:51 AM UTC 24
Finished Oct 15 11:51:46 AM UTC 24
Peak memory 603088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158034071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3158034071
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_fmt.3321009036
Short name T576
Test name
Test status
Simulation time 109042168 ps
CPU time 1.58 seconds
Started Oct 15 11:50:52 AM UTC 24
Finished Oct 15 11:50:55 AM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321009036 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fmt.3321009036
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_rx.1681827126
Short name T578
Test name
Test status
Simulation time 1460827395 ps
CPU time 4.85 seconds
Started Oct 15 11:50:54 AM UTC 24
Finished Oct 15 11:51:00 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681827126 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.1681827126
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_watermark.4029687743
Short name T115
Test name
Test status
Simulation time 14269415976 ps
CPU time 107.49 seconds
Started Oct 15 11:50:51 AM UTC 24
Finished Oct 15 11:52:41 AM UTC 24
Peak memory 1522756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029687743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.4029687743
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_may_nack.2589079342
Short name T595
Test name
Test status
Simulation time 1340214502 ps
CPU time 6.21 seconds
Started Oct 15 11:51:23 AM UTC 24
Finished Oct 15 11:51:30 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589079342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2589079342
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_override.1020132098
Short name T572
Test name
Test status
Simulation time 26798478 ps
CPU time 1.06 seconds
Started Oct 15 11:50:51 AM UTC 24
Finished Oct 15 11:50:53 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020132098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1020132098
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_perf.2382275928
Short name T1638
Test name
Test status
Simulation time 70201675835 ps
CPU time 3246.64 seconds
Started Oct 15 11:50:56 AM UTC 24
Finished Oct 15 12:45:31 PM UTC 24
Peak memory 6613960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382275928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.2382275928
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_perf_precise.3052046448
Short name T587
Test name
Test status
Simulation time 6037622896 ps
CPU time 21.89 seconds
Started Oct 15 11:50:56 AM UTC 24
Finished Oct 15 11:51:19 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052046448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.3052046448
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_smoke.4046030051
Short name T597
Test name
Test status
Simulation time 3984451075 ps
CPU time 39.31 seconds
Started Oct 15 11:50:51 AM UTC 24
Finished Oct 15 11:51:32 AM UTC 24
Peak memory 377800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046030051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.4046030051
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_stretch_timeout.3732134307
Short name T533
Test name
Test status
Simulation time 2844426168 ps
CPU time 38.17 seconds
Started Oct 15 11:50:56 AM UTC 24
Finished Oct 15 11:51:35 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732134307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.3732134307
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_bad_addr.4033787940
Short name T591
Test name
Test status
Simulation time 861196233 ps
CPU time 4.82 seconds
Started Oct 15 11:51:20 AM UTC 24
Finished Oct 15 11:51:26 AM UTC 24
Peak memory 225820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4033787940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_ad
dr.4033787940
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_tx.2368671512
Short name T590
Test name
Test status
Simulation time 685521795 ps
CPU time 2.76 seconds
Started Oct 15 11:51:19 AM UTC 24
Finished Oct 15 11:51:23 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368671
512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_tx.2368671512
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_acq.3824467604
Short name T598
Test name
Test status
Simulation time 540402594 ps
CPU time 5.24 seconds
Started Oct 15 11:51:26 AM UTC 24
Finished Oct 15 11:51:33 AM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824467
604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_watermar
ks_acq.3824467604
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_tx.821474145
Short name T593
Test name
Test status
Simulation time 153134607 ps
CPU time 2.34 seconds
Started Oct 15 11:51:26 AM UTC 24
Finished Oct 15 11:51:30 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8214741
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_watermarks
_tx.821474145
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_intr_smoke.2734261632
Short name T584
Test name
Test status
Simulation time 2146814276 ps
CPU time 7.57 seconds
Started Oct 15 11:51:06 AM UTC 24
Finished Oct 15 11:51:15 AM UTC 24
Peak memory 229860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273426
1632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_smoke.2734261632
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_intr_stress_wr.1574036307
Short name T659
Test name
Test status
Simulation time 19958340679 ps
CPU time 105.23 seconds
Started Oct 15 11:51:06 AM UTC 24
Finished Oct 15 11:52:54 AM UTC 24
Peak memory 1403896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1574036307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_stres
s_wr.1574036307
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull.1195812116
Short name T134
Test name
Test status
Simulation time 1219878292 ps
CPU time 4.83 seconds
Started Oct 15 11:51:31 AM UTC 24
Finished Oct 15 11:51:37 AM UTC 24
Peak memory 225608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195812
116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_acqfull.1195812116
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull_addr.878481453
Short name T133
Test name
Test status
Simulation time 864707235 ps
CPU time 4.46 seconds
Started Oct 15 11:51:31 AM UTC 24
Finished Oct 15 11:51:36 AM UTC 24
Peak memory 215412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8784814
53 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_acqfull_addr.878481453
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_nack_txstretch.154956963
Short name T601
Test name
Test status
Simulation time 505987491 ps
CPU time 2.14 seconds
Started Oct 15 11:51:32 AM UTC 24
Finished Oct 15 11:51:35 AM UTC 24
Peak memory 232252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549569
63 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_txstretch.154956963
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_perf.3914163456
Short name T594
Test name
Test status
Simulation time 784629225 ps
CPU time 8.93 seconds
Started Oct 15 11:51:20 AM UTC 24
Finished Oct 15 11:51:30 AM UTC 24
Peak memory 231848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914163
456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_perf.3914163456
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_smbus_maxlen.1435828176
Short name T132
Test name
Test status
Simulation time 494981943 ps
CPU time 4.75 seconds
Started Oct 15 11:51:29 AM UTC 24
Finished Oct 15 11:51:35 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435828
176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smbus_maxlen.1435828176
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_smoke.4056018740
Short name T588
Test name
Test status
Simulation time 4047209960 ps
CPU time 15.82 seconds
Started Oct 15 11:51:02 AM UTC 24
Finished Oct 15 11:51:19 AM UTC 24
Peak memory 230052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056018740 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smoke.4056018740
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_stress_all.4198231966
Short name T1077
Test name
Test status
Simulation time 47760614907 ps
CPU time 933.04 seconds
Started Oct 15 11:51:20 AM UTC 24
Finished Oct 15 12:07:02 PM UTC 24
Peak memory 8977624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419823
1966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_all.4198231966
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_stress_rd.2713030689
Short name T529
Test name
Test status
Simulation time 11689876195 ps
CPU time 32.52 seconds
Started Oct 15 11:51:02 AM UTC 24
Finished Oct 15 11:51:36 AM UTC 24
Peak memory 232468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713030689 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_rd.2713030689
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_stress_wr.617538907
Short name T1197
Test name
Test status
Simulation time 64264037718 ps
CPU time 1136.48 seconds
Started Oct 15 11:51:02 AM UTC 24
Finished Oct 15 12:10:09 PM UTC 24
Peak memory 10990468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617538907 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_wr.617538907
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_stretch.794330489
Short name T583
Test name
Test status
Simulation time 3094130827 ps
CPU time 8.21 seconds
Started Oct 15 11:51:05 AM UTC 24
Finished Oct 15 11:51:14 AM UTC 24
Peak memory 283568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794330489 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stretch.794330489
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_timeout.1333215971
Short name T592
Test name
Test status
Simulation time 4922100288 ps
CPU time 11.72 seconds
Started Oct 15 11:51:16 AM UTC 24
Finished Oct 15 11:51:28 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333215
971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_timeout.1333215971
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_target_tx_stretch_ctrl.2456145222
Short name T600
Test name
Test status
Simulation time 141135876 ps
CPU time 5.85 seconds
Started Oct 15 11:51:27 AM UTC 24
Finished Oct 15 11:51:34 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456145
222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.2456145222
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_alert_test.328823979
Short name T622
Test name
Test status
Simulation time 14993950 ps
CPU time 0.97 seconds
Started Oct 15 11:52:06 AM UTC 24
Finished Oct 15 11:52:09 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328823979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.328823979
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_error_intr.4072138920
Short name T604
Test name
Test status
Simulation time 199942438 ps
CPU time 10.74 seconds
Started Oct 15 11:51:39 AM UTC 24
Finished Oct 15 11:51:51 AM UTC 24
Peak memory 261092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072138920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.4072138920
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_fmt_empty.3021798789
Short name T610
Test name
Test status
Simulation time 837884651 ps
CPU time 21.29 seconds
Started Oct 15 11:51:36 AM UTC 24
Finished Oct 15 11:51:59 AM UTC 24
Peak memory 310412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021798789 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empty.3021798789
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_full.2900134309
Short name T638
Test name
Test status
Simulation time 7873515452 ps
CPU time 59.75 seconds
Started Oct 15 11:51:37 AM UTC 24
Finished Oct 15 11:52:39 AM UTC 24
Peak memory 359424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900134309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.2900134309
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_overflow.1469564768
Short name T637
Test name
Test status
Simulation time 8795573559 ps
CPU time 61.52 seconds
Started Oct 15 11:51:35 AM UTC 24
Finished Oct 15 11:52:38 AM UTC 24
Peak memory 699392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469564768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.1469564768
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_fmt.3641148981
Short name T136
Test name
Test status
Simulation time 296638876 ps
CPU time 1.33 seconds
Started Oct 15 11:51:36 AM UTC 24
Finished Oct 15 11:51:38 AM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641148981 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fmt.3641148981
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_rx.1662242226
Short name T140
Test name
Test status
Simulation time 279498136 ps
CPU time 9.88 seconds
Started Oct 15 11:51:36 AM UTC 24
Finished Oct 15 11:51:47 AM UTC 24
Peak memory 260940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662242226 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.1662242226
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_watermark.1857168068
Short name T651
Test name
Test status
Simulation time 3316464297 ps
CPU time 73.91 seconds
Started Oct 15 11:51:35 AM UTC 24
Finished Oct 15 11:52:51 AM UTC 24
Peak memory 990132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857168068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.1857168068
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_may_nack.3918366224
Short name T620
Test name
Test status
Simulation time 1312772726 ps
CPU time 6.79 seconds
Started Oct 15 11:52:00 AM UTC 24
Finished Oct 15 11:52:08 AM UTC 24
Peak memory 215644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918366224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.3918366224
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_override.3200638830
Short name T142
Test name
Test status
Simulation time 29469130 ps
CPU time 0.96 seconds
Started Oct 15 11:51:34 AM UTC 24
Finished Oct 15 11:51:36 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200638830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.3200638830
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_perf.3359772284
Short name T603
Test name
Test status
Simulation time 3368713134 ps
CPU time 11.71 seconds
Started Oct 15 11:51:37 AM UTC 24
Finished Oct 15 11:51:50 AM UTC 24
Peak memory 298056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359772284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.3359772284
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_perf_precise.2570813342
Short name T138
Test name
Test status
Simulation time 63873578 ps
CPU time 2.57 seconds
Started Oct 15 11:51:37 AM UTC 24
Finished Oct 15 11:51:41 AM UTC 24
Peak memory 240456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570813342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.2570813342
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_smoke.1801214632
Short name T660
Test name
Test status
Simulation time 16172984032 ps
CPU time 78.91 seconds
Started Oct 15 11:51:33 AM UTC 24
Finished Oct 15 11:52:54 AM UTC 24
Peak memory 365788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801214632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1801214632
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_stress_all.1547461211
Short name T243
Test name
Test status
Simulation time 48404390708 ps
CPU time 674.77 seconds
Started Oct 15 11:51:39 AM UTC 24
Finished Oct 15 12:03:01 PM UTC 24
Peak memory 1688524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547461211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.1547461211
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_host_stretch_timeout.3087651533
Short name T602
Test name
Test status
Simulation time 2123971042 ps
CPU time 11.06 seconds
Started Oct 15 11:51:37 AM UTC 24
Finished Oct 15 11:51:50 AM UTC 24
Peak memory 228076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087651533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3087651533
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_bad_addr.1822539916
Short name T618
Test name
Test status
Simulation time 1396374173 ps
CPU time 8.52 seconds
Started Oct 15 11:51:57 AM UTC 24
Finished Oct 15 11:52:06 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1822539916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_bad_ad
dr.1822539916
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_acq.1874429380
Short name T608
Test name
Test status
Simulation time 561091783 ps
CPU time 2.16 seconds
Started Oct 15 11:51:52 AM UTC 24
Finished Oct 15 11:51:56 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874429
380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_acq.1874429380
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_tx.463308966
Short name T609
Test name
Test status
Simulation time 414246137 ps
CPU time 1.73 seconds
Started Oct 15 11:51:55 AM UTC 24
Finished Oct 15 11:51:58 AM UTC 24
Peak memory 213508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4633089
66 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_tx.463308966
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_acq.2839556283
Short name T616
Test name
Test status
Simulation time 5680727018 ps
CPU time 3.68 seconds
Started Oct 15 11:52:01 AM UTC 24
Finished Oct 15 11:52:06 AM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839556
283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_watermar
ks_acq.2839556283
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_tx.1720833069
Short name T619
Test name
Test status
Simulation time 939688800 ps
CPU time 2.04 seconds
Started Oct 15 11:52:03 AM UTC 24
Finished Oct 15 11:52:06 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720833
069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_watermark
s_tx.1720833069
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_intr_smoke.2059603286
Short name T613
Test name
Test status
Simulation time 5978663481 ps
CPU time 14.03 seconds
Started Oct 15 11:51:48 AM UTC 24
Finished Oct 15 11:52:03 AM UTC 24
Peak memory 242568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205960
3286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_smoke.2059603286
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_intr_stress_wr.3763699095
Short name T615
Test name
Test status
Simulation time 3373518797 ps
CPU time 11.79 seconds
Started Oct 15 11:51:51 AM UTC 24
Finished Oct 15 11:52:05 AM UTC 24
Peak memory 578440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3763699095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_stres
s_wr.3763699095
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull.1413725000
Short name T626
Test name
Test status
Simulation time 1018226301 ps
CPU time 4.65 seconds
Started Oct 15 11:52:05 AM UTC 24
Finished Oct 15 11:52:11 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413725
000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_acqfull.1413725000
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull_addr.2409521117
Short name T628
Test name
Test status
Simulation time 432098709 ps
CPU time 4.37 seconds
Started Oct 15 11:52:06 AM UTC 24
Finished Oct 15 11:52:12 AM UTC 24
Peak memory 215804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409521
117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_acqfull_ad
dr.2409521117
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_nack_txstretch.1039258577
Short name T625
Test name
Test status
Simulation time 146504133 ps
CPU time 2.49 seconds
Started Oct 15 11:52:06 AM UTC 24
Finished Oct 15 11:52:10 AM UTC 24
Peak memory 232576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039258
577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_txstretch.1039258577
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_perf.1625586531
Short name T617
Test name
Test status
Simulation time 893498940 ps
CPU time 8.21 seconds
Started Oct 15 11:51:56 AM UTC 24
Finished Oct 15 11:52:06 AM UTC 24
Peak memory 227676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625586
531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_perf.1625586531
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_smbus_maxlen.3975779396
Short name T624
Test name
Test status
Simulation time 980127336 ps
CPU time 4.4 seconds
Started Oct 15 11:52:04 AM UTC 24
Finished Oct 15 11:52:10 AM UTC 24
Peak memory 215168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975779
396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smbus_maxlen.3975779396
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_smoke.2911137940
Short name T621
Test name
Test status
Simulation time 3302438911 ps
CPU time 27.29 seconds
Started Oct 15 11:51:40 AM UTC 24
Finished Oct 15 11:52:08 AM UTC 24
Peak memory 225744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911137940 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smoke.2911137940
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_stress_all.572006749
Short name T831
Test name
Test status
Simulation time 97404986327 ps
CPU time 395.9 seconds
Started Oct 15 11:51:56 AM UTC 24
Finished Oct 15 11:58:37 AM UTC 24
Peak memory 3029936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572006
749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_all.572006749
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_stress_rd.1830895649
Short name T611
Test name
Test status
Simulation time 702596206 ps
CPU time 16.95 seconds
Started Oct 15 11:51:42 AM UTC 24
Finished Oct 15 11:52:00 AM UTC 24
Peak memory 219628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830895649 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_rd.1830895649
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_stress_wr.2655252162
Short name T854
Test name
Test status
Simulation time 57597691269 ps
CPU time 444.57 seconds
Started Oct 15 11:51:40 AM UTC 24
Finished Oct 15 11:59:09 AM UTC 24
Peak memory 5153860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655252162 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_wr.2655252162
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_stretch.1893055452
Short name T631
Test name
Test status
Simulation time 4747938769 ps
CPU time 29.99 seconds
Started Oct 15 11:51:47 AM UTC 24
Finished Oct 15 11:52:18 AM UTC 24
Peak memory 369600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893055452 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stretch.1893055452
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_timeout.2301118907
Short name T612
Test name
Test status
Simulation time 1347704379 ps
CPU time 10 seconds
Started Oct 15 11:51:51 AM UTC 24
Finished Oct 15 11:52:03 AM UTC 24
Peak memory 232336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301118
907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_timeout.2301118907
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/15.i2c_target_tx_stretch_ctrl.2180743202
Short name T627
Test name
Test status
Simulation time 238716624 ps
CPU time 5.98 seconds
Started Oct 15 11:52:04 AM UTC 24
Finished Oct 15 11:52:11 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180743
202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.2180743202
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_alert_test.1123064138
Short name T655
Test name
Test status
Simulation time 16956808 ps
CPU time 1.02 seconds
Started Oct 15 11:52:51 AM UTC 24
Finished Oct 15 11:52:53 AM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123064138 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.1123064138
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_host_error_intr.3697784908
Short name T630
Test name
Test status
Simulation time 89819560 ps
CPU time 2.2 seconds
Started Oct 15 11:52:13 AM UTC 24
Finished Oct 15 11:52:16 AM UTC 24
Peak memory 226164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697784908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.3697784908
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_fmt_empty.1531055654
Short name T639
Test name
Test status
Simulation time 467923902 ps
CPU time 26.98 seconds
Started Oct 15 11:52:11 AM UTC 24
Finished Oct 15 11:52:39 AM UTC 24
Peak memory 297860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531055654 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empty.1531055654
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_full.2643921396
Short name T694
Test name
Test status
Simulation time 5040116320 ps
CPU time 96.56 seconds
Started Oct 15 11:52:11 AM UTC 24
Finished Oct 15 11:53:50 AM UTC 24
Peak memory 527624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643921396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2643921396
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_overflow.2805470872
Short name T664
Test name
Test status
Simulation time 3216595409 ps
CPU time 48.98 seconds
Started Oct 15 11:52:10 AM UTC 24
Finished Oct 15 11:53:00 AM UTC 24
Peak memory 607436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805470872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.2805470872
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_fmt.1915255252
Short name T629
Test name
Test status
Simulation time 1237490200 ps
CPU time 1.62 seconds
Started Oct 15 11:52:10 AM UTC 24
Finished Oct 15 11:52:12 AM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915255252 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fmt.1915255252
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_rx.2350007399
Short name T633
Test name
Test status
Simulation time 446677345 ps
CPU time 17.2 seconds
Started Oct 15 11:52:11 AM UTC 24
Finished Oct 15 11:52:29 AM UTC 24
Peak memory 267128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350007399 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.2350007399
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_watermark.2015863246
Short name T116
Test name
Test status
Simulation time 17279737273 ps
CPU time 82.52 seconds
Started Oct 15 11:52:09 AM UTC 24
Finished Oct 15 11:53:33 AM UTC 24
Peak memory 1012876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015863246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.2015863246
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_host_may_nack.1152921495
Short name T257
Test name
Test status
Simulation time 998296133 ps
CPU time 8.96 seconds
Started Oct 15 11:52:43 AM UTC 24
Finished Oct 15 11:52:53 AM UTC 24
Peak memory 215648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152921495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.1152921495
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_host_override.2393938929
Short name T623
Test name
Test status
Simulation time 45989041 ps
CPU time 1.01 seconds
Started Oct 15 11:52:07 AM UTC 24
Finished Oct 15 11:52:10 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393938929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.2393938929
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_host_perf.3154262106
Short name T641
Test name
Test status
Simulation time 3005535195 ps
CPU time 28.29 seconds
Started Oct 15 11:52:12 AM UTC 24
Finished Oct 15 11:52:41 AM UTC 24
Peak memory 236048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154262106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.3154262106
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_host_perf_precise.3921876251
Short name T632
Test name
Test status
Simulation time 863530817 ps
CPU time 10.23 seconds
Started Oct 15 11:52:12 AM UTC 24
Finished Oct 15 11:52:23 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921876251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.3921876251
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_host_smoke.1702533035
Short name T646
Test name
Test status
Simulation time 1885460020 ps
CPU time 38.82 seconds
Started Oct 15 11:52:07 AM UTC 24
Finished Oct 15 11:52:48 AM UTC 24
Peak memory 357376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702533035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.1702533035
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_host_stress_all.561920923
Short name T914
Test name
Test status
Simulation time 11935754626 ps
CPU time 553.87 seconds
Started Oct 15 11:52:17 AM UTC 24
Finished Oct 15 12:01:37 PM UTC 24
Peak memory 2548736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561920923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.561920923
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_host_stretch_timeout.536103049
Short name T654
Test name
Test status
Simulation time 721588450 ps
CPU time 38.24 seconds
Started Oct 15 11:52:13 AM UTC 24
Finished Oct 15 11:52:53 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536103049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.536103049
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_bad_addr.2177110541
Short name T650
Test name
Test status
Simulation time 785094880 ps
CPU time 6.77 seconds
Started Oct 15 11:52:42 AM UTC 24
Finished Oct 15 11:52:50 AM UTC 24
Peak memory 232492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2177110541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_ad
dr.2177110541
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_acq.3670098474
Short name T643
Test name
Test status
Simulation time 172239752 ps
CPU time 2.27 seconds
Started Oct 15 11:52:40 AM UTC 24
Finished Oct 15 11:52:43 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670098
474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_acq.3670098474
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_tx.230074728
Short name T642
Test name
Test status
Simulation time 147127518 ps
CPU time 1.67 seconds
Started Oct 15 11:52:40 AM UTC 24
Finished Oct 15 11:52:43 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300747
28 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_tx.230074728
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_acq.2364904233
Short name T649
Test name
Test status
Simulation time 566071979 ps
CPU time 4.15 seconds
Started Oct 15 11:52:44 AM UTC 24
Finished Oct 15 11:52:50 AM UTC 24
Peak memory 215788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364904
233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_watermar
ks_acq.2364904233
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_tx.3496179701
Short name T647
Test name
Test status
Simulation time 726434554 ps
CPU time 2.03 seconds
Started Oct 15 11:52:46 AM UTC 24
Finished Oct 15 11:52:49 AM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496179
701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_watermark
s_tx.3496179701
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_intr_smoke.468123289
Short name T640
Test name
Test status
Simulation time 817355342 ps
CPU time 7.85 seconds
Started Oct 15 11:52:32 AM UTC 24
Finished Oct 15 11:52:40 AM UTC 24
Peak memory 229728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468123
289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_smoke.468123289
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_intr_stress_wr.1609448992
Short name T670
Test name
Test status
Simulation time 19218828929 ps
CPU time 43.23 seconds
Started Oct 15 11:52:35 AM UTC 24
Finished Oct 15 11:53:19 AM UTC 24
Peak memory 793548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1609448992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_stres
s_wr.1609448992
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull.988652015
Short name T657
Test name
Test status
Simulation time 396667311 ps
CPU time 3.49 seconds
Started Oct 15 11:52:49 AM UTC 24
Finished Oct 15 11:52:53 AM UTC 24
Peak memory 226020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9886520
15 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_acqfull.988652015
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull_addr.2831794474
Short name T662
Test name
Test status
Simulation time 3553842012 ps
CPU time 4.9 seconds
Started Oct 15 11:52:50 AM UTC 24
Finished Oct 15 11:52:56 AM UTC 24
Peak memory 215552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831794
474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_acqfull_ad
dr.2831794474
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_nack_txstretch.4222762990
Short name T658
Test name
Test status
Simulation time 266991975 ps
CPU time 2.43 seconds
Started Oct 15 11:52:50 AM UTC 24
Finished Oct 15 11:52:53 AM UTC 24
Peak memory 232520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222762
990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_txstretch.4222762990
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_perf.3361536681
Short name T645
Test name
Test status
Simulation time 2134689986 ps
CPU time 4.56 seconds
Started Oct 15 11:52:41 AM UTC 24
Finished Oct 15 11:52:47 AM UTC 24
Peak memory 231976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361536
681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_perf.3361536681
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_smbus_maxlen.2686369000
Short name T653
Test name
Test status
Simulation time 1804190619 ps
CPU time 3.96 seconds
Started Oct 15 11:52:48 AM UTC 24
Finished Oct 15 11:52:53 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686369
000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smbus_maxlen.2686369000
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_smoke.2532925028
Short name T644
Test name
Test status
Simulation time 1104142278 ps
CPU time 24.01 seconds
Started Oct 15 11:52:19 AM UTC 24
Finished Oct 15 11:52:45 AM UTC 24
Peak memory 227804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532925028 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smoke.2532925028
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_stress_all.2162403967
Short name T689
Test name
Test status
Simulation time 5959936536 ps
CPU time 54.06 seconds
Started Oct 15 11:52:42 AM UTC 24
Finished Oct 15 11:53:38 AM UTC 24
Peak memory 291844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216240
3967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_all.2162403967
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_stress_rd.476164241
Short name T679
Test name
Test status
Simulation time 2462503753 ps
CPU time 62.29 seconds
Started Oct 15 11:52:24 AM UTC 24
Finished Oct 15 11:53:29 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476164241 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_rd.476164241
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_stress_wr.4062152810
Short name T1134
Test name
Test status
Simulation time 54787767645 ps
CPU time 963.13 seconds
Started Oct 15 11:52:19 AM UTC 24
Finished Oct 15 12:08:33 PM UTC 24
Peak memory 8785092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062152810 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_wr.4062152810
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_stretch.705157192
Short name T635
Test name
Test status
Simulation time 525362026 ps
CPU time 2.88 seconds
Started Oct 15 11:52:30 AM UTC 24
Finished Oct 15 11:52:33 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705157192 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stretch.705157192
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_timeout.246387552
Short name T648
Test name
Test status
Simulation time 1416855999 ps
CPU time 11.95 seconds
Started Oct 15 11:52:36 AM UTC 24
Finished Oct 15 11:52:49 AM UTC 24
Peak memory 232268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463875
52 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_timeout.246387552
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/16.i2c_target_tx_stretch_ctrl.1549708310
Short name T652
Test name
Test status
Simulation time 101429825 ps
CPU time 4.48 seconds
Started Oct 15 11:52:47 AM UTC 24
Finished Oct 15 11:52:52 AM UTC 24
Peak memory 215720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549708
310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.1549708310
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_alert_test.3765718417
Short name T687
Test name
Test status
Simulation time 15925572 ps
CPU time 0.99 seconds
Started Oct 15 11:53:34 AM UTC 24
Finished Oct 15 11:53:36 AM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765718417 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.3765718417
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_host_error_intr.1142389970
Short name T663
Test name
Test status
Simulation time 103534817 ps
CPU time 2.51 seconds
Started Oct 15 11:52:55 AM UTC 24
Finished Oct 15 11:52:58 AM UTC 24
Peak memory 225848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142389970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.1142389970
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_fmt_empty.2173508415
Short name T672
Test name
Test status
Simulation time 818589503 ps
CPU time 26.65 seconds
Started Oct 15 11:52:54 AM UTC 24
Finished Oct 15 11:53:22 AM UTC 24
Peak memory 300164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173508415 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empty.2173508415
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_full.4127569155
Short name T792
Test name
Test status
Simulation time 32553804649 ps
CPU time 247.81 seconds
Started Oct 15 11:52:55 AM UTC 24
Finished Oct 15 11:57:06 AM UTC 24
Peak memory 912384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127569155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.4127569155
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_overflow.3620366664
Short name T722
Test name
Test status
Simulation time 7203997893 ps
CPU time 96.22 seconds
Started Oct 15 11:52:53 AM UTC 24
Finished Oct 15 11:54:31 AM UTC 24
Peak memory 598920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620366664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.3620366664
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_fmt.999039284
Short name T661
Test name
Test status
Simulation time 270304682 ps
CPU time 1.31 seconds
Started Oct 15 11:52:53 AM UTC 24
Finished Oct 15 11:52:55 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999039284 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fmt.999039284
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_rx.1642771920
Short name T665
Test name
Test status
Simulation time 1433391584 ps
CPU time 5.11 seconds
Started Oct 15 11:52:54 AM UTC 24
Finished Oct 15 11:53:01 AM UTC 24
Peak memory 215656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642771920 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.1642771920
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_watermark.2148450935
Short name T754
Test name
Test status
Simulation time 26594362992 ps
CPU time 180.07 seconds
Started Oct 15 11:52:53 AM UTC 24
Finished Oct 15 11:55:56 AM UTC 24
Peak memory 943092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148450935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2148450935
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_host_may_nack.4033642742
Short name T258
Test name
Test status
Simulation time 2668093953 ps
CPU time 15.72 seconds
Started Oct 15 11:53:24 AM UTC 24
Finished Oct 15 11:53:41 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033642742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.4033642742
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_host_mode_toggle.643394487
Short name T82
Test name
Test status
Simulation time 238929970 ps
CPU time 3.21 seconds
Started Oct 15 11:53:24 AM UTC 24
Finished Oct 15 11:53:28 AM UTC 24
Peak memory 242584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643394487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.643394487
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_host_override.801271113
Short name T656
Test name
Test status
Simulation time 45323772 ps
CPU time 1.02 seconds
Started Oct 15 11:52:51 AM UTC 24
Finished Oct 15 11:52:53 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801271113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.801271113
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_host_perf_precise.3534045839
Short name T676
Test name
Test status
Simulation time 764220994 ps
CPU time 28.01 seconds
Started Oct 15 11:52:55 AM UTC 24
Finished Oct 15 11:53:24 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534045839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.3534045839
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_host_smoke.777416197
Short name T728
Test name
Test status
Simulation time 8557734432 ps
CPU time 112.95 seconds
Started Oct 15 11:52:51 AM UTC 24
Finished Oct 15 11:54:46 AM UTC 24
Peak memory 428996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777416197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.777416197
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_host_stretch_timeout.3983262228
Short name T667
Test name
Test status
Simulation time 1610803600 ps
CPU time 16.63 seconds
Started Oct 15 11:52:55 AM UTC 24
Finished Oct 15 11:53:12 AM UTC 24
Peak memory 232220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983262228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.3983262228
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_bad_addr.3347928620
Short name T683
Test name
Test status
Simulation time 1079912922 ps
CPU time 10.11 seconds
Started Oct 15 11:53:23 AM UTC 24
Finished Oct 15 11:53:34 AM UTC 24
Peak memory 232168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3347928620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_ad
dr.3347928620
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_acq.853218767
Short name T671
Test name
Test status
Simulation time 174983351 ps
CPU time 2.18 seconds
Started Oct 15 11:53:19 AM UTC 24
Finished Oct 15 11:53:22 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8532187
67 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_acq.853218767
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_tx.1334594185
Short name T674
Test name
Test status
Simulation time 199944182 ps
CPU time 2.27 seconds
Started Oct 15 11:53:20 AM UTC 24
Finished Oct 15 11:53:23 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334594
185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_tx.1334594185
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_acq.4193036270
Short name T680
Test name
Test status
Simulation time 2235025059 ps
CPU time 3.44 seconds
Started Oct 15 11:53:25 AM UTC 24
Finished Oct 15 11:53:30 AM UTC 24
Peak memory 215652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193036
270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_watermar
ks_acq.4193036270
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_tx.4220267352
Short name T681
Test name
Test status
Simulation time 598601619 ps
CPU time 2.77 seconds
Started Oct 15 11:53:26 AM UTC 24
Finished Oct 15 11:53:30 AM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220267
352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_watermark
s_tx.4220267352
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_intr_smoke.3704229014
Short name T668
Test name
Test status
Simulation time 972228433 ps
CPU time 6.35 seconds
Started Oct 15 11:53:10 AM UTC 24
Finished Oct 15 11:53:18 AM UTC 24
Peak memory 230060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370422
9014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_smoke.3704229014
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_intr_stress_wr.2341438249
Short name T675
Test name
Test status
Simulation time 2765390147 ps
CPU time 8.59 seconds
Started Oct 15 11:53:13 AM UTC 24
Finished Oct 15 11:53:23 AM UTC 24
Peak memory 215588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2341438249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_stres
s_wr.2341438249
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull.13233510
Short name T686
Test name
Test status
Simulation time 1032028170 ps
CPU time 4.31 seconds
Started Oct 15 11:53:29 AM UTC 24
Finished Oct 15 11:53:35 AM UTC 24
Peak memory 225652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323351
0 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_acqfull.13233510
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull_addr.1499118453
Short name T688
Test name
Test status
Simulation time 976604237 ps
CPU time 5.41 seconds
Started Oct 15 11:53:30 AM UTC 24
Finished Oct 15 11:53:37 AM UTC 24
Peak memory 215412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499118
453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_acqfull_ad
dr.1499118453
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_perf.120372620
Short name T678
Test name
Test status
Simulation time 664606455 ps
CPU time 5.15 seconds
Started Oct 15 11:53:21 AM UTC 24
Finished Oct 15 11:53:27 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203726
20 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_perf.120372620
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_smbus_maxlen.1449695368
Short name T684
Test name
Test status
Simulation time 508919045 ps
CPU time 3.85 seconds
Started Oct 15 11:53:29 AM UTC 24
Finished Oct 15 11:53:35 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449695
368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smbus_maxlen.1449695368
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_smoke.133503821
Short name T614
Test name
Test status
Simulation time 828558983 ps
CPU time 16.14 seconds
Started Oct 15 11:52:57 AM UTC 24
Finished Oct 15 11:53:14 AM UTC 24
Peak memory 226216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133503821 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smoke.133503821
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_stress_all.655393015
Short name T721
Test name
Test status
Simulation time 69445861192 ps
CPU time 66.73 seconds
Started Oct 15 11:53:23 AM UTC 24
Finished Oct 15 11:54:31 AM UTC 24
Peak memory 1043784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655393
015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_all.655393015
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_stress_rd.1119269321
Short name T666
Test name
Test status
Simulation time 345374120 ps
CPU time 6.99 seconds
Started Oct 15 11:53:01 AM UTC 24
Finished Oct 15 11:53:09 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119269321 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_rd.1119269321
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_stress_wr.373064852
Short name T1115
Test name
Test status
Simulation time 53873359590 ps
CPU time 901.63 seconds
Started Oct 15 11:52:59 AM UTC 24
Finished Oct 15 12:08:10 PM UTC 24
Peak memory 8707016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373064852 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_wr.373064852
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_stretch.2055980047
Short name T607
Test name
Test status
Simulation time 1667989759 ps
CPU time 11.6 seconds
Started Oct 15 11:53:01 AM UTC 24
Finished Oct 15 11:53:14 AM UTC 24
Peak memory 251008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055980047 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stretch.2055980047
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_timeout.1359804157
Short name T677
Test name
Test status
Simulation time 1365979022 ps
CPU time 10.26 seconds
Started Oct 15 11:53:14 AM UTC 24
Finished Oct 15 11:53:26 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359804
157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_timeout.1359804157
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/17.i2c_target_tx_stretch_ctrl.4045697081
Short name T682
Test name
Test status
Simulation time 235042709 ps
CPU time 5.04 seconds
Started Oct 15 11:53:27 AM UTC 24
Finished Oct 15 11:53:33 AM UTC 24
Peak memory 215852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045697
081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.4045697081
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_alert_test.3348102375
Short name T716
Test name
Test status
Simulation time 15559346 ps
CPU time 1 seconds
Started Oct 15 11:54:23 AM UTC 24
Finished Oct 15 11:54:25 AM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348102375 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3348102375
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_host_error_intr.3801547045
Short name T691
Test name
Test status
Simulation time 332455825 ps
CPU time 1.9 seconds
Started Oct 15 11:53:42 AM UTC 24
Finished Oct 15 11:53:45 AM UTC 24
Peak memory 225392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801547045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.3801547045
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_fmt_empty.1470622297
Short name T695
Test name
Test status
Simulation time 2848710083 ps
CPU time 18.37 seconds
Started Oct 15 11:53:37 AM UTC 24
Finished Oct 15 11:53:57 AM UTC 24
Peak memory 269260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470622297 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empty.1470622297
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_full.777007438
Short name T735
Test name
Test status
Simulation time 3383400711 ps
CPU time 88.09 seconds
Started Oct 15 11:53:38 AM UTC 24
Finished Oct 15 11:55:08 AM UTC 24
Peak memory 225884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777007438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.777007438
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_overflow.2700324019
Short name T760
Test name
Test status
Simulation time 9119848893 ps
CPU time 155.04 seconds
Started Oct 15 11:53:36 AM UTC 24
Finished Oct 15 11:56:14 AM UTC 24
Peak memory 795580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700324019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2700324019
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_rx.3625570101
Short name T692
Test name
Test status
Simulation time 344325234 ps
CPU time 6.2 seconds
Started Oct 15 11:53:38 AM UTC 24
Finished Oct 15 11:53:45 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625570101 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.3625570101
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_watermark.3572997049
Short name T730
Test name
Test status
Simulation time 13399518032 ps
CPU time 75.43 seconds
Started Oct 15 11:53:36 AM UTC 24
Finished Oct 15 11:54:53 AM UTC 24
Peak memory 1002364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572997049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3572997049
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_host_may_nack.348176872
Short name T713
Test name
Test status
Simulation time 536479688 ps
CPU time 7.52 seconds
Started Oct 15 11:54:14 AM UTC 24
Finished Oct 15 11:54:22 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348176872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.348176872
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_host_override.3846578996
Short name T143
Test name
Test status
Simulation time 21218843 ps
CPU time 1.04 seconds
Started Oct 15 11:53:35 AM UTC 24
Finished Oct 15 11:53:37 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846578996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.3846578996
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_host_perf.4275076970
Short name T771
Test name
Test status
Simulation time 5223914730 ps
CPU time 176.07 seconds
Started Oct 15 11:53:39 AM UTC 24
Finished Oct 15 11:56:38 AM UTC 24
Peak memory 1432332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275076970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.4275076970
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_host_perf_precise.3637112246
Short name T693
Test name
Test status
Simulation time 166856408 ps
CPU time 5.06 seconds
Started Oct 15 11:53:39 AM UTC 24
Finished Oct 15 11:53:45 AM UTC 24
Peak memory 240428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637112246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.3637112246
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_host_smoke.2578862490
Short name T701
Test name
Test status
Simulation time 1435194074 ps
CPU time 31.96 seconds
Started Oct 15 11:53:35 AM UTC 24
Finished Oct 15 11:54:08 AM UTC 24
Peak memory 330696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578862490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2578862490
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_host_stretch_timeout.1314533138
Short name T698
Test name
Test status
Simulation time 1168850420 ps
CPU time 24.63 seconds
Started Oct 15 11:53:40 AM UTC 24
Finished Oct 15 11:54:06 AM UTC 24
Peak memory 225776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314533138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.1314533138
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_bad_addr.3735453048
Short name T712
Test name
Test status
Simulation time 930462992 ps
CPU time 8.86 seconds
Started Oct 15 11:54:11 AM UTC 24
Finished Oct 15 11:54:21 AM UTC 24
Peak memory 226028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3735453048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_bad_ad
dr.3735453048
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_acq.622173329
Short name T705
Test name
Test status
Simulation time 231367996 ps
CPU time 2.46 seconds
Started Oct 15 11:54:09 AM UTC 24
Finished Oct 15 11:54:13 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6221733
29 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_acq.622173329
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_tx.1707016504
Short name T704
Test name
Test status
Simulation time 195267200 ps
CPU time 1.61 seconds
Started Oct 15 11:54:09 AM UTC 24
Finished Oct 15 11:54:12 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707016
504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_tx.1707016504
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_acq.2803059331
Short name T711
Test name
Test status
Simulation time 608683547 ps
CPU time 2.86 seconds
Started Oct 15 11:54:16 AM UTC 24
Finished Oct 15 11:54:20 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803059
331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_watermar
ks_acq.2803059331
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_tx.3438167122
Short name T710
Test name
Test status
Simulation time 430540437 ps
CPU time 1.49 seconds
Started Oct 15 11:54:17 AM UTC 24
Finished Oct 15 11:54:19 AM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438167
122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_watermark
s_tx.3438167122
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_hrst.4020600850
Short name T707
Test name
Test status
Simulation time 888498494 ps
CPU time 2.88 seconds
Started Oct 15 11:54:12 AM UTC 24
Finished Oct 15 11:54:16 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020600
850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_hrst.4020600850
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_intr_smoke.2337471217
Short name T703
Test name
Test status
Simulation time 4147984402 ps
CPU time 10.17 seconds
Started Oct 15 11:53:58 AM UTC 24
Finished Oct 15 11:54:09 AM UTC 24
Peak memory 230124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233747
1217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_smoke.2337471217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_intr_stress_wr.53994787
Short name T732
Test name
Test status
Simulation time 6592302638 ps
CPU time 60.31 seconds
Started Oct 15 11:54:00 AM UTC 24
Finished Oct 15 11:55:02 AM UTC 24
Peak memory 1823688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=53994787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.53994787
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull.3253975660
Short name T717
Test name
Test status
Simulation time 558687559 ps
CPU time 5.46 seconds
Started Oct 15 11:54:20 AM UTC 24
Finished Oct 15 11:54:27 AM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253975
660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_acqfull.3253975660
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull_addr.2416225359
Short name T51
Test name
Test status
Simulation time 3308610788 ps
CPU time 4.25 seconds
Started Oct 15 11:54:20 AM UTC 24
Finished Oct 15 11:54:25 AM UTC 24
Peak memory 215680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416225
359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_acqfull_ad
dr.2416225359
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_nack_txstretch.1644751116
Short name T714
Test name
Test status
Simulation time 259915570 ps
CPU time 1.68 seconds
Started Oct 15 11:54:21 AM UTC 24
Finished Oct 15 11:54:24 AM UTC 24
Peak memory 231192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644751
116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_txstretch.1644751116
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_perf.1370625027
Short name T709
Test name
Test status
Simulation time 2393413073 ps
CPU time 6.56 seconds
Started Oct 15 11:54:09 AM UTC 24
Finished Oct 15 11:54:17 AM UTC 24
Peak memory 225808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370625
027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_perf.1370625027
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_smbus_maxlen.1651399574
Short name T715
Test name
Test status
Simulation time 601219030 ps
CPU time 5.09 seconds
Started Oct 15 11:54:18 AM UTC 24
Finished Oct 15 11:54:24 AM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651399
574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smbus_maxlen.1651399574
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_smoke.475894391
Short name T699
Test name
Test status
Simulation time 1077965413 ps
CPU time 20.79 seconds
Started Oct 15 11:53:46 AM UTC 24
Finished Oct 15 11:54:08 AM UTC 24
Peak memory 225972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475894391 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smoke.475894391
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_stress_rd.396616389
Short name T702
Test name
Test status
Simulation time 730697845 ps
CPU time 20.05 seconds
Started Oct 15 11:53:47 AM UTC 24
Finished Oct 15 11:54:08 AM UTC 24
Peak memory 231900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396616389 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_rd.396616389
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_stress_wr.3824002447
Short name T700
Test name
Test status
Simulation time 32065429409 ps
CPU time 19.89 seconds
Started Oct 15 11:53:47 AM UTC 24
Finished Oct 15 11:54:08 AM UTC 24
Peak memory 353204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824002447 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_wr.3824002447
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_stretch.3656616046
Short name T697
Test name
Test status
Simulation time 3070535106 ps
CPU time 11.87 seconds
Started Oct 15 11:53:50 AM UTC 24
Finished Oct 15 11:54:03 AM UTC 24
Peak memory 225780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656616046 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stretch.3656616046
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_timeout.263320655
Short name T708
Test name
Test status
Simulation time 3958804791 ps
CPU time 10.4 seconds
Started Oct 15 11:54:04 AM UTC 24
Finished Oct 15 11:54:16 AM UTC 24
Peak memory 232712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633206
55 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_timeout.263320655
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/18.i2c_target_tx_stretch_ctrl.4012685398
Short name T719
Test name
Test status
Simulation time 310649552 ps
CPU time 10.47 seconds
Started Oct 15 11:54:17 AM UTC 24
Finished Oct 15 11:54:28 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012685
398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.4012685398
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_alert_test.4205404160
Short name T746
Test name
Test status
Simulation time 36000411 ps
CPU time 0.97 seconds
Started Oct 15 11:55:33 AM UTC 24
Finished Oct 15 11:55:35 AM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205404160 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.4205404160
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_host_error_intr.2385748289
Short name T727
Test name
Test status
Simulation time 754838303 ps
CPU time 3.91 seconds
Started Oct 15 11:54:36 AM UTC 24
Finished Oct 15 11:54:41 AM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385748289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.2385748289
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_fmt_empty.903019320
Short name T725
Test name
Test status
Simulation time 337587535 ps
CPU time 8.52 seconds
Started Oct 15 11:54:29 AM UTC 24
Finished Oct 15 11:54:39 AM UTC 24
Peak memory 285572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903019320 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empty.903019320
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_full.2088283076
Short name T785
Test name
Test status
Simulation time 4105620012 ps
CPU time 141.06 seconds
Started Oct 15 11:54:32 AM UTC 24
Finished Oct 15 11:56:56 AM UTC 24
Peak memory 605444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088283076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2088283076
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_overflow.2315445780
Short name T758
Test name
Test status
Simulation time 5570383484 ps
CPU time 97.54 seconds
Started Oct 15 11:54:27 AM UTC 24
Finished Oct 15 11:56:06 AM UTC 24
Peak memory 924680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315445780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.2315445780
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_fmt.259043701
Short name T720
Test name
Test status
Simulation time 750787253 ps
CPU time 1.87 seconds
Started Oct 15 11:54:28 AM UTC 24
Finished Oct 15 11:54:31 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259043701 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fmt.259043701
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_rx.2853567666
Short name T723
Test name
Test status
Simulation time 126782649 ps
CPU time 4.77 seconds
Started Oct 15 11:54:29 AM UTC 24
Finished Oct 15 11:54:35 AM UTC 24
Peak memory 234372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853567666 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.2853567666
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_watermark.3418574134
Short name T752
Test name
Test status
Simulation time 11077294423 ps
CPU time 86.25 seconds
Started Oct 15 11:54:27 AM UTC 24
Finished Oct 15 11:55:55 AM UTC 24
Peak memory 953292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418574134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3418574134
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_host_mode_toggle.2933481449
Short name T742
Test name
Test status
Simulation time 280190285 ps
CPU time 5.35 seconds
Started Oct 15 11:55:22 AM UTC 24
Finished Oct 15 11:55:28 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933481449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.2933481449
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_host_override.662985214
Short name T718
Test name
Test status
Simulation time 28357418 ps
CPU time 1.16 seconds
Started Oct 15 11:54:26 AM UTC 24
Finished Oct 15 11:54:28 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662985214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.662985214
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_host_perf.3262463461
Short name T863
Test name
Test status
Simulation time 75929129171 ps
CPU time 300.36 seconds
Started Oct 15 11:54:32 AM UTC 24
Finished Oct 15 11:59:37 AM UTC 24
Peak memory 1598520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262463461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.3262463461
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_host_perf_precise.3228113444
Short name T724
Test name
Test status
Simulation time 313890926 ps
CPU time 1.79 seconds
Started Oct 15 11:54:32 AM UTC 24
Finished Oct 15 11:54:35 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228113444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.3228113444
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_host_smoke.2835433537
Short name T729
Test name
Test status
Simulation time 5428713913 ps
CPU time 24.99 seconds
Started Oct 15 11:54:25 AM UTC 24
Finished Oct 15 11:54:51 AM UTC 24
Peak memory 379856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835433537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2835433537
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_host_stress_all.1965132463
Short name T244
Test name
Test status
Simulation time 6560003333 ps
CPU time 415.84 seconds
Started Oct 15 11:54:39 AM UTC 24
Finished Oct 15 12:01:40 PM UTC 24
Peak memory 800076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965132463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.1965132463
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_host_stretch_timeout.3331049070
Short name T731
Test name
Test status
Simulation time 3994129670 ps
CPU time 18.92 seconds
Started Oct 15 11:54:36 AM UTC 24
Finished Oct 15 11:54:56 AM UTC 24
Peak memory 242644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331049070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3331049070
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_bad_addr.3839846858
Short name T706
Test name
Test status
Simulation time 1388318138 ps
CPU time 9.95 seconds
Started Oct 15 11:55:15 AM UTC 24
Finished Oct 15 11:55:27 AM UTC 24
Peak memory 232264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3839846858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_ad
dr.3839846858
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_acq.3019809013
Short name T736
Test name
Test status
Simulation time 222195642 ps
CPU time 2.4 seconds
Started Oct 15 11:55:09 AM UTC 24
Finished Oct 15 11:55:13 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019809
013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_acq.3019809013
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_tx.2684166329
Short name T737
Test name
Test status
Simulation time 198424331 ps
CPU time 2.39 seconds
Started Oct 15 11:55:10 AM UTC 24
Finished Oct 15 11:55:14 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684166
329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_tx.2684166329
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_acq.2362976191
Short name T741
Test name
Test status
Simulation time 332992534 ps
CPU time 2.42 seconds
Started Oct 15 11:55:24 AM UTC 24
Finished Oct 15 11:55:27 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362976
191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_watermar
ks_acq.2362976191
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_tx.3352290100
Short name T740
Test name
Test status
Simulation time 188302076 ps
CPU time 2.07 seconds
Started Oct 15 11:55:24 AM UTC 24
Finished Oct 15 11:55:27 AM UTC 24
Peak memory 215180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352290
100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_watermark
s_tx.3352290100
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_hrst.2931191154
Short name T690
Test name
Test status
Simulation time 1260712625 ps
CPU time 2.87 seconds
Started Oct 15 11:55:19 AM UTC 24
Finished Oct 15 11:55:23 AM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931191
154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_hrst.2931191154
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_intr_smoke.3549219055
Short name T734
Test name
Test status
Simulation time 2896451150 ps
CPU time 7.2 seconds
Started Oct 15 11:54:57 AM UTC 24
Finished Oct 15 11:55:05 AM UTC 24
Peak memory 230116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354921
9055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_smoke.3549219055
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_intr_stress_wr.4132473369
Short name T777
Test name
Test status
Simulation time 32240674553 ps
CPU time 99.11 seconds
Started Oct 15 11:55:03 AM UTC 24
Finished Oct 15 11:56:44 AM UTC 24
Peak memory 1921996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4132473369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_stres
s_wr.4132473369
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull.51823064
Short name T745
Test name
Test status
Simulation time 549007463 ps
CPU time 4.75 seconds
Started Oct 15 11:55:28 AM UTC 24
Finished Oct 15 11:55:34 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5182306
4 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_acqfull.51823064
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull_addr.2957126098
Short name T747
Test name
Test status
Simulation time 621559113 ps
CPU time 5.09 seconds
Started Oct 15 11:55:29 AM UTC 24
Finished Oct 15 11:55:36 AM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957126
098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_acqfull_ad
dr.2957126098
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_nack_txstretch.3380978594
Short name T748
Test name
Test status
Simulation time 139331026 ps
CPU time 1.63 seconds
Started Oct 15 11:55:33 AM UTC 24
Finished Oct 15 11:55:36 AM UTC 24
Peak memory 231212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380978
594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_txstretch.3380978594
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_perf.617919501
Short name T669
Test name
Test status
Simulation time 6015090932 ps
CPU time 7.33 seconds
Started Oct 15 11:55:13 AM UTC 24
Finished Oct 15 11:55:22 AM UTC 24
Peak memory 226096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6179195
01 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_perf.617919501
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_smbus_maxlen.88210998
Short name T743
Test name
Test status
Simulation time 1000508604 ps
CPU time 3.36 seconds
Started Oct 15 11:55:28 AM UTC 24
Finished Oct 15 11:55:33 AM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8821099
8 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smbus_maxlen.88210998
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_smoke.3322220686
Short name T685
Test name
Test status
Simulation time 3832897896 ps
CPU time 34.1 seconds
Started Oct 15 11:54:42 AM UTC 24
Finished Oct 15 11:55:18 AM UTC 24
Peak memory 226076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322220686 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smoke.3322220686
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_stress_all.2620035920
Short name T761
Test name
Test status
Simulation time 16316146979 ps
CPU time 59.67 seconds
Started Oct 15 11:55:14 AM UTC 24
Finished Oct 15 11:56:16 AM UTC 24
Peak memory 330704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262003
5920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_all.2620035920
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_stress_rd.2312678468
Short name T733
Test name
Test status
Simulation time 794175995 ps
CPU time 11.23 seconds
Started Oct 15 11:54:52 AM UTC 24
Finished Oct 15 11:55:04 AM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312678468 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_rd.2312678468
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_stress_wr.4232634837
Short name T750
Test name
Test status
Simulation time 34800805995 ps
CPU time 55.74 seconds
Started Oct 15 11:54:47 AM UTC 24
Finished Oct 15 11:55:44 AM UTC 24
Peak memory 912248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232634837 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_wr.4232634837
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_stretch.1015586095
Short name T673
Test name
Test status
Simulation time 2947519037 ps
CPU time 27.4 seconds
Started Oct 15 11:54:54 AM UTC 24
Finished Oct 15 11:55:22 AM UTC 24
Peak memory 324872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015586095 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stretch.1015586095
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_timeout.1658188738
Short name T738
Test name
Test status
Simulation time 2788354583 ps
CPU time 8.71 seconds
Started Oct 15 11:55:05 AM UTC 24
Finished Oct 15 11:55:15 AM UTC 24
Peak memory 232172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658188
738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_timeout.1658188738
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/19.i2c_target_tx_stretch_ctrl.4008681518
Short name T744
Test name
Test status
Simulation time 102505338 ps
CPU time 4.64 seconds
Started Oct 15 11:55:28 AM UTC 24
Finished Oct 15 11:55:34 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008681
518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.4008681518
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_alert_test.4075884741
Short name T45
Test name
Test status
Simulation time 44710823 ps
CPU time 0.98 seconds
Started Oct 15 11:41:39 AM UTC 24
Finished Oct 15 11:41:41 AM UTC 24
Peak memory 213392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075884741 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.4075884741
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_error_intr.4097296515
Short name T19
Test name
Test status
Simulation time 751192656 ps
CPU time 3.24 seconds
Started Oct 15 11:41:19 AM UTC 24
Finished Oct 15 11:41:23 AM UTC 24
Peak memory 225784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097296515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.4097296515
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_fmt_empty.4171570802
Short name T254
Test name
Test status
Simulation time 519592841 ps
CPU time 5.56 seconds
Started Oct 15 11:41:17 AM UTC 24
Finished Oct 15 11:41:23 AM UTC 24
Peak memory 256900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171570802 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty.4171570802
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_full.2513081903
Short name T29
Test name
Test status
Simulation time 3125204793 ps
CPU time 200.64 seconds
Started Oct 15 11:41:18 AM UTC 24
Finished Oct 15 11:44:42 AM UTC 24
Peak memory 625620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513081903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.2513081903
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_overflow.3117490277
Short name T100
Test name
Test status
Simulation time 2088144273 ps
CPU time 57.92 seconds
Started Oct 15 11:41:15 AM UTC 24
Finished Oct 15 11:42:15 AM UTC 24
Peak memory 675024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117490277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3117490277
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_fmt.2054280598
Short name T39
Test name
Test status
Simulation time 172184454 ps
CPU time 1.66 seconds
Started Oct 15 11:41:17 AM UTC 24
Finished Oct 15 11:41:19 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054280598 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt.2054280598
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_watermark.3300304245
Short name T390
Test name
Test status
Simulation time 17622563717 ps
CPU time 213.52 seconds
Started Oct 15 11:41:15 AM UTC 24
Finished Oct 15 11:44:52 AM UTC 24
Peak memory 1252276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300304245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.3300304245
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_may_nack.849735681
Short name T13
Test name
Test status
Simulation time 992351116 ps
CPU time 10.43 seconds
Started Oct 15 11:41:31 AM UTC 24
Finished Oct 15 11:41:43 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849735681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.849735681
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_mode_toggle.3229760093
Short name T25
Test name
Test status
Simulation time 157255831 ps
CPU time 7.36 seconds
Started Oct 15 11:41:30 AM UTC 24
Finished Oct 15 11:41:39 AM UTC 24
Peak memory 226144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229760093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.3229760093
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_override.2415726236
Short name T99
Test name
Test status
Simulation time 89790500 ps
CPU time 0.92 seconds
Started Oct 15 11:41:14 AM UTC 24
Finished Oct 15 11:41:16 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415726236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.2415726236
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_perf_precise.1534141892
Short name T226
Test name
Test status
Simulation time 181941749 ps
CPU time 8.86 seconds
Started Oct 15 11:41:19 AM UTC 24
Finished Oct 15 11:41:29 AM UTC 24
Peak memory 246604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534141892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.1534141892
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_smoke.3367877185
Short name T188
Test name
Test status
Simulation time 1407503133 ps
CPU time 26.75 seconds
Started Oct 15 11:41:14 AM UTC 24
Finished Oct 15 11:41:42 AM UTC 24
Peak memory 379720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367877185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.3367877185
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_host_stretch_timeout.2999921083
Short name T292
Test name
Test status
Simulation time 1330695594 ps
CPU time 29.45 seconds
Started Oct 15 11:41:19 AM UTC 24
Finished Oct 15 11:41:50 AM UTC 24
Peak memory 242560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999921083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.2999921083
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_sec_cm.2663035128
Short name T93
Test name
Test status
Simulation time 36995966 ps
CPU time 1.36 seconds
Started Oct 15 11:41:38 AM UTC 24
Finished Oct 15 11:41:40 AM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663035128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2663035128
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_bad_addr.1463575234
Short name T69
Test name
Test status
Simulation time 3903445117 ps
CPU time 8.38 seconds
Started Oct 15 11:41:28 AM UTC 24
Finished Oct 15 11:41:38 AM UTC 24
Peak memory 228080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1463575234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.1463575234
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_acq.1168065451
Short name T87
Test name
Test status
Simulation time 228353376 ps
CPU time 2.61 seconds
Started Oct 15 11:41:24 AM UTC 24
Finished Oct 15 11:41:27 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168065
451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_acq.1168065451
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_tx.2879360912
Short name T302
Test name
Test status
Simulation time 659363342 ps
CPU time 2.08 seconds
Started Oct 15 11:41:26 AM UTC 24
Finished Oct 15 11:41:29 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879360
912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_tx.2879360912
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_acq.983737173
Short name T95
Test name
Test status
Simulation time 904584968 ps
CPU time 4.8 seconds
Started Oct 15 11:41:33 AM UTC 24
Finished Oct 15 11:41:38 AM UTC 24
Peak memory 215460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9837371
73 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_watermarks
_acq.983737173
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_tx.3781708727
Short name T94
Test name
Test status
Simulation time 692465086 ps
CPU time 2.66 seconds
Started Oct 15 11:41:33 AM UTC 24
Finished Oct 15 11:41:36 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781708
727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_watermarks
_tx.3781708727
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_intr_smoke.1639933529
Short name T92
Test name
Test status
Simulation time 858383783 ps
CPU time 8.98 seconds
Started Oct 15 11:41:23 AM UTC 24
Finished Oct 15 11:41:33 AM UTC 24
Peak memory 229864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163993
3529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_smoke.1639933529
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_intr_stress_wr.945471898
Short name T55
Test name
Test status
Simulation time 19144452356 ps
CPU time 99.38 seconds
Started Oct 15 11:41:23 AM UTC 24
Finished Oct 15 11:43:04 AM UTC 24
Peak memory 1596360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=945471898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.945471898
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull.2302608294
Short name T90
Test name
Test status
Simulation time 7697376507 ps
CPU time 5.08 seconds
Started Oct 15 11:41:34 AM UTC 24
Finished Oct 15 11:41:40 AM UTC 24
Peak memory 225700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302608
294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_acqfull.2302608294
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull_addr.1384867999
Short name T71
Test name
Test status
Simulation time 484998376 ps
CPU time 4.91 seconds
Started Oct 15 11:41:37 AM UTC 24
Finished Oct 15 11:41:43 AM UTC 24
Peak memory 215408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384867
999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.1384867999
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_perf.3431609431
Short name T91
Test name
Test status
Simulation time 4908347318 ps
CPU time 5.52 seconds
Started Oct 15 11:41:26 AM UTC 24
Finished Oct 15 11:41:33 AM UTC 24
Peak memory 232476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431609
431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_perf.3431609431
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_smbus_maxlen.408905815
Short name T186
Test name
Test status
Simulation time 465661545 ps
CPU time 4.35 seconds
Started Oct 15 11:41:34 AM UTC 24
Finished Oct 15 11:41:39 AM UTC 24
Peak memory 215176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089058
15 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smbus_maxlen.408905815
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_smoke.450679298
Short name T306
Test name
Test status
Simulation time 5768400533 ps
CPU time 27.55 seconds
Started Oct 15 11:41:20 AM UTC 24
Finished Oct 15 11:41:49 AM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450679298 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smoke.450679298
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_stress_all.785491365
Short name T154
Test name
Test status
Simulation time 8068555740 ps
CPU time 50.35 seconds
Started Oct 15 11:41:26 AM UTC 24
Finished Oct 15 11:42:18 AM UTC 24
Peak memory 324552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785491
365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_all.785491365
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_stress_wr.1266962931
Short name T194
Test name
Test status
Simulation time 53941419821 ps
CPU time 367.52 seconds
Started Oct 15 11:41:20 AM UTC 24
Finished Oct 15 11:47:32 AM UTC 24
Peak memory 4459384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266962931 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_wr.1266962931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_stretch.2636783263
Short name T305
Test name
Test status
Simulation time 2970975518 ps
CPU time 2.53 seconds
Started Oct 15 11:41:22 AM UTC 24
Finished Oct 15 11:41:25 AM UTC 24
Peak memory 232224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636783263 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stretch.2636783263
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/2.i2c_target_timeout.2780551912
Short name T79
Test name
Test status
Simulation time 3093186057 ps
CPU time 14.07 seconds
Started Oct 15 11:41:23 AM UTC 24
Finished Oct 15 11:41:38 AM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780551
912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_timeout.2780551912
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/2.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_alert_test.2197332738
Short name T779
Test name
Test status
Simulation time 15480239 ps
CPU time 1.01 seconds
Started Oct 15 11:56:45 AM UTC 24
Finished Oct 15 11:56:47 AM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197332738 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.2197332738
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_host_error_intr.4001316808
Short name T755
Test name
Test status
Simulation time 137390342 ps
CPU time 2.82 seconds
Started Oct 15 11:55:57 AM UTC 24
Finished Oct 15 11:56:01 AM UTC 24
Peak memory 225852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001316808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.4001316808
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_fmt_empty.3828395091
Short name T757
Test name
Test status
Simulation time 1941027956 ps
CPU time 26.23 seconds
Started Oct 15 11:55:39 AM UTC 24
Finished Oct 15 11:56:06 AM UTC 24
Peak memory 287732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828395091 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empty.3828395091
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_full.733765332
Short name T793
Test name
Test status
Simulation time 8270393397 ps
CPU time 79.73 seconds
Started Oct 15 11:55:45 AM UTC 24
Finished Oct 15 11:57:06 AM UTC 24
Peak memory 420800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733765332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.733765332
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_overflow.3068312638
Short name T790
Test name
Test status
Simulation time 2478749958 ps
CPU time 84.8 seconds
Started Oct 15 11:55:37 AM UTC 24
Finished Oct 15 11:57:03 AM UTC 24
Peak memory 809928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068312638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3068312638
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_fmt.2012251445
Short name T749
Test name
Test status
Simulation time 312860975 ps
CPU time 2.36 seconds
Started Oct 15 11:55:37 AM UTC 24
Finished Oct 15 11:55:40 AM UTC 24
Peak memory 215716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012251445 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fmt.2012251445
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_rx.1350963867
Short name T753
Test name
Test status
Simulation time 806397951 ps
CPU time 13.89 seconds
Started Oct 15 11:55:41 AM UTC 24
Finished Oct 15 11:55:56 AM UTC 24
Peak memory 215368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350963867 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.1350963867
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_watermark.3722644804
Short name T117
Test name
Test status
Simulation time 5891175429 ps
CPU time 70.68 seconds
Started Oct 15 11:55:37 AM UTC 24
Finished Oct 15 11:56:49 AM UTC 24
Peak memory 906116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722644804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.3722644804
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_host_may_nack.2928145307
Short name T262
Test name
Test status
Simulation time 1216360425 ps
CPU time 18.19 seconds
Started Oct 15 11:56:37 AM UTC 24
Finished Oct 15 11:56:56 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928145307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.2928145307
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_host_mode_toggle.3040164199
Short name T769
Test name
Test status
Simulation time 229158768 ps
CPU time 2.74 seconds
Started Oct 15 11:56:31 AM UTC 24
Finished Oct 15 11:56:35 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040164199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3040164199
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_host_override.3123007241
Short name T144
Test name
Test status
Simulation time 18803923 ps
CPU time 1.15 seconds
Started Oct 15 11:55:35 AM UTC 24
Finished Oct 15 11:55:38 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123007241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.3123007241
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_host_perf.2859654952
Short name T824
Test name
Test status
Simulation time 49591303344 ps
CPU time 139.85 seconds
Started Oct 15 11:55:55 AM UTC 24
Finished Oct 15 11:58:17 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859654952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2859654952
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_host_perf_precise.2275818259
Short name T1036
Test name
Test status
Simulation time 24223070003 ps
CPU time 589.72 seconds
Started Oct 15 11:55:56 AM UTC 24
Finished Oct 15 12:05:53 PM UTC 24
Peak memory 215588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275818259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.2275818259
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_host_smoke.3931224711
Short name T759
Test name
Test status
Simulation time 1430907955 ps
CPU time 32.33 seconds
Started Oct 15 11:55:34 AM UTC 24
Finished Oct 15 11:56:08 AM UTC 24
Peak memory 324884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931224711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.3931224711
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_host_stretch_timeout.702718515
Short name T762
Test name
Test status
Simulation time 956732968 ps
CPU time 21.88 seconds
Started Oct 15 11:55:57 AM UTC 24
Finished Oct 15 11:56:20 AM UTC 24
Peak memory 232048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702718515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.702718515
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_bad_addr.1500576825
Short name T773
Test name
Test status
Simulation time 5554100763 ps
CPU time 12.98 seconds
Started Oct 15 11:56:28 AM UTC 24
Finished Oct 15 11:56:43 AM UTC 24
Peak memory 232396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1500576825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_bad_ad
dr.1500576825
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_acq.3205547331
Short name T764
Test name
Test status
Simulation time 247688876 ps
CPU time 2.93 seconds
Started Oct 15 11:56:22 AM UTC 24
Finished Oct 15 11:56:26 AM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205547
331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_acq.3205547331
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_tx.3717344071
Short name T767
Test name
Test status
Simulation time 249528996 ps
CPU time 2.4 seconds
Started Oct 15 11:56:26 AM UTC 24
Finished Oct 15 11:56:30 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717344
071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_tx.3717344071
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_acq.4244753068
Short name T775
Test name
Test status
Simulation time 1412477640 ps
CPU time 3.39 seconds
Started Oct 15 11:56:39 AM UTC 24
Finished Oct 15 11:56:43 AM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244753
068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_watermar
ks_acq.4244753068
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_tx.2196911521
Short name T776
Test name
Test status
Simulation time 323494359 ps
CPU time 2.49 seconds
Started Oct 15 11:56:40 AM UTC 24
Finished Oct 15 11:56:44 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196911
521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_watermark
s_tx.2196911521
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_intr_smoke.947149926
Short name T765
Test name
Test status
Simulation time 4788823025 ps
CPU time 10.96 seconds
Started Oct 15 11:56:15 AM UTC 24
Finished Oct 15 11:56:27 AM UTC 24
Peak memory 232516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947149
926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_smoke.947149926
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_intr_stress_wr.1769615736
Short name T877
Test name
Test status
Simulation time 17160820085 ps
CPU time 219.37 seconds
Started Oct 15 11:56:17 AM UTC 24
Finished Oct 15 11:59:59 AM UTC 24
Peak memory 4344776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1769615736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_stres
s_wr.1769615736
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull.2854442176
Short name T781
Test name
Test status
Simulation time 964975066 ps
CPU time 3.44 seconds
Started Oct 15 11:56:44 AM UTC 24
Finished Oct 15 11:56:48 AM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854442
176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_acqfull.2854442176
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull_addr.3705858875
Short name T782
Test name
Test status
Simulation time 928968363 ps
CPU time 4.93 seconds
Started Oct 15 11:56:44 AM UTC 24
Finished Oct 15 11:56:50 AM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705858
875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_acqfull_ad
dr.3705858875
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_perf.1302107436
Short name T772
Test name
Test status
Simulation time 3057019862 ps
CPU time 10.28 seconds
Started Oct 15 11:56:27 AM UTC 24
Finished Oct 15 11:56:39 AM UTC 24
Peak memory 232280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302107
436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_perf.1302107436
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_smbus_maxlen.2818087317
Short name T780
Test name
Test status
Simulation time 3299277161 ps
CPU time 3.45 seconds
Started Oct 15 11:56:44 AM UTC 24
Finished Oct 15 11:56:48 AM UTC 24
Peak memory 215564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818087
317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smbus_maxlen.2818087317
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_smoke.918798183
Short name T763
Test name
Test status
Simulation time 812039840 ps
CPU time 13.03 seconds
Started Oct 15 11:56:06 AM UTC 24
Finished Oct 15 11:56:21 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918798183 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smoke.918798183
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_stress_all.868142298
Short name T851
Test name
Test status
Simulation time 74569454118 ps
CPU time 154.41 seconds
Started Oct 15 11:56:27 AM UTC 24
Finished Oct 15 11:59:04 AM UTC 24
Peak memory 2132936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868142
298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_all.868142298
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_stress_rd.1904972663
Short name T770
Test name
Test status
Simulation time 5126536087 ps
CPU time 28.49 seconds
Started Oct 15 11:56:08 AM UTC 24
Finished Oct 15 11:56:37 AM UTC 24
Peak memory 242700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904972663 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_rd.1904972663
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_stress_wr.1552725400
Short name T974
Test name
Test status
Simulation time 62168661715 ps
CPU time 452.29 seconds
Started Oct 15 11:56:07 AM UTC 24
Finished Oct 15 12:03:45 PM UTC 24
Peak memory 5026692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552725400 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_wr.1552725400
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_timeout.467350402
Short name T768
Test name
Test status
Simulation time 10105631223 ps
CPU time 8.4 seconds
Started Oct 15 11:56:21 AM UTC 24
Finished Oct 15 11:56:30 AM UTC 24
Peak memory 232336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4673504
02 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_timeout.467350402
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/20.i2c_target_tx_stretch_ctrl.2041697512
Short name T778
Test name
Test status
Simulation time 154010406 ps
CPU time 3.89 seconds
Started Oct 15 11:56:40 AM UTC 24
Finished Oct 15 11:56:45 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041697
512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.2041697512
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_alert_test.3197276053
Short name T809
Test name
Test status
Simulation time 60586746 ps
CPU time 0.95 seconds
Started Oct 15 11:57:40 AM UTC 24
Finished Oct 15 11:57:42 AM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197276053 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3197276053
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_host_error_intr.1881153083
Short name T789
Test name
Test status
Simulation time 111305967 ps
CPU time 3.55 seconds
Started Oct 15 11:56:57 AM UTC 24
Finished Oct 15 11:57:02 AM UTC 24
Peak memory 225796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881153083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.1881153083
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_fmt_empty.8404962
Short name T786
Test name
Test status
Simulation time 346877265 ps
CPU time 7.26 seconds
Started Oct 15 11:56:50 AM UTC 24
Finished Oct 15 11:56:58 AM UTC 24
Peak memory 287596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8404962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empty.8404962
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_full.1896858413
Short name T816
Test name
Test status
Simulation time 9538529811 ps
CPU time 56.85 seconds
Started Oct 15 11:56:51 AM UTC 24
Finished Oct 15 11:57:50 AM UTC 24
Peak memory 533444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896858413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.1896858413
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_overflow.1315733101
Short name T821
Test name
Test status
Simulation time 1434790201 ps
CPU time 80.4 seconds
Started Oct 15 11:56:49 AM UTC 24
Finished Oct 15 11:58:12 AM UTC 24
Peak memory 500624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315733101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.1315733101
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_fmt.2851670433
Short name T784
Test name
Test status
Simulation time 430908220 ps
CPU time 1.55 seconds
Started Oct 15 11:56:50 AM UTC 24
Finished Oct 15 11:56:52 AM UTC 24
Peak memory 215712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851670433 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fmt.2851670433
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_rx.4173351917
Short name T791
Test name
Test status
Simulation time 184557172 ps
CPU time 12.9 seconds
Started Oct 15 11:56:50 AM UTC 24
Finished Oct 15 11:57:04 AM UTC 24
Peak memory 249088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173351917 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.4173351917
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_watermark.1191553251
Short name T836
Test name
Test status
Simulation time 3029384304 ps
CPU time 113.77 seconds
Started Oct 15 11:56:48 AM UTC 24
Finished Oct 15 11:58:44 AM UTC 24
Peak memory 658380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191553251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.1191553251
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_host_mode_toggle.365538231
Short name T799
Test name
Test status
Simulation time 733584226 ps
CPU time 3.87 seconds
Started Oct 15 11:57:24 AM UTC 24
Finished Oct 15 11:57:29 AM UTC 24
Peak memory 234640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365538231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.365538231
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_host_override.1641493114
Short name T783
Test name
Test status
Simulation time 120571582 ps
CPU time 1.03 seconds
Started Oct 15 11:56:48 AM UTC 24
Finished Oct 15 11:56:51 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641493114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1641493114
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_host_perf.159419404
Short name T788
Test name
Test status
Simulation time 1292923860 ps
CPU time 6.64 seconds
Started Oct 15 11:56:52 AM UTC 24
Finished Oct 15 11:57:00 AM UTC 24
Peak memory 240448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159419404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.159419404
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_host_perf_precise.1609969685
Short name T787
Test name
Test status
Simulation time 74736378 ps
CPU time 4.36 seconds
Started Oct 15 11:56:53 AM UTC 24
Finished Oct 15 11:56:59 AM UTC 24
Peak memory 227636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609969685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.1609969685
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_host_smoke.1460505997
Short name T797
Test name
Test status
Simulation time 11075770827 ps
CPU time 34.82 seconds
Started Oct 15 11:56:46 AM UTC 24
Finished Oct 15 11:57:23 AM UTC 24
Peak memory 339140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460505997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.1460505997
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_host_stretch_timeout.2819712581
Short name T808
Test name
Test status
Simulation time 1043176835 ps
CPU time 43.38 seconds
Started Oct 15 11:56:57 AM UTC 24
Finished Oct 15 11:57:42 AM UTC 24
Peak memory 228072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819712581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.2819712581
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_bad_addr.1904911796
Short name T802
Test name
Test status
Simulation time 1702025700 ps
CPU time 9.73 seconds
Started Oct 15 11:57:23 AM UTC 24
Finished Oct 15 11:57:34 AM UTC 24
Peak memory 227812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1904911796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_bad_ad
dr.1904911796
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_acq.3266070836
Short name T297
Test name
Test status
Simulation time 186391797 ps
CPU time 2.28 seconds
Started Oct 15 11:57:16 AM UTC 24
Finished Oct 15 11:57:19 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266070
836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_acq.3266070836
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_tx.1475509320
Short name T796
Test name
Test status
Simulation time 221506242 ps
CPU time 1.61 seconds
Started Oct 15 11:57:20 AM UTC 24
Finished Oct 15 11:57:22 AM UTC 24
Peak memory 225576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475509
320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_tx.1475509320
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_acq.3006813463
Short name T803
Test name
Test status
Simulation time 736119212 ps
CPU time 2.72 seconds
Started Oct 15 11:57:30 AM UTC 24
Finished Oct 15 11:57:34 AM UTC 24
Peak memory 215580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006813
463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_watermar
ks_acq.3006813463
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_tx.3442938333
Short name T801
Test name
Test status
Simulation time 213215934 ps
CPU time 1.35 seconds
Started Oct 15 11:57:30 AM UTC 24
Finished Oct 15 11:57:33 AM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442938
333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_watermark
s_tx.3442938333
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_hrst.2028522027
Short name T798
Test name
Test status
Simulation time 690773043 ps
CPU time 4.05 seconds
Started Oct 15 11:57:23 AM UTC 24
Finished Oct 15 11:57:28 AM UTC 24
Peak memory 217500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028522
027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_hrst.2028522027
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_intr_smoke.1666319142
Short name T795
Test name
Test status
Simulation time 6509680223 ps
CPU time 16.81 seconds
Started Oct 15 11:57:04 AM UTC 24
Finished Oct 15 11:57:22 AM UTC 24
Peak memory 242632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166631
9142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_smoke.1666319142
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_intr_stress_wr.3652665708
Short name T812
Test name
Test status
Simulation time 8275890169 ps
CPU time 35.48 seconds
Started Oct 15 11:57:07 AM UTC 24
Finished Oct 15 11:57:43 AM UTC 24
Peak memory 357248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3652665708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_stres
s_wr.3652665708
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull.2668250176
Short name T807
Test name
Test status
Simulation time 853218694 ps
CPU time 3.95 seconds
Started Oct 15 11:57:35 AM UTC 24
Finished Oct 15 11:57:40 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668250
176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_acqfull.2668250176
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull_addr.492762651
Short name T813
Test name
Test status
Simulation time 639806364 ps
CPU time 3.96 seconds
Started Oct 15 11:57:39 AM UTC 24
Finished Oct 15 11:57:44 AM UTC 24
Peak memory 215412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4927626
51 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_acqfull_addr.492762651
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_nack_txstretch.1363869542
Short name T810
Test name
Test status
Simulation time 136000866 ps
CPU time 2.34 seconds
Started Oct 15 11:57:39 AM UTC 24
Finished Oct 15 11:57:42 AM UTC 24
Peak memory 232588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363869
542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_txstretch.1363869542
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_perf.3277851083
Short name T800
Test name
Test status
Simulation time 4445142264 ps
CPU time 8.1 seconds
Started Oct 15 11:57:20 AM UTC 24
Finished Oct 15 11:57:29 AM UTC 24
Peak memory 231840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277851
083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_perf.3277851083
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_smbus_maxlen.2404181110
Short name T805
Test name
Test status
Simulation time 738625681 ps
CPU time 2.57 seconds
Started Oct 15 11:57:35 AM UTC 24
Finished Oct 15 11:57:38 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404181
110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smbus_maxlen.2404181110
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_smoke.2511971184
Short name T275
Test name
Test status
Simulation time 3527619859 ps
CPU time 22.46 seconds
Started Oct 15 11:56:59 AM UTC 24
Finished Oct 15 11:57:23 AM UTC 24
Peak memory 225744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511971184 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smoke.2511971184
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_stress_all.65555436
Short name T820
Test name
Test status
Simulation time 30814358580 ps
CPU time 42.46 seconds
Started Oct 15 11:57:23 AM UTC 24
Finished Oct 15 11:58:07 AM UTC 24
Peak memory 248712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655554
36 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_all.65555436
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_stress_rd.3685302258
Short name T804
Test name
Test status
Simulation time 2364576635 ps
CPU time 33.95 seconds
Started Oct 15 11:57:02 AM UTC 24
Finished Oct 15 11:57:38 AM UTC 24
Peak memory 244672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685302258 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_rd.3685302258
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_stress_wr.3806058795
Short name T871
Test name
Test status
Simulation time 30143229627 ps
CPU time 171.19 seconds
Started Oct 15 11:57:00 AM UTC 24
Finished Oct 15 11:59:54 AM UTC 24
Peak memory 2636668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806058795 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_wr.3806058795
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_timeout.637749753
Short name T794
Test name
Test status
Simulation time 9098556856 ps
CPU time 9.84 seconds
Started Oct 15 11:57:08 AM UTC 24
Finished Oct 15 11:57:19 AM UTC 24
Peak memory 242560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6377497
53 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_timeout.637749753
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/21.i2c_target_tx_stretch_ctrl.2773281178
Short name T806
Test name
Test status
Simulation time 140982586 ps
CPU time 4.31 seconds
Started Oct 15 11:57:33 AM UTC 24
Finished Oct 15 11:57:39 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773281
178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.2773281178
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_alert_test.2486547818
Short name T846
Test name
Test status
Simulation time 50440057 ps
CPU time 0.94 seconds
Started Oct 15 11:58:50 AM UTC 24
Finished Oct 15 11:58:52 AM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486547818 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.2486547818
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_host_error_intr.595259841
Short name T819
Test name
Test status
Simulation time 168400809 ps
CPU time 3.57 seconds
Started Oct 15 11:57:53 AM UTC 24
Finished Oct 15 11:57:57 AM UTC 24
Peak memory 248828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595259841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.595259841
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_fmt_empty.1160377555
Short name T817
Test name
Test status
Simulation time 249134512 ps
CPU time 6.89 seconds
Started Oct 15 11:57:44 AM UTC 24
Finished Oct 15 11:57:52 AM UTC 24
Peak memory 265100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160377555 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empty.1160377555
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_full.3078523341
Short name T893
Test name
Test status
Simulation time 16629385395 ps
CPU time 183.55 seconds
Started Oct 15 11:57:44 AM UTC 24
Finished Oct 15 12:00:51 PM UTC 24
Peak memory 275380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078523341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.3078523341
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_overflow.3423648969
Short name T840
Test name
Test status
Simulation time 8385197678 ps
CPU time 63.99 seconds
Started Oct 15 11:57:43 AM UTC 24
Finished Oct 15 11:58:49 AM UTC 24
Peak memory 652552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423648969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.3423648969
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_fmt.2071198066
Short name T814
Test name
Test status
Simulation time 539485326 ps
CPU time 1.89 seconds
Started Oct 15 11:57:43 AM UTC 24
Finished Oct 15 11:57:46 AM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071198066 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fmt.2071198066
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_rx.1200096796
Short name T815
Test name
Test status
Simulation time 300236722 ps
CPU time 4.1 seconds
Started Oct 15 11:57:44 AM UTC 24
Finished Oct 15 11:57:49 AM UTC 24
Peak memory 215784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200096796 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.1200096796
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_watermark.4056280025
Short name T118
Test name
Test status
Simulation time 26746425030 ps
CPU time 124.51 seconds
Started Oct 15 11:57:43 AM UTC 24
Finished Oct 15 11:59:50 AM UTC 24
Peak memory 1612804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056280025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.4056280025
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_host_may_nack.4149378605
Short name T837
Test name
Test status
Simulation time 301410179 ps
CPU time 5 seconds
Started Oct 15 11:58:39 AM UTC 24
Finished Oct 15 11:58:45 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149378605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.4149378605
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_host_mode_toggle.303900402
Short name T838
Test name
Test status
Simulation time 504524422 ps
CPU time 6.15 seconds
Started Oct 15 11:58:38 AM UTC 24
Finished Oct 15 11:58:45 AM UTC 24
Peak memory 232624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303900402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.303900402
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_host_override.2465885145
Short name T811
Test name
Test status
Simulation time 46655034 ps
CPU time 1.08 seconds
Started Oct 15 11:57:41 AM UTC 24
Finished Oct 15 11:57:43 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465885145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2465885145
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_host_perf.3904157964
Short name T818
Test name
Test status
Simulation time 1080842956 ps
CPU time 6.94 seconds
Started Oct 15 11:57:46 AM UTC 24
Finished Oct 15 11:57:54 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904157964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.3904157964
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_host_perf_precise.1648599737
Short name T823
Test name
Test status
Simulation time 864759079 ps
CPU time 24.1 seconds
Started Oct 15 11:57:51 AM UTC 24
Finished Oct 15 11:58:16 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648599737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.1648599737
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_host_smoke.236467395
Short name T852
Test name
Test status
Simulation time 6121221187 ps
CPU time 84.24 seconds
Started Oct 15 11:57:40 AM UTC 24
Finished Oct 15 11:59:06 AM UTC 24
Peak memory 363392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236467395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.236467395
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_host_stretch_timeout.4202880917
Short name T828
Test name
Test status
Simulation time 2617528387 ps
CPU time 40.13 seconds
Started Oct 15 11:57:51 AM UTC 24
Finished Oct 15 11:58:32 AM UTC 24
Peak memory 226212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202880917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.4202880917
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_bad_addr.905885101
Short name T834
Test name
Test status
Simulation time 2881580822 ps
CPU time 7.09 seconds
Started Oct 15 11:58:35 AM UTC 24
Finished Oct 15 11:58:43 AM UTC 24
Peak memory 228080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=905885101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.905885101
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_acq.2393257955
Short name T827
Test name
Test status
Simulation time 232673338 ps
CPU time 1.37 seconds
Started Oct 15 11:58:30 AM UTC 24
Finished Oct 15 11:58:32 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393257
955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_acq.2393257955
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_tx.4108314563
Short name T830
Test name
Test status
Simulation time 249260595 ps
CPU time 3.17 seconds
Started Oct 15 11:58:31 AM UTC 24
Finished Oct 15 11:58:35 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108314
563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_tx.4108314563
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_acq.2435411375
Short name T835
Test name
Test status
Simulation time 179764777 ps
CPU time 1.31 seconds
Started Oct 15 11:58:41 AM UTC 24
Finished Oct 15 11:58:43 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435411
375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_watermar
ks_acq.2435411375
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_tx.3508766042
Short name T839
Test name
Test status
Simulation time 53276358 ps
CPU time 1.4 seconds
Started Oct 15 11:58:44 AM UTC 24
Finished Oct 15 11:58:47 AM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508766
042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_watermark
s_tx.3508766042
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_hrst.338918779
Short name T833
Test name
Test status
Simulation time 304043598 ps
CPU time 3.71 seconds
Started Oct 15 11:58:36 AM UTC 24
Finished Oct 15 11:58:41 AM UTC 24
Peak memory 232212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389187
79 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_hrst.338918779
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_intr_smoke.4141005512
Short name T826
Test name
Test status
Simulation time 849637516 ps
CPU time 7.51 seconds
Started Oct 15 11:58:17 AM UTC 24
Finished Oct 15 11:58:26 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414100
5512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_smoke.4141005512
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_intr_stress_wr.4161532733
Short name T911
Test name
Test status
Simulation time 24367897044 ps
CPU time 174.47 seconds
Started Oct 15 11:58:18 AM UTC 24
Finished Oct 15 12:01:16 PM UTC 24
Peak memory 2118532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4161532733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_stres
s_wr.4161532733
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull_addr.1317353082
Short name T843
Test name
Test status
Simulation time 571488567 ps
CPU time 3.21 seconds
Started Oct 15 11:58:46 AM UTC 24
Finished Oct 15 11:58:51 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317353
082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_acqfull_ad
dr.1317353082
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_nack_txstretch.2582729061
Short name T844
Test name
Test status
Simulation time 506965725 ps
CPU time 2.18 seconds
Started Oct 15 11:58:48 AM UTC 24
Finished Oct 15 11:58:51 AM UTC 24
Peak memory 232328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582729
061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_txstretch.2582729061
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_perf.1798604456
Short name T832
Test name
Test status
Simulation time 461583813 ps
CPU time 4.34 seconds
Started Oct 15 11:58:33 AM UTC 24
Finished Oct 15 11:58:38 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798604
456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_perf.1798604456
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_smbus_maxlen.1270839445
Short name T841
Test name
Test status
Simulation time 1339160201 ps
CPU time 2.65 seconds
Started Oct 15 11:58:45 AM UTC 24
Finished Oct 15 11:58:49 AM UTC 24
Peak memory 215172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270839
445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smbus_maxlen.1270839445
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_smoke.2094454398
Short name T822
Test name
Test status
Simulation time 1700902907 ps
CPU time 13.35 seconds
Started Oct 15 11:57:58 AM UTC 24
Finished Oct 15 11:58:13 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094454398 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smoke.2094454398
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_stress_all.4046646926
Short name T944
Test name
Test status
Simulation time 18846384799 ps
CPU time 239.77 seconds
Started Oct 15 11:58:33 AM UTC 24
Finished Oct 15 12:02:36 PM UTC 24
Peak memory 3148740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404664
6926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_all.4046646926
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_stress_rd.3439397549
Short name T845
Test name
Test status
Simulation time 3570355792 ps
CPU time 36.62 seconds
Started Oct 15 11:58:13 AM UTC 24
Finished Oct 15 11:58:51 AM UTC 24
Peak memory 249104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439397549 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_rd.3439397549
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_stress_wr.952694308
Short name T885
Test name
Test status
Simulation time 37925937129 ps
CPU time 136.35 seconds
Started Oct 15 11:58:08 AM UTC 24
Finished Oct 15 12:00:27 PM UTC 24
Peak memory 2411716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952694308 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_wr.952694308
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_stretch.4052249324
Short name T825
Test name
Test status
Simulation time 3869900216 ps
CPU time 8.26 seconds
Started Oct 15 11:58:14 AM UTC 24
Finished Oct 15 11:58:24 AM UTC 24
Peak memory 357248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052249324 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stretch.4052249324
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_timeout.156108084
Short name T829
Test name
Test status
Simulation time 14591926966 ps
CPU time 8.31 seconds
Started Oct 15 11:58:24 AM UTC 24
Finished Oct 15 11:58:34 AM UTC 24
Peak memory 232372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561080
84 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_timeout.156108084
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/22.i2c_target_tx_stretch_ctrl.1422537117
Short name T842
Test name
Test status
Simulation time 256577719 ps
CPU time 5.19 seconds
Started Oct 15 11:58:44 AM UTC 24
Finished Oct 15 11:58:51 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422537
117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.1422537117
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_alert_test.3584446243
Short name T875
Test name
Test status
Simulation time 52643309 ps
CPU time 1 seconds
Started Oct 15 11:59:55 AM UTC 24
Finished Oct 15 11:59:57 AM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584446243 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.3584446243
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_host_error_intr.1594512513
Short name T855
Test name
Test status
Simulation time 265879686 ps
CPU time 3.72 seconds
Started Oct 15 11:59:05 AM UTC 24
Finished Oct 15 11:59:09 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594512513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.1594512513
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_fmt_empty.3478362355
Short name T850
Test name
Test status
Simulation time 732908449 ps
CPU time 9.53 seconds
Started Oct 15 11:58:53 AM UTC 24
Finished Oct 15 11:59:04 AM UTC 24
Peak memory 291752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478362355 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empty.3478362355
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_full.642346262
Short name T884
Test name
Test status
Simulation time 14178348657 ps
CPU time 88.39 seconds
Started Oct 15 11:58:54 AM UTC 24
Finished Oct 15 12:00:24 PM UTC 24
Peak memory 693384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642346262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.642346262
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_overflow.3351144541
Short name T886
Test name
Test status
Simulation time 11758799351 ps
CPU time 94.44 seconds
Started Oct 15 11:58:52 AM UTC 24
Finished Oct 15 12:00:28 PM UTC 24
Peak memory 877576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351144541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.3351144541
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_fmt.4117982191
Short name T848
Test name
Test status
Simulation time 343060410 ps
CPU time 1.65 seconds
Started Oct 15 11:58:52 AM UTC 24
Finished Oct 15 11:58:55 AM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117982191 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fmt.4117982191
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_rx.1090159894
Short name T849
Test name
Test status
Simulation time 151999032 ps
CPU time 5.53 seconds
Started Oct 15 11:58:54 AM UTC 24
Finished Oct 15 11:59:01 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090159894 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.1090159894
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_watermark.3545024919
Short name T119
Test name
Test status
Simulation time 20218626455 ps
CPU time 116.8 seconds
Started Oct 15 11:58:52 AM UTC 24
Finished Oct 15 12:00:51 PM UTC 24
Peak memory 1506300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545024919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3545024919
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_host_may_nack.1791568357
Short name T261
Test name
Test status
Simulation time 285174869 ps
CPU time 12.43 seconds
Started Oct 15 11:59:42 AM UTC 24
Finished Oct 15 11:59:55 AM UTC 24
Peak memory 215520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791568357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.1791568357
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_host_override.3061209772
Short name T847
Test name
Test status
Simulation time 20328100 ps
CPU time 1.04 seconds
Started Oct 15 11:58:52 AM UTC 24
Finished Oct 15 11:58:54 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061209772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.3061209772
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_host_perf.1167704421
Short name T895
Test name
Test status
Simulation time 3083601450 ps
CPU time 116.77 seconds
Started Oct 15 11:58:55 AM UTC 24
Finished Oct 15 12:00:54 PM UTC 24
Peak memory 240564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167704421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.1167704421
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_host_perf_precise.1856022654
Short name T853
Test name
Test status
Simulation time 168611120 ps
CPU time 4.76 seconds
Started Oct 15 11:59:01 AM UTC 24
Finished Oct 15 11:59:07 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856022654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.1856022654
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_host_smoke.2124249204
Short name T858
Test name
Test status
Simulation time 7850758660 ps
CPU time 37.63 seconds
Started Oct 15 11:58:50 AM UTC 24
Finished Oct 15 11:59:29 AM UTC 24
Peak memory 367544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124249204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.2124249204
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_host_stretch_timeout.454900305
Short name T856
Test name
Test status
Simulation time 1193255548 ps
CPU time 9.03 seconds
Started Oct 15 11:59:04 AM UTC 24
Finished Oct 15 11:59:15 AM UTC 24
Peak memory 232004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454900305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.454900305
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_bad_addr.1796377098
Short name T866
Test name
Test status
Simulation time 1261644683 ps
CPU time 3.48 seconds
Started Oct 15 11:59:38 AM UTC 24
Finished Oct 15 11:59:42 AM UTC 24
Peak memory 226016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1796377098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_bad_ad
dr.1796377098
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_acq.1985574501
Short name T862
Test name
Test status
Simulation time 141087400 ps
CPU time 1.65 seconds
Started Oct 15 11:59:30 AM UTC 24
Finished Oct 15 11:59:33 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985574
501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_acq.1985574501
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_tx.798853927
Short name T294
Test name
Test status
Simulation time 805886584 ps
CPU time 2.93 seconds
Started Oct 15 11:59:32 AM UTC 24
Finished Oct 15 11:59:37 AM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7988539
27 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_tx.798853927
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_acq.492687413
Short name T867
Test name
Test status
Simulation time 985215216 ps
CPU time 4.9 seconds
Started Oct 15 11:59:43 AM UTC 24
Finished Oct 15 11:59:49 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4926874
13 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_watermark
s_acq.492687413
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_tx.3629664490
Short name T869
Test name
Test status
Simulation time 464246265 ps
CPU time 2.2 seconds
Started Oct 15 11:59:48 AM UTC 24
Finished Oct 15 11:59:51 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629664
490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_watermark
s_tx.3629664490
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_intr_smoke.3276373510
Short name T860
Test name
Test status
Simulation time 655599242 ps
CPU time 7.44 seconds
Started Oct 15 11:59:21 AM UTC 24
Finished Oct 15 11:59:29 AM UTC 24
Peak memory 232708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327637
3510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_smoke.3276373510
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_intr_stress_wr.607805801
Short name T923
Test name
Test status
Simulation time 12321531170 ps
CPU time 153.51 seconds
Started Oct 15 11:59:24 AM UTC 24
Finished Oct 15 12:02:00 PM UTC 24
Peak memory 2940120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=607805801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_stress
_wr.607805801
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull.2707864188
Short name T873
Test name
Test status
Simulation time 7072070330 ps
CPU time 4.03 seconds
Started Oct 15 11:59:51 AM UTC 24
Finished Oct 15 11:59:56 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707864
188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_acqfull.2707864188
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull_addr.881420343
Short name T876
Test name
Test status
Simulation time 475773229 ps
CPU time 4.89 seconds
Started Oct 15 11:59:52 AM UTC 24
Finished Oct 15 11:59:58 AM UTC 24
Peak memory 215348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8814203
43 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_acqfull_addr.881420343
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_perf.3834263110
Short name T865
Test name
Test status
Simulation time 1374752941 ps
CPU time 6.22 seconds
Started Oct 15 11:59:33 AM UTC 24
Finished Oct 15 11:59:41 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834263
110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_perf.3834263110
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_smbus_maxlen.640298362
Short name T872
Test name
Test status
Simulation time 1622367114 ps
CPU time 3.45 seconds
Started Oct 15 11:59:50 AM UTC 24
Finished Oct 15 11:59:55 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6402983
62 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smbus_maxlen.640298362
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_smoke.1763522644
Short name T861
Test name
Test status
Simulation time 1254001899 ps
CPU time 22.86 seconds
Started Oct 15 11:59:08 AM UTC 24
Finished Oct 15 11:59:32 AM UTC 24
Peak memory 226016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763522644 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smoke.1763522644
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_stress_all.980565867
Short name T881
Test name
Test status
Simulation time 27055870952 ps
CPU time 35.57 seconds
Started Oct 15 11:59:35 AM UTC 24
Finished Oct 15 12:00:12 PM UTC 24
Peak memory 242644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980565
867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_all.980565867
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_stress_rd.4245223567
Short name T859
Test name
Test status
Simulation time 1194806830 ps
CPU time 18.1 seconds
Started Oct 15 11:59:10 AM UTC 24
Finished Oct 15 11:59:29 AM UTC 24
Peak memory 232388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245223567 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_rd.4245223567
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_stress_wr.2383852567
Short name T976
Test name
Test status
Simulation time 67503857616 ps
CPU time 281.55 seconds
Started Oct 15 11:59:10 AM UTC 24
Finished Oct 15 12:03:55 PM UTC 24
Peak memory 3242876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383852567 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_wr.2383852567
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_stretch.4070806882
Short name T857
Test name
Test status
Simulation time 576595914 ps
CPU time 2.81 seconds
Started Oct 15 11:59:16 AM UTC 24
Finished Oct 15 11:59:20 AM UTC 24
Peak memory 225716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070806882 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stretch.4070806882
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_timeout.3249347947
Short name T864
Test name
Test status
Simulation time 4241152436 ps
CPU time 9.54 seconds
Started Oct 15 11:59:29 AM UTC 24
Finished Oct 15 11:59:40 AM UTC 24
Peak memory 232756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249347
947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_timeout.3249347947
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/23.i2c_target_tx_stretch_ctrl.119511676
Short name T870
Test name
Test status
Simulation time 58917485 ps
CPU time 2.34 seconds
Started Oct 15 11:59:50 AM UTC 24
Finished Oct 15 11:59:54 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195116
76 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.119511676
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_alert_test.1390998261
Short name T901
Test name
Test status
Simulation time 58856210 ps
CPU time 1.04 seconds
Started Oct 15 12:00:57 PM UTC 24
Finished Oct 15 12:01:00 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390998261 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.1390998261
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_host_error_intr.130388654
Short name T882
Test name
Test status
Simulation time 636067635 ps
CPU time 1.87 seconds
Started Oct 15 12:00:12 PM UTC 24
Finished Oct 15 12:00:15 PM UTC 24
Peak memory 225448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130388654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.130388654
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_fmt_empty.1709304971
Short name T880
Test name
Test status
Simulation time 1109543520 ps
CPU time 7.57 seconds
Started Oct 15 11:59:59 AM UTC 24
Finished Oct 15 12:00:07 PM UTC 24
Peak memory 271280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709304971 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empty.1709304971
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_full.795869804
Short name T975
Test name
Test status
Simulation time 6420591421 ps
CPU time 226.5 seconds
Started Oct 15 12:00:00 PM UTC 24
Finished Oct 15 12:03:50 PM UTC 24
Peak memory 527676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795869804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.795869804
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_overflow.3008763657
Short name T887
Test name
Test status
Simulation time 1449402135 ps
CPU time 44.63 seconds
Started Oct 15 11:59:58 AM UTC 24
Finished Oct 15 12:00:44 PM UTC 24
Peak memory 549836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008763657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.3008763657
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_fmt.1175551365
Short name T878
Test name
Test status
Simulation time 429769047 ps
CPU time 1.27 seconds
Started Oct 15 11:59:59 AM UTC 24
Finished Oct 15 12:00:01 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175551365 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fmt.1175551365
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_rx.3864151401
Short name T879
Test name
Test status
Simulation time 163598354 ps
CPU time 5.53 seconds
Started Oct 15 12:00:00 PM UTC 24
Finished Oct 15 12:00:07 PM UTC 24
Peak memory 236744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864151401 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.3864151401
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_watermark.2368983784
Short name T927
Test name
Test status
Simulation time 4135535615 ps
CPU time 125.87 seconds
Started Oct 15 11:59:58 AM UTC 24
Finished Oct 15 12:02:06 PM UTC 24
Peak memory 1227844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368983784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.2368983784
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_host_may_nack.3775236958
Short name T900
Test name
Test status
Simulation time 1221150985 ps
CPU time 5.9 seconds
Started Oct 15 12:00:52 PM UTC 24
Finished Oct 15 12:00:59 PM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775236958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.3775236958
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_host_override.1600037588
Short name T145
Test name
Test status
Simulation time 220496706 ps
CPU time 1.12 seconds
Started Oct 15 11:59:57 AM UTC 24
Finished Oct 15 11:59:59 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600037588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1600037588
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_host_perf.344212082
Short name T1314
Test name
Test status
Simulation time 73384988346 ps
CPU time 807.73 seconds
Started Oct 15 12:00:02 PM UTC 24
Finished Oct 15 12:13:43 PM UTC 24
Peak memory 259264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344212082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.344212082
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_host_perf_precise.3955174827
Short name T868
Test name
Test status
Simulation time 2842986605 ps
CPU time 29.53 seconds
Started Oct 15 12:00:07 PM UTC 24
Finished Oct 15 12:00:38 PM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955174827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.3955174827
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_host_smoke.3986890073
Short name T874
Test name
Test status
Simulation time 1582916041 ps
CPU time 35.46 seconds
Started Oct 15 11:59:55 AM UTC 24
Finished Oct 15 12:00:32 PM UTC 24
Peak memory 392328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986890073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.3986890073
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_host_stress_all.2373428955
Short name T23
Test name
Test status
Simulation time 20123835833 ps
CPU time 243.67 seconds
Started Oct 15 12:00:16 PM UTC 24
Finished Oct 15 12:04:24 PM UTC 24
Peak memory 553928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373428955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.2373428955
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_host_stretch_timeout.3712898432
Short name T883
Test name
Test status
Simulation time 994348731 ps
CPU time 13.24 seconds
Started Oct 15 12:00:08 PM UTC 24
Finished Oct 15 12:00:23 PM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712898432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3712898432
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_bad_addr.1209332655
Short name T896
Test name
Test status
Simulation time 1501301118 ps
CPU time 4.15 seconds
Started Oct 15 12:00:49 PM UTC 24
Finished Oct 15 12:00:55 PM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1209332655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_ad
dr.1209332655
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_acq.2443304559
Short name T890
Test name
Test status
Simulation time 151559168 ps
CPU time 1.68 seconds
Started Oct 15 12:00:45 PM UTC 24
Finished Oct 15 12:00:48 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443304
559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_acq.2443304559
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_tx.312400920
Short name T892
Test name
Test status
Simulation time 933954522 ps
CPU time 3.21 seconds
Started Oct 15 12:00:46 PM UTC 24
Finished Oct 15 12:00:51 PM UTC 24
Peak memory 224392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124009
20 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_tx.312400920
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_acq.1029605939
Short name T899
Test name
Test status
Simulation time 2339370375 ps
CPU time 3.73 seconds
Started Oct 15 12:00:52 PM UTC 24
Finished Oct 15 12:00:56 PM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029605
939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_watermar
ks_acq.1029605939
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_tx.2882479788
Short name T898
Test name
Test status
Simulation time 661383869 ps
CPU time 2.27 seconds
Started Oct 15 12:00:52 PM UTC 24
Finished Oct 15 12:00:55 PM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882479
788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_watermark
s_tx.2882479788
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_intr_smoke.4171525123
Short name T726
Test name
Test status
Simulation time 1024111487 ps
CPU time 5.24 seconds
Started Oct 15 12:00:33 PM UTC 24
Finished Oct 15 12:00:39 PM UTC 24
Peak memory 232352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417152
5123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_smoke.4171525123
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_intr_stress_wr.3926657047
Short name T947
Test name
Test status
Simulation time 23417880481 ps
CPU time 126.91 seconds
Started Oct 15 12:00:39 PM UTC 24
Finished Oct 15 12:02:48 PM UTC 24
Peak memory 1317816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3926657047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_stres
s_wr.3926657047
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull.4273729852
Short name T906
Test name
Test status
Simulation time 2937323824 ps
CPU time 4.48 seconds
Started Oct 15 12:00:56 PM UTC 24
Finished Oct 15 12:01:02 PM UTC 24
Peak memory 225956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273729
852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_acqfull.4273729852
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull_addr.3583672707
Short name T905
Test name
Test status
Simulation time 2037302305 ps
CPU time 4.32 seconds
Started Oct 15 12:00:56 PM UTC 24
Finished Oct 15 12:01:01 PM UTC 24
Peak memory 215412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583672
707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_acqfull_ad
dr.3583672707
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_perf.3704181269
Short name T897
Test name
Test status
Simulation time 542404262 ps
CPU time 5.44 seconds
Started Oct 15 12:00:48 PM UTC 24
Finished Oct 15 12:00:55 PM UTC 24
Peak memory 229856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704181
269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_perf.3704181269
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_smbus_maxlen.1940121947
Short name T904
Test name
Test status
Simulation time 1056727902 ps
CPU time 4.5 seconds
Started Oct 15 12:00:55 PM UTC 24
Finished Oct 15 12:01:01 PM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940121
947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smbus_maxlen.1940121947
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_smoke.1308416491
Short name T739
Test name
Test status
Simulation time 4619970974 ps
CPU time 18.35 seconds
Started Oct 15 12:00:24 PM UTC 24
Finished Oct 15 12:00:43 PM UTC 24
Peak memory 226080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308416491 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smoke.1308416491
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_stress_all.3542182870
Short name T1004
Test name
Test status
Simulation time 45142598443 ps
CPU time 223.85 seconds
Started Oct 15 12:00:48 PM UTC 24
Finished Oct 15 12:04:35 PM UTC 24
Peak memory 2372876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354218
2870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_all.3542182870
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_stress_rd.484411779
Short name T888
Test name
Test status
Simulation time 968154226 ps
CPU time 16.1 seconds
Started Oct 15 12:00:28 PM UTC 24
Finished Oct 15 12:00:45 PM UTC 24
Peak memory 231908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484411779 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_rd.484411779
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_stress_wr.4062528347
Short name T1118
Test name
Test status
Simulation time 58262024143 ps
CPU time 463.03 seconds
Started Oct 15 12:00:26 PM UTC 24
Finished Oct 15 12:08:14 PM UTC 24
Peak memory 4903812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062528347 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_wr.4062528347
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_stretch.2354591772
Short name T891
Test name
Test status
Simulation time 1970275586 ps
CPU time 18.98 seconds
Started Oct 15 12:00:29 PM UTC 24
Finished Oct 15 12:00:49 PM UTC 24
Peak memory 414592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354591772 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stretch.2354591772
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_timeout.3115393941
Short name T894
Test name
Test status
Simulation time 4815763831 ps
CPU time 10.05 seconds
Started Oct 15 12:00:40 PM UTC 24
Finished Oct 15 12:00:51 PM UTC 24
Peak memory 232520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115393
941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_timeout.3115393941
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/24.i2c_target_tx_stretch_ctrl.1516689274
Short name T903
Test name
Test status
Simulation time 188399688 ps
CPU time 3.81 seconds
Started Oct 15 12:00:55 PM UTC 24
Finished Oct 15 12:01:00 PM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516689
274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.1516689274
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_alert_test.2465310689
Short name T936
Test name
Test status
Simulation time 25579583 ps
CPU time 1.02 seconds
Started Oct 15 12:02:12 PM UTC 24
Finished Oct 15 12:02:14 PM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465310689 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.2465310689
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_host_error_intr.3134513102
Short name T913
Test name
Test status
Simulation time 580309416 ps
CPU time 2.6 seconds
Started Oct 15 12:01:16 PM UTC 24
Finished Oct 15 12:01:20 PM UTC 24
Peak memory 225792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134513102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3134513102
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_fmt_empty.95149798
Short name T909
Test name
Test status
Simulation time 221511322 ps
CPU time 6.34 seconds
Started Oct 15 12:01:03 PM UTC 24
Finished Oct 15 12:01:10 PM UTC 24
Peak memory 258940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95149798 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empty.95149798
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_full.2928549428
Short name T902
Test name
Test status
Simulation time 3959026769 ps
CPU time 126.6 seconds
Started Oct 15 12:01:04 PM UTC 24
Finished Oct 15 12:03:13 PM UTC 24
Peak memory 529416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928549428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.2928549428
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_overflow.1321792177
Short name T918
Test name
Test status
Simulation time 1687072388 ps
CPU time 47.56 seconds
Started Oct 15 12:01:01 PM UTC 24
Finished Oct 15 12:01:50 PM UTC 24
Peak memory 576716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321792177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.1321792177
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_fmt.3721330130
Short name T908
Test name
Test status
Simulation time 97260879 ps
CPU time 1.85 seconds
Started Oct 15 12:01:02 PM UTC 24
Finished Oct 15 12:01:04 PM UTC 24
Peak memory 215704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721330130 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fmt.3721330130
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_rx.773824001
Short name T912
Test name
Test status
Simulation time 1009206829 ps
CPU time 13.34 seconds
Started Oct 15 12:01:03 PM UTC 24
Finished Oct 15 12:01:17 PM UTC 24
Peak memory 263048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773824001 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.773824001
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_watermark.1693386918
Short name T1072
Test name
Test status
Simulation time 4404733885 ps
CPU time 345.53 seconds
Started Oct 15 12:01:00 PM UTC 24
Finished Oct 15 12:06:51 PM UTC 24
Peak memory 1342412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693386918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.1693386918
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_host_may_nack.526466549
Short name T934
Test name
Test status
Simulation time 4800196586 ps
CPU time 8.42 seconds
Started Oct 15 12:02:05 PM UTC 24
Finished Oct 15 12:02:14 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526466549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.526466549
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_host_override.114810444
Short name T907
Test name
Test status
Simulation time 78237596 ps
CPU time 1.02 seconds
Started Oct 15 12:01:00 PM UTC 24
Finished Oct 15 12:01:03 PM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114810444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.114810444
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_host_perf.3880703168
Short name T1064
Test name
Test status
Simulation time 28967825104 ps
CPU time 332.29 seconds
Started Oct 15 12:01:05 PM UTC 24
Finished Oct 15 12:06:42 PM UTC 24
Peak memory 298240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880703168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.3880703168
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_host_perf_precise.1669493287
Short name T910
Test name
Test status
Simulation time 84792421 ps
CPU time 1.35 seconds
Started Oct 15 12:01:11 PM UTC 24
Finished Oct 15 12:01:13 PM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669493287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.1669493287
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_host_smoke.2911221123
Short name T926
Test name
Test status
Simulation time 1636380292 ps
CPU time 64.78 seconds
Started Oct 15 12:00:59 PM UTC 24
Finished Oct 15 12:02:06 PM UTC 24
Peak memory 314504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911221123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.2911221123
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_host_stretch_timeout.2966928737
Short name T915
Test name
Test status
Simulation time 2719084294 ps
CPU time 29.12 seconds
Started Oct 15 12:01:14 PM UTC 24
Finished Oct 15 12:01:45 PM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966928737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.2966928737
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_bad_addr.4254222842
Short name T929
Test name
Test status
Simulation time 7088621103 ps
CPU time 6.89 seconds
Started Oct 15 12:01:59 PM UTC 24
Finished Oct 15 12:02:07 PM UTC 24
Peak memory 232656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4254222842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_bad_ad
dr.4254222842
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_acq.3007233258
Short name T919
Test name
Test status
Simulation time 240711471 ps
CPU time 2.88 seconds
Started Oct 15 12:01:51 PM UTC 24
Finished Oct 15 12:01:55 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007233
258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_acq.3007233258
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_tx.1699509522
Short name T920
Test name
Test status
Simulation time 300883841 ps
CPU time 1.35 seconds
Started Oct 15 12:01:53 PM UTC 24
Finished Oct 15 12:01:56 PM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699509
522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_tx.1699509522
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_acq.2403528245
Short name T931
Test name
Test status
Simulation time 426994054 ps
CPU time 4.47 seconds
Started Oct 15 12:02:06 PM UTC 24
Finished Oct 15 12:02:11 PM UTC 24
Peak memory 215432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403528
245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_watermar
ks_acq.2403528245
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_tx.4065948253
Short name T930
Test name
Test status
Simulation time 265348208 ps
CPU time 2.09 seconds
Started Oct 15 12:02:07 PM UTC 24
Finished Oct 15 12:02:10 PM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065948
253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_watermark
s_tx.4065948253
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_intr_smoke.294447507
Short name T917
Test name
Test status
Simulation time 2198488902 ps
CPU time 6.62 seconds
Started Oct 15 12:01:42 PM UTC 24
Finished Oct 15 12:01:49 PM UTC 24
Peak memory 232404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294447
507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_smoke.294447507
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_intr_stress_wr.2860873366
Short name T945
Test name
Test status
Simulation time 12265810385 ps
CPU time 58.23 seconds
Started Oct 15 12:01:46 PM UTC 24
Finished Oct 15 12:02:46 PM UTC 24
Peak memory 1150160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2860873366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_stres
s_wr.2860873366
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull.2895336836
Short name T935
Test name
Test status
Simulation time 521464904 ps
CPU time 5.09 seconds
Started Oct 15 12:02:08 PM UTC 24
Finished Oct 15 12:02:14 PM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895336
836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_acqfull.2895336836
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull_addr.2807439973
Short name T933
Test name
Test status
Simulation time 950714873 ps
CPU time 4.05 seconds
Started Oct 15 12:02:08 PM UTC 24
Finished Oct 15 12:02:13 PM UTC 24
Peak memory 215412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807439
973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_acqfull_ad
dr.2807439973
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_perf.3869911877
Short name T924
Test name
Test status
Simulation time 614346086 ps
CPU time 7.82 seconds
Started Oct 15 12:01:56 PM UTC 24
Finished Oct 15 12:02:05 PM UTC 24
Peak memory 231888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869911
877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_perf.3869911877
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_smbus_maxlen.3785803150
Short name T932
Test name
Test status
Simulation time 2765400816 ps
CPU time 3.4 seconds
Started Oct 15 12:02:07 PM UTC 24
Finished Oct 15 12:02:11 PM UTC 24
Peak memory 215372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785803
150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smbus_maxlen.3785803150
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_smoke.1102115860
Short name T928
Test name
Test status
Simulation time 4815011780 ps
CPU time 44.79 seconds
Started Oct 15 12:01:20 PM UTC 24
Finished Oct 15 12:02:07 PM UTC 24
Peak memory 229848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102115860 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smoke.1102115860
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_stress_all.3443446659
Short name T951
Test name
Test status
Simulation time 9488465266 ps
CPU time 60.66 seconds
Started Oct 15 12:01:56 PM UTC 24
Finished Oct 15 12:02:59 PM UTC 24
Peak memory 232448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344344
6659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_all.3443446659
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_stress_rd.139019875
Short name T916
Test name
Test status
Simulation time 8827364357 ps
CPU time 9.38 seconds
Started Oct 15 12:01:37 PM UTC 24
Finished Oct 15 12:01:48 PM UTC 24
Peak memory 227748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139019875 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_rd.139019875
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_stress_wr.2404359245
Short name T921
Test name
Test status
Simulation time 29054187072 ps
CPU time 31.23 seconds
Started Oct 15 12:01:25 PM UTC 24
Finished Oct 15 12:01:58 PM UTC 24
Peak memory 648064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404359245 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_wr.2404359245
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_stretch.3405962995
Short name T925
Test name
Test status
Simulation time 4298240671 ps
CPU time 25.54 seconds
Started Oct 15 12:01:39 PM UTC 24
Finished Oct 15 12:02:05 PM UTC 24
Peak memory 320580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405962995 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stretch.3405962995
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_timeout.354588052
Short name T922
Test name
Test status
Simulation time 3388462800 ps
CPU time 10.35 seconds
Started Oct 15 12:01:49 PM UTC 24
Finished Oct 15 12:02:00 PM UTC 24
Peak memory 232648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545880
52 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_timeout.354588052
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/25.i2c_target_tx_stretch_ctrl.3797846647
Short name T939
Test name
Test status
Simulation time 1054754774 ps
CPU time 14.44 seconds
Started Oct 15 12:02:07 PM UTC 24
Finished Oct 15 12:02:22 PM UTC 24
Peak memory 215660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797846
647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.3797846647
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_alert_test.2226583576
Short name T962
Test name
Test status
Simulation time 29076654 ps
CPU time 1.01 seconds
Started Oct 15 12:03:15 PM UTC 24
Finished Oct 15 12:03:17 PM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226583576 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.2226583576
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_host_error_intr.926111011
Short name T943
Test name
Test status
Simulation time 200758065 ps
CPU time 2.85 seconds
Started Oct 15 12:02:29 PM UTC 24
Finished Oct 15 12:02:33 PM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926111011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.926111011
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_fmt_empty.1474403719
Short name T941
Test name
Test status
Simulation time 579992524 ps
CPU time 11.59 seconds
Started Oct 15 12:02:16 PM UTC 24
Finished Oct 15 12:02:28 PM UTC 24
Peak memory 314224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474403719 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empty.1474403719
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_full.3206377075
Short name T968
Test name
Test status
Simulation time 6077221484 ps
CPU time 74.09 seconds
Started Oct 15 12:02:20 PM UTC 24
Finished Oct 15 12:03:36 PM UTC 24
Peak memory 394632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206377075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.3206377075
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_overflow.934338886
Short name T978
Test name
Test status
Simulation time 2732401369 ps
CPU time 98.22 seconds
Started Oct 15 12:02:16 PM UTC 24
Finished Oct 15 12:03:56 PM UTC 24
Peak memory 334792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934338886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.934338886
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_fmt.4145216374
Short name T938
Test name
Test status
Simulation time 418234593 ps
CPU time 2 seconds
Started Oct 15 12:02:16 PM UTC 24
Finished Oct 15 12:02:19 PM UTC 24
Peak memory 215652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145216374 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fmt.4145216374
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_rx.635597213
Short name T940
Test name
Test status
Simulation time 235337724 ps
CPU time 9 seconds
Started Oct 15 12:02:17 PM UTC 24
Finished Oct 15 12:02:27 PM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635597213 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.635597213
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_watermark.3647559102
Short name T1079
Test name
Test status
Simulation time 18899589522 ps
CPU time 287.37 seconds
Started Oct 15 12:02:16 PM UTC 24
Finished Oct 15 12:07:07 PM UTC 24
Peak memory 1426380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647559102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.3647559102
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_host_may_nack.2986378793
Short name T889
Test name
Test status
Simulation time 645764104 ps
CPU time 6.07 seconds
Started Oct 15 12:03:07 PM UTC 24
Finished Oct 15 12:03:14 PM UTC 24
Peak memory 215520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986378793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.2986378793
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_host_override.2700394701
Short name T937
Test name
Test status
Simulation time 287843250 ps
CPU time 0.96 seconds
Started Oct 15 12:02:14 PM UTC 24
Finished Oct 15 12:02:16 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700394701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.2700394701
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_host_perf_precise.4268502241
Short name T942
Test name
Test status
Simulation time 501893805 ps
CPU time 7.64 seconds
Started Oct 15 12:02:23 PM UTC 24
Finished Oct 15 12:02:32 PM UTC 24
Peak memory 215444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268502241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.4268502241
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_host_smoke.2685698750
Short name T984
Test name
Test status
Simulation time 1874625321 ps
CPU time 112.42 seconds
Started Oct 15 12:02:12 PM UTC 24
Finished Oct 15 12:04:07 PM UTC 24
Peak memory 396536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685698750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.2685698750
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_host_stress_all.3082788384
Short name T245
Test name
Test status
Simulation time 27801066555 ps
CPU time 346.31 seconds
Started Oct 15 12:02:32 PM UTC 24
Finished Oct 15 12:08:23 PM UTC 24
Peak memory 1527120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082788384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.3082788384
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_host_stretch_timeout.204615781
Short name T948
Test name
Test status
Simulation time 3440465190 ps
CPU time 19.63 seconds
Started Oct 15 12:02:28 PM UTC 24
Finished Oct 15 12:02:49 PM UTC 24
Peak memory 229872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204615781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.204615781
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_bad_addr.366310535
Short name T961
Test name
Test status
Simulation time 2750884507 ps
CPU time 13.12 seconds
Started Oct 15 12:03:02 PM UTC 24
Finished Oct 15 12:03:17 PM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=366310535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.366310535
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_acq.3909961834
Short name T952
Test name
Test status
Simulation time 306285326 ps
CPU time 2.15 seconds
Started Oct 15 12:02:58 PM UTC 24
Finished Oct 15 12:03:01 PM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909961
834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_acq.3909961834
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_tx.529843881
Short name T953
Test name
Test status
Simulation time 532843317 ps
CPU time 1.93 seconds
Started Oct 15 12:02:59 PM UTC 24
Finished Oct 15 12:03:02 PM UTC 24
Peak memory 215520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5298438
81 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_tx.529843881
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_acq.2209931659
Short name T958
Test name
Test status
Simulation time 2024443969 ps
CPU time 4.21 seconds
Started Oct 15 12:03:08 PM UTC 24
Finished Oct 15 12:03:13 PM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209931
659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_watermar
ks_acq.2209931659
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_tx.285815463
Short name T959
Test name
Test status
Simulation time 1649357069 ps
CPU time 1.35 seconds
Started Oct 15 12:03:11 PM UTC 24
Finished Oct 15 12:03:13 PM UTC 24
Peak memory 213556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858154
63 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_watermarks
_tx.285815463
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_hrst.3083949758
Short name T956
Test name
Test status
Simulation time 425653603 ps
CPU time 2.59 seconds
Started Oct 15 12:03:03 PM UTC 24
Finished Oct 15 12:03:07 PM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083949
758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_hrst.3083949758
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_intr_smoke.413647470
Short name T950
Test name
Test status
Simulation time 3677861772 ps
CPU time 7.6 seconds
Started Oct 15 12:02:49 PM UTC 24
Finished Oct 15 12:02:58 PM UTC 24
Peak memory 232452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413647
470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_smoke.413647470
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_intr_stress_wr.4187710562
Short name T1114
Test name
Test status
Simulation time 21815095919 ps
CPU time 307.31 seconds
Started Oct 15 12:02:49 PM UTC 24
Finished Oct 15 12:08:00 PM UTC 24
Peak memory 3849096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4187710562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_stres
s_wr.4187710562
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull.3448823635
Short name T965
Test name
Test status
Simulation time 613326257 ps
CPU time 6.04 seconds
Started Oct 15 12:03:14 PM UTC 24
Finished Oct 15 12:03:21 PM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448823
635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_acqfull.3448823635
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull_addr.1271866564
Short name T964
Test name
Test status
Simulation time 3749302043 ps
CPU time 4.31 seconds
Started Oct 15 12:03:14 PM UTC 24
Finished Oct 15 12:03:19 PM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271866
564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_acqfull_ad
dr.1271866564
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_perf.3477408021
Short name T957
Test name
Test status
Simulation time 603068628 ps
CPU time 6.99 seconds
Started Oct 15 12:03:02 PM UTC 24
Finished Oct 15 12:03:10 PM UTC 24
Peak memory 226076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477408
021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_perf.3477408021
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_smbus_maxlen.3585859465
Short name T963
Test name
Test status
Simulation time 440469791 ps
CPU time 3.47 seconds
Started Oct 15 12:03:14 PM UTC 24
Finished Oct 15 12:03:18 PM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585859
465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smbus_maxlen.3585859465
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_smoke.200724775
Short name T949
Test name
Test status
Simulation time 6167798736 ps
CPU time 21.03 seconds
Started Oct 15 12:02:34 PM UTC 24
Finished Oct 15 12:02:57 PM UTC 24
Peak memory 225332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200724775 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smoke.200724775
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_stress_all.2735242211
Short name T969
Test name
Test status
Simulation time 7595308670 ps
CPU time 33.28 seconds
Started Oct 15 12:03:02 PM UTC 24
Finished Oct 15 12:03:37 PM UTC 24
Peak memory 281560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273524
2211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_all.2735242211
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_stress_rd.1439298345
Short name T946
Test name
Test status
Simulation time 1011372871 ps
CPU time 9.86 seconds
Started Oct 15 12:02:37 PM UTC 24
Finished Oct 15 12:02:48 PM UTC 24
Peak memory 227808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439298345 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_rd.1439298345
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_stress_wr.3059455185
Short name T1037
Test name
Test status
Simulation time 59826040914 ps
CPU time 197.62 seconds
Started Oct 15 12:02:34 PM UTC 24
Finished Oct 15 12:05:55 PM UTC 24
Peak memory 2724736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059455185 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_wr.3059455185
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_stretch.25561808
Short name T955
Test name
Test status
Simulation time 2572728982 ps
CPU time 17.32 seconds
Started Oct 15 12:02:47 PM UTC 24
Finished Oct 15 12:03:05 PM UTC 24
Peak memory 248688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25561808 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stretch.25561808
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_timeout.3742121701
Short name T954
Test name
Test status
Simulation time 5533255394 ps
CPU time 13.04 seconds
Started Oct 15 12:02:50 PM UTC 24
Finished Oct 15 12:03:04 PM UTC 24
Peak memory 242568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742121
701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_timeout.3742121701
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/26.i2c_target_tx_stretch_ctrl.3166075926
Short name T960
Test name
Test status
Simulation time 162983970 ps
CPU time 2.68 seconds
Started Oct 15 12:03:11 PM UTC 24
Finished Oct 15 12:03:14 PM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166075
926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.3166075926
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_alert_test.1252320268
Short name T999
Test name
Test status
Simulation time 16359049 ps
CPU time 1.05 seconds
Started Oct 15 12:04:23 PM UTC 24
Finished Oct 15 12:04:26 PM UTC 24
Peak memory 215484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252320268 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.1252320268
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_host_error_intr.3183967889
Short name T973
Test name
Test status
Simulation time 54420562 ps
CPU time 2.1 seconds
Started Oct 15 12:03:39 PM UTC 24
Finished Oct 15 12:03:42 PM UTC 24
Peak memory 226104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183967889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3183967889
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_fmt_empty.2110310463
Short name T970
Test name
Test status
Simulation time 2699412246 ps
CPU time 15.02 seconds
Started Oct 15 12:03:22 PM UTC 24
Finished Oct 15 12:03:38 PM UTC 24
Peak memory 279472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110310463 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empty.2110310463
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_full.1177026708
Short name T997
Test name
Test status
Simulation time 4022722007 ps
CPU time 117.34 seconds
Started Oct 15 12:03:25 PM UTC 24
Finished Oct 15 12:05:24 PM UTC 24
Peak memory 539652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177026708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.1177026708
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_overflow.3507543169
Short name T994
Test name
Test status
Simulation time 4911307886 ps
CPU time 61.06 seconds
Started Oct 15 12:03:20 PM UTC 24
Finished Oct 15 12:04:22 PM UTC 24
Peak memory 789380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507543169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3507543169
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_fmt.1619615342
Short name T966
Test name
Test status
Simulation time 136222273 ps
CPU time 1.94 seconds
Started Oct 15 12:03:21 PM UTC 24
Finished Oct 15 12:03:24 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619615342 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fmt.1619615342
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_rx.1341942931
Short name T967
Test name
Test status
Simulation time 155836522 ps
CPU time 11.43 seconds
Started Oct 15 12:03:22 PM UTC 24
Finished Oct 15 12:03:34 PM UTC 24
Peak memory 242560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341942931 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.1341942931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_watermark.2076685360
Short name T998
Test name
Test status
Simulation time 5642448731 ps
CPU time 64.21 seconds
Started Oct 15 12:03:20 PM UTC 24
Finished Oct 15 12:04:25 PM UTC 24
Peak memory 992524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076685360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.2076685360
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_host_may_nack.1688305187
Short name T259
Test name
Test status
Simulation time 315012322 ps
CPU time 17.21 seconds
Started Oct 15 12:04:11 PM UTC 24
Finished Oct 15 12:04:29 PM UTC 24
Peak memory 215460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688305187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.1688305187
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_host_mode_toggle.2786479323
Short name T987
Test name
Test status
Simulation time 107702701 ps
CPU time 2.64 seconds
Started Oct 15 12:04:10 PM UTC 24
Finished Oct 15 12:04:13 PM UTC 24
Peak memory 232260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786479323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.2786479323
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_host_override.2875168576
Short name T146
Test name
Test status
Simulation time 119325722 ps
CPU time 1.1 seconds
Started Oct 15 12:03:18 PM UTC 24
Finished Oct 15 12:03:21 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875168576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.2875168576
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_host_perf.961022081
Short name T977
Test name
Test status
Simulation time 4073623877 ps
CPU time 18.81 seconds
Started Oct 15 12:03:35 PM UTC 24
Finished Oct 15 12:03:55 PM UTC 24
Peak memory 240568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961022081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.961022081
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_host_perf_precise.3308629230
Short name T971
Test name
Test status
Simulation time 90349876 ps
CPU time 1.44 seconds
Started Oct 15 12:03:37 PM UTC 24
Finished Oct 15 12:03:40 PM UTC 24
Peak memory 235496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308629230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.3308629230
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_host_smoke.1639173023
Short name T972
Test name
Test status
Simulation time 2054628510 ps
CPU time 22.11 seconds
Started Oct 15 12:03:17 PM UTC 24
Finished Oct 15 12:03:41 PM UTC 24
Peak memory 291700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639173023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.1639173023
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_host_stretch_timeout.2323024412
Short name T979
Test name
Test status
Simulation time 384856241 ps
CPU time 18.45 seconds
Started Oct 15 12:03:38 PM UTC 24
Finished Oct 15 12:03:58 PM UTC 24
Peak memory 226084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323024412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.2323024412
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_bad_addr.4243333642
Short name T990
Test name
Test status
Simulation time 1802082430 ps
CPU time 9.53 seconds
Started Oct 15 12:04:06 PM UTC 24
Finished Oct 15 12:04:17 PM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4243333642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_ad
dr.4243333642
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_acq.1612499067
Short name T982
Test name
Test status
Simulation time 274307507 ps
CPU time 1.54 seconds
Started Oct 15 12:04:02 PM UTC 24
Finished Oct 15 12:04:05 PM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612499
067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_acq.1612499067
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_tx.2865427258
Short name T983
Test name
Test status
Simulation time 1799304586 ps
CPU time 2.42 seconds
Started Oct 15 12:04:02 PM UTC 24
Finished Oct 15 12:04:06 PM UTC 24
Peak memory 215588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865427
258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_tx.2865427258
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_acq.2707678418
Short name T992
Test name
Test status
Simulation time 416458920 ps
CPU time 5.08 seconds
Started Oct 15 12:04:14 PM UTC 24
Finished Oct 15 12:04:20 PM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707678
418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_watermar
ks_acq.2707678418
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_tx.2406388155
Short name T991
Test name
Test status
Simulation time 141535017 ps
CPU time 2.03 seconds
Started Oct 15 12:04:14 PM UTC 24
Finished Oct 15 12:04:17 PM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406388
155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_watermark
s_tx.2406388155
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_hrst.1951276521
Short name T988
Test name
Test status
Simulation time 1405191226 ps
CPU time 4.62 seconds
Started Oct 15 12:04:07 PM UTC 24
Finished Oct 15 12:04:13 PM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951276
521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_hrst.1951276521
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_intr_smoke.3040702852
Short name T985
Test name
Test status
Simulation time 1167260199 ps
CPU time 11.97 seconds
Started Oct 15 12:03:56 PM UTC 24
Finished Oct 15 12:04:09 PM UTC 24
Peak memory 232336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304070
2852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_smoke.3040702852
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_intr_stress_wr.1562469798
Short name T1014
Test name
Test status
Simulation time 27158277800 ps
CPU time 63.72 seconds
Started Oct 15 12:03:56 PM UTC 24
Finished Oct 15 12:05:01 PM UTC 24
Peak memory 1512524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1562469798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_stres
s_wr.1562469798
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull.3842478802
Short name T58
Test name
Test status
Simulation time 2119119571 ps
CPU time 5.64 seconds
Started Oct 15 12:04:18 PM UTC 24
Finished Oct 15 12:04:25 PM UTC 24
Peak memory 225960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842478
802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_acqfull.3842478802
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull_addr.2923216781
Short name T52
Test name
Test status
Simulation time 575523386 ps
CPU time 4.9 seconds
Started Oct 15 12:04:18 PM UTC 24
Finished Oct 15 12:04:24 PM UTC 24
Peak memory 215744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923216
781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_acqfull_ad
dr.2923216781
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_perf.3085860959
Short name T989
Test name
Test status
Simulation time 1318240606 ps
CPU time 8.28 seconds
Started Oct 15 12:04:04 PM UTC 24
Finished Oct 15 12:04:14 PM UTC 24
Peak memory 231832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085860
959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_perf.3085860959
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_smbus_maxlen.1175414138
Short name T993
Test name
Test status
Simulation time 3696888949 ps
CPU time 4.02 seconds
Started Oct 15 12:04:17 PM UTC 24
Finished Oct 15 12:04:22 PM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175414
138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smbus_maxlen.1175414138
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_smoke.2068902934
Short name T980
Test name
Test status
Simulation time 8046628821 ps
CPU time 18.25 seconds
Started Oct 15 12:03:41 PM UTC 24
Finished Oct 15 12:04:01 PM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068902934 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smoke.2068902934
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_stress_all.1568793866
Short name T1723
Test name
Test status
Simulation time 66696908121 ps
CPU time 1413.46 seconds
Started Oct 15 12:04:05 PM UTC 24
Finished Oct 15 12:27:51 PM UTC 24
Peak memory 8721672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156879
3866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_all.1568793866
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_stress_rd.2784231410
Short name T1008
Test name
Test status
Simulation time 2807376265 ps
CPU time 61.76 seconds
Started Oct 15 12:03:46 PM UTC 24
Finished Oct 15 12:04:49 PM UTC 24
Peak memory 227876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784231410 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_rd.2784231410
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_stress_wr.681402863
Short name T996
Test name
Test status
Simulation time 27078497198 ps
CPU time 39.33 seconds
Started Oct 15 12:03:43 PM UTC 24
Finished Oct 15 12:04:24 PM UTC 24
Peak memory 498632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681402863 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_wr.681402863
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_stretch.3237961515
Short name T981
Test name
Test status
Simulation time 4296043483 ps
CPU time 11.71 seconds
Started Oct 15 12:03:51 PM UTC 24
Finished Oct 15 12:04:04 PM UTC 24
Peak memory 298372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237961515 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stretch.3237961515
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_timeout.3617454221
Short name T986
Test name
Test status
Simulation time 2362629114 ps
CPU time 11.29 seconds
Started Oct 15 12:03:57 PM UTC 24
Finished Oct 15 12:04:09 PM UTC 24
Peak memory 226088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617454
221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_timeout.3617454221
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_tx_stretch_ctrl.3036885720
Short name T995
Test name
Test status
Simulation time 321556579 ps
CPU time 7.39 seconds
Started Oct 15 12:04:15 PM UTC 24
Finished Oct 15 12:04:24 PM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036885
720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.3036885720
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_alert_test.1315575970
Short name T1027
Test name
Test status
Simulation time 18966901 ps
CPU time 1.06 seconds
Started Oct 15 12:05:14 PM UTC 24
Finished Oct 15 12:05:16 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315575970 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.1315575970
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_host_error_intr.3372206661
Short name T1005
Test name
Test status
Simulation time 608816983 ps
CPU time 4.5 seconds
Started Oct 15 12:04:30 PM UTC 24
Finished Oct 15 12:04:36 PM UTC 24
Peak memory 232408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372206661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.3372206661
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_fmt_empty.3684092145
Short name T1007
Test name
Test status
Simulation time 579367298 ps
CPU time 17.36 seconds
Started Oct 15 12:04:26 PM UTC 24
Finished Oct 15 12:04:44 PM UTC 24
Peak memory 269252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684092145 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empty.3684092145
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_full.2594944596
Short name T1105
Test name
Test status
Simulation time 6013930783 ps
CPU time 190.3 seconds
Started Oct 15 12:04:27 PM UTC 24
Finished Oct 15 12:07:40 PM UTC 24
Peak memory 850780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594944596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.2594944596
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_overflow.811143451
Short name T1041
Test name
Test status
Simulation time 7229651089 ps
CPU time 107.93 seconds
Started Oct 15 12:04:26 PM UTC 24
Finished Oct 15 12:06:16 PM UTC 24
Peak memory 638144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811143451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.811143451
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_fmt.2166315768
Short name T1001
Test name
Test status
Simulation time 110558511 ps
CPU time 1.5 seconds
Started Oct 15 12:04:26 PM UTC 24
Finished Oct 15 12:04:28 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166315768 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fmt.2166315768
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_rx.675741277
Short name T1002
Test name
Test status
Simulation time 161764968 ps
CPU time 3.99 seconds
Started Oct 15 12:04:26 PM UTC 24
Finished Oct 15 12:04:31 PM UTC 24
Peak memory 244624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675741277 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.675741277
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_watermark.359516484
Short name T1081
Test name
Test status
Simulation time 2909386538 ps
CPU time 161.69 seconds
Started Oct 15 12:04:24 PM UTC 24
Finished Oct 15 12:07:09 PM UTC 24
Peak memory 918524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359516484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.359516484
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_host_may_nack.4210418273
Short name T1029
Test name
Test status
Simulation time 287203292 ps
CPU time 11.28 seconds
Started Oct 15 12:05:04 PM UTC 24
Finished Oct 15 12:05:17 PM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210418273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.4210418273
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_host_override.1418464054
Short name T1000
Test name
Test status
Simulation time 88520387 ps
CPU time 1.03 seconds
Started Oct 15 12:04:24 PM UTC 24
Finished Oct 15 12:04:27 PM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418464054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1418464054
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_host_perf.2789122018
Short name T1048
Test name
Test status
Simulation time 3105326661 ps
CPU time 118.63 seconds
Started Oct 15 12:04:27 PM UTC 24
Finished Oct 15 12:06:28 PM UTC 24
Peak memory 240084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789122018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.2789122018
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_host_perf_precise.3058727539
Short name T1003
Test name
Test status
Simulation time 309474341 ps
CPU time 4.5 seconds
Started Oct 15 12:04:28 PM UTC 24
Finished Oct 15 12:04:34 PM UTC 24
Peak memory 215380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058727539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.3058727539
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_host_smoke.1795245162
Short name T1015
Test name
Test status
Simulation time 3086065927 ps
CPU time 36.89 seconds
Started Oct 15 12:04:23 PM UTC 24
Finished Oct 15 12:05:02 PM UTC 24
Peak memory 396288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795245162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1795245162
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_host_stretch_timeout.3030705194
Short name T1006
Test name
Test status
Simulation time 1167482392 ps
CPU time 13.79 seconds
Started Oct 15 12:04:29 PM UTC 24
Finished Oct 15 12:04:44 PM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030705194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.3030705194
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_bad_addr.491099931
Short name T1020
Test name
Test status
Simulation time 2048837259 ps
CPU time 9.07 seconds
Started Oct 15 12:04:59 PM UTC 24
Finished Oct 15 12:05:09 PM UTC 24
Peak memory 226028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=491099931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.491099931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_acq.1532275589
Short name T1011
Test name
Test status
Simulation time 164770739 ps
CPU time 1.34 seconds
Started Oct 15 12:04:55 PM UTC 24
Finished Oct 15 12:04:57 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532275
589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_acq.1532275589
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_tx.3424839104
Short name T1013
Test name
Test status
Simulation time 263224615 ps
CPU time 1.82 seconds
Started Oct 15 12:04:55 PM UTC 24
Finished Oct 15 12:04:58 PM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424839
104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_tx.3424839104
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_acq.3048432767
Short name T1022
Test name
Test status
Simulation time 483629451 ps
CPU time 4.69 seconds
Started Oct 15 12:05:05 PM UTC 24
Finished Oct 15 12:05:11 PM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048432
767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_watermar
ks_acq.3048432767
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_tx.4194882937
Short name T1021
Test name
Test status
Simulation time 312769162 ps
CPU time 2.27 seconds
Started Oct 15 12:05:07 PM UTC 24
Finished Oct 15 12:05:10 PM UTC 24
Peak memory 215176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194882
937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_watermark
s_tx.4194882937
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_hrst.1044291608
Short name T1019
Test name
Test status
Simulation time 304087179 ps
CPU time 3.47 seconds
Started Oct 15 12:05:02 PM UTC 24
Finished Oct 15 12:05:07 PM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044291
608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_hrst.1044291608
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_intr_smoke.2718701029
Short name T1010
Test name
Test status
Simulation time 15494866464 ps
CPU time 7.81 seconds
Started Oct 15 12:04:46 PM UTC 24
Finished Oct 15 12:04:54 PM UTC 24
Peak memory 232376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271870
1029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_smoke.2718701029
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_intr_stress_wr.1232197101
Short name T1024
Test name
Test status
Simulation time 8450976547 ps
CPU time 25.94 seconds
Started Oct 15 12:04:46 PM UTC 24
Finished Oct 15 12:05:13 PM UTC 24
Peak memory 619728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1232197101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_stres
s_wr.1232197101
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull.238241741
Short name T1026
Test name
Test status
Simulation time 1648903517 ps
CPU time 3.83 seconds
Started Oct 15 12:05:11 PM UTC 24
Finished Oct 15 12:05:16 PM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382417
41 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_acqfull.238241741
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull_addr.2525397444
Short name T1030
Test name
Test status
Simulation time 827307091 ps
CPU time 3.97 seconds
Started Oct 15 12:05:12 PM UTC 24
Finished Oct 15 12:05:17 PM UTC 24
Peak memory 215872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525397
444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_acqfull_ad
dr.2525397444
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_nack_txstretch.2865714777
Short name T1028
Test name
Test status
Simulation time 247430748 ps
CPU time 2.33 seconds
Started Oct 15 12:05:13 PM UTC 24
Finished Oct 15 12:05:16 PM UTC 24
Peak memory 232328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865714
777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_txstretch.2865714777
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_perf.907125963
Short name T1018
Test name
Test status
Simulation time 519290914 ps
CPU time 5.97 seconds
Started Oct 15 12:04:58 PM UTC 24
Finished Oct 15 12:05:05 PM UTC 24
Peak memory 229884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9071259
63 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_perf.907125963
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_smbus_maxlen.2673578976
Short name T1025
Test name
Test status
Simulation time 1849547451 ps
CPU time 4.48 seconds
Started Oct 15 12:05:10 PM UTC 24
Finished Oct 15 12:05:15 PM UTC 24
Peak memory 215376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673578
976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smbus_maxlen.2673578976
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_smoke.3212453089
Short name T1012
Test name
Test status
Simulation time 4638369539 ps
CPU time 21.72 seconds
Started Oct 15 12:04:34 PM UTC 24
Finished Oct 15 12:04:57 PM UTC 24
Peak memory 225756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212453089 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smoke.3212453089
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_stress_all.986237060
Short name T1067
Test name
Test status
Simulation time 53766580603 ps
CPU time 104.65 seconds
Started Oct 15 12:04:58 PM UTC 24
Finished Oct 15 12:06:45 PM UTC 24
Peak memory 1493884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986237
060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_all.986237060
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_stress_rd.274357844
Short name T1042
Test name
Test status
Simulation time 7096985224 ps
CPU time 97.71 seconds
Started Oct 15 12:04:36 PM UTC 24
Finished Oct 15 12:06:16 PM UTC 24
Peak memory 229868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274357844 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_rd.274357844
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_stress_wr.1955597959
Short name T1308
Test name
Test status
Simulation time 46020435389 ps
CPU time 532.36 seconds
Started Oct 15 12:04:36 PM UTC 24
Finished Oct 15 12:13:35 PM UTC 24
Peak memory 6681468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955597959 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_wr.1955597959
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_stretch.318711461
Short name T1009
Test name
Test status
Simulation time 3930846116 ps
CPU time 7.65 seconds
Started Oct 15 12:04:42 PM UTC 24
Finished Oct 15 12:04:51 PM UTC 24
Peak memory 365760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318711461 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stretch.318711461
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_timeout.3774033054
Short name T1016
Test name
Test status
Simulation time 2447653098 ps
CPU time 12.78 seconds
Started Oct 15 12:04:50 PM UTC 24
Finished Oct 15 12:05:04 PM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774033
054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_timeout.3774033054
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/28.i2c_target_tx_stretch_ctrl.1850868908
Short name T1023
Test name
Test status
Simulation time 112750315 ps
CPU time 3.97 seconds
Started Oct 15 12:05:08 PM UTC 24
Finished Oct 15 12:05:13 PM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850868
908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.1850868908
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_alert_test.1904703839
Short name T1063
Test name
Test status
Simulation time 26222679 ps
CPU time 1.07 seconds
Started Oct 15 12:06:39 PM UTC 24
Finished Oct 15 12:06:41 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904703839 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1904703839
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_host_error_intr.1486315969
Short name T1017
Test name
Test status
Simulation time 151799290 ps
CPU time 6.57 seconds
Started Oct 15 12:05:33 PM UTC 24
Finished Oct 15 12:05:41 PM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486315969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.1486315969
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_fmt_empty.2339982826
Short name T1034
Test name
Test status
Simulation time 233003061 ps
CPU time 13.72 seconds
Started Oct 15 12:05:17 PM UTC 24
Finished Oct 15 12:05:32 PM UTC 24
Peak memory 259204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339982826 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empty.2339982826
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_full.697762120
Short name T1097
Test name
Test status
Simulation time 2945039436 ps
CPU time 162.78 seconds
Started Oct 15 12:05:21 PM UTC 24
Finished Oct 15 12:08:06 PM UTC 24
Peak memory 336816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697762120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.697762120
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_overflow.1991416194
Short name T1091
Test name
Test status
Simulation time 8094911842 ps
CPU time 123.52 seconds
Started Oct 15 12:05:17 PM UTC 24
Finished Oct 15 12:07:23 PM UTC 24
Peak memory 517056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991416194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1991416194
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_fmt.3742520133
Short name T1032
Test name
Test status
Simulation time 732946662 ps
CPU time 1.92 seconds
Started Oct 15 12:05:17 PM UTC 24
Finished Oct 15 12:05:20 PM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742520133 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fmt.3742520133
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_rx.2065011722
Short name T1033
Test name
Test status
Simulation time 300692287 ps
CPU time 3.4 seconds
Started Oct 15 12:05:20 PM UTC 24
Finished Oct 15 12:05:24 PM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065011722 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.2065011722
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_watermark.3295692065
Short name T1148
Test name
Test status
Simulation time 3856611158 ps
CPU time 220.22 seconds
Started Oct 15 12:05:17 PM UTC 24
Finished Oct 15 12:09:01 PM UTC 24
Peak memory 1193024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295692065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.3295692065
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_host_may_nack.1223477505
Short name T1056
Test name
Test status
Simulation time 1044081637 ps
CPU time 4.52 seconds
Started Oct 15 12:06:30 PM UTC 24
Finished Oct 15 12:06:36 PM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223477505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.1223477505
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_host_mode_toggle.13123512
Short name T1053
Test name
Test status
Simulation time 290477124 ps
CPU time 4 seconds
Started Oct 15 12:06:28 PM UTC 24
Finished Oct 15 12:06:33 PM UTC 24
Peak memory 229792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13123512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.13123512
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_host_override.3919063748
Short name T1031
Test name
Test status
Simulation time 18359685 ps
CPU time 1.06 seconds
Started Oct 15 12:05:16 PM UTC 24
Finished Oct 15 12:05:18 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919063748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3919063748
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_host_perf.378938459
Short name T1049
Test name
Test status
Simulation time 2635247334 ps
CPU time 63.11 seconds
Started Oct 15 12:05:25 PM UTC 24
Finished Oct 15 12:06:29 PM UTC 24
Peak memory 240156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378938459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.378938459
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_host_perf_precise.3600391050
Short name T1202
Test name
Test status
Simulation time 23144400148 ps
CPU time 292.96 seconds
Started Oct 15 12:05:25 PM UTC 24
Finished Oct 15 12:10:22 PM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600391050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.3600391050
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_host_smoke.825023791
Short name T1039
Test name
Test status
Simulation time 3767238828 ps
CPU time 43.33 seconds
Started Oct 15 12:05:16 PM UTC 24
Finished Oct 15 12:06:01 PM UTC 24
Peak memory 412624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825023791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.825023791
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_host_stretch_timeout.1536971712
Short name T1035
Test name
Test status
Simulation time 765906092 ps
CPU time 15.9 seconds
Started Oct 15 12:05:26 PM UTC 24
Finished Oct 15 12:05:43 PM UTC 24
Peak memory 231856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536971712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.1536971712
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_bad_addr.2318105139
Short name T1052
Test name
Test status
Simulation time 636280018 ps
CPU time 6.67 seconds
Started Oct 15 12:06:25 PM UTC 24
Finished Oct 15 12:06:33 PM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2318105139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_bad_ad
dr.2318105139
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_acq.3387532775
Short name T1044
Test name
Test status
Simulation time 232569447 ps
CPU time 2.27 seconds
Started Oct 15 12:06:18 PM UTC 24
Finished Oct 15 12:06:21 PM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387532
775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_acq.3387532775
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_tx.652920067
Short name T1045
Test name
Test status
Simulation time 222872824 ps
CPU time 2.49 seconds
Started Oct 15 12:06:20 PM UTC 24
Finished Oct 15 12:06:23 PM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6529200
67 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_tx.652920067
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_acq.457780254
Short name T1055
Test name
Test status
Simulation time 355306270 ps
CPU time 2.92 seconds
Started Oct 15 12:06:32 PM UTC 24
Finished Oct 15 12:06:35 PM UTC 24
Peak memory 215436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4577802
54 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_watermark
s_acq.457780254
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_tx.1345914644
Short name T1054
Test name
Test status
Simulation time 400018708 ps
CPU time 1.31 seconds
Started Oct 15 12:06:32 PM UTC 24
Finished Oct 15 12:06:34 PM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345914
644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_watermark
s_tx.1345914644
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_hrst.3637618308
Short name T1051
Test name
Test status
Simulation time 1983106308 ps
CPU time 3.79 seconds
Started Oct 15 12:06:26 PM UTC 24
Finished Oct 15 12:06:31 PM UTC 24
Peak memory 225824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637618
308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_hrst.3637618308
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_intr_smoke.538117004
Short name T1040
Test name
Test status
Simulation time 7376647144 ps
CPU time 11.44 seconds
Started Oct 15 12:06:02 PM UTC 24
Finished Oct 15 12:06:14 PM UTC 24
Peak memory 226156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538117
004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_smoke.538117004
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_intr_stress_wr.550194154
Short name T1071
Test name
Test status
Simulation time 13108487901 ps
CPU time 34.23 seconds
Started Oct 15 12:06:15 PM UTC 24
Finished Oct 15 12:06:51 PM UTC 24
Peak memory 857228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=550194154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_stress
_wr.550194154
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull.1032725389
Short name T1061
Test name
Test status
Simulation time 1469566713 ps
CPU time 4.03 seconds
Started Oct 15 12:06:35 PM UTC 24
Finished Oct 15 12:06:40 PM UTC 24
Peak memory 225700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032725
389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_acqfull.1032725389
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull_addr.2363185634
Short name T1065
Test name
Test status
Simulation time 522470497 ps
CPU time 5.07 seconds
Started Oct 15 12:06:36 PM UTC 24
Finished Oct 15 12:06:42 PM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363185
634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_acqfull_ad
dr.2363185634
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_nack_txstretch.1142287559
Short name T1062
Test name
Test status
Simulation time 652404811 ps
CPU time 2.58 seconds
Started Oct 15 12:06:37 PM UTC 24
Finished Oct 15 12:06:41 PM UTC 24
Peak memory 232264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142287
559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_txstretch.1142287559
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_perf.1374656153
Short name T1050
Test name
Test status
Simulation time 1183123189 ps
CPU time 7.81 seconds
Started Oct 15 12:06:22 PM UTC 24
Finished Oct 15 12:06:31 PM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374656
153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_perf.1374656153
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_smbus_maxlen.1453023084
Short name T1059
Test name
Test status
Simulation time 1690931799 ps
CPU time 2.27 seconds
Started Oct 15 12:06:35 PM UTC 24
Finished Oct 15 12:06:38 PM UTC 24
Peak memory 215184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453023
084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smbus_maxlen.1453023084
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_smoke.2870696882
Short name T1038
Test name
Test status
Simulation time 3424174214 ps
CPU time 14.96 seconds
Started Oct 15 12:05:44 PM UTC 24
Finished Oct 15 12:06:00 PM UTC 24
Peak memory 225748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870696882 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smoke.2870696882
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_stress_all.370947075
Short name T1076
Test name
Test status
Simulation time 8101254129 ps
CPU time 32.33 seconds
Started Oct 15 12:06:24 PM UTC 24
Finished Oct 15 12:06:58 PM UTC 24
Peak memory 259012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370947
075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_all.370947075
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_stress_rd.149462211
Short name T1043
Test name
Test status
Simulation time 932600154 ps
CPU time 19.5 seconds
Started Oct 15 12:05:56 PM UTC 24
Finished Oct 15 12:06:17 PM UTC 24
Peak memory 232532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149462211 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_rd.149462211
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_stress_wr.3341874186
Short name T1047
Test name
Test status
Simulation time 7786669166 ps
CPU time 30.39 seconds
Started Oct 15 12:05:53 PM UTC 24
Finished Oct 15 12:06:26 PM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341874186 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_wr.3341874186
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_stretch.2116653938
Short name T1069
Test name
Test status
Simulation time 4770806931 ps
CPU time 42.93 seconds
Started Oct 15 12:06:01 PM UTC 24
Finished Oct 15 12:06:46 PM UTC 24
Peak memory 1016780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116653938 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stretch.2116653938
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_timeout.83096615
Short name T1046
Test name
Test status
Simulation time 1093565793 ps
CPU time 6.63 seconds
Started Oct 15 12:06:17 PM UTC 24
Finished Oct 15 12:06:25 PM UTC 24
Peak memory 225900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8309661
5 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_timeout.83096615
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/29.i2c_target_tx_stretch_ctrl.2155434575
Short name T1058
Test name
Test status
Simulation time 62726715 ps
CPU time 2.91 seconds
Started Oct 15 12:06:34 PM UTC 24
Finished Oct 15 12:06:38 PM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155434
575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.2155434575
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_alert_test.3049786891
Short name T311
Test name
Test status
Simulation time 37853147 ps
CPU time 0.93 seconds
Started Oct 15 11:42:11 AM UTC 24
Finished Oct 15 11:42:13 AM UTC 24
Peak memory 213392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049786891 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.3049786891
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_error_intr.3841154515
Short name T120
Test name
Test status
Simulation time 366629148 ps
CPU time 7.45 seconds
Started Oct 15 11:41:44 AM UTC 24
Finished Oct 15 11:41:52 AM UTC 24
Peak memory 249100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841154515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3841154515
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_fmt_empty.4292475250
Short name T121
Test name
Test status
Simulation time 1637465708 ps
CPU time 12.08 seconds
Started Oct 15 11:41:41 AM UTC 24
Finished Oct 15 11:41:55 AM UTC 24
Peak memory 302268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292475250 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty.4292475250
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_full.1596406279
Short name T167
Test name
Test status
Simulation time 8448454552 ps
CPU time 100.12 seconds
Started Oct 15 11:41:42 AM UTC 24
Finished Oct 15 11:43:24 AM UTC 24
Peak memory 486272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596406279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.1596406279
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_overflow.230311117
Short name T101
Test name
Test status
Simulation time 9837816299 ps
CPU time 64.8 seconds
Started Oct 15 11:41:40 AM UTC 24
Finished Oct 15 11:42:47 AM UTC 24
Peak memory 842772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230311117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.230311117
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_fmt.2585512319
Short name T249
Test name
Test status
Simulation time 395980550 ps
CPU time 1.34 seconds
Started Oct 15 11:41:41 AM UTC 24
Finished Oct 15 11:41:44 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585512319 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt.2585512319
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_rx.1055248423
Short name T189
Test name
Test status
Simulation time 847496091 ps
CPU time 6.62 seconds
Started Oct 15 11:41:41 AM UTC 24
Finished Oct 15 11:41:49 AM UTC 24
Peak memory 244608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055248423 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.1055248423
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_watermark.3732407912
Short name T403
Test name
Test status
Simulation time 21336395664 ps
CPU time 216.23 seconds
Started Oct 15 11:41:40 AM UTC 24
Finished Oct 15 11:45:20 AM UTC 24
Peak memory 1310016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732407912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.3732407912
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_may_nack.3117436300
Short name T42
Test name
Test status
Simulation time 437636138 ps
CPU time 7.43 seconds
Started Oct 15 11:42:03 AM UTC 24
Finished Oct 15 11:42:12 AM UTC 24
Peak memory 215588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117436300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.3117436300
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_mode_toggle.1227875692
Short name T26
Test name
Test status
Simulation time 231193234 ps
CPU time 2.59 seconds
Started Oct 15 11:42:01 AM UTC 24
Finished Oct 15 11:42:05 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227875692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.1227875692
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_override.3529345533
Short name T187
Test name
Test status
Simulation time 44367853 ps
CPU time 1.07 seconds
Started Oct 15 11:41:40 AM UTC 24
Finished Oct 15 11:41:42 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529345533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3529345533
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_perf.2612028217
Short name T1727
Test name
Test status
Simulation time 48958522403 ps
CPU time 2906.86 seconds
Started Oct 15 11:41:43 AM UTC 24
Finished Oct 15 12:30:40 PM UTC 24
Peak memory 3515264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612028217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.2612028217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_perf_precise.3479564734
Short name T126
Test name
Test status
Simulation time 866763203 ps
CPU time 15.44 seconds
Started Oct 15 11:41:43 AM UTC 24
Finished Oct 15 11:41:59 AM UTC 24
Peak memory 347208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479564734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.3479564734
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_smoke.2912239045
Short name T174
Test name
Test status
Simulation time 6631365686 ps
CPU time 27.75 seconds
Started Oct 15 11:41:39 AM UTC 24
Finished Oct 15 11:42:08 AM UTC 24
Peak memory 310528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912239045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.2912239045
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_stress_all.2880105982
Short name T766
Test name
Test status
Simulation time 113094428980 ps
CPU time 873.87 seconds
Started Oct 15 11:41:44 AM UTC 24
Finished Oct 15 11:56:27 AM UTC 24
Peak memory 2098124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880105982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.2880105982
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_stretch_timeout.3741783091
Short name T152
Test name
Test status
Simulation time 1199003454 ps
CPU time 30.58 seconds
Started Oct 15 11:41:43 AM UTC 24
Finished Oct 15 11:42:15 AM UTC 24
Peak memory 225780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741783091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3741783091
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_sec_cm.1031249255
Short name T179
Test name
Test status
Simulation time 63805882 ps
CPU time 1.49 seconds
Started Oct 15 11:42:09 AM UTC 24
Finished Oct 15 11:42:12 AM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031249255 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1031249255
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_bad_addr.2459409544
Short name T173
Test name
Test status
Simulation time 3540361539 ps
CPU time 8.3 seconds
Started Oct 15 11:41:59 AM UTC 24
Finished Oct 15 11:42:08 AM UTC 24
Peak memory 232440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2459409544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.2459409544
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_acq.3664383007
Short name T123
Test name
Test status
Simulation time 164514453 ps
CPU time 1.67 seconds
Started Oct 15 11:41:53 AM UTC 24
Finished Oct 15 11:41:56 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664383
007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_acq.3664383007
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_tx.1198653589
Short name T125
Test name
Test status
Simulation time 172257509 ps
CPU time 1.99 seconds
Started Oct 15 11:41:55 AM UTC 24
Finished Oct 15 11:41:58 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198653
589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_tx.1198653589
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_acq.2794299764
Short name T310
Test name
Test status
Simulation time 6396417102 ps
CPU time 5.93 seconds
Started Oct 15 11:42:05 AM UTC 24
Finished Oct 15 11:42:12 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794299
764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_watermark
s_acq.2794299764
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_tx.3164698549
Short name T175
Test name
Test status
Simulation time 176462787 ps
CPU time 2.58 seconds
Started Oct 15 11:42:05 AM UTC 24
Finished Oct 15 11:42:09 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164698
549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_watermarks
_tx.3164698549
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_intr_smoke.2194212277
Short name T307
Test name
Test status
Simulation time 4500885921 ps
CPU time 10.93 seconds
Started Oct 15 11:41:50 AM UTC 24
Finished Oct 15 11:42:02 AM UTC 24
Peak memory 244696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219421
2277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_smoke.2194212277
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_intr_stress_wr.4260516667
Short name T375
Test name
Test status
Simulation time 14774963043 ps
CPU time 149.17 seconds
Started Oct 15 11:41:50 AM UTC 24
Finished Oct 15 11:44:22 AM UTC 24
Peak memory 2251652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4260516667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_stress
_wr.4260516667
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull.4249207688
Short name T161
Test name
Test status
Simulation time 479097328 ps
CPU time 3.61 seconds
Started Oct 15 11:42:08 AM UTC 24
Finished Oct 15 11:42:13 AM UTC 24
Peak memory 226144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249207
688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_acqfull.4249207688
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull_addr.2095230532
Short name T151
Test name
Test status
Simulation time 533732879 ps
CPU time 3.63 seconds
Started Oct 15 11:42:09 AM UTC 24
Finished Oct 15 11:42:14 AM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095230
532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.2095230532
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_perf.268903916
Short name T309
Test name
Test status
Simulation time 1084238788 ps
CPU time 6.77 seconds
Started Oct 15 11:41:57 AM UTC 24
Finished Oct 15 11:42:04 AM UTC 24
Peak memory 229800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689039
16 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_perf.268903916
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_smbus_maxlen.3770066978
Short name T178
Test name
Test status
Simulation time 1038231226 ps
CPU time 3.93 seconds
Started Oct 15 11:42:06 AM UTC 24
Finished Oct 15 11:42:11 AM UTC 24
Peak memory 215172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770066
978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smbus_maxlen.3770066978
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_smoke.1338689535
Short name T172
Test name
Test status
Simulation time 719914941 ps
CPU time 22.27 seconds
Started Oct 15 11:41:44 AM UTC 24
Finished Oct 15 11:42:07 AM UTC 24
Peak memory 232716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338689535 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smoke.1338689535
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_stress_all.718225669
Short name T548
Test name
Test status
Simulation time 38278932593 ps
CPU time 487.48 seconds
Started Oct 15 11:41:57 AM UTC 24
Finished Oct 15 11:50:10 AM UTC 24
Peak memory 4623576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718225
669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_all.718225669
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_stress_rd.1025194677
Short name T156
Test name
Test status
Simulation time 4689565896 ps
CPU time 31.76 seconds
Started Oct 15 11:41:49 AM UTC 24
Finished Oct 15 11:42:22 AM UTC 24
Peak memory 242564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025194677 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_rd.1025194677
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_stress_wr.450129750
Short name T471
Test name
Test status
Simulation time 72542790740 ps
CPU time 359.43 seconds
Started Oct 15 11:41:45 AM UTC 24
Finished Oct 15 11:47:49 AM UTC 24
Peak memory 3699784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450129750 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_wr.450129750
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_stretch.4264463442
Short name T353
Test name
Test status
Simulation time 2808162245 ps
CPU time 109.67 seconds
Started Oct 15 11:41:50 AM UTC 24
Finished Oct 15 11:43:42 AM UTC 24
Peak memory 842624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264463442 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stretch.4264463442
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_timeout.3176083473
Short name T124
Test name
Test status
Simulation time 2494450896 ps
CPU time 6.21 seconds
Started Oct 15 11:41:50 AM UTC 24
Finished Oct 15 11:41:57 AM UTC 24
Peak memory 232456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176083
473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_timeout.3176083473
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_target_tx_stretch_ctrl.2282842792
Short name T177
Test name
Test status
Simulation time 165130797 ps
CPU time 4.23 seconds
Started Oct 15 11:42:05 AM UTC 24
Finished Oct 15 11:42:10 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282842
792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.2282842792
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_alert_test.2548877954
Short name T1099
Test name
Test status
Simulation time 52295773 ps
CPU time 0.98 seconds
Started Oct 15 12:07:26 PM UTC 24
Finished Oct 15 12:07:28 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548877954 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.2548877954
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_host_error_intr.151351346
Short name T1074
Test name
Test status
Simulation time 485036726 ps
CPU time 2.65 seconds
Started Oct 15 12:06:50 PM UTC 24
Finished Oct 15 12:06:54 PM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151351346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.151351346
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_fmt_empty.1533634641
Short name T1073
Test name
Test status
Simulation time 1006910709 ps
CPU time 8.79 seconds
Started Oct 15 12:06:43 PM UTC 24
Finished Oct 15 12:06:52 PM UTC 24
Peak memory 293892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533634641 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empty.1533634641
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_full.3590378298
Short name T1136
Test name
Test status
Simulation time 4285326616 ps
CPU time 112.71 seconds
Started Oct 15 12:06:45 PM UTC 24
Finished Oct 15 12:08:40 PM UTC 24
Peak memory 400256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590378298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.3590378298
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_overflow.2060847627
Short name T1123
Test name
Test status
Simulation time 6471108771 ps
CPU time 99.7 seconds
Started Oct 15 12:06:41 PM UTC 24
Finished Oct 15 12:08:23 PM UTC 24
Peak memory 596864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060847627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.2060847627
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_fmt.2457645558
Short name T1068
Test name
Test status
Simulation time 672295393 ps
CPU time 1.49 seconds
Started Oct 15 12:06:42 PM UTC 24
Finished Oct 15 12:06:45 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457645558 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fmt.2457645558
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_rx.1427753458
Short name T1075
Test name
Test status
Simulation time 262252222 ps
CPU time 12.6 seconds
Started Oct 15 12:06:44 PM UTC 24
Finished Oct 15 12:06:57 PM UTC 24
Peak memory 244612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427753458 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.1427753458
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_watermark.3589481368
Short name T1209
Test name
Test status
Simulation time 5106798761 ps
CPU time 228.12 seconds
Started Oct 15 12:06:41 PM UTC 24
Finished Oct 15 12:10:33 PM UTC 24
Peak memory 1270788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589481368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3589481368
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_host_may_nack.3321798005
Short name T1109
Test name
Test status
Simulation time 984754067 ps
CPU time 26.16 seconds
Started Oct 15 12:07:17 PM UTC 24
Finished Oct 15 12:07:45 PM UTC 24
Peak memory 215776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321798005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.3321798005
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_host_override.335110202
Short name T1066
Test name
Test status
Simulation time 83307450 ps
CPU time 1.04 seconds
Started Oct 15 12:06:41 PM UTC 24
Finished Oct 15 12:06:43 PM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335110202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.335110202
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_host_perf.131639852
Short name T1183
Test name
Test status
Simulation time 5000976221 ps
CPU time 189.83 seconds
Started Oct 15 12:06:46 PM UTC 24
Finished Oct 15 12:09:58 PM UTC 24
Peak memory 225892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131639852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.131639852
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_host_perf_precise.1264290831
Short name T1070
Test name
Test status
Simulation time 94351744 ps
CPU time 2.1 seconds
Started Oct 15 12:06:46 PM UTC 24
Finished Oct 15 12:06:49 PM UTC 24
Peak memory 215668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264290831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.1264290831
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_host_smoke.3889232616
Short name T1089
Test name
Test status
Simulation time 8626368394 ps
CPU time 38.65 seconds
Started Oct 15 12:06:39 PM UTC 24
Finished Oct 15 12:07:19 PM UTC 24
Peak memory 429060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889232616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.3889232616
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_host_stress_all.280293044
Short name T1429
Test name
Test status
Simulation time 38309057318 ps
CPU time 580.55 seconds
Started Oct 15 12:06:51 PM UTC 24
Finished Oct 15 12:16:39 PM UTC 24
Peak memory 2294784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280293044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.280293044
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_host_stretch_timeout.833798535
Short name T1078
Test name
Test status
Simulation time 872325871 ps
CPU time 15.82 seconds
Started Oct 15 12:06:47 PM UTC 24
Finished Oct 15 12:07:04 PM UTC 24
Peak memory 231840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833798535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.833798535
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_bad_addr.1881359826
Short name T1092
Test name
Test status
Simulation time 931093426 ps
CPU time 9.34 seconds
Started Oct 15 12:07:13 PM UTC 24
Finished Oct 15 12:07:23 PM UTC 24
Peak memory 229844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1881359826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_bad_ad
dr.1881359826
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_acq.597989921
Short name T1083
Test name
Test status
Simulation time 1236292023 ps
CPU time 2.3 seconds
Started Oct 15 12:07:09 PM UTC 24
Finished Oct 15 12:07:12 PM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5979899
21 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_acq.597989921
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_tx.2451355230
Short name T1084
Test name
Test status
Simulation time 248455379 ps
CPU time 1.88 seconds
Started Oct 15 12:07:10 PM UTC 24
Finished Oct 15 12:07:13 PM UTC 24
Peak memory 225576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451355
230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_tx.2451355230
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_acq.3343873581
Short name T1093
Test name
Test status
Simulation time 566131419 ps
CPU time 5.45 seconds
Started Oct 15 12:07:18 PM UTC 24
Finished Oct 15 12:07:25 PM UTC 24
Peak memory 215436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343873
581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_watermar
ks_acq.3343873581
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_tx.3763429468
Short name T1090
Test name
Test status
Simulation time 127493119 ps
CPU time 2 seconds
Started Oct 15 12:07:19 PM UTC 24
Finished Oct 15 12:07:22 PM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763429
468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_watermark
s_tx.3763429468
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_hrst.671098608
Short name T1087
Test name
Test status
Simulation time 962418500 ps
CPU time 2.44 seconds
Started Oct 15 12:07:14 PM UTC 24
Finished Oct 15 12:07:18 PM UTC 24
Peak memory 225900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6710986
08 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_hrst.671098608
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_intr_smoke.1821853932
Short name T1080
Test name
Test status
Simulation time 3639615350 ps
CPU time 8.36 seconds
Started Oct 15 12:06:58 PM UTC 24
Finished Oct 15 12:07:08 PM UTC 24
Peak memory 229868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182185
3932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_smoke.1821853932
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_intr_stress_wr.3531736076
Short name T1095
Test name
Test status
Simulation time 15281247325 ps
CPU time 21.73 seconds
Started Oct 15 12:07:02 PM UTC 24
Finished Oct 15 12:07:25 PM UTC 24
Peak memory 574344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3531736076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_stres
s_wr.3531736076
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull.4253219969
Short name T1101
Test name
Test status
Simulation time 477089938 ps
CPU time 4.6 seconds
Started Oct 15 12:07:24 PM UTC 24
Finished Oct 15 12:07:29 PM UTC 24
Peak memory 226148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253219
969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_acqfull.4253219969
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull_addr.1074884978
Short name T1098
Test name
Test status
Simulation time 2556024020 ps
CPU time 2.93 seconds
Started Oct 15 12:07:24 PM UTC 24
Finished Oct 15 12:07:28 PM UTC 24
Peak memory 215476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074884
978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_acqfull_ad
dr.1074884978
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_perf.3198977560
Short name T1088
Test name
Test status
Simulation time 546237993 ps
CPU time 5.63 seconds
Started Oct 15 12:07:12 PM UTC 24
Finished Oct 15 12:07:19 PM UTC 24
Peak memory 225684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198977
560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_perf.3198977560
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_smbus_maxlen.4007986381
Short name T1096
Test name
Test status
Simulation time 435652460 ps
CPU time 2.7 seconds
Started Oct 15 12:07:23 PM UTC 24
Finished Oct 15 12:07:26 PM UTC 24
Peak memory 215240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007986
381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smbus_maxlen.4007986381
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_smoke.792219106
Short name T1085
Test name
Test status
Simulation time 2851765534 ps
CPU time 21.85 seconds
Started Oct 15 12:06:52 PM UTC 24
Finished Oct 15 12:07:15 PM UTC 24
Peak memory 225756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792219106 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smoke.792219106
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_stress_all.4071034704
Short name T1178
Test name
Test status
Simulation time 61139247033 ps
CPU time 153.92 seconds
Started Oct 15 12:07:12 PM UTC 24
Finished Oct 15 12:09:48 PM UTC 24
Peak memory 963852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407103
4704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_all.4071034704
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_stress_rd.3278063692
Short name T1082
Test name
Test status
Simulation time 13031873763 ps
CPU time 15.1 seconds
Started Oct 15 12:06:54 PM UTC 24
Finished Oct 15 12:07:11 PM UTC 24
Peak memory 231916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278063692 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_rd.3278063692
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_stress_wr.618035391
Short name T1216
Test name
Test status
Simulation time 33256673953 ps
CPU time 223.93 seconds
Started Oct 15 12:06:53 PM UTC 24
Finished Oct 15 12:10:40 PM UTC 24
Peak memory 3398856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618035391 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_wr.618035391
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_stretch.4276791186
Short name T1102
Test name
Test status
Simulation time 6131242049 ps
CPU time 31.03 seconds
Started Oct 15 12:06:58 PM UTC 24
Finished Oct 15 12:07:31 PM UTC 24
Peak memory 552180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276791186 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stretch.4276791186
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_timeout.3134418028
Short name T1086
Test name
Test status
Simulation time 6736765878 ps
CPU time 10.85 seconds
Started Oct 15 12:07:05 PM UTC 24
Finished Oct 15 12:07:17 PM UTC 24
Peak memory 242956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134418
028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_timeout.3134418028
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/30.i2c_target_tx_stretch_ctrl.3891619937
Short name T1094
Test name
Test status
Simulation time 96606493 ps
CPU time 3.41 seconds
Started Oct 15 12:07:20 PM UTC 24
Finished Oct 15 12:07:25 PM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891619
937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.3891619937
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_alert_test.2537889193
Short name T1128
Test name
Test status
Simulation time 17103066 ps
CPU time 0.98 seconds
Started Oct 15 12:08:25 PM UTC 24
Finished Oct 15 12:08:27 PM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537889193 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2537889193
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_host_error_intr.3078845969
Short name T1110
Test name
Test status
Simulation time 2665387279 ps
CPU time 5.01 seconds
Started Oct 15 12:07:41 PM UTC 24
Finished Oct 15 12:07:47 PM UTC 24
Peak memory 261280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078845969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3078845969
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_fmt_empty.266994549
Short name T1107
Test name
Test status
Simulation time 846373475 ps
CPU time 10.55 seconds
Started Oct 15 12:07:29 PM UTC 24
Finished Oct 15 12:07:41 PM UTC 24
Peak memory 306052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266994549 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empty.266994549
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_full.4012763020
Short name T1129
Test name
Test status
Simulation time 3718347832 ps
CPU time 55.06 seconds
Started Oct 15 12:07:30 PM UTC 24
Finished Oct 15 12:08:27 PM UTC 24
Peak memory 574732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012763020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.4012763020
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_overflow.2143847438
Short name T1188
Test name
Test status
Simulation time 10103300455 ps
CPU time 152.94 seconds
Started Oct 15 12:07:28 PM UTC 24
Finished Oct 15 12:10:04 PM UTC 24
Peak memory 808196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143847438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.2143847438
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_fmt.1617285585
Short name T1103
Test name
Test status
Simulation time 197481932 ps
CPU time 1.33 seconds
Started Oct 15 12:07:29 PM UTC 24
Finished Oct 15 12:07:32 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617285585 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fmt.1617285585
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_rx.824842152
Short name T1104
Test name
Test status
Simulation time 262584206 ps
CPU time 8.64 seconds
Started Oct 15 12:07:29 PM UTC 24
Finished Oct 15 12:07:39 PM UTC 24
Peak memory 234564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824842152 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.824842152
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_watermark.2955167401
Short name T1138
Test name
Test status
Simulation time 3705885110 ps
CPU time 72.29 seconds
Started Oct 15 12:07:27 PM UTC 24
Finished Oct 15 12:08:41 PM UTC 24
Peak memory 1096648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955167401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.2955167401
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_host_may_nack.3212440153
Short name T265
Test name
Test status
Simulation time 672664616 ps
CPU time 17.77 seconds
Started Oct 15 12:08:13 PM UTC 24
Finished Oct 15 12:08:32 PM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212440153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.3212440153
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_host_mode_toggle.976675486
Short name T1117
Test name
Test status
Simulation time 137117663 ps
CPU time 1.46 seconds
Started Oct 15 12:08:10 PM UTC 24
Finished Oct 15 12:08:12 PM UTC 24
Peak memory 232156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976675486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.976675486
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_host_override.575601369
Short name T1100
Test name
Test status
Simulation time 73762911 ps
CPU time 1.09 seconds
Started Oct 15 12:07:26 PM UTC 24
Finished Oct 15 12:07:28 PM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575601369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.575601369
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_host_perf.513184344
Short name T1135
Test name
Test status
Simulation time 13740037702 ps
CPU time 60.07 seconds
Started Oct 15 12:07:32 PM UTC 24
Finished Oct 15 12:08:33 PM UTC 24
Peak memory 531772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513184344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.513184344
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_host_perf_precise.3027037497
Short name T1106
Test name
Test status
Simulation time 446709233 ps
CPU time 6.69 seconds
Started Oct 15 12:07:33 PM UTC 24
Finished Oct 15 12:07:40 PM UTC 24
Peak memory 307968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027037497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.3027037497
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_host_smoke.3456739220
Short name T1108
Test name
Test status
Simulation time 1143468824 ps
CPU time 16.31 seconds
Started Oct 15 12:07:26 PM UTC 24
Finished Oct 15 12:07:43 PM UTC 24
Peak memory 314376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456739220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.3456739220
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_host_stress_all.3674072170
Short name T130
Test name
Test status
Simulation time 21544085731 ps
CPU time 352.78 seconds
Started Oct 15 12:07:41 PM UTC 24
Finished Oct 15 12:13:39 PM UTC 24
Peak memory 2266320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674072170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.3674072170
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_host_stretch_timeout.1243428454
Short name T1112
Test name
Test status
Simulation time 484123984 ps
CPU time 13.11 seconds
Started Oct 15 12:07:40 PM UTC 24
Finished Oct 15 12:07:55 PM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243428454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1243428454
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_bad_addr.4268310017
Short name T1119
Test name
Test status
Simulation time 1213111724 ps
CPU time 6.74 seconds
Started Oct 15 12:08:08 PM UTC 24
Finished Oct 15 12:08:16 PM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4268310017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_ad
dr.4268310017
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_tx.2928368349
Short name T88
Test name
Test status
Simulation time 270055746 ps
CPU time 2.86 seconds
Started Oct 15 12:08:05 PM UTC 24
Finished Oct 15 12:08:08 PM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928368
349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_tx.2928368349
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_acq.3981436685
Short name T1120
Test name
Test status
Simulation time 1290705097 ps
CPU time 2.3 seconds
Started Oct 15 12:08:13 PM UTC 24
Finished Oct 15 12:08:16 PM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981436
685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_watermar
ks_acq.3981436685
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_tx.1813665972
Short name T1121
Test name
Test status
Simulation time 175817730 ps
CPU time 1.31 seconds
Started Oct 15 12:08:14 PM UTC 24
Finished Oct 15 12:08:16 PM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813665
972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_watermark
s_tx.1813665972
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_intr_smoke.2985250602
Short name T1060
Test name
Test status
Simulation time 806509346 ps
CPU time 9.06 seconds
Started Oct 15 12:07:53 PM UTC 24
Finished Oct 15 12:08:03 PM UTC 24
Peak memory 232252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298525
0602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_smoke.2985250602
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_intr_stress_wr.793505178
Short name T1296
Test name
Test status
Simulation time 22242364455 ps
CPU time 287.24 seconds
Started Oct 15 12:07:55 PM UTC 24
Finished Oct 15 12:12:46 PM UTC 24
Peak memory 5563276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=793505178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_stress
_wr.793505178
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull.200782208
Short name T1124
Test name
Test status
Simulation time 2165945003 ps
CPU time 5.22 seconds
Started Oct 15 12:08:17 PM UTC 24
Finished Oct 15 12:08:24 PM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007822
08 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_acqfull.200782208
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull_addr.1171257057
Short name T1127
Test name
Test status
Simulation time 3282620042 ps
CPU time 3.99 seconds
Started Oct 15 12:08:21 PM UTC 24
Finished Oct 15 12:08:27 PM UTC 24
Peak memory 215552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171257
057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_acqfull_ad
dr.1171257057
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_nack_txstretch.826227354
Short name T1130
Test name
Test status
Simulation time 819375631 ps
CPU time 2.57 seconds
Started Oct 15 12:08:24 PM UTC 24
Finished Oct 15 12:08:27 PM UTC 24
Peak memory 232252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8262273
54 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_txstretch.826227354
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_perf.3875552500
Short name T1116
Test name
Test status
Simulation time 510778421 ps
CPU time 6.45 seconds
Started Oct 15 12:08:05 PM UTC 24
Finished Oct 15 12:08:12 PM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875552
500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_perf.3875552500
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_smbus_maxlen.2257451444
Short name T1122
Test name
Test status
Simulation time 540654508 ps
CPU time 2.86 seconds
Started Oct 15 12:08:17 PM UTC 24
Finished Oct 15 12:08:21 PM UTC 24
Peak memory 215168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257451
444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smbus_maxlen.2257451444
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_smoke.330048727
Short name T1113
Test name
Test status
Simulation time 3256271549 ps
CPU time 11.58 seconds
Started Oct 15 12:07:42 PM UTC 24
Finished Oct 15 12:07:55 PM UTC 24
Peak memory 225836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330048727 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smoke.330048727
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_stress_all.3028081296
Short name T1142
Test name
Test status
Simulation time 15236837768 ps
CPU time 44.62 seconds
Started Oct 15 12:08:07 PM UTC 24
Finished Oct 15 12:08:53 PM UTC 24
Peak memory 248764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302808
1296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_all.3028081296
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_stress_rd.180190873
Short name T1139
Test name
Test status
Simulation time 9842765227 ps
CPU time 60.22 seconds
Started Oct 15 12:07:46 PM UTC 24
Finished Oct 15 12:08:48 PM UTC 24
Peak memory 227820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180190873 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_rd.180190873
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_stress_wr.3413285459
Short name T1166
Test name
Test status
Simulation time 45809321561 ps
CPU time 96.8 seconds
Started Oct 15 12:07:44 PM UTC 24
Finished Oct 15 12:09:23 PM UTC 24
Peak memory 1770696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413285459 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_wr.3413285459
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_stretch.2896081107
Short name T1111
Test name
Test status
Simulation time 237579684 ps
CPU time 2.78 seconds
Started Oct 15 12:07:48 PM UTC 24
Finished Oct 15 12:07:52 PM UTC 24
Peak memory 215476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896081107 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stretch.2896081107
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_timeout.4015463023
Short name T1057
Test name
Test status
Simulation time 1011692167 ps
CPU time 5.68 seconds
Started Oct 15 12:07:55 PM UTC 24
Finished Oct 15 12:08:02 PM UTC 24
Peak memory 229804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015463
023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_timeout.4015463023
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/31.i2c_target_tx_stretch_ctrl.1577541726
Short name T1125
Test name
Test status
Simulation time 191873406 ps
CPU time 7.04 seconds
Started Oct 15 12:08:16 PM UTC 24
Finished Oct 15 12:08:24 PM UTC 24
Peak memory 217580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577541
726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.1577541726
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_alert_test.553110813
Short name T1157
Test name
Test status
Simulation time 16289477 ps
CPU time 0.94 seconds
Started Oct 15 12:09:08 PM UTC 24
Finished Oct 15 12:09:10 PM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553110813 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.553110813
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_host_error_intr.3354390004
Short name T1137
Test name
Test status
Simulation time 228374208 ps
CPU time 5.92 seconds
Started Oct 15 12:08:33 PM UTC 24
Finished Oct 15 12:08:40 PM UTC 24
Peak memory 261220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354390004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.3354390004
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_fmt_empty.3640591977
Short name T1152
Test name
Test status
Simulation time 7327356482 ps
CPU time 36.26 seconds
Started Oct 15 12:08:28 PM UTC 24
Finished Oct 15 12:09:06 PM UTC 24
Peak memory 353144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640591977 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empty.3640591977
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_full.2243969708
Short name T1205
Test name
Test status
Simulation time 8673449055 ps
CPU time 114.94 seconds
Started Oct 15 12:08:29 PM UTC 24
Finished Oct 15 12:10:26 PM UTC 24
Peak memory 558408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243969708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2243969708
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_overflow.1324670699
Short name T1149
Test name
Test status
Simulation time 1390730009 ps
CPU time 34.53 seconds
Started Oct 15 12:08:27 PM UTC 24
Finished Oct 15 12:09:03 PM UTC 24
Peak memory 377672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324670699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1324670699
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_fmt.1842693670
Short name T1132
Test name
Test status
Simulation time 436458573 ps
CPU time 1.04 seconds
Started Oct 15 12:08:28 PM UTC 24
Finished Oct 15 12:08:30 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842693670 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fmt.1842693670
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_rx.442937683
Short name T1133
Test name
Test status
Simulation time 466447992 ps
CPU time 3.36 seconds
Started Oct 15 12:08:28 PM UTC 24
Finished Oct 15 12:08:33 PM UTC 24
Peak memory 232384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442937683 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.442937683
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_watermark.3497722765
Short name T1187
Test name
Test status
Simulation time 2880115802 ps
CPU time 94.36 seconds
Started Oct 15 12:08:27 PM UTC 24
Finished Oct 15 12:10:03 PM UTC 24
Peak memory 947192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497722765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.3497722765
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_host_may_nack.1104394486
Short name T266
Test name
Test status
Simulation time 3355807602 ps
CPU time 17.35 seconds
Started Oct 15 12:09:02 PM UTC 24
Finished Oct 15 12:09:20 PM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104394486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.1104394486
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_host_override.291066568
Short name T1131
Test name
Test status
Simulation time 43047786 ps
CPU time 1.01 seconds
Started Oct 15 12:08:26 PM UTC 24
Finished Oct 15 12:08:28 PM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291066568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.291066568
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_host_perf.1595265147
Short name T1243
Test name
Test status
Simulation time 6584048562 ps
CPU time 169.99 seconds
Started Oct 15 12:08:30 PM UTC 24
Finished Oct 15 12:11:23 PM UTC 24
Peak memory 687048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595265147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1595265147
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_host_perf_precise.2449766837
Short name T1141
Test name
Test status
Simulation time 302847398 ps
CPU time 17.98 seconds
Started Oct 15 12:08:31 PM UTC 24
Finished Oct 15 12:08:51 PM UTC 24
Peak memory 271220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449766837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.2449766837
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_host_smoke.3444623126
Short name T1164
Test name
Test status
Simulation time 1354845943 ps
CPU time 53.53 seconds
Started Oct 15 12:08:25 PM UTC 24
Finished Oct 15 12:09:20 PM UTC 24
Peak memory 314368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444623126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.3444623126
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_host_stress_all.1476108352
Short name T253
Test name
Test status
Simulation time 28636544873 ps
CPU time 409.68 seconds
Started Oct 15 12:08:34 PM UTC 24
Finished Oct 15 12:15:28 PM UTC 24
Peak memory 1330316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476108352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.1476108352
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_host_stretch_timeout.3174859770
Short name T1140
Test name
Test status
Simulation time 943241434 ps
CPU time 16.66 seconds
Started Oct 15 12:08:32 PM UTC 24
Finished Oct 15 12:08:50 PM UTC 24
Peak memory 232756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174859770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.3174859770
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_bad_addr.3624890326
Short name T1155
Test name
Test status
Simulation time 1934381115 ps
CPU time 7.68 seconds
Started Oct 15 12:08:59 PM UTC 24
Finished Oct 15 12:09:07 PM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3624890326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_bad_ad
dr.3624890326
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_acq.1968154511
Short name T1144
Test name
Test status
Simulation time 182102328 ps
CPU time 1.81 seconds
Started Oct 15 12:08:53 PM UTC 24
Finished Oct 15 12:08:56 PM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968154
511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_acq.1968154511
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_tx.1187760197
Short name T1145
Test name
Test status
Simulation time 690080214 ps
CPU time 1.75 seconds
Started Oct 15 12:08:55 PM UTC 24
Finished Oct 15 12:08:58 PM UTC 24
Peak memory 217580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187760
197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_tx.1187760197
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_acq.402454373
Short name T1156
Test name
Test status
Simulation time 1903658241 ps
CPU time 4.87 seconds
Started Oct 15 12:09:04 PM UTC 24
Finished Oct 15 12:09:10 PM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024543
73 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_watermark
s_acq.402454373
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_tx.1898659555
Short name T1153
Test name
Test status
Simulation time 618081187 ps
CPU time 2.18 seconds
Started Oct 15 12:09:04 PM UTC 24
Finished Oct 15 12:09:07 PM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898659
555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_watermark
s_tx.1898659555
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_intr_smoke.2495232419
Short name T1146
Test name
Test status
Simulation time 1037321022 ps
CPU time 9 seconds
Started Oct 15 12:08:49 PM UTC 24
Finished Oct 15 12:08:59 PM UTC 24
Peak memory 229708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249523
2419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_smoke.2495232419
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_intr_stress_wr.2675753171
Short name T1171
Test name
Test status
Simulation time 20642491409 ps
CPU time 45.32 seconds
Started Oct 15 12:08:50 PM UTC 24
Finished Oct 15 12:09:37 PM UTC 24
Peak memory 871428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2675753171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_stres
s_wr.2675753171
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull.1664472213
Short name T1159
Test name
Test status
Simulation time 2041411442 ps
CPU time 5.39 seconds
Started Oct 15 12:09:07 PM UTC 24
Finished Oct 15 12:09:14 PM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664472
213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_acqfull.1664472213
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull_addr.808872310
Short name T1160
Test name
Test status
Simulation time 2094693856 ps
CPU time 4.81 seconds
Started Oct 15 12:09:08 PM UTC 24
Finished Oct 15 12:09:14 PM UTC 24
Peak memory 215300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8088723
10 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_acqfull_addr.808872310
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_perf.2912671117
Short name T1154
Test name
Test status
Simulation time 842180334 ps
CPU time 9.62 seconds
Started Oct 15 12:08:56 PM UTC 24
Finished Oct 15 12:09:07 PM UTC 24
Peak memory 231776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912671
117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_perf.2912671117
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_smbus_maxlen.1599292402
Short name T1158
Test name
Test status
Simulation time 2032939260 ps
CPU time 4.71 seconds
Started Oct 15 12:09:05 PM UTC 24
Finished Oct 15 12:09:11 PM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599292
402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smbus_maxlen.1599292402
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_smoke.41699389
Short name T1147
Test name
Test status
Simulation time 6254899806 ps
CPU time 23.87 seconds
Started Oct 15 12:08:35 PM UTC 24
Finished Oct 15 12:09:00 PM UTC 24
Peak memory 229788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41699389 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smoke.41699389
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_stress_all.669602986
Short name T1273
Test name
Test status
Simulation time 17346686160 ps
CPU time 196.11 seconds
Started Oct 15 12:08:56 PM UTC 24
Finished Oct 15 12:12:16 PM UTC 24
Peak memory 2331640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669602
986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_all.669602986
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_stress_rd.2633955732
Short name T1143
Test name
Test status
Simulation time 1598559205 ps
CPU time 11.96 seconds
Started Oct 15 12:08:42 PM UTC 24
Finished Oct 15 12:08:55 PM UTC 24
Peak memory 230176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633955732 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_rd.2633955732
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.339946026
Short name T1163
Test name
Test status
Simulation time 13312482919 ps
CPU time 36.62 seconds
Started Oct 15 12:08:41 PM UTC 24
Finished Oct 15 12:09:19 PM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339946026 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_wr.339946026
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_timeout.836844306
Short name T1150
Test name
Test status
Simulation time 1858474022 ps
CPU time 11.16 seconds
Started Oct 15 12:08:51 PM UTC 24
Finished Oct 15 12:09:03 PM UTC 24
Peak memory 232328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8368443
06 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_timeout.836844306
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/32.i2c_target_tx_stretch_ctrl.2122770653
Short name T1161
Test name
Test status
Simulation time 675145531 ps
CPU time 9.83 seconds
Started Oct 15 12:09:04 PM UTC 24
Finished Oct 15 12:09:15 PM UTC 24
Peak memory 226088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122770
653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.2122770653
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_alert_test.1378464665
Short name T1126
Test name
Test status
Simulation time 25745703 ps
CPU time 0.85 seconds
Started Oct 15 12:10:01 PM UTC 24
Finished Oct 15 12:10:03 PM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378464665 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.1378464665
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_host_error_intr.242884267
Short name T1169
Test name
Test status
Simulation time 81624839 ps
CPU time 4.29 seconds
Started Oct 15 12:09:21 PM UTC 24
Finished Oct 15 12:09:27 PM UTC 24
Peak memory 227964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242884267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.242884267
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_fmt_empty.3420025905
Short name T1168
Test name
Test status
Simulation time 1352731134 ps
CPU time 9.1 seconds
Started Oct 15 12:09:15 PM UTC 24
Finished Oct 15 12:09:26 PM UTC 24
Peak memory 285500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420025905 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empty.3420025905
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_full.1199243241
Short name T1260
Test name
Test status
Simulation time 3214311670 ps
CPU time 152.3 seconds
Started Oct 15 12:09:16 PM UTC 24
Finished Oct 15 12:11:51 PM UTC 24
Peak memory 361488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199243241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.1199243241
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_overflow.510062118
Short name T1248
Test name
Test status
Simulation time 7753420301 ps
CPU time 132.01 seconds
Started Oct 15 12:09:13 PM UTC 24
Finished Oct 15 12:11:27 PM UTC 24
Peak memory 691148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510062118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.510062118
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_fmt.393224472
Short name T1162
Test name
Test status
Simulation time 353572045 ps
CPU time 1.64 seconds
Started Oct 15 12:09:15 PM UTC 24
Finished Oct 15 12:09:18 PM UTC 24
Peak memory 212772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393224472 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fmt.393224472
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_rx.1893005252
Short name T1167
Test name
Test status
Simulation time 2596488064 ps
CPU time 7.49 seconds
Started Oct 15 12:09:15 PM UTC 24
Finished Oct 15 12:09:24 PM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893005252 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.1893005252
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_watermark.2857758009
Short name T1334
Test name
Test status
Simulation time 5010422685 ps
CPU time 285.41 seconds
Started Oct 15 12:09:12 PM UTC 24
Finished Oct 15 12:14:01 PM UTC 24
Peak memory 1498372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857758009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.2857758009
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_host_may_nack.4220089263
Short name T1199
Test name
Test status
Simulation time 1303753256 ps
CPU time 17.89 seconds
Started Oct 15 12:09:53 PM UTC 24
Finished Oct 15 12:10:12 PM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220089263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.4220089263
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_host_mode_toggle.1874300555
Short name T1181
Test name
Test status
Simulation time 269353151 ps
CPU time 5.82 seconds
Started Oct 15 12:09:50 PM UTC 24
Finished Oct 15 12:09:56 PM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874300555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1874300555
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_host_override.3534490156
Short name T147
Test name
Test status
Simulation time 66771313 ps
CPU time 1.01 seconds
Started Oct 15 12:09:12 PM UTC 24
Finished Oct 15 12:09:14 PM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534490156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3534490156
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_host_perf.324441029
Short name T1212
Test name
Test status
Simulation time 3642892602 ps
CPU time 73.12 seconds
Started Oct 15 12:09:19 PM UTC 24
Finished Oct 15 12:10:34 PM UTC 24
Peak memory 263032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324441029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.324441029
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_host_perf_precise.3374720470
Short name T1165
Test name
Test status
Simulation time 97107718 ps
CPU time 1.64 seconds
Started Oct 15 12:09:19 PM UTC 24
Finished Oct 15 12:09:22 PM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374720470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.3374720470
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_host_smoke.509472322
Short name T1177
Test name
Test status
Simulation time 1446314176 ps
CPU time 34.64 seconds
Started Oct 15 12:09:10 PM UTC 24
Finished Oct 15 12:09:47 PM UTC 24
Peak memory 359232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509472322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.509472322
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_host_stretch_timeout.4268253499
Short name T1172
Test name
Test status
Simulation time 4482185932 ps
CPU time 15.9 seconds
Started Oct 15 12:09:20 PM UTC 24
Finished Oct 15 12:09:38 PM UTC 24
Peak memory 229928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268253499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.4268253499
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_bad_addr.757950352
Short name T1185
Test name
Test status
Simulation time 1393495315 ps
CPU time 11.92 seconds
Started Oct 15 12:09:46 PM UTC 24
Finished Oct 15 12:09:59 PM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=757950352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.757950352
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_acq.1959853548
Short name T1174
Test name
Test status
Simulation time 2553619635 ps
CPU time 2.04 seconds
Started Oct 15 12:09:40 PM UTC 24
Finished Oct 15 12:09:43 PM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959853
548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_acq.1959853548
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_tx.3986428713
Short name T1176
Test name
Test status
Simulation time 704901776 ps
CPU time 2.67 seconds
Started Oct 15 12:09:42 PM UTC 24
Finished Oct 15 12:09:46 PM UTC 24
Peak memory 215664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986428
713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_tx.3986428713
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_acq.2660139819
Short name T1186
Test name
Test status
Simulation time 595463626 ps
CPU time 5.12 seconds
Started Oct 15 12:09:55 PM UTC 24
Finished Oct 15 12:10:01 PM UTC 24
Peak memory 215704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660139
819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_watermar
ks_acq.2660139819
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_tx.4005957048
Short name T1184
Test name
Test status
Simulation time 362284965 ps
CPU time 1.9 seconds
Started Oct 15 12:09:56 PM UTC 24
Finished Oct 15 12:09:59 PM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005957
048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_watermark
s_tx.4005957048
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_intr_smoke.4065841481
Short name T1175
Test name
Test status
Simulation time 953299089 ps
CPU time 9.79 seconds
Started Oct 15 12:09:33 PM UTC 24
Finished Oct 15 12:09:44 PM UTC 24
Peak memory 229732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406584
1481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_smoke.4065841481
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_intr_stress_wr.1819146889
Short name T1231
Test name
Test status
Simulation time 14476792805 ps
CPU time 68.14 seconds
Started Oct 15 12:09:38 PM UTC 24
Finished Oct 15 12:10:48 PM UTC 24
Peak memory 1827720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1819146889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_stres
s_wr.1819146889
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull.3750194032
Short name T1192
Test name
Test status
Simulation time 2295131484 ps
CPU time 5.82 seconds
Started Oct 15 12:09:59 PM UTC 24
Finished Oct 15 12:10:06 PM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750194
032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_acqfull.3750194032
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull_addr.3452276094
Short name T1193
Test name
Test status
Simulation time 2340413128 ps
CPU time 4.73 seconds
Started Oct 15 12:10:00 PM UTC 24
Finished Oct 15 12:10:06 PM UTC 24
Peak memory 215552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452276
094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_acqfull_ad
dr.3452276094
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_nack_txstretch.3073400935
Short name T1189
Test name
Test status
Simulation time 186620685 ps
CPU time 2.83 seconds
Started Oct 15 12:10:00 PM UTC 24
Finished Oct 15 12:10:04 PM UTC 24
Peak memory 232392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073400
935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_txstretch.3073400935
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_perf.541988087
Short name T1180
Test name
Test status
Simulation time 1271958567 ps
CPU time 8.65 seconds
Started Oct 15 12:09:44 PM UTC 24
Finished Oct 15 12:09:54 PM UTC 24
Peak memory 231900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5419880
87 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_perf.541988087
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_smbus_maxlen.690013758
Short name T1191
Test name
Test status
Simulation time 3927689190 ps
CPU time 4.77 seconds
Started Oct 15 12:09:59 PM UTC 24
Finished Oct 15 12:10:05 PM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6900137
58 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smbus_maxlen.690013758
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_smoke.3886602801
Short name T1182
Test name
Test status
Simulation time 845589602 ps
CPU time 33.3 seconds
Started Oct 15 12:09:23 PM UTC 24
Finished Oct 15 12:09:58 PM UTC 24
Peak memory 226012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886602801 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smoke.3886602801
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_stress_all.981697596
Short name T1315
Test name
Test status
Simulation time 27488701192 ps
CPU time 235.64 seconds
Started Oct 15 12:09:45 PM UTC 24
Finished Oct 15 12:13:45 PM UTC 24
Peak memory 2913212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981697
596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_all.981697596
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_stress_rd.3870012948
Short name T1173
Test name
Test status
Simulation time 2551537072 ps
CPU time 11.45 seconds
Started Oct 15 12:09:27 PM UTC 24
Finished Oct 15 12:09:39 PM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870012948 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_rd.3870012948
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_stress_wr.1174033994
Short name T1194
Test name
Test status
Simulation time 35764809370 ps
CPU time 40.16 seconds
Started Oct 15 12:09:25 PM UTC 24
Finished Oct 15 12:10:06 PM UTC 24
Peak memory 750460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174033994 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_wr.1174033994
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_stretch.785164739
Short name T1170
Test name
Test status
Simulation time 695390941 ps
CPU time 3.48 seconds
Started Oct 15 12:09:28 PM UTC 24
Finished Oct 15 12:09:32 PM UTC 24
Peak memory 228408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785164739 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stretch.785164739
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_timeout.1055374905
Short name T1179
Test name
Test status
Simulation time 1313205690 ps
CPU time 12.58 seconds
Started Oct 15 12:09:38 PM UTC 24
Finished Oct 15 12:09:52 PM UTC 24
Peak memory 226020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055374
905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_timeout.1055374905
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/33.i2c_target_tx_stretch_ctrl.1802236339
Short name T1190
Test name
Test status
Simulation time 198774301 ps
CPU time 6.51 seconds
Started Oct 15 12:09:57 PM UTC 24
Finished Oct 15 12:10:05 PM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802236
339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.1802236339
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_alert_test.2290032154
Short name T1226
Test name
Test status
Simulation time 26305162 ps
CPU time 0.99 seconds
Started Oct 15 12:10:43 PM UTC 24
Finished Oct 15 12:10:45 PM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290032154 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.2290032154
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_host_error_intr.2857863884
Short name T1200
Test name
Test status
Simulation time 116224736 ps
CPU time 2.11 seconds
Started Oct 15 12:10:09 PM UTC 24
Finished Oct 15 12:10:12 PM UTC 24
Peak memory 225852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857863884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.2857863884
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_fmt_empty.1578243839
Short name T1204
Test name
Test status
Simulation time 1350742919 ps
CPU time 17.34 seconds
Started Oct 15 12:10:06 PM UTC 24
Finished Oct 15 12:10:24 PM UTC 24
Peak memory 269116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578243839 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empty.1578243839
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_full.3318615096
Short name T1238
Test name
Test status
Simulation time 6745131886 ps
CPU time 59.1 seconds
Started Oct 15 12:10:07 PM UTC 24
Finished Oct 15 12:11:08 PM UTC 24
Peak memory 322764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318615096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.3318615096
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_overflow.3594485439
Short name T1286
Test name
Test status
Simulation time 8472233480 ps
CPU time 147.61 seconds
Started Oct 15 12:10:05 PM UTC 24
Finished Oct 15 12:12:35 PM UTC 24
Peak memory 732364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594485439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3594485439
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_fmt.2605866830
Short name T1196
Test name
Test status
Simulation time 170402156 ps
CPU time 1.39 seconds
Started Oct 15 12:10:06 PM UTC 24
Finished Oct 15 12:10:08 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605866830 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fmt.2605866830
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_rx.1929334344
Short name T1201
Test name
Test status
Simulation time 159316248 ps
CPU time 12.7 seconds
Started Oct 15 12:10:07 PM UTC 24
Finished Oct 15 12:10:21 PM UTC 24
Peak memory 244592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929334344 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.1929334344
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_watermark.3776082978
Short name T1341
Test name
Test status
Simulation time 8346528491 ps
CPU time 246.05 seconds
Started Oct 15 12:10:05 PM UTC 24
Finished Oct 15 12:14:14 PM UTC 24
Peak memory 1281280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776082978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.3776082978
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_host_may_nack.3433117285
Short name T1223
Test name
Test status
Simulation time 3089118778 ps
CPU time 6.74 seconds
Started Oct 15 12:10:36 PM UTC 24
Finished Oct 15 12:10:44 PM UTC 24
Peak memory 214844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433117285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.3433117285
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_host_override.1901452185
Short name T1195
Test name
Test status
Simulation time 42669032 ps
CPU time 0.98 seconds
Started Oct 15 12:10:04 PM UTC 24
Finished Oct 15 12:10:06 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901452185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1901452185
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_host_perf.3164716840
Short name T1210
Test name
Test status
Simulation time 8120427066 ps
CPU time 24.46 seconds
Started Oct 15 12:10:07 PM UTC 24
Finished Oct 15 12:10:33 PM UTC 24
Peak memory 428924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164716840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.3164716840
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_host_perf_precise.3658431200
Short name T1198
Test name
Test status
Simulation time 92702899 ps
CPU time 1.84 seconds
Started Oct 15 12:10:07 PM UTC 24
Finished Oct 15 12:10:10 PM UTC 24
Peak memory 215476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658431200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.3658431200
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_host_smoke.6449421
Short name T1232
Test name
Test status
Simulation time 6874440556 ps
CPU time 42.35 seconds
Started Oct 15 12:10:04 PM UTC 24
Finished Oct 15 12:10:48 PM UTC 24
Peak memory 347172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6449421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_hos
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.6449421
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_host_stretch_timeout.143988602
Short name T1218
Test name
Test status
Simulation time 667968268 ps
CPU time 30.56 seconds
Started Oct 15 12:10:09 PM UTC 24
Finished Oct 15 12:10:41 PM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143988602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.143988602
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_bad_addr.1324533963
Short name T1221
Test name
Test status
Simulation time 5384431721 ps
CPU time 8.49 seconds
Started Oct 15 12:10:33 PM UTC 24
Finished Oct 15 12:10:43 PM UTC 24
Peak memory 231896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1324533963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_bad_ad
dr.1324533963
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_acq.4206194370
Short name T1211
Test name
Test status
Simulation time 168923180 ps
CPU time 1.15 seconds
Started Oct 15 12:10:32 PM UTC 24
Finished Oct 15 12:10:34 PM UTC 24
Peak memory 213512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206194
370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_acq.4206194370
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_tx.4262392150
Short name T1214
Test name
Test status
Simulation time 479955003 ps
CPU time 1.96 seconds
Started Oct 15 12:10:33 PM UTC 24
Finished Oct 15 12:10:36 PM UTC 24
Peak memory 225496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262392
150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_tx.4262392150
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_acq.722380487
Short name T1220
Test name
Test status
Simulation time 415736727 ps
CPU time 4.23 seconds
Started Oct 15 12:10:37 PM UTC 24
Finished Oct 15 12:10:42 PM UTC 24
Peak memory 215044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7223804
87 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_watermark
s_acq.722380487
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_tx.3213801812
Short name T1219
Test name
Test status
Simulation time 288373483 ps
CPU time 1.84 seconds
Started Oct 15 12:10:39 PM UTC 24
Finished Oct 15 12:10:41 PM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213801
812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_watermark
s_tx.3213801812
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_intr_smoke.1359524648
Short name T1208
Test name
Test status
Simulation time 3919758911 ps
CPU time 8.39 seconds
Started Oct 15 12:10:23 PM UTC 24
Finished Oct 15 12:10:32 PM UTC 24
Peak memory 232656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135952
4648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_smoke.1359524648
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_intr_stress_wr.3349521278
Short name T1268
Test name
Test status
Simulation time 7880434168 ps
CPU time 90.7 seconds
Started Oct 15 12:10:24 PM UTC 24
Finished Oct 15 12:11:56 PM UTC 24
Peak memory 2118524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3349521278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_stres
s_wr.3349521278
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull.1789384008
Short name T1230
Test name
Test status
Simulation time 6250189520 ps
CPU time 4.98 seconds
Started Oct 15 12:10:42 PM UTC 24
Finished Oct 15 12:10:48 PM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789384
008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_acqfull.1789384008
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull_addr.2875627509
Short name T1227
Test name
Test status
Simulation time 497524055 ps
CPU time 3.95 seconds
Started Oct 15 12:10:42 PM UTC 24
Finished Oct 15 12:10:47 PM UTC 24
Peak memory 215412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875627
509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_acqfull_ad
dr.2875627509
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_nack_txstretch.2111481745
Short name T1224
Test name
Test status
Simulation time 258716801 ps
CPU time 1.49 seconds
Started Oct 15 12:10:42 PM UTC 24
Finished Oct 15 12:10:44 PM UTC 24
Peak memory 232716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111481
745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_txstretch.2111481745
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_perf.3263894449
Short name T1217
Test name
Test status
Simulation time 2702846832 ps
CPU time 6.3 seconds
Started Oct 15 12:10:33 PM UTC 24
Finished Oct 15 12:10:40 PM UTC 24
Peak memory 231944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263894
449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_perf.3263894449
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_smbus_maxlen.2271720320
Short name T1225
Test name
Test status
Simulation time 1906494403 ps
CPU time 2.75 seconds
Started Oct 15 12:10:41 PM UTC 24
Finished Oct 15 12:10:44 PM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271720
320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smbus_maxlen.2271720320
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_smoke.950374545
Short name T1234
Test name
Test status
Simulation time 4652534515 ps
CPU time 48.42 seconds
Started Oct 15 12:10:11 PM UTC 24
Finished Oct 15 12:11:01 PM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950374545 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smoke.950374545
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_stress_all.205807880
Short name T1483
Test name
Test status
Simulation time 34642158274 ps
CPU time 458.08 seconds
Started Oct 15 12:10:33 PM UTC 24
Finished Oct 15 12:18:16 PM UTC 24
Peak memory 6593616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205807
880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_all.205807880
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_stress_rd.2155301841
Short name T1215
Test name
Test status
Simulation time 18741680601 ps
CPU time 24.81 seconds
Started Oct 15 12:10:13 PM UTC 24
Finished Oct 15 12:10:39 PM UTC 24
Peak memory 248716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155301841 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_rd.2155301841
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_stress_wr.3008988448
Short name T1203
Test name
Test status
Simulation time 7167639108 ps
CPU time 9.75 seconds
Started Oct 15 12:10:12 PM UTC 24
Finished Oct 15 12:10:23 PM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008988448 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_wr.3008988448
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_stretch.4284930542
Short name T1206
Test name
Test status
Simulation time 1519521027 ps
CPU time 8.14 seconds
Started Oct 15 12:10:22 PM UTC 24
Finished Oct 15 12:10:31 PM UTC 24
Peak memory 275264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284930542 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stretch.4284930542
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/34.i2c_target_timeout.373235327
Short name T1213
Test name
Test status
Simulation time 4640589256 ps
CPU time 9.23 seconds
Started Oct 15 12:10:25 PM UTC 24
Finished Oct 15 12:10:35 PM UTC 24
Peak memory 232456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732353
27 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_timeout.373235327
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/34.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_alert_test.1880557097
Short name T1257
Test name
Test status
Simulation time 40971386 ps
CPU time 0.95 seconds
Started Oct 15 12:11:37 PM UTC 24
Finished Oct 15 12:11:39 PM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880557097 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.1880557097
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_host_error_intr.944967734
Short name T1233
Test name
Test status
Simulation time 241201873 ps
CPU time 2.33 seconds
Started Oct 15 12:10:49 PM UTC 24
Finished Oct 15 12:10:53 PM UTC 24
Peak memory 226228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944967734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.944967734
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_fmt_empty.765970851
Short name T1237
Test name
Test status
Simulation time 1070170664 ps
CPU time 15.61 seconds
Started Oct 15 12:10:46 PM UTC 24
Finished Oct 15 12:11:03 PM UTC 24
Peak memory 334724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765970851 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empty.765970851
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_full.880315934
Short name T1292
Test name
Test status
Simulation time 6402895103 ps
CPU time 111.01 seconds
Started Oct 15 12:10:49 PM UTC 24
Finished Oct 15 12:12:42 PM UTC 24
Peak memory 560196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880315934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.880315934
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_overflow.2651897410
Short name T1222
Test name
Test status
Simulation time 1802197256 ps
CPU time 63.58 seconds
Started Oct 15 12:10:45 PM UTC 24
Finished Oct 15 12:11:51 PM UTC 24
Peak memory 662604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651897410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2651897410
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_fmt.2829730865
Short name T1229
Test name
Test status
Simulation time 275687045 ps
CPU time 1.42 seconds
Started Oct 15 12:10:45 PM UTC 24
Finished Oct 15 12:10:48 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829730865 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fmt.2829730865
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_rx.2175811624
Short name T1235
Test name
Test status
Simulation time 883175596 ps
CPU time 12.62 seconds
Started Oct 15 12:10:48 PM UTC 24
Finished Oct 15 12:11:02 PM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175811624 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx.2175811624
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_watermark.854730793
Short name T1399
Test name
Test status
Simulation time 8999000606 ps
CPU time 299.52 seconds
Started Oct 15 12:10:45 PM UTC 24
Finished Oct 15 12:15:49 PM UTC 24
Peak memory 1366980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854730793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.854730793
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_host_may_nack.1626684769
Short name T1259
Test name
Test status
Simulation time 2353444445 ps
CPU time 10.2 seconds
Started Oct 15 12:11:28 PM UTC 24
Finished Oct 15 12:11:40 PM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626684769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.1626684769
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_host_mode_toggle.2614717654
Short name T1250
Test name
Test status
Simulation time 68783578 ps
CPU time 3.02 seconds
Started Oct 15 12:11:28 PM UTC 24
Finished Oct 15 12:11:32 PM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614717654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.2614717654
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_host_override.2052559082
Short name T1228
Test name
Test status
Simulation time 15518258 ps
CPU time 0.98 seconds
Started Oct 15 12:10:45 PM UTC 24
Finished Oct 15 12:10:47 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052559082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2052559082
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_host_perf.1308070867
Short name T1465
Test name
Test status
Simulation time 7231253354 ps
CPU time 411.49 seconds
Started Oct 15 12:10:49 PM UTC 24
Finished Oct 15 12:17:46 PM UTC 24
Peak memory 1626856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308070867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.1308070867
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_host_perf_precise.2098772988
Short name T1249
Test name
Test status
Simulation time 2426348191 ps
CPU time 39.31 seconds
Started Oct 15 12:10:49 PM UTC 24
Finished Oct 15 12:11:30 PM UTC 24
Peak memory 235948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098772988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.2098772988
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_host_smoke.4189357608
Short name T1242
Test name
Test status
Simulation time 2190777162 ps
CPU time 37.12 seconds
Started Oct 15 12:10:44 PM UTC 24
Finished Oct 15 12:11:23 PM UTC 24
Peak memory 314316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189357608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.4189357608
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_host_stretch_timeout.1941416559
Short name T1236
Test name
Test status
Simulation time 1161728430 ps
CPU time 11.73 seconds
Started Oct 15 12:10:49 PM UTC 24
Finished Oct 15 12:11:02 PM UTC 24
Peak memory 227744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941416559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.1941416559
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_bad_addr.3645759491
Short name T1256
Test name
Test status
Simulation time 1937302485 ps
CPU time 8.49 seconds
Started Oct 15 12:11:27 PM UTC 24
Finished Oct 15 12:11:37 PM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3645759491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_ad
dr.3645759491
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_acq.2221181565
Short name T1245
Test name
Test status
Simulation time 480744860 ps
CPU time 1.63 seconds
Started Oct 15 12:11:24 PM UTC 24
Finished Oct 15 12:11:26 PM UTC 24
Peak memory 225180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221181
565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_acq.2221181565
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_tx.2011671677
Short name T1247
Test name
Test status
Simulation time 274784428 ps
CPU time 2.1 seconds
Started Oct 15 12:11:24 PM UTC 24
Finished Oct 15 12:11:27 PM UTC 24
Peak memory 214896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011671
677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_tx.2011671677
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_acq.1875819441
Short name T1255
Test name
Test status
Simulation time 965445745 ps
CPU time 4.74 seconds
Started Oct 15 12:11:30 PM UTC 24
Finished Oct 15 12:11:36 PM UTC 24
Peak memory 215496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875819
441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_watermar
ks_acq.1875819441
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_tx.2605224884
Short name T1254
Test name
Test status
Simulation time 97732381 ps
CPU time 1.62 seconds
Started Oct 15 12:11:33 PM UTC 24
Finished Oct 15 12:11:36 PM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605224
884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_watermark
s_tx.2605224884
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_hrst.411487977
Short name T1251
Test name
Test status
Simulation time 393344026 ps
CPU time 4.88 seconds
Started Oct 15 12:11:27 PM UTC 24
Finished Oct 15 12:11:33 PM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114879
77 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_hrst.411487977
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_intr_smoke.2064443688
Short name T1240
Test name
Test status
Simulation time 6036644001 ps
CPU time 11.12 seconds
Started Oct 15 12:11:08 PM UTC 24
Finished Oct 15 12:11:21 PM UTC 24
Peak memory 232352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206444
3688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_smoke.2064443688
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_intr_stress_wr.460678354
Short name T1269
Test name
Test status
Simulation time 16513214078 ps
CPU time 35.61 seconds
Started Oct 15 12:11:21 PM UTC 24
Finished Oct 15 12:11:58 PM UTC 24
Peak memory 740228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=460678354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_stress
_wr.460678354
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull.445534174
Short name T1262
Test name
Test status
Simulation time 778460668 ps
CPU time 4.82 seconds
Started Oct 15 12:11:36 PM UTC 24
Finished Oct 15 12:11:42 PM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4455341
74 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_acqfull.445534174
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull_addr.2108118823
Short name T1261
Test name
Test status
Simulation time 1680082347 ps
CPU time 4.21 seconds
Started Oct 15 12:11:36 PM UTC 24
Finished Oct 15 12:11:41 PM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108118
823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_acqfull_ad
dr.2108118823
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_perf.1656518828
Short name T1252
Test name
Test status
Simulation time 2254759139 ps
CPU time 7.62 seconds
Started Oct 15 12:11:25 PM UTC 24
Finished Oct 15 12:11:34 PM UTC 24
Peak memory 226080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656518
828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_perf.1656518828
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_smbus_maxlen.260558585
Short name T1258
Test name
Test status
Simulation time 442920124 ps
CPU time 3.95 seconds
Started Oct 15 12:11:35 PM UTC 24
Finished Oct 15 12:11:39 PM UTC 24
Peak memory 215164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605585
85 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smbus_maxlen.260558585
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_smoke.3792522059
Short name T1244
Test name
Test status
Simulation time 2090786986 ps
CPU time 20.21 seconds
Started Oct 15 12:11:02 PM UTC 24
Finished Oct 15 12:11:24 PM UTC 24
Peak memory 226016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792522059 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smoke.3792522059
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_stress_all.2040854516
Short name T1336
Test name
Test status
Simulation time 30548997782 ps
CPU time 155.01 seconds
Started Oct 15 12:11:26 PM UTC 24
Finished Oct 15 12:14:03 PM UTC 24
Peak memory 2077956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204085
4516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_all.2040854516
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_stress_rd.513574767
Short name T1246
Test name
Test status
Simulation time 765247867 ps
CPU time 21.92 seconds
Started Oct 15 12:11:03 PM UTC 24
Finished Oct 15 12:11:26 PM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513574767 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_rd.513574767
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_stress_wr.1945226578
Short name T1241
Test name
Test status
Simulation time 11216596547 ps
CPU time 18.61 seconds
Started Oct 15 12:11:02 PM UTC 24
Finished Oct 15 12:11:22 PM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945226578 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_wr.1945226578
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_stretch.81104560
Short name T1239
Test name
Test status
Simulation time 1212820313 ps
CPU time 13.98 seconds
Started Oct 15 12:11:04 PM UTC 24
Finished Oct 15 12:11:20 PM UTC 24
Peak memory 251048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81104560 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stretch.81104560
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_timeout.141757463
Short name T1253
Test name
Test status
Simulation time 1199189375 ps
CPU time 12.16 seconds
Started Oct 15 12:11:22 PM UTC 24
Finished Oct 15 12:11:35 PM UTC 24
Peak memory 227684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417574
63 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_timeout.141757463
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/35.i2c_target_tx_stretch_ctrl.4255232089
Short name T1265
Test name
Test status
Simulation time 382379396 ps
CPU time 9.89 seconds
Started Oct 15 12:11:34 PM UTC 24
Finished Oct 15 12:11:44 PM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255232
089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.4255232089
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_alert_test.2746517398
Short name T1294
Test name
Test status
Simulation time 20172094 ps
CPU time 1.05 seconds
Started Oct 15 12:12:41 PM UTC 24
Finished Oct 15 12:12:43 PM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746517398 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2746517398
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_host_error_intr.4082122644
Short name T1207
Test name
Test status
Simulation time 586137570 ps
CPU time 1.88 seconds
Started Oct 15 12:11:52 PM UTC 24
Finished Oct 15 12:11:55 PM UTC 24
Peak memory 215588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082122644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.4082122644
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_fmt_empty.1571271986
Short name T1267
Test name
Test status
Simulation time 1504994499 ps
CPU time 12.02 seconds
Started Oct 15 12:11:42 PM UTC 24
Finished Oct 15 12:11:55 PM UTC 24
Peak memory 322436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571271986 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empty.1571271986
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_full.1622944210
Short name T1310
Test name
Test status
Simulation time 5533318934 ps
CPU time 114.52 seconds
Started Oct 15 12:11:43 PM UTC 24
Finished Oct 15 12:13:40 PM UTC 24
Peak memory 648464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622944210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.1622944210
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_overflow.365946706
Short name T1348
Test name
Test status
Simulation time 5525675754 ps
CPU time 167.34 seconds
Started Oct 15 12:11:40 PM UTC 24
Finished Oct 15 12:14:30 PM UTC 24
Peak memory 894144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365946706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.365946706
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_fmt.3990506614
Short name T1264
Test name
Test status
Simulation time 382888654 ps
CPU time 1.71 seconds
Started Oct 15 12:11:41 PM UTC 24
Finished Oct 15 12:11:44 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990506614 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fmt.3990506614
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_rx.3226519050
Short name T1266
Test name
Test status
Simulation time 172123895 ps
CPU time 5.87 seconds
Started Oct 15 12:11:42 PM UTC 24
Finished Oct 15 12:11:49 PM UTC 24
Peak memory 215652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226519050 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.3226519050
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_watermark.76139477
Short name T1369
Test name
Test status
Simulation time 15162641527 ps
CPU time 203.9 seconds
Started Oct 15 12:11:40 PM UTC 24
Finished Oct 15 12:15:07 PM UTC 24
Peak memory 1184776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76139477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.76139477
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_host_may_nack.1586055127
Short name T1283
Test name
Test status
Simulation time 1370428510 ps
CPU time 5.49 seconds
Started Oct 15 12:12:25 PM UTC 24
Finished Oct 15 12:12:32 PM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586055127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.1586055127
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_host_override.3917109360
Short name T1263
Test name
Test status
Simulation time 56344249 ps
CPU time 1.1 seconds
Started Oct 15 12:11:40 PM UTC 24
Finished Oct 15 12:11:42 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917109360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.3917109360
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_host_perf.2111369978
Short name T1311
Test name
Test status
Simulation time 2753820191 ps
CPU time 114.22 seconds
Started Oct 15 12:11:45 PM UTC 24
Finished Oct 15 12:13:41 PM UTC 24
Peak memory 240508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111369978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.2111369978
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_host_perf_precise.3527625013
Short name T1299
Test name
Test status
Simulation time 24562235352 ps
CPU time 68.41 seconds
Started Oct 15 12:11:46 PM UTC 24
Finished Oct 15 12:12:56 PM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527625013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.3527625013
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_host_smoke.2269307487
Short name T1270
Test name
Test status
Simulation time 1444517798 ps
CPU time 24.23 seconds
Started Oct 15 12:11:38 PM UTC 24
Finished Oct 15 12:12:03 PM UTC 24
Peak memory 320720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269307487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.2269307487
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_host_stretch_timeout.918058135
Short name T1271
Test name
Test status
Simulation time 532175188 ps
CPU time 14.01 seconds
Started Oct 15 12:11:50 PM UTC 24
Finished Oct 15 12:12:05 PM UTC 24
Peak memory 225612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918058135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.918058135
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_bad_addr.1815633516
Short name T1284
Test name
Test status
Simulation time 1202433704 ps
CPU time 10.9 seconds
Started Oct 15 12:12:21 PM UTC 24
Finished Oct 15 12:12:33 PM UTC 24
Peak memory 229788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1815633516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_bad_ad
dr.1815633516
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_acq.1379169088
Short name T1280
Test name
Test status
Simulation time 288525293 ps
CPU time 1.83 seconds
Started Oct 15 12:12:17 PM UTC 24
Finished Oct 15 12:12:20 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379169
088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_acq.1379169088
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_tx.3517517550
Short name T1281
Test name
Test status
Simulation time 276512648 ps
CPU time 2 seconds
Started Oct 15 12:12:18 PM UTC 24
Finished Oct 15 12:12:21 PM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517517
550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_tx.3517517550
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_acq.2515076358
Short name T1285
Test name
Test status
Simulation time 604163899 ps
CPU time 4.39 seconds
Started Oct 15 12:12:28 PM UTC 24
Finished Oct 15 12:12:34 PM UTC 24
Peak memory 215444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515076
358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_watermar
ks_acq.2515076358
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_tx.3509482469
Short name T1287
Test name
Test status
Simulation time 432443738 ps
CPU time 1.96 seconds
Started Oct 15 12:12:32 PM UTC 24
Finished Oct 15 12:12:36 PM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509482
469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_watermark
s_tx.3509482469
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_intr_smoke.1963663958
Short name T1275
Test name
Test status
Simulation time 1051919754 ps
CPU time 10.87 seconds
Started Oct 15 12:12:04 PM UTC 24
Finished Oct 15 12:12:16 PM UTC 24
Peak memory 230056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196366
3958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_smoke.1963663958
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_intr_stress_wr.787926047
Short name T1276
Test name
Test status
Simulation time 22607497103 ps
CPU time 12.3 seconds
Started Oct 15 12:12:05 PM UTC 24
Finished Oct 15 12:12:19 PM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=787926047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_stress
_wr.787926047
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull.3993071241
Short name T1290
Test name
Test status
Simulation time 934636760 ps
CPU time 4.87 seconds
Started Oct 15 12:12:36 PM UTC 24
Finished Oct 15 12:12:41 PM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993071
241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_acqfull.3993071241
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull_addr.3501888813
Short name T1291
Test name
Test status
Simulation time 3818376545 ps
CPU time 3.94 seconds
Started Oct 15 12:12:37 PM UTC 24
Finished Oct 15 12:12:42 PM UTC 24
Peak memory 215476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501888
813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_acqfull_ad
dr.3501888813
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_perf.2112553707
Short name T1282
Test name
Test status
Simulation time 438438657 ps
CPU time 6.03 seconds
Started Oct 15 12:12:20 PM UTC 24
Finished Oct 15 12:12:27 PM UTC 24
Peak memory 225936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112553
707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_perf.2112553707
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_smbus_maxlen.519187072
Short name T1289
Test name
Test status
Simulation time 467874266 ps
CPU time 4.06 seconds
Started Oct 15 12:12:34 PM UTC 24
Finished Oct 15 12:12:40 PM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5191870
72 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smbus_maxlen.519187072
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_smoke.1329662322
Short name T1272
Test name
Test status
Simulation time 2028556898 ps
CPU time 8.72 seconds
Started Oct 15 12:11:56 PM UTC 24
Finished Oct 15 12:12:06 PM UTC 24
Peak memory 225676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329662322 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smoke.1329662322
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_stress_all.2847584201
Short name T1317
Test name
Test status
Simulation time 42536106318 ps
CPU time 84.41 seconds
Started Oct 15 12:12:20 PM UTC 24
Finished Oct 15 12:13:46 PM UTC 24
Peak memory 248764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284758
4201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_all.2847584201
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_stress_rd.2222103046
Short name T1274
Test name
Test status
Simulation time 675075862 ps
CPU time 17.79 seconds
Started Oct 15 12:11:57 PM UTC 24
Finished Oct 15 12:12:16 PM UTC 24
Peak memory 227812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222103046 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_rd.2222103046
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_stress_wr.3348249644
Short name T1305
Test name
Test status
Simulation time 19798859172 ps
CPU time 86.98 seconds
Started Oct 15 12:11:56 PM UTC 24
Finished Oct 15 12:13:25 PM UTC 24
Peak memory 215968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348249644 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_wr.3348249644
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_stretch.871991380
Short name T1304
Test name
Test status
Simulation time 3527514846 ps
CPU time 84.68 seconds
Started Oct 15 12:11:58 PM UTC 24
Finished Oct 15 12:13:25 PM UTC 24
Peak memory 568256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871991380 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stretch.871991380
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_timeout.3243446012
Short name T1277
Test name
Test status
Simulation time 2547904724 ps
CPU time 11.5 seconds
Started Oct 15 12:12:06 PM UTC 24
Finished Oct 15 12:12:19 PM UTC 24
Peak memory 242556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243446
012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_timeout.3243446012
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/36.i2c_target_tx_stretch_ctrl.2032265600
Short name T1288
Test name
Test status
Simulation time 78456960 ps
CPU time 2.82 seconds
Started Oct 15 12:12:34 PM UTC 24
Finished Oct 15 12:12:39 PM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032265
600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.2032265600
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_alert_test.3642478694
Short name T1325
Test name
Test status
Simulation time 18129217 ps
CPU time 0.92 seconds
Started Oct 15 12:13:52 PM UTC 24
Finished Oct 15 12:13:54 PM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642478694 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.3642478694
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_host_error_intr.949288681
Short name T1302
Test name
Test status
Simulation time 616342559 ps
CPU time 3.69 seconds
Started Oct 15 12:13:07 PM UTC 24
Finished Oct 15 12:13:11 PM UTC 24
Peak memory 225792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949288681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.949288681
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_fmt_empty.176158604
Short name T1300
Test name
Test status
Simulation time 224489170 ps
CPU time 14.13 seconds
Started Oct 15 12:12:46 PM UTC 24
Finished Oct 15 12:13:01 PM UTC 24
Peak memory 260972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176158604 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empty.176158604
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_full.2844367411
Short name T1319
Test name
Test status
Simulation time 13617295768 ps
CPU time 99.56 seconds
Started Oct 15 12:12:47 PM UTC 24
Finished Oct 15 12:14:29 PM UTC 24
Peak memory 670572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844367411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.2844367411
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_overflow.2554225131
Short name T1350
Test name
Test status
Simulation time 4985773215 ps
CPU time 110.03 seconds
Started Oct 15 12:12:44 PM UTC 24
Finished Oct 15 12:14:36 PM UTC 24
Peak memory 550220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554225131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.2554225131
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_fmt.3665381665
Short name T1297
Test name
Test status
Simulation time 296145076 ps
CPU time 1.4 seconds
Started Oct 15 12:12:44 PM UTC 24
Finished Oct 15 12:12:46 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665381665 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fmt.3665381665
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_rx.1235580683
Short name T1298
Test name
Test status
Simulation time 929509609 ps
CPU time 5.73 seconds
Started Oct 15 12:12:47 PM UTC 24
Finished Oct 15 12:12:54 PM UTC 24
Peak memory 257220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235580683 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.1235580683
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_watermark.1811432240
Short name T1372
Test name
Test status
Simulation time 2699631755 ps
CPU time 150.88 seconds
Started Oct 15 12:12:43 PM UTC 24
Finished Oct 15 12:15:16 PM UTC 24
Peak memory 857040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811432240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1811432240
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_host_may_nack.1802467222
Short name T1340
Test name
Test status
Simulation time 504752578 ps
CPU time 23.2 seconds
Started Oct 15 12:13:46 PM UTC 24
Finished Oct 15 12:14:11 PM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802467222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.1802467222
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_host_override.1456208384
Short name T1295
Test name
Test status
Simulation time 51460217 ps
CPU time 1.16 seconds
Started Oct 15 12:12:43 PM UTC 24
Finished Oct 15 12:12:45 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456208384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.1456208384
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_host_perf.3149684681
Short name T1731
Test name
Test status
Simulation time 99042746147 ps
CPU time 1370.36 seconds
Started Oct 15 12:12:55 PM UTC 24
Finished Oct 15 12:36:01 PM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149684681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3149684681
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_host_perf_precise.299020260
Short name T1301
Test name
Test status
Simulation time 734670306 ps
CPU time 7.86 seconds
Started Oct 15 12:12:56 PM UTC 24
Finished Oct 15 12:13:05 PM UTC 24
Peak memory 242484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299020260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.299020260
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_host_smoke.961502000
Short name T1303
Test name
Test status
Simulation time 2784901792 ps
CPU time 30.57 seconds
Started Oct 15 12:12:42 PM UTC 24
Finished Oct 15 12:13:14 PM UTC 24
Peak memory 336768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961502000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.961502000
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_host_stretch_timeout.3500438054
Short name T1307
Test name
Test status
Simulation time 2139698247 ps
CPU time 27.85 seconds
Started Oct 15 12:13:03 PM UTC 24
Finished Oct 15 12:13:32 PM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500438054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.3500438054
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_bad_addr.2984369331
Short name T1330
Test name
Test status
Simulation time 4887907473 ps
CPU time 12.47 seconds
Started Oct 15 12:13:43 PM UTC 24
Finished Oct 15 12:13:57 PM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2984369331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_ad
dr.2984369331
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_acq.1040488937
Short name T1313
Test name
Test status
Simulation time 141015474 ps
CPU time 1.39 seconds
Started Oct 15 12:13:40 PM UTC 24
Finished Oct 15 12:13:42 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040488
937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_acq.1040488937
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_tx.2512699872
Short name T1316
Test name
Test status
Simulation time 582166649 ps
CPU time 2.37 seconds
Started Oct 15 12:13:42 PM UTC 24
Finished Oct 15 12:13:45 PM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512699
872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_tx.2512699872
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_acq.3878439844
Short name T1322
Test name
Test status
Simulation time 187795562 ps
CPU time 1.31 seconds
Started Oct 15 12:13:47 PM UTC 24
Finished Oct 15 12:13:50 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878439
844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_watermar
ks_acq.3878439844
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_tx.956502732
Short name T1324
Test name
Test status
Simulation time 929461172 ps
CPU time 1.95 seconds
Started Oct 15 12:13:47 PM UTC 24
Finished Oct 15 12:13:50 PM UTC 24
Peak memory 213632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9565027
32 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_watermarks
_tx.956502732
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_hrst.383530209
Short name T1321
Test name
Test status
Simulation time 216104813 ps
CPU time 2.85 seconds
Started Oct 15 12:13:44 PM UTC 24
Finished Oct 15 12:13:48 PM UTC 24
Peak memory 225716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835302
09 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_hrst.383530209
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_intr_smoke.3294191953
Short name T1309
Test name
Test status
Simulation time 3224155938 ps
CPU time 6.8 seconds
Started Oct 15 12:13:29 PM UTC 24
Finished Oct 15 12:13:37 PM UTC 24
Peak memory 225756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329419
1953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_smoke.3294191953
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_intr_stress_wr.1177703184
Short name T1479
Test name
Test status
Simulation time 18042202088 ps
CPU time 278.37 seconds
Started Oct 15 12:13:32 PM UTC 24
Finished Oct 15 12:18:15 PM UTC 24
Peak memory 4592512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1177703184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_stres
s_wr.1177703184
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull.1972883862
Short name T1327
Test name
Test status
Simulation time 512641556 ps
CPU time 4.59 seconds
Started Oct 15 12:13:49 PM UTC 24
Finished Oct 15 12:13:55 PM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972883
862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_acqfull.1972883862
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull_addr.3652833720
Short name T1329
Test name
Test status
Simulation time 778088380 ps
CPU time 5.26 seconds
Started Oct 15 12:13:50 PM UTC 24
Finished Oct 15 12:13:57 PM UTC 24
Peak memory 215744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652833
720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_acqfull_ad
dr.3652833720
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_nack_txstretch.2705423777
Short name T1328
Test name
Test status
Simulation time 1211440891 ps
CPU time 2.42 seconds
Started Oct 15 12:13:52 PM UTC 24
Finished Oct 15 12:13:55 PM UTC 24
Peak memory 232592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705423
777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_txstretch.2705423777
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_perf.3366712588
Short name T1320
Test name
Test status
Simulation time 662995671 ps
CPU time 5.29 seconds
Started Oct 15 12:13:42 PM UTC 24
Finished Oct 15 12:13:48 PM UTC 24
Peak memory 232628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366712
588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_perf.3366712588
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_smbus_maxlen.1740298271
Short name T1326
Test name
Test status
Simulation time 383302980 ps
CPU time 3.37 seconds
Started Oct 15 12:13:49 PM UTC 24
Finished Oct 15 12:13:54 PM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740298
271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smbus_maxlen.1740298271
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_smoke.1717042032
Short name T1306
Test name
Test status
Simulation time 3273739884 ps
CPU time 14.97 seconds
Started Oct 15 12:13:12 PM UTC 24
Finished Oct 15 12:13:28 PM UTC 24
Peak memory 225824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717042032 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smoke.1717042032
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_stress_all.3435314046
Short name T1364
Test name
Test status
Simulation time 8491997573 ps
CPU time 65.29 seconds
Started Oct 15 12:13:43 PM UTC 24
Finished Oct 15 12:14:50 PM UTC 24
Peak memory 291772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343531
4046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_all.3435314046
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_stress_rd.3489712986
Short name T1333
Test name
Test status
Simulation time 4824312601 ps
CPU time 30.47 seconds
Started Oct 15 12:13:26 PM UTC 24
Finished Oct 15 12:13:58 PM UTC 24
Peak memory 232392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489712986 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_rd.3489712986
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_stress_wr.1730189060
Short name T1631
Test name
Test status
Simulation time 70445120538 ps
CPU time 666.16 seconds
Started Oct 15 12:13:15 PM UTC 24
Finished Oct 15 12:24:28 PM UTC 24
Peak memory 6396872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730189060 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_wr.1730189060
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_stretch.2210135348
Short name T1318
Test name
Test status
Simulation time 2363160045 ps
CPU time 19.28 seconds
Started Oct 15 12:13:26 PM UTC 24
Finished Oct 15 12:13:47 PM UTC 24
Peak memory 570244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210135348 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stretch.2210135348
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_timeout.3291650756
Short name T1323
Test name
Test status
Simulation time 5495229078 ps
CPU time 13.76 seconds
Started Oct 15 12:13:35 PM UTC 24
Finished Oct 15 12:13:50 PM UTC 24
Peak memory 232376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291650
756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_timeout.3291650756
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_tx_stretch_ctrl.547182125
Short name T1332
Test name
Test status
Simulation time 168385686 ps
CPU time 7.52 seconds
Started Oct 15 12:13:48 PM UTC 24
Finished Oct 15 12:13:57 PM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5471821
25 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.547182125
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_alert_test.3038263702
Short name T1357
Test name
Test status
Simulation time 95814939 ps
CPU time 0.94 seconds
Started Oct 15 12:14:41 PM UTC 24
Finished Oct 15 12:14:42 PM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038263702 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.3038263702
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_host_error_intr.577816371
Short name T1342
Test name
Test status
Simulation time 1657753042 ps
CPU time 9.19 seconds
Started Oct 15 12:14:05 PM UTC 24
Finished Oct 15 12:14:15 PM UTC 24
Peak memory 259292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577816371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.577816371
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_fmt_empty.3869677266
Short name T1339
Test name
Test status
Simulation time 373078110 ps
CPU time 8.74 seconds
Started Oct 15 12:13:58 PM UTC 24
Finished Oct 15 12:14:08 PM UTC 24
Peak memory 289664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869677266 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empty.3869677266
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_full.272603381
Short name T1371
Test name
Test status
Simulation time 3081386148 ps
CPU time 75.09 seconds
Started Oct 15 12:13:58 PM UTC 24
Finished Oct 15 12:15:15 PM UTC 24
Peak memory 574400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272603381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.272603381
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_overflow.3344085288
Short name T1382
Test name
Test status
Simulation time 3087318005 ps
CPU time 96.04 seconds
Started Oct 15 12:13:56 PM UTC 24
Finished Oct 15 12:15:34 PM UTC 24
Peak memory 607572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344085288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.3344085288
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_fmt.2659567827
Short name T1335
Test name
Test status
Simulation time 332048526 ps
CPU time 2.08 seconds
Started Oct 15 12:13:58 PM UTC 24
Finished Oct 15 12:14:02 PM UTC 24
Peak memory 215648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659567827 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fmt.2659567827
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_rx.2424125005
Short name T1337
Test name
Test status
Simulation time 119760429 ps
CPU time 4.95 seconds
Started Oct 15 12:13:58 PM UTC 24
Finished Oct 15 12:14:04 PM UTC 24
Peak memory 234372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424125005 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.2424125005
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_watermark.1803883240
Short name T1460
Test name
Test status
Simulation time 3527488450 ps
CPU time 207.84 seconds
Started Oct 15 12:13:56 PM UTC 24
Finished Oct 15 12:17:27 PM UTC 24
Peak memory 1070084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803883240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1803883240
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_host_may_nack.1646611290
Short name T1354
Test name
Test status
Simulation time 6092955104 ps
CPU time 7.09 seconds
Started Oct 15 12:14:31 PM UTC 24
Finished Oct 15 12:14:39 PM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646611290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.1646611290
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_host_override.3404013047
Short name T1331
Test name
Test status
Simulation time 31793313 ps
CPU time 1.09 seconds
Started Oct 15 12:13:55 PM UTC 24
Finished Oct 15 12:13:57 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404013047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3404013047
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_host_perf.3960159822
Short name T1279
Test name
Test status
Simulation time 491296689 ps
CPU time 24.8 seconds
Started Oct 15 12:13:59 PM UTC 24
Finished Oct 15 12:14:25 PM UTC 24
Peak memory 275512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960159822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.3960159822
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_host_perf_precise.1824672956
Short name T1338
Test name
Test status
Simulation time 717659901 ps
CPU time 3.44 seconds
Started Oct 15 12:14:02 PM UTC 24
Finished Oct 15 12:14:07 PM UTC 24
Peak memory 215356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824672956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.1824672956
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_host_smoke.1217741141
Short name T1293
Test name
Test status
Simulation time 7088023354 ps
CPU time 30.05 seconds
Started Oct 15 12:13:55 PM UTC 24
Finished Oct 15 12:14:26 PM UTC 24
Peak memory 414596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217741141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1217741141
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_host_stretch_timeout.2093917517
Short name T1356
Test name
Test status
Simulation time 846016350 ps
CPU time 36.72 seconds
Started Oct 15 12:14:02 PM UTC 24
Finished Oct 15 12:14:41 PM UTC 24
Peak memory 226148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093917517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.2093917517
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_bad_addr.28893147
Short name T1362
Test name
Test status
Simulation time 6768241072 ps
CPU time 14.66 seconds
Started Oct 15 12:14:30 PM UTC 24
Finished Oct 15 12:14:46 PM UTC 24
Peak memory 232528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=28893147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.28893147
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_acq.1403165503
Short name T1347
Test name
Test status
Simulation time 238452005 ps
CPU time 2.78 seconds
Started Oct 15 12:14:26 PM UTC 24
Finished Oct 15 12:14:30 PM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403165
503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_acq.1403165503
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_tx.2784993213
Short name T1346
Test name
Test status
Simulation time 145626728 ps
CPU time 1.58 seconds
Started Oct 15 12:14:27 PM UTC 24
Finished Oct 15 12:14:30 PM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784993
213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_tx.2784993213
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_acq.3456110289
Short name T1355
Test name
Test status
Simulation time 2111670934 ps
CPU time 5.25 seconds
Started Oct 15 12:14:33 PM UTC 24
Finished Oct 15 12:14:39 PM UTC 24
Peak memory 215360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456110
289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_watermar
ks_acq.3456110289
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_tx.3470143653
Short name T1352
Test name
Test status
Simulation time 441208172 ps
CPU time 1.73 seconds
Started Oct 15 12:14:34 PM UTC 24
Finished Oct 15 12:14:37 PM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470143
653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_watermark
s_tx.3470143653
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_hrst.4039107898
Short name T1351
Test name
Test status
Simulation time 5179537174 ps
CPU time 4.7 seconds
Started Oct 15 12:14:31 PM UTC 24
Finished Oct 15 12:14:37 PM UTC 24
Peak memory 225900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039107
898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_hrst.4039107898
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_intr_smoke.3008189272
Short name T1345
Test name
Test status
Simulation time 4043638676 ps
CPU time 10.17 seconds
Started Oct 15 12:14:16 PM UTC 24
Finished Oct 15 12:14:27 PM UTC 24
Peak memory 232708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300818
9272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_smoke.3008189272
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_intr_stress_wr.913433226
Short name T1409
Test name
Test status
Simulation time 10993162056 ps
CPU time 103.69 seconds
Started Oct 15 12:14:20 PM UTC 24
Finished Oct 15 12:16:06 PM UTC 24
Peak memory 2657236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=913433226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_stress
_wr.913433226
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull.4179029513
Short name T1360
Test name
Test status
Simulation time 5685242751 ps
CPU time 5.43 seconds
Started Oct 15 12:14:37 PM UTC 24
Finished Oct 15 12:14:44 PM UTC 24
Peak memory 225776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179029
513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_acqfull.4179029513
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull_addr.1448718914
Short name T1361
Test name
Test status
Simulation time 455089089 ps
CPU time 4.83 seconds
Started Oct 15 12:14:38 PM UTC 24
Finished Oct 15 12:14:44 PM UTC 24
Peak memory 215412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448718
914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_acqfull_ad
dr.1448718914
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_perf.259437261
Short name T1353
Test name
Test status
Simulation time 615792621 ps
CPU time 7.8 seconds
Started Oct 15 12:14:29 PM UTC 24
Finished Oct 15 12:14:37 PM UTC 24
Peak memory 227760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594372
61 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_perf.259437261
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_smbus_maxlen.2552863961
Short name T1358
Test name
Test status
Simulation time 503731554 ps
CPU time 4.49 seconds
Started Oct 15 12:14:37 PM UTC 24
Finished Oct 15 12:14:43 PM UTC 24
Peak memory 215172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552863
961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smbus_maxlen.2552863961
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_smoke.100069708
Short name T1278
Test name
Test status
Simulation time 815027147 ps
CPU time 15.85 seconds
Started Oct 15 12:14:08 PM UTC 24
Finished Oct 15 12:14:25 PM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100069708 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smoke.100069708
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_stress_all.274841374
Short name T1398
Test name
Test status
Simulation time 30839261594 ps
CPU time 77.23 seconds
Started Oct 15 12:14:30 PM UTC 24
Finished Oct 15 12:15:49 PM UTC 24
Peak memory 324876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274841
374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_all.274841374
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_stress_rd.3359607114
Short name T1343
Test name
Test status
Simulation time 1224618092 ps
CPU time 6.65 seconds
Started Oct 15 12:14:12 PM UTC 24
Finished Oct 15 12:14:20 PM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359607114 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_rd.3359607114
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_stress_wr.1025757033
Short name T1377
Test name
Test status
Simulation time 63923096600 ps
CPU time 76.9 seconds
Started Oct 15 12:14:10 PM UTC 24
Finished Oct 15 12:15:28 PM UTC 24
Peak memory 1262592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025757033 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_wr.1025757033
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_stretch.3028870848
Short name T1344
Test name
Test status
Simulation time 3924084751 ps
CPU time 6.23 seconds
Started Oct 15 12:14:15 PM UTC 24
Finished Oct 15 12:14:22 PM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028870848 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stretch.3028870848
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/38.i2c_target_timeout.3279517044
Short name T1349
Test name
Test status
Simulation time 6668581166 ps
CPU time 7.65 seconds
Started Oct 15 12:14:23 PM UTC 24
Finished Oct 15 12:14:32 PM UTC 24
Peak memory 232704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279517
044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_timeout.3279517044
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/38.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_alert_test.2331340030
Short name T1390
Test name
Test status
Simulation time 17298636 ps
CPU time 0.97 seconds
Started Oct 15 12:15:37 PM UTC 24
Finished Oct 15 12:15:40 PM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331340030 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.2331340030
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_host_error_intr.2234822661
Short name T1367
Test name
Test status
Simulation time 336718487 ps
CPU time 4.14 seconds
Started Oct 15 12:14:52 PM UTC 24
Finished Oct 15 12:14:58 PM UTC 24
Peak memory 225836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234822661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2234822661
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_fmt_empty.3281681343
Short name T1366
Test name
Test status
Simulation time 619663076 ps
CPU time 10.31 seconds
Started Oct 15 12:14:45 PM UTC 24
Finished Oct 15 12:14:56 PM UTC 24
Peak memory 242492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281681343 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empty.3281681343
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_full.2152650009
Short name T1439
Test name
Test status
Simulation time 1986308466 ps
CPU time 126.94 seconds
Started Oct 15 12:14:45 PM UTC 24
Finished Oct 15 12:16:54 PM UTC 24
Peak memory 525096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152650009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.2152650009
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_overflow.2024545917
Short name T1445
Test name
Test status
Simulation time 7677563619 ps
CPU time 135.78 seconds
Started Oct 15 12:14:44 PM UTC 24
Finished Oct 15 12:17:02 PM UTC 24
Peak memory 664512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024545917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2024545917
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_fmt.3817330130
Short name T1363
Test name
Test status
Simulation time 113234691 ps
CPU time 1.78 seconds
Started Oct 15 12:14:44 PM UTC 24
Finished Oct 15 12:14:47 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817330130 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fmt.3817330130
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_rx.300425817
Short name T1365
Test name
Test status
Simulation time 137014380 ps
CPU time 5.1 seconds
Started Oct 15 12:14:45 PM UTC 24
Finished Oct 15 12:14:51 PM UTC 24
Peak memory 215784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300425817 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.300425817
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_watermark.1530609068
Short name T1440
Test name
Test status
Simulation time 9862434582 ps
CPU time 129.35 seconds
Started Oct 15 12:14:43 PM UTC 24
Finished Oct 15 12:16:55 PM UTC 24
Peak memory 1361152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530609068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1530609068
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_host_may_nack.4237318031
Short name T1383
Test name
Test status
Simulation time 450738648 ps
CPU time 5.57 seconds
Started Oct 15 12:15:29 PM UTC 24
Finished Oct 15 12:15:36 PM UTC 24
Peak memory 215784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237318031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.4237318031
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_host_mode_toggle.2008040132
Short name T1380
Test name
Test status
Simulation time 58672017 ps
CPU time 2.42 seconds
Started Oct 15 12:15:29 PM UTC 24
Finished Oct 15 12:15:32 PM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008040132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.2008040132
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_host_override.1746492079
Short name T1359
Test name
Test status
Simulation time 28719166 ps
CPU time 1.09 seconds
Started Oct 15 12:14:42 PM UTC 24
Finished Oct 15 12:14:44 PM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746492079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.1746492079
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_host_perf.1728960873
Short name T1387
Test name
Test status
Simulation time 12714882739 ps
CPU time 50.35 seconds
Started Oct 15 12:14:46 PM UTC 24
Finished Oct 15 12:15:38 PM UTC 24
Peak memory 242752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728960873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.1728960873
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_host_perf_precise.328594573
Short name T1368
Test name
Test status
Simulation time 3039946392 ps
CPU time 15.78 seconds
Started Oct 15 12:14:47 PM UTC 24
Finished Oct 15 12:15:04 PM UTC 24
Peak memory 369528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328594573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.328594573
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_host_smoke.1758296786
Short name T1376
Test name
Test status
Simulation time 4132705726 ps
CPU time 42.03 seconds
Started Oct 15 12:14:42 PM UTC 24
Finished Oct 15 12:15:25 PM UTC 24
Peak memory 389932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758296786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1758296786
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_host_stretch_timeout.3494319231
Short name T1389
Test name
Test status
Simulation time 2294644763 ps
CPU time 46.45 seconds
Started Oct 15 12:14:51 PM UTC 24
Finished Oct 15 12:15:39 PM UTC 24
Peak memory 225820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494319231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.3494319231
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_bad_addr.3730651375
Short name T1379
Test name
Test status
Simulation time 1080298467 ps
CPU time 5.51 seconds
Started Oct 15 12:15:26 PM UTC 24
Finished Oct 15 12:15:32 PM UTC 24
Peak memory 225948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3730651375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_ad
dr.3730651375
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_acq.1024408451
Short name T1373
Test name
Test status
Simulation time 2572190986 ps
CPU time 2.12 seconds
Started Oct 15 12:15:18 PM UTC 24
Finished Oct 15 12:15:22 PM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024408
451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_acq.1024408451
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_tx.2482955230
Short name T1374
Test name
Test status
Simulation time 364374651 ps
CPU time 1.62 seconds
Started Oct 15 12:15:20 PM UTC 24
Finished Oct 15 12:15:23 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482955
230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_tx.2482955230
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_acq.805360427
Short name T1386
Test name
Test status
Simulation time 918912756 ps
CPU time 4.21 seconds
Started Oct 15 12:15:32 PM UTC 24
Finished Oct 15 12:15:38 PM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8053604
27 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_watermark
s_acq.805360427
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_tx.902006291
Short name T1384
Test name
Test status
Simulation time 721553144 ps
CPU time 1.87 seconds
Started Oct 15 12:15:33 PM UTC 24
Finished Oct 15 12:15:36 PM UTC 24
Peak memory 213632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9020062
91 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_watermarks
_tx.902006291
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_intr_smoke.3009981889
Short name T1378
Test name
Test status
Simulation time 6293577823 ps
CPU time 15.35 seconds
Started Oct 15 12:15:14 PM UTC 24
Finished Oct 15 12:15:31 PM UTC 24
Peak memory 244680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300998
1889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_smoke.3009981889
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_intr_stress_wr.2790339649
Short name T1401
Test name
Test status
Simulation time 26660267508 ps
CPU time 41.63 seconds
Started Oct 15 12:15:14 PM UTC 24
Finished Oct 15 12:15:57 PM UTC 24
Peak memory 895876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2790339649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_stres
s_wr.2790339649
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull.960904160
Short name T1394
Test name
Test status
Simulation time 2058286072 ps
CPU time 5.43 seconds
Started Oct 15 12:15:35 PM UTC 24
Finished Oct 15 12:15:42 PM UTC 24
Peak memory 225960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9609041
60 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_acqfull.960904160
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull_addr.1101063423
Short name T1392
Test name
Test status
Simulation time 850429638 ps
CPU time 3.57 seconds
Started Oct 15 12:15:36 PM UTC 24
Finished Oct 15 12:15:41 PM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101063
423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_acqfull_ad
dr.1101063423
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_nack_txstretch.3478491933
Short name T1393
Test name
Test status
Simulation time 151743935 ps
CPU time 2.69 seconds
Started Oct 15 12:15:37 PM UTC 24
Finished Oct 15 12:15:41 PM UTC 24
Peak memory 232260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478491
933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_txstretch.3478491933
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_perf.3775018543
Short name T1381
Test name
Test status
Simulation time 767483622 ps
CPU time 8.64 seconds
Started Oct 15 12:15:22 PM UTC 24
Finished Oct 15 12:15:32 PM UTC 24
Peak memory 232332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775018
543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_perf.3775018543
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_smbus_maxlen.1102665505
Short name T1388
Test name
Test status
Simulation time 425488741 ps
CPU time 4.43 seconds
Started Oct 15 12:15:33 PM UTC 24
Finished Oct 15 12:15:39 PM UTC 24
Peak memory 215148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102665
505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smbus_maxlen.1102665505
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_stress_all.3267769098
Short name T1598
Test name
Test status
Simulation time 55692627933 ps
CPU time 1451.79 seconds
Started Oct 15 12:15:25 PM UTC 24
Finished Oct 15 12:39:50 PM UTC 24
Peak memory 11312084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326776
9098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_all.3267769098
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_stress_rd.3882146515
Short name T1425
Test name
Test status
Simulation time 6131598213 ps
CPU time 79.54 seconds
Started Oct 15 12:15:06 PM UTC 24
Finished Oct 15 12:16:27 PM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882146515 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_rd.3882146515
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_stress_wr.2850008217
Short name T1395
Test name
Test status
Simulation time 13844352248 ps
CPU time 36.9 seconds
Started Oct 15 12:15:05 PM UTC 24
Finished Oct 15 12:15:43 PM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850008217 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_wr.2850008217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_stretch.2543006647
Short name T1370
Test name
Test status
Simulation time 1819089463 ps
CPU time 3.95 seconds
Started Oct 15 12:15:08 PM UTC 24
Finished Oct 15 12:15:13 PM UTC 24
Peak memory 244548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543006647 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stretch.2543006647
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_timeout.1368304408
Short name T1375
Test name
Test status
Simulation time 2617250734 ps
CPU time 7.84 seconds
Started Oct 15 12:15:16 PM UTC 24
Finished Oct 15 12:15:25 PM UTC 24
Peak memory 248692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368304
408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_timeout.1368304408
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_tx_stretch_ctrl.3364905696
Short name T1385
Test name
Test status
Simulation time 57661478 ps
CPU time 2.44 seconds
Started Oct 15 12:15:33 PM UTC 24
Finished Oct 15 12:15:37 PM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364905
696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.3364905696
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_alert_test.3403582483
Short name T326
Test name
Test status
Simulation time 56804941 ps
CPU time 0.93 seconds
Started Oct 15 11:42:47 AM UTC 24
Finished Oct 15 11:42:49 AM UTC 24
Peak memory 213392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403582483 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.3403582483
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_error_intr.1257662232
Short name T155
Test name
Test status
Simulation time 294987154 ps
CPU time 4.21 seconds
Started Oct 15 11:42:15 AM UTC 24
Finished Oct 15 11:42:20 AM UTC 24
Peak memory 232360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257662232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.1257662232
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_fmt_empty.3079411177
Short name T315
Test name
Test status
Simulation time 664657505 ps
CPU time 19.34 seconds
Started Oct 15 11:42:14 AM UTC 24
Finished Oct 15 11:42:35 AM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079411177 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty.3079411177
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_full.2726790085
Short name T27
Test name
Test status
Simulation time 40697035845 ps
CPU time 98.55 seconds
Started Oct 15 11:42:14 AM UTC 24
Finished Oct 15 11:43:55 AM UTC 24
Peak memory 256960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726790085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.2726790085
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_overflow.1708864429
Short name T192
Test name
Test status
Simulation time 2239990470 ps
CPU time 145.19 seconds
Started Oct 15 11:42:13 AM UTC 24
Finished Oct 15 11:44:41 AM UTC 24
Peak memory 764816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708864429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.1708864429
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_fmt.1182022796
Short name T153
Test name
Test status
Simulation time 334461662 ps
CPU time 1.65 seconds
Started Oct 15 11:42:13 AM UTC 24
Finished Oct 15 11:42:16 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182022796 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt.1182022796
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_rx.2086456157
Short name T162
Test name
Test status
Simulation time 244639614 ps
CPU time 15.97 seconds
Started Oct 15 11:42:14 AM UTC 24
Finished Oct 15 11:42:31 AM UTC 24
Peak memory 254904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086456157 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.2086456157
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_watermark.2753003756
Short name T112
Test name
Test status
Simulation time 20744124590 ps
CPU time 111.43 seconds
Started Oct 15 11:42:13 AM UTC 24
Finished Oct 15 11:44:07 AM UTC 24
Peak memory 1432964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753003756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.2753003756
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_may_nack.1990790980
Short name T267
Test name
Test status
Simulation time 1528335272 ps
CPU time 8.84 seconds
Started Oct 15 11:42:38 AM UTC 24
Finished Oct 15 11:42:48 AM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990790980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.1990790980
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_perf.3240625968
Short name T40
Test name
Test status
Simulation time 12563421258 ps
CPU time 492.27 seconds
Started Oct 15 11:42:15 AM UTC 24
Finished Oct 15 11:50:34 AM UTC 24
Peak memory 253128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240625968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3240625968
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_perf_precise.1419709280
Short name T157
Test name
Test status
Simulation time 152511283 ps
CPU time 8.48 seconds
Started Oct 15 11:42:15 AM UTC 24
Finished Oct 15 11:42:25 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419709280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.1419709280
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_smoke.4163682699
Short name T324
Test name
Test status
Simulation time 7978419480 ps
CPU time 34.56 seconds
Started Oct 15 11:42:12 AM UTC 24
Finished Oct 15 11:42:48 AM UTC 24
Peak memory 332804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163682699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.4163682699
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_host_stretch_timeout.2775022204
Short name T289
Test name
Test status
Simulation time 829317151 ps
CPU time 21.34 seconds
Started Oct 15 11:42:15 AM UTC 24
Finished Oct 15 11:42:38 AM UTC 24
Peak memory 231912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775022204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.2775022204
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_sec_cm.838679482
Short name T203
Test name
Test status
Simulation time 226016360 ps
CPU time 1.45 seconds
Started Oct 15 11:42:46 AM UTC 24
Finished Oct 15 11:42:48 AM UTC 24
Peak memory 244940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838679482 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.838679482
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_bad_addr.1705944105
Short name T319
Test name
Test status
Simulation time 3723307330 ps
CPU time 8.87 seconds
Started Oct 15 11:42:35 AM UTC 24
Finished Oct 15 11:42:45 AM UTC 24
Peak memory 232460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1705944105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1705944105
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_acq.3669034559
Short name T313
Test name
Test status
Simulation time 278051742 ps
CPU time 2.42 seconds
Started Oct 15 11:42:30 AM UTC 24
Finished Oct 15 11:42:34 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669034
559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_acq.3669034559
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_tx.3629550448
Short name T316
Test name
Test status
Simulation time 495067256 ps
CPU time 1.49 seconds
Started Oct 15 11:42:32 AM UTC 24
Finished Oct 15 11:42:36 AM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629550
448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_tx.3629550448
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_acq.1868609550
Short name T323
Test name
Test status
Simulation time 1432368484 ps
CPU time 2.82 seconds
Started Oct 15 11:42:42 AM UTC 24
Finished Oct 15 11:42:46 AM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868609
550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_watermark
s_acq.1868609550
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_tx.1072938067
Short name T322
Test name
Test status
Simulation time 47979522 ps
CPU time 1.4 seconds
Started Oct 15 11:42:43 AM UTC 24
Finished Oct 15 11:42:46 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072938
067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_watermarks
_tx.1072938067
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_intr_smoke.3103863813
Short name T314
Test name
Test status
Simulation time 1016914148 ps
CPU time 10.15 seconds
Started Oct 15 11:42:23 AM UTC 24
Finished Oct 15 11:42:34 AM UTC 24
Peak memory 232748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310386
3813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_smoke.3103863813
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_intr_stress_wr.227470969
Short name T382
Test name
Test status
Simulation time 12754460160 ps
CPU time 120.8 seconds
Started Oct 15 11:42:26 AM UTC 24
Finished Oct 15 11:44:29 AM UTC 24
Peak memory 3138500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=227470969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.227470969
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull.1545308948
Short name T328
Test name
Test status
Simulation time 508807823 ps
CPU time 4.94 seconds
Started Oct 15 11:42:45 AM UTC 24
Finished Oct 15 11:42:51 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545308
948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_acqfull.1545308948
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull_addr.1817168341
Short name T329
Test name
Test status
Simulation time 473214909 ps
CPU time 4.01 seconds
Started Oct 15 11:42:46 AM UTC 24
Finished Oct 15 11:42:51 AM UTC 24
Peak memory 215484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817168
341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.1817168341
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_nack_txstretch.3103088445
Short name T62
Test name
Test status
Simulation time 586251906 ps
CPU time 2.09 seconds
Started Oct 15 11:42:46 AM UTC 24
Finished Oct 15 11:42:49 AM UTC 24
Peak memory 232328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103088
445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_txstretch.3103088445
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_perf.1131578098
Short name T320
Test name
Test status
Simulation time 1544388186 ps
CPU time 9.23 seconds
Started Oct 15 11:42:34 AM UTC 24
Finished Oct 15 11:42:45 AM UTC 24
Peak memory 229860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131578
098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_perf.1131578098
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_smbus_maxlen.1548694152
Short name T325
Test name
Test status
Simulation time 428376240 ps
CPU time 2.54 seconds
Started Oct 15 11:42:45 AM UTC 24
Finished Oct 15 11:42:48 AM UTC 24
Peak memory 215172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548694
152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smbus_maxlen.1548694152
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_smoke.3907140395
Short name T317
Test name
Test status
Simulation time 1270530023 ps
CPU time 18.85 seconds
Started Oct 15 11:42:16 AM UTC 24
Finished Oct 15 11:42:37 AM UTC 24
Peak memory 225356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907140395 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smoke.3907140395
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_stress_all.3862536348
Short name T452
Test name
Test status
Simulation time 22092198781 ps
CPU time 262.17 seconds
Started Oct 15 11:42:35 AM UTC 24
Finished Oct 15 11:47:01 AM UTC 24
Peak memory 3968328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386253
6348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_all.3862536348
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_stress_rd.2740842546
Short name T321
Test name
Test status
Simulation time 4742670171 ps
CPU time 25.05 seconds
Started Oct 15 11:42:19 AM UTC 24
Finished Oct 15 11:42:45 AM UTC 24
Peak memory 244732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740842546 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_rd.2740842546
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_stress_wr.3181736969
Short name T60
Test name
Test status
Simulation time 39420997602 ps
CPU time 112.61 seconds
Started Oct 15 11:42:18 AM UTC 24
Finished Oct 15 11:44:13 AM UTC 24
Peak memory 1985480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181736969 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_wr.3181736969
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_timeout.2871621745
Short name T318
Test name
Test status
Simulation time 3313489339 ps
CPU time 12.98 seconds
Started Oct 15 11:42:29 AM UTC 24
Finished Oct 15 11:42:43 AM UTC 24
Peak memory 232368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871621
745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_timeout.2871621745
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/4.i2c_target_tx_stretch_ctrl.2302377736
Short name T330
Test name
Test status
Simulation time 255990643 ps
CPU time 5.74 seconds
Started Oct 15 11:42:45 AM UTC 24
Finished Oct 15 11:42:51 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302377
736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.2302377736
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_alert_test.3019490176
Short name T1405
Test name
Test status
Simulation time 17316991 ps
CPU time 0.93 seconds
Started Oct 15 12:16:16 PM UTC 24
Finished Oct 15 12:16:18 PM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019490176 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.3019490176
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_host_error_intr.4196781507
Short name T1397
Test name
Test status
Simulation time 91311992 ps
CPU time 3.07 seconds
Started Oct 15 12:15:44 PM UTC 24
Finished Oct 15 12:15:48 PM UTC 24
Peak memory 225716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196781507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.4196781507
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_fmt_empty.1629673566
Short name T1404
Test name
Test status
Simulation time 246530213 ps
CPU time 16.1 seconds
Started Oct 15 12:15:42 PM UTC 24
Finished Oct 15 12:15:59 PM UTC 24
Peak memory 250752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629673566 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empty.1629673566
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_full.3421154368
Short name T1432
Test name
Test status
Simulation time 13040997512 ps
CPU time 61.44 seconds
Started Oct 15 12:15:42 PM UTC 24
Finished Oct 15 12:16:45 PM UTC 24
Peak memory 277564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421154368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.3421154368
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_overflow.493796195
Short name T1494
Test name
Test status
Simulation time 32049050237 ps
CPU time 174.59 seconds
Started Oct 15 12:15:41 PM UTC 24
Finished Oct 15 12:18:38 PM UTC 24
Peak memory 787392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493796195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.493796195
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_fmt.333112455
Short name T1396
Test name
Test status
Simulation time 95261040 ps
CPU time 1.4 seconds
Started Oct 15 12:15:41 PM UTC 24
Finished Oct 15 12:15:43 PM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333112455 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fmt.333112455
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_rx.1433558589
Short name T1402
Test name
Test status
Simulation time 395764403 ps
CPU time 14.44 seconds
Started Oct 15 12:15:42 PM UTC 24
Finished Oct 15 12:15:57 PM UTC 24
Peak memory 252848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433558589 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.1433558589
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_watermark.3790048270
Short name T1535
Test name
Test status
Simulation time 8320707023 ps
CPU time 261.45 seconds
Started Oct 15 12:15:40 PM UTC 24
Finished Oct 15 12:20:05 PM UTC 24
Peak memory 1301644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790048270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.3790048270
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_host_may_nack.1198634508
Short name T1391
Test name
Test status
Simulation time 10157878224 ps
CPU time 9.18 seconds
Started Oct 15 12:16:08 PM UTC 24
Finished Oct 15 12:16:18 PM UTC 24
Peak memory 215592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198634508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.1198634508
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_host_override.2212268996
Short name T148
Test name
Test status
Simulation time 18080044 ps
CPU time 1.03 seconds
Started Oct 15 12:15:40 PM UTC 24
Finished Oct 15 12:15:42 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212268996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.2212268996
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_host_perf.3865565575
Short name T1729
Test name
Test status
Simulation time 25760695430 ps
CPU time 1002.33 seconds
Started Oct 15 12:15:42 PM UTC 24
Finished Oct 15 12:32:35 PM UTC 24
Peak memory 4130044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865565575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3865565575
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_host_perf_precise.1456980696
Short name T1400
Test name
Test status
Simulation time 728221027 ps
CPU time 6.42 seconds
Started Oct 15 12:15:43 PM UTC 24
Finished Oct 15 12:15:51 PM UTC 24
Peak memory 232268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456980696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.1456980696
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_host_smoke.2042415388
Short name T1403
Test name
Test status
Simulation time 1174860560 ps
CPU time 19.12 seconds
Started Oct 15 12:15:39 PM UTC 24
Finished Oct 15 12:15:59 PM UTC 24
Peak memory 347024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042415388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2042415388
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_host_stress_all.2811387645
Short name T1563
Test name
Test status
Simulation time 46724853106 ps
CPU time 331.45 seconds
Started Oct 15 12:15:49 PM UTC 24
Finished Oct 15 12:21:25 PM UTC 24
Peak memory 2124828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811387645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.2811387645
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_host_stretch_timeout.3495830502
Short name T1406
Test name
Test status
Simulation time 4068166213 ps
CPU time 15.93 seconds
Started Oct 15 12:15:44 PM UTC 24
Finished Oct 15 12:16:01 PM UTC 24
Peak memory 232036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495830502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.3495830502
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_bad_addr.981155732
Short name T1412
Test name
Test status
Simulation time 781056900 ps
CPU time 4.77 seconds
Started Oct 15 12:16:04 PM UTC 24
Finished Oct 15 12:16:10 PM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=981155732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.981155732
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_acq.1348123269
Short name T1407
Test name
Test status
Simulation time 231379815 ps
CPU time 2.34 seconds
Started Oct 15 12:16:00 PM UTC 24
Finished Oct 15 12:16:03 PM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348123
269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_acq.1348123269
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_tx.3420575529
Short name T1408
Test name
Test status
Simulation time 474046673 ps
CPU time 1.62 seconds
Started Oct 15 12:16:02 PM UTC 24
Finished Oct 15 12:16:05 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420575
529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_tx.3420575529
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_acq.432137700
Short name T1416
Test name
Test status
Simulation time 1258265141 ps
CPU time 2.82 seconds
Started Oct 15 12:16:10 PM UTC 24
Finished Oct 15 12:16:14 PM UTC 24
Peak memory 215460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4321377
00 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_watermark
s_acq.432137700
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_tx.3863103944
Short name T1415
Test name
Test status
Simulation time 75130579 ps
CPU time 1.58 seconds
Started Oct 15 12:16:11 PM UTC 24
Finished Oct 15 12:16:13 PM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863103
944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_watermark
s_tx.3863103944
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_intr_smoke.3901315187
Short name T1410
Test name
Test status
Simulation time 4768669625 ps
CPU time 7.94 seconds
Started Oct 15 12:15:58 PM UTC 24
Finished Oct 15 12:16:07 PM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390131
5187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_smoke.3901315187
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_intr_stress_wr.867456488
Short name T1414
Test name
Test status
Simulation time 5243947931 ps
CPU time 13.26 seconds
Started Oct 15 12:15:59 PM UTC 24
Finished Oct 15 12:16:13 PM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=867456488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_stress
_wr.867456488
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull.3414331143
Short name T1421
Test name
Test status
Simulation time 580427319 ps
CPU time 5.11 seconds
Started Oct 15 12:16:14 PM UTC 24
Finished Oct 15 12:16:20 PM UTC 24
Peak memory 226084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414331
143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_acqfull.3414331143
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull_addr.1552509687
Short name T1422
Test name
Test status
Simulation time 1752537259 ps
CPU time 5.27 seconds
Started Oct 15 12:16:14 PM UTC 24
Finished Oct 15 12:16:20 PM UTC 24
Peak memory 215484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552509
687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_acqfull_ad
dr.1552509687
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_nack_txstretch.162747171
Short name T1420
Test name
Test status
Simulation time 130887641 ps
CPU time 2.13 seconds
Started Oct 15 12:16:14 PM UTC 24
Finished Oct 15 12:16:17 PM UTC 24
Peak memory 232644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627471
71 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_txstretch.162747171
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_perf.2801568977
Short name T1413
Test name
Test status
Simulation time 752162670 ps
CPU time 7.33 seconds
Started Oct 15 12:16:02 PM UTC 24
Finished Oct 15 12:16:11 PM UTC 24
Peak memory 230056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801568
977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_perf.2801568977
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_smbus_maxlen.2608567678
Short name T1419
Test name
Test status
Simulation time 2270498575 ps
CPU time 3.97 seconds
Started Oct 15 12:16:12 PM UTC 24
Finished Oct 15 12:16:17 PM UTC 24
Peak memory 215564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608567
678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smbus_maxlen.2608567678
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_smoke.139178623
Short name T1418
Test name
Test status
Simulation time 920784866 ps
CPU time 28.12 seconds
Started Oct 15 12:15:49 PM UTC 24
Finished Oct 15 12:16:19 PM UTC 24
Peak memory 225860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139178623 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smoke.139178623
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_stress_all.2210151408
Short name T1430
Test name
Test status
Simulation time 8620071505 ps
CPU time 34.88 seconds
Started Oct 15 12:16:03 PM UTC 24
Finished Oct 15 12:16:39 PM UTC 24
Peak memory 242900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221015
1408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_all.2210151408
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_stress_rd.2266648001
Short name T1424
Test name
Test status
Simulation time 4113354395 ps
CPU time 29.74 seconds
Started Oct 15 12:15:52 PM UTC 24
Finished Oct 15 12:16:23 PM UTC 24
Peak memory 226140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266648001 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_rd.2266648001
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_stress_wr.1039994367
Short name T1517
Test name
Test status
Simulation time 59173304976 ps
CPU time 215.89 seconds
Started Oct 15 12:15:50 PM UTC 24
Finished Oct 15 12:19:29 PM UTC 24
Peak memory 2489216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039994367 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_wr.1039994367
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_timeout.3443326308
Short name T1411
Test name
Test status
Simulation time 4939579563 ps
CPU time 9.01 seconds
Started Oct 15 12:15:59 PM UTC 24
Finished Oct 15 12:16:09 PM UTC 24
Peak memory 232460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443326
308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_timeout.3443326308
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_target_tx_stretch_ctrl.4031421757
Short name T1417
Test name
Test status
Simulation time 99813100 ps
CPU time 3.45 seconds
Started Oct 15 12:16:11 PM UTC 24
Finished Oct 15 12:16:15 PM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031421
757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.4031421757
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_alert_test.196637627
Short name T1451
Test name
Test status
Simulation time 27287560 ps
CPU time 1.01 seconds
Started Oct 15 12:17:06 PM UTC 24
Finished Oct 15 12:17:08 PM UTC 24
Peak memory 215612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196637627 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.196637627
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_host_error_intr.2029945380
Short name T1427
Test name
Test status
Simulation time 178392407 ps
CPU time 2.37 seconds
Started Oct 15 12:16:28 PM UTC 24
Finished Oct 15 12:16:32 PM UTC 24
Peak memory 225796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029945380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.2029945380
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_fmt_empty.660574666
Short name T1428
Test name
Test status
Simulation time 227116072 ps
CPU time 13.96 seconds
Started Oct 15 12:16:20 PM UTC 24
Finished Oct 15 12:16:35 PM UTC 24
Peak memory 258948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660574666 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empty.660574666
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_full.2332428436
Short name T1514
Test name
Test status
Simulation time 31784386346 ps
CPU time 183.25 seconds
Started Oct 15 12:16:21 PM UTC 24
Finished Oct 15 12:19:27 PM UTC 24
Peak memory 646100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332428436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2332428436
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_overflow.118013014
Short name T1435
Test name
Test status
Simulation time 6591866742 ps
CPU time 31.3 seconds
Started Oct 15 12:16:19 PM UTC 24
Finished Oct 15 12:16:51 PM UTC 24
Peak memory 415044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118013014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.118013014
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_fmt.1949191772
Short name T1423
Test name
Test status
Simulation time 298871645 ps
CPU time 1.41 seconds
Started Oct 15 12:16:20 PM UTC 24
Finished Oct 15 12:16:22 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949191772 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fmt.1949191772
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_rx.3229471254
Short name T1426
Test name
Test status
Simulation time 850280187 ps
CPU time 7.11 seconds
Started Oct 15 12:16:21 PM UTC 24
Finished Oct 15 12:16:29 PM UTC 24
Peak memory 256956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229471254 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.3229471254
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_watermark.1296169367
Short name T1520
Test name
Test status
Simulation time 3284087059 ps
CPU time 189.07 seconds
Started Oct 15 12:16:18 PM UTC 24
Finished Oct 15 12:19:31 PM UTC 24
Peak memory 984388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296169367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1296169367
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_host_may_nack.3006183174
Short name T1455
Test name
Test status
Simulation time 8166750132 ps
CPU time 12.76 seconds
Started Oct 15 12:16:58 PM UTC 24
Finished Oct 15 12:17:12 PM UTC 24
Peak memory 215580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006183174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.3006183174
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_host_override.131317578
Short name T1312
Test name
Test status
Simulation time 27052630 ps
CPU time 1.04 seconds
Started Oct 15 12:16:17 PM UTC 24
Finished Oct 15 12:16:19 PM UTC 24
Peak memory 215344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131317578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.131317578
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_host_perf.2330903091
Short name T1436
Test name
Test status
Simulation time 7026996288 ps
CPU time 29.26 seconds
Started Oct 15 12:16:22 PM UTC 24
Finished Oct 15 12:16:53 PM UTC 24
Peak memory 246984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330903091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.2330903091
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_host_perf_precise.2912561985
Short name T1574
Test name
Test status
Simulation time 23230757913 ps
CPU time 319.03 seconds
Started Oct 15 12:16:23 PM UTC 24
Finished Oct 15 12:21:47 PM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912561985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.2912561985
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_host_smoke.3135590510
Short name T1434
Test name
Test status
Simulation time 1857295218 ps
CPU time 32.47 seconds
Started Oct 15 12:16:17 PM UTC 24
Finished Oct 15 12:16:51 PM UTC 24
Peak memory 348972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135590510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.3135590510
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_host_stretch_timeout.3912014389
Short name T1431
Test name
Test status
Simulation time 1872750530 ps
CPU time 19.14 seconds
Started Oct 15 12:16:23 PM UTC 24
Finished Oct 15 12:16:43 PM UTC 24
Peak memory 242312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912014389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3912014389
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_bad_addr.2927021507
Short name T1449
Test name
Test status
Simulation time 3923327468 ps
CPU time 9.19 seconds
Started Oct 15 12:16:55 PM UTC 24
Finished Oct 15 12:17:06 PM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2927021507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_ad
dr.2927021507
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_acq.2132229193
Short name T1442
Test name
Test status
Simulation time 841496815 ps
CPU time 3.11 seconds
Started Oct 15 12:16:52 PM UTC 24
Finished Oct 15 12:16:56 PM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132229
193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_acq.2132229193
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_tx.4057630265
Short name T1441
Test name
Test status
Simulation time 158165058 ps
CPU time 1.93 seconds
Started Oct 15 12:16:53 PM UTC 24
Finished Oct 15 12:16:56 PM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057630
265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_tx.4057630265
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_acq.1940604790
Short name T1447
Test name
Test status
Simulation time 516773197 ps
CPU time 5.15 seconds
Started Oct 15 12:16:59 PM UTC 24
Finished Oct 15 12:17:05 PM UTC 24
Peak memory 215704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940604
790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_watermar
ks_acq.1940604790
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_tx.2063036978
Short name T1446
Test name
Test status
Simulation time 229580838 ps
CPU time 1.8 seconds
Started Oct 15 12:17:00 PM UTC 24
Finished Oct 15 12:17:03 PM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063036
978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_watermark
s_tx.2063036978
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_intr_smoke.2166567731
Short name T1438
Test name
Test status
Simulation time 2458648123 ps
CPU time 8.51 seconds
Started Oct 15 12:16:44 PM UTC 24
Finished Oct 15 12:16:53 PM UTC 24
Peak memory 229868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216656
7731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_smoke.2166567731
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_intr_stress_wr.823698731
Short name T1505
Test name
Test status
Simulation time 24440533405 ps
CPU time 142.81 seconds
Started Oct 15 12:16:46 PM UTC 24
Finished Oct 15 12:19:11 PM UTC 24
Peak memory 2743632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=823698731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_stress
_wr.823698731
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull.2022368635
Short name T1452
Test name
Test status
Simulation time 2402692301 ps
CPU time 5.24 seconds
Started Oct 15 12:17:03 PM UTC 24
Finished Oct 15 12:17:09 PM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022368
635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_acqfull.2022368635
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull_addr.1265655977
Short name T1453
Test name
Test status
Simulation time 486291659 ps
CPU time 4.51 seconds
Started Oct 15 12:17:04 PM UTC 24
Finished Oct 15 12:17:10 PM UTC 24
Peak memory 215424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265655
977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_acqfull_ad
dr.1265655977
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_nack_txstretch.3352690803
Short name T1454
Test name
Test status
Simulation time 154132699 ps
CPU time 2.5 seconds
Started Oct 15 12:17:06 PM UTC 24
Finished Oct 15 12:17:10 PM UTC 24
Peak memory 232260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352690
803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_txstretch.3352690803
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_perf.2173093783
Short name T1444
Test name
Test status
Simulation time 1607032001 ps
CPU time 4.9 seconds
Started Oct 15 12:16:54 PM UTC 24
Finished Oct 15 12:17:00 PM UTC 24
Peak memory 217512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173093
783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_perf.2173093783
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_smbus_maxlen.2607294249
Short name T1450
Test name
Test status
Simulation time 1944702590 ps
CPU time 4.75 seconds
Started Oct 15 12:17:01 PM UTC 24
Finished Oct 15 12:17:07 PM UTC 24
Peak memory 215168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607294
249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smbus_maxlen.2607294249
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_smoke.2286192236
Short name T1437
Test name
Test status
Simulation time 4368771538 ps
CPU time 19.52 seconds
Started Oct 15 12:16:32 PM UTC 24
Finished Oct 15 12:16:53 PM UTC 24
Peak memory 225948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286192236 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smoke.2286192236
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_stress_all.2723916863
Short name T1458
Test name
Test status
Simulation time 3285114030 ps
CPU time 29.55 seconds
Started Oct 15 12:16:54 PM UTC 24
Finished Oct 15 12:17:25 PM UTC 24
Peak memory 232336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272391
6863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_all.2723916863
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_stress_rd.2740324785
Short name T1462
Test name
Test status
Simulation time 3682704758 ps
CPU time 55.16 seconds
Started Oct 15 12:16:40 PM UTC 24
Finished Oct 15 12:17:36 PM UTC 24
Peak memory 225816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740324785 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_rd.2740324785
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_stress_wr.511252392
Short name T1524
Test name
Test status
Simulation time 37459380093 ps
CPU time 174.11 seconds
Started Oct 15 12:16:36 PM UTC 24
Finished Oct 15 12:19:32 PM UTC 24
Peak memory 2290628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511252392 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_wr.511252392
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_stretch.2630448412
Short name T1433
Test name
Test status
Simulation time 309807240 ps
CPU time 6.69 seconds
Started Oct 15 12:16:41 PM UTC 24
Finished Oct 15 12:16:48 PM UTC 24
Peak memory 225956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630448412 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stretch.2630448412
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_timeout.2828913976
Short name T1443
Test name
Test status
Simulation time 959941458 ps
CPU time 9.03 seconds
Started Oct 15 12:16:49 PM UTC 24
Finished Oct 15 12:16:59 PM UTC 24
Peak memory 232232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828913
976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_timeout.2828913976
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_target_tx_stretch_ctrl.354465730
Short name T1448
Test name
Test status
Simulation time 58883854 ps
CPU time 2.45 seconds
Started Oct 15 12:17:01 PM UTC 24
Finished Oct 15 12:17:05 PM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544657
30 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.354465730
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_alert_test.1595830742
Short name T1486
Test name
Test status
Simulation time 17061841 ps
CPU time 1.02 seconds
Started Oct 15 12:18:16 PM UTC 24
Finished Oct 15 12:18:18 PM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595830742 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.1595830742
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_host_error_intr.2415281803
Short name T1461
Test name
Test status
Simulation time 1222736539 ps
CPU time 3.81 seconds
Started Oct 15 12:17:27 PM UTC 24
Finished Oct 15 12:17:32 PM UTC 24
Peak memory 227884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415281803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2415281803
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_fmt_empty.2075294359
Short name T1459
Test name
Test status
Simulation time 463092525 ps
CPU time 14.1 seconds
Started Oct 15 12:17:11 PM UTC 24
Finished Oct 15 12:17:26 PM UTC 24
Peak memory 312372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075294359 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empty.2075294359
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_full.1634471166
Short name T1509
Test name
Test status
Simulation time 6283036989 ps
CPU time 123.89 seconds
Started Oct 15 12:17:13 PM UTC 24
Finished Oct 15 12:19:19 PM UTC 24
Peak memory 705480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634471166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.1634471166
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_overflow.903334800
Short name T1480
Test name
Test status
Simulation time 2750033692 ps
CPU time 62.78 seconds
Started Oct 15 12:17:11 PM UTC 24
Finished Oct 15 12:18:15 PM UTC 24
Peak memory 890180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903334800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.903334800
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_fmt.1507654611
Short name T1456
Test name
Test status
Simulation time 121500249 ps
CPU time 1.86 seconds
Started Oct 15 12:17:11 PM UTC 24
Finished Oct 15 12:17:13 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507654611 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fmt.1507654611
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_rx.1900102429
Short name T1457
Test name
Test status
Simulation time 410112511 ps
CPU time 7.16 seconds
Started Oct 15 12:17:12 PM UTC 24
Finished Oct 15 12:17:20 PM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900102429 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.1900102429
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.4008533158
Short name T1498
Test name
Test status
Simulation time 7948733204 ps
CPU time 101.96 seconds
Started Oct 15 12:17:09 PM UTC 24
Finished Oct 15 12:18:54 PM UTC 24
Peak memory 1213700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008533158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.4008533158
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_host_may_nack.1240470804
Short name T1482
Test name
Test status
Simulation time 448294307 ps
CPU time 6.49 seconds
Started Oct 15 12:18:09 PM UTC 24
Finished Oct 15 12:18:16 PM UTC 24
Peak memory 215776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240470804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.1240470804
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_host_override.3169480432
Short name T149
Test name
Test status
Simulation time 27559996 ps
CPU time 1.08 seconds
Started Oct 15 12:17:08 PM UTC 24
Finished Oct 15 12:17:11 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169480432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.3169480432
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_host_perf.2767122106
Short name T1466
Test name
Test status
Simulation time 2631457703 ps
CPU time 34.36 seconds
Started Oct 15 12:17:14 PM UTC 24
Finished Oct 15 12:17:50 PM UTC 24
Peak memory 215780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767122106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2767122106
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_host_perf_precise.3587506103
Short name T1467
Test name
Test status
Simulation time 2336344723 ps
CPU time 28.79 seconds
Started Oct 15 12:17:21 PM UTC 24
Finished Oct 15 12:17:51 PM UTC 24
Peak memory 237932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587506103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.3587506103
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_host_smoke.2710513570
Short name T1463
Test name
Test status
Simulation time 1642799682 ps
CPU time 33.98 seconds
Started Oct 15 12:17:06 PM UTC 24
Finished Oct 15 12:17:42 PM UTC 24
Peak memory 297928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710513570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.2710513570
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_host_stretch_timeout.4103364433
Short name T1464
Test name
Test status
Simulation time 12024814278 ps
CPU time 18.25 seconds
Started Oct 15 12:17:26 PM UTC 24
Finished Oct 15 12:17:46 PM UTC 24
Peak memory 242692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103364433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.4103364433
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_bad_addr.65452951
Short name T1476
Test name
Test status
Simulation time 554002660 ps
CPU time 6.11 seconds
Started Oct 15 12:18:02 PM UTC 24
Finished Oct 15 12:18:10 PM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=65452951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.65452951
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_acq.3029291844
Short name T1470
Test name
Test status
Simulation time 492055797 ps
CPU time 2.11 seconds
Started Oct 15 12:17:58 PM UTC 24
Finished Oct 15 12:18:01 PM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029291
844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_acq.3029291844
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_tx.3051200940
Short name T1472
Test name
Test status
Simulation time 468314995 ps
CPU time 3.09 seconds
Started Oct 15 12:17:59 PM UTC 24
Finished Oct 15 12:18:03 PM UTC 24
Peak memory 226032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051200
940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_tx.3051200940
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_acq.1410685192
Short name T1478
Test name
Test status
Simulation time 1589176779 ps
CPU time 4.36 seconds
Started Oct 15 12:18:09 PM UTC 24
Finished Oct 15 12:18:14 PM UTC 24
Peak memory 215440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410685
192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_watermar
ks_acq.1410685192
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_tx.627676827
Short name T1477
Test name
Test status
Simulation time 106141097 ps
CPU time 1.86 seconds
Started Oct 15 12:18:09 PM UTC 24
Finished Oct 15 12:18:12 PM UTC 24
Peak memory 213632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6276768
27 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_watermarks
_tx.627676827
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_hrst.1567947728
Short name T1475
Test name
Test status
Simulation time 362492957 ps
CPU time 3.5 seconds
Started Oct 15 12:18:03 PM UTC 24
Finished Oct 15 12:18:08 PM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567947
728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_hrst.1567947728
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_intr_smoke.2329251113
Short name T1468
Test name
Test status
Simulation time 2537785470 ps
CPU time 8.85 seconds
Started Oct 15 12:17:47 PM UTC 24
Finished Oct 15 12:17:57 PM UTC 24
Peak memory 232692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232925
1113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_smoke.2329251113
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_intr_stress_wr.379107833
Short name T1500
Test name
Test status
Simulation time 14255772071 ps
CPU time 69.08 seconds
Started Oct 15 12:17:51 PM UTC 24
Finished Oct 15 12:19:02 PM UTC 24
Peak memory 1002448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=379107833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_stress
_wr.379107833
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull.2137529923
Short name T1489
Test name
Test status
Simulation time 3867371503 ps
CPU time 5.02 seconds
Started Oct 15 12:18:15 PM UTC 24
Finished Oct 15 12:18:21 PM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137529
923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_acqfull.2137529923
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull_addr.1069529292
Short name T1490
Test name
Test status
Simulation time 488504799 ps
CPU time 4.64 seconds
Started Oct 15 12:18:16 PM UTC 24
Finished Oct 15 12:18:22 PM UTC 24
Peak memory 215412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069529
292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_acqfull_ad
dr.1069529292
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_nack_txstretch.2992681533
Short name T1488
Test name
Test status
Simulation time 337303444 ps
CPU time 2.69 seconds
Started Oct 15 12:18:16 PM UTC 24
Finished Oct 15 12:18:20 PM UTC 24
Peak memory 232328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992681
533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_txstretch.2992681533
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_perf.134090448
Short name T1473
Test name
Test status
Simulation time 1040133939 ps
CPU time 6.54 seconds
Started Oct 15 12:18:00 PM UTC 24
Finished Oct 15 12:18:08 PM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340904
48 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_perf.134090448
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_smbus_maxlen.1343352269
Short name T1485
Test name
Test status
Simulation time 935198788 ps
CPU time 3.68 seconds
Started Oct 15 12:18:13 PM UTC 24
Finished Oct 15 12:18:18 PM UTC 24
Peak memory 215176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343352
269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smbus_maxlen.1343352269
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_smoke.2426427597
Short name T1481
Test name
Test status
Simulation time 1096691016 ps
CPU time 41.64 seconds
Started Oct 15 12:17:32 PM UTC 24
Finished Oct 15 12:18:16 PM UTC 24
Peak memory 227868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426427597 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smoke.2426427597
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.3937093765
Short name T1696
Test name
Test status
Simulation time 41605727789 ps
CPU time 498.19 seconds
Started Oct 15 12:18:01 PM UTC 24
Finished Oct 15 12:26:25 PM UTC 24
Peak memory 5604424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393709
3765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_all.3937093765
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_stress_rd.1682811407
Short name T1469
Test name
Test status
Simulation time 755930234 ps
CPU time 13.25 seconds
Started Oct 15 12:17:43 PM UTC 24
Finished Oct 15 12:17:57 PM UTC 24
Peak memory 227660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682811407 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_rd.1682811407
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.3263879357
Short name T1626
Test name
Test status
Simulation time 39433696913 ps
CPU time 398.55 seconds
Started Oct 15 12:17:38 PM UTC 24
Finished Oct 15 12:24:21 PM UTC 24
Peak memory 4740300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263879357 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_wr.3263879357
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_timeout.4038395139
Short name T1471
Test name
Test status
Simulation time 4471717788 ps
CPU time 9.85 seconds
Started Oct 15 12:17:52 PM UTC 24
Finished Oct 15 12:18:03 PM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038395
139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_timeout.4038395139
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_tx_stretch_ctrl.160255636
Short name T1484
Test name
Test status
Simulation time 134233764 ps
CPU time 5.17 seconds
Started Oct 15 12:18:11 PM UTC 24
Finished Oct 15 12:18:17 PM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602556
36 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.160255636
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_alert_test.473534015
Short name T1519
Test name
Test status
Simulation time 19204167 ps
CPU time 1.02 seconds
Started Oct 15 12:19:28 PM UTC 24
Finished Oct 15 12:19:30 PM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473534015 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.473534015
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_host_error_intr.1809585964
Short name T1495
Test name
Test status
Simulation time 182421081 ps
CPU time 3.43 seconds
Started Oct 15 12:18:35 PM UTC 24
Finished Oct 15 12:18:40 PM UTC 24
Peak memory 225724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809585964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1809585964
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_fmt_empty.2517123669
Short name T1492
Test name
Test status
Simulation time 195560086 ps
CPU time 9.4 seconds
Started Oct 15 12:18:21 PM UTC 24
Finished Oct 15 12:18:31 PM UTC 24
Peak memory 232256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517123669 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empty.2517123669
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_full.2802848989
Short name T1561
Test name
Test status
Simulation time 2430606596 ps
CPU time 167.12 seconds
Started Oct 15 12:18:22 PM UTC 24
Finished Oct 15 12:21:12 PM UTC 24
Peak memory 590776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802848989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.2802848989
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_overflow.2192797281
Short name T1533
Test name
Test status
Simulation time 1596936544 ps
CPU time 102.88 seconds
Started Oct 15 12:18:19 PM UTC 24
Finished Oct 15 12:20:04 PM UTC 24
Peak memory 609352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192797281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.2192797281
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_fmt.2114185102
Short name T1491
Test name
Test status
Simulation time 62686677 ps
CPU time 1.44 seconds
Started Oct 15 12:18:20 PM UTC 24
Finished Oct 15 12:18:22 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114185102 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fmt.2114185102
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_rx.2761051318
Short name T1493
Test name
Test status
Simulation time 363207358 ps
CPU time 12.17 seconds
Started Oct 15 12:18:21 PM UTC 24
Finished Oct 15 12:18:34 PM UTC 24
Peak memory 249084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761051318 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.2761051318
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.1609654606
Short name T1588
Test name
Test status
Simulation time 3855845228 ps
CPU time 231.58 seconds
Started Oct 15 12:18:19 PM UTC 24
Finished Oct 15 12:22:14 PM UTC 24
Peak memory 1084620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609654606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.1609654606
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_host_may_nack.2619210750
Short name T1518
Test name
Test status
Simulation time 1626608783 ps
CPU time 8.96 seconds
Started Oct 15 12:19:19 PM UTC 24
Finished Oct 15 12:19:29 PM UTC 24
Peak memory 215720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619210750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.2619210750
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_host_mode_toggle.4017751015
Short name T1512
Test name
Test status
Simulation time 179052218 ps
CPU time 3.9 seconds
Started Oct 15 12:19:19 PM UTC 24
Finished Oct 15 12:19:23 PM UTC 24
Peak memory 238732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017751015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.4017751015
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_host_override.382692307
Short name T1487
Test name
Test status
Simulation time 49033568 ps
CPU time 1.08 seconds
Started Oct 15 12:18:17 PM UTC 24
Finished Oct 15 12:18:20 PM UTC 24
Peak memory 214440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382692307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.382692307
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_host_perf.4287908320
Short name T1496
Test name
Test status
Simulation time 709251131 ps
CPU time 17.96 seconds
Started Oct 15 12:18:23 PM UTC 24
Finished Oct 15 12:18:42 PM UTC 24
Peak memory 227740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287908320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.4287908320
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_host_perf_precise.1050955350
Short name T1504
Test name
Test status
Simulation time 2503934421 ps
CPU time 45.09 seconds
Started Oct 15 12:18:23 PM UTC 24
Finished Oct 15 12:19:10 PM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050955350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.1050955350
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_host_smoke.1820320085
Short name T1529
Test name
Test status
Simulation time 1428505639 ps
CPU time 83.32 seconds
Started Oct 15 12:18:17 PM UTC 24
Finished Oct 15 12:19:43 PM UTC 24
Peak memory 383644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820320085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.1820320085
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_host_stretch_timeout.3893899913
Short name T1497
Test name
Test status
Simulation time 2833431272 ps
CPU time 14.91 seconds
Started Oct 15 12:18:32 PM UTC 24
Finished Oct 15 12:18:49 PM UTC 24
Peak memory 232720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893899913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.3893899913
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_bad_addr.369931095
Short name T1510
Test name
Test status
Simulation time 3324810994 ps
CPU time 6.54 seconds
Started Oct 15 12:19:12 PM UTC 24
Finished Oct 15 12:19:20 PM UTC 24
Peak memory 229860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=369931095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.369931095
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_acq.568682198
Short name T1503
Test name
Test status
Simulation time 355823627 ps
CPU time 1.3 seconds
Started Oct 15 12:19:07 PM UTC 24
Finished Oct 15 12:19:09 PM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5686821
98 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_acq.568682198
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_tx.2093739472
Short name T1506
Test name
Test status
Simulation time 189180019 ps
CPU time 1.93 seconds
Started Oct 15 12:19:10 PM UTC 24
Finished Oct 15 12:19:13 PM UTC 24
Peak memory 215228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093739
472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_tx.2093739472
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_acq.4221323971
Short name T1513
Test name
Test status
Simulation time 786534353 ps
CPU time 4.38 seconds
Started Oct 15 12:19:20 PM UTC 24
Finished Oct 15 12:19:25 PM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221323
971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_watermar
ks_acq.4221323971
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_tx.1300276941
Short name T1511
Test name
Test status
Simulation time 116237023 ps
CPU time 1.49 seconds
Started Oct 15 12:19:21 PM UTC 24
Finished Oct 15 12:19:23 PM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300276
941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_watermark
s_tx.1300276941
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_intr_smoke.372385540
Short name T1502
Test name
Test status
Simulation time 686074622 ps
CPU time 7.72 seconds
Started Oct 15 12:19:00 PM UTC 24
Finished Oct 15 12:19:09 PM UTC 24
Peak memory 232764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372385
540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_smoke.372385540
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_intr_stress_wr.4193561527
Short name T1589
Test name
Test status
Simulation time 23668705972 ps
CPU time 190.65 seconds
Started Oct 15 12:19:01 PM UTC 24
Finished Oct 15 12:22:15 PM UTC 24
Peak memory 2825168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4193561527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_stres
s_wr.4193561527
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull.4058877993
Short name T1523
Test name
Test status
Simulation time 563929620 ps
CPU time 5.09 seconds
Started Oct 15 12:19:26 PM UTC 24
Finished Oct 15 12:19:32 PM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058877
993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_acqfull.4058877993
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull_addr.3647669267
Short name T1525
Test name
Test status
Simulation time 1076762762 ps
CPU time 5.34 seconds
Started Oct 15 12:19:28 PM UTC 24
Finished Oct 15 12:19:35 PM UTC 24
Peak memory 215484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647669
267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_acqfull_ad
dr.3647669267
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_nack_txstretch.3845551916
Short name T1521
Test name
Test status
Simulation time 140405504 ps
CPU time 2.11 seconds
Started Oct 15 12:19:28 PM UTC 24
Finished Oct 15 12:19:31 PM UTC 24
Peak memory 232260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845551
916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_txstretch.3845551916
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_perf.2569416576
Short name T1508
Test name
Test status
Simulation time 584846790 ps
CPU time 6.8 seconds
Started Oct 15 12:19:10 PM UTC 24
Finished Oct 15 12:19:18 PM UTC 24
Peak memory 232024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569416
576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_perf.2569416576
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_smbus_maxlen.3390511998
Short name T1516
Test name
Test status
Simulation time 448498400 ps
CPU time 2.4 seconds
Started Oct 15 12:19:24 PM UTC 24
Finished Oct 15 12:19:27 PM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390511
998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smbus_maxlen.3390511998
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_smoke.2029854345
Short name T1499
Test name
Test status
Simulation time 1289422982 ps
CPU time 17.06 seconds
Started Oct 15 12:18:40 PM UTC 24
Finished Oct 15 12:18:59 PM UTC 24
Peak memory 225960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029854345 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smoke.2029854345
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.4079340565
Short name T1538
Test name
Test status
Simulation time 34629303003 ps
CPU time 59.74 seconds
Started Oct 15 12:19:10 PM UTC 24
Finished Oct 15 12:20:12 PM UTC 24
Peak memory 658416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407934
0565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_all.4079340565
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_stress_rd.3517324857
Short name T1474
Test name
Test status
Simulation time 593331059 ps
CPU time 9.54 seconds
Started Oct 15 12:18:50 PM UTC 24
Finished Oct 15 12:19:00 PM UTC 24
Peak memory 227812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517324857 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_rd.3517324857
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.1803723230
Short name T1608
Test name
Test status
Simulation time 49680964730 ps
CPU time 296.16 seconds
Started Oct 15 12:18:43 PM UTC 24
Finished Oct 15 12:23:43 PM UTC 24
Peak memory 3804028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803723230 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_wr.1803723230
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_stretch.815729599
Short name T1501
Test name
Test status
Simulation time 1262024778 ps
CPU time 6.71 seconds
Started Oct 15 12:18:55 PM UTC 24
Finished Oct 15 12:19:03 PM UTC 24
Peak memory 252852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815729599 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stretch.815729599
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_timeout.579200421
Short name T1507
Test name
Test status
Simulation time 14760327070 ps
CPU time 12.97 seconds
Started Oct 15 12:19:03 PM UTC 24
Finished Oct 15 12:19:17 PM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5792004
21 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_timeout.579200421
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_tx_stretch_ctrl.2888687586
Short name T1515
Test name
Test status
Simulation time 53266791 ps
CPU time 2.34 seconds
Started Oct 15 12:19:24 PM UTC 24
Finished Oct 15 12:19:27 PM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888687
586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.2888687586
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_alert_test.1198754815
Short name T1551
Test name
Test status
Simulation time 20505824 ps
CPU time 0.99 seconds
Started Oct 15 12:20:25 PM UTC 24
Finished Oct 15 12:20:28 PM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198754815 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.1198754815
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_host_error_intr.509393425
Short name T1532
Test name
Test status
Simulation time 426172623 ps
CPU time 8.78 seconds
Started Oct 15 12:19:42 PM UTC 24
Finished Oct 15 12:19:52 PM UTC 24
Peak memory 249108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509393425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.509393425
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_fmt_empty.1961997511
Short name T1527
Test name
Test status
Simulation time 265772316 ps
CPU time 4.87 seconds
Started Oct 15 12:19:33 PM UTC 24
Finished Oct 15 12:19:39 PM UTC 24
Peak memory 252736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961997511 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empty.1961997511
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.615783894
Short name T1562
Test name
Test status
Simulation time 3053852707 ps
CPU time 103.22 seconds
Started Oct 15 12:19:34 PM UTC 24
Finished Oct 15 12:21:19 PM UTC 24
Peak memory 592904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615783894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.615783894
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.1534906785
Short name T1549
Test name
Test status
Simulation time 2029214171 ps
CPU time 53.9 seconds
Started Oct 15 12:19:31 PM UTC 24
Finished Oct 15 12:20:27 PM UTC 24
Peak memory 730004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534906785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.1534906785
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_fmt.44141610
Short name T1526
Test name
Test status
Simulation time 1179431991 ps
CPU time 1.86 seconds
Started Oct 15 12:19:33 PM UTC 24
Finished Oct 15 12:19:36 PM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44141610 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fmt.44141610
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_rx.3035544882
Short name T1528
Test name
Test status
Simulation time 257401377 ps
CPU time 6.99 seconds
Started Oct 15 12:19:33 PM UTC 24
Finished Oct 15 12:19:41 PM UTC 24
Peak memory 240448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035544882 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.3035544882
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.2308449113
Short name T1571
Test name
Test status
Simulation time 10715598815 ps
CPU time 128.19 seconds
Started Oct 15 12:19:31 PM UTC 24
Finished Oct 15 12:21:42 PM UTC 24
Peak memory 805760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308449113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2308449113
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_host_may_nack.2778453971
Short name T1552
Test name
Test status
Simulation time 2524576802 ps
CPU time 9.62 seconds
Started Oct 15 12:20:17 PM UTC 24
Finished Oct 15 12:20:28 PM UTC 24
Peak memory 215964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778453971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.2778453971
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_host_override.1827149803
Short name T1522
Test name
Test status
Simulation time 41955714 ps
CPU time 1.04 seconds
Started Oct 15 12:19:29 PM UTC 24
Finished Oct 15 12:19:32 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827149803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.1827149803
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_host_perf.2137025836
Short name T1536
Test name
Test status
Simulation time 1530361323 ps
CPU time 29.31 seconds
Started Oct 15 12:19:35 PM UTC 24
Finished Oct 15 12:20:06 PM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137025836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2137025836
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_host_perf_precise.2942208423
Short name T1556
Test name
Test status
Simulation time 2848916446 ps
CPU time 60.49 seconds
Started Oct 15 12:19:36 PM UTC 24
Finished Oct 15 12:20:38 PM UTC 24
Peak memory 650180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942208423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.2942208423
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_host_smoke.1343662643
Short name T1531
Test name
Test status
Simulation time 5110460012 ps
CPU time 20.9 seconds
Started Oct 15 12:19:29 PM UTC 24
Finished Oct 15 12:19:52 PM UTC 24
Peak memory 281532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343662643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.1343662643
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_host_stretch_timeout.181331357
Short name T1530
Test name
Test status
Simulation time 1446611265 ps
CPU time 5.44 seconds
Started Oct 15 12:19:40 PM UTC 24
Finished Oct 15 12:19:47 PM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181331357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.181331357
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_bad_addr.2006430200
Short name T1541
Test name
Test status
Simulation time 2934290906 ps
CPU time 3.1 seconds
Started Oct 15 12:20:12 PM UTC 24
Finished Oct 15 12:20:16 PM UTC 24
Peak memory 225824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2006430200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_bad_ad
dr.2006430200
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_acq.240837571
Short name T1537
Test name
Test status
Simulation time 1469970704 ps
CPU time 1.73 seconds
Started Oct 15 12:20:07 PM UTC 24
Finished Oct 15 12:20:10 PM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408375
71 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_acq.240837571
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_acq.3381563168
Short name T1545
Test name
Test status
Simulation time 1823432746 ps
CPU time 5.09 seconds
Started Oct 15 12:20:18 PM UTC 24
Finished Oct 15 12:20:24 PM UTC 24
Peak memory 215908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381563
168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_watermar
ks_acq.3381563168
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_tx.513618574
Short name T1544
Test name
Test status
Simulation time 385287723 ps
CPU time 1.72 seconds
Started Oct 15 12:20:18 PM UTC 24
Finished Oct 15 12:20:20 PM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5136185
74 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_watermarks
_tx.513618574
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_intr_smoke.1234734210
Short name T1534
Test name
Test status
Simulation time 4146526950 ps
CPU time 8.97 seconds
Started Oct 15 12:19:54 PM UTC 24
Finished Oct 15 12:20:04 PM UTC 24
Peak memory 232172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123473
4210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_smoke.1234734210
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.2402800410
Short name T1658
Test name
Test status
Simulation time 21393258980 ps
CPU time 294.94 seconds
Started Oct 15 12:20:05 PM UTC 24
Finished Oct 15 12:25:03 PM UTC 24
Peak memory 3714188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2402800410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_stres
s_wr.2402800410
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull.1874142949
Short name T1550
Test name
Test status
Simulation time 491989709 ps
CPU time 5.03 seconds
Started Oct 15 12:20:21 PM UTC 24
Finished Oct 15 12:20:27 PM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874142
949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_acqfull.1874142949
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull_addr.1603479950
Short name T1547
Test name
Test status
Simulation time 571759102 ps
CPU time 3.48 seconds
Started Oct 15 12:20:21 PM UTC 24
Finished Oct 15 12:20:26 PM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603479
950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_acqfull_ad
dr.1603479950
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_perf.2719628343
Short name T1542
Test name
Test status
Simulation time 2229590377 ps
CPU time 6.9 seconds
Started Oct 15 12:20:10 PM UTC 24
Finished Oct 15 12:20:18 PM UTC 24
Peak memory 232584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719628
343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_perf.2719628343
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_smbus_maxlen.642015852
Short name T1546
Test name
Test status
Simulation time 460453080 ps
CPU time 4.29 seconds
Started Oct 15 12:20:19 PM UTC 24
Finished Oct 15 12:20:24 PM UTC 24
Peak memory 215168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6420158
52 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smbus_maxlen.642015852
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_smoke.1509031756
Short name T1543
Test name
Test status
Simulation time 4244641163 ps
CPU time 31.34 seconds
Started Oct 15 12:19:47 PM UTC 24
Finished Oct 15 12:20:20 PM UTC 24
Peak memory 230184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509031756 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smoke.1509031756
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.3029928842
Short name T1653
Test name
Test status
Simulation time 84155582891 ps
CPU time 2047.66 seconds
Started Oct 15 12:20:12 PM UTC 24
Finished Oct 15 12:54:40 PM UTC 24
Peak memory 11744196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302992
8842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_all.3029928842
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_stress_rd.3009553583
Short name T1539
Test name
Test status
Simulation time 875021222 ps
CPU time 18.92 seconds
Started Oct 15 12:19:52 PM UTC 24
Finished Oct 15 12:20:13 PM UTC 24
Peak memory 232324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009553583 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_rd.3009553583
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.3049307321
Short name T1725
Test name
Test status
Simulation time 40877507647 ps
CPU time 531.31 seconds
Started Oct 15 12:19:51 PM UTC 24
Finished Oct 15 12:28:49 PM UTC 24
Peak memory 5483588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049307321 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_wr.3049307321
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_timeout.1992561683
Short name T1540
Test name
Test status
Simulation time 4225179268 ps
CPU time 7.83 seconds
Started Oct 15 12:20:05 PM UTC 24
Finished Oct 15 12:20:14 PM UTC 24
Peak memory 232380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992561
683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_timeout.1992561683
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_tx_stretch_ctrl.1248935845
Short name T1548
Test name
Test status
Simulation time 239804296 ps
CPU time 7.35 seconds
Started Oct 15 12:20:18 PM UTC 24
Finished Oct 15 12:20:26 PM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248935
845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.1248935845
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_alert_test.807539847
Short name T1581
Test name
Test status
Simulation time 22665349 ps
CPU time 0.97 seconds
Started Oct 15 12:21:55 PM UTC 24
Finished Oct 15 12:21:57 PM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807539847 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.807539847
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_error_intr.1620421649
Short name T1559
Test name
Test status
Simulation time 92304462 ps
CPU time 3.8 seconds
Started Oct 15 12:20:42 PM UTC 24
Finished Oct 15 12:20:47 PM UTC 24
Peak memory 225788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620421649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.1620421649
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_fmt_empty.3558696245
Short name T1557
Test name
Test status
Simulation time 446773775 ps
CPU time 10.2 seconds
Started Oct 15 12:20:29 PM UTC 24
Finished Oct 15 12:20:41 PM UTC 24
Peak memory 310280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558696245 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empty.3558696245
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.424570786
Short name T1610
Test name
Test status
Simulation time 25535636886 ps
CPU time 191.58 seconds
Started Oct 15 12:20:31 PM UTC 24
Finished Oct 15 12:23:45 PM UTC 24
Peak memory 613308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424570786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.424570786
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.214131993
Short name T1605
Test name
Test status
Simulation time 2496889508 ps
CPU time 187.07 seconds
Started Oct 15 12:20:28 PM UTC 24
Finished Oct 15 12:23:38 PM UTC 24
Peak memory 836540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214131993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.214131993
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_fmt.1832722094
Short name T1555
Test name
Test status
Simulation time 450197471 ps
CPU time 1.86 seconds
Started Oct 15 12:20:28 PM UTC 24
Finished Oct 15 12:20:31 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832722094 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fmt.1832722094
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_rx.3193617844
Short name T1558
Test name
Test status
Simulation time 230843684 ps
CPU time 12.09 seconds
Started Oct 15 12:20:31 PM UTC 24
Finished Oct 15 12:20:44 PM UTC 24
Peak memory 215368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193617844 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.3193617844
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.790512083
Short name T1643
Test name
Test status
Simulation time 7683263810 ps
CPU time 251.38 seconds
Started Oct 15 12:20:28 PM UTC 24
Finished Oct 15 12:24:43 PM UTC 24
Peak memory 1215432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790512083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.790512083
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.151914428
Short name T1582
Test name
Test status
Simulation time 1031817161 ps
CPU time 8.71 seconds
Started Oct 15 12:21:48 PM UTC 24
Finished Oct 15 12:21:57 PM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151914428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.151914428
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_override.3019751915
Short name T1554
Test name
Test status
Simulation time 24716214 ps
CPU time 1.04 seconds
Started Oct 15 12:20:27 PM UTC 24
Finished Oct 15 12:20:30 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019751915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.3019751915
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_perf.1607090498
Short name T1560
Test name
Test status
Simulation time 7022358792 ps
CPU time 22.4 seconds
Started Oct 15 12:20:32 PM UTC 24
Finished Oct 15 12:20:55 PM UTC 24
Peak memory 324668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607090498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.1607090498
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_perf_precise.2467069310
Short name T1716
Test name
Test status
Simulation time 24252716777 ps
CPU time 379.03 seconds
Started Oct 15 12:20:33 PM UTC 24
Finished Oct 15 12:26:57 PM UTC 24
Peak memory 936776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467069310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.2467069310
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.1218223483
Short name T1585
Test name
Test status
Simulation time 1990977654 ps
CPU time 90.23 seconds
Started Oct 15 12:20:27 PM UTC 24
Finished Oct 15 12:22:00 PM UTC 24
Peak memory 396212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218223483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.1218223483
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.873726555
Short name T1564
Test name
Test status
Simulation time 4235915397 ps
CPU time 52.01 seconds
Started Oct 15 12:20:39 PM UTC 24
Finished Oct 15 12:21:33 PM UTC 24
Peak memory 225896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873726555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.873726555
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.3918568556
Short name T1553
Test name
Test status
Simulation time 4335665379 ps
CPU time 8.02 seconds
Started Oct 15 12:21:42 PM UTC 24
Finished Oct 15 12:21:51 PM UTC 24
Peak memory 225892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3918568556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_bad_ad
dr.3918568556
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_acq.971233114
Short name T1569
Test name
Test status
Simulation time 537021478 ps
CPU time 1.7 seconds
Started Oct 15 12:21:36 PM UTC 24
Finished Oct 15 12:21:39 PM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9712331
14 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_acq.971233114
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_tx.690575038
Short name T1570
Test name
Test status
Simulation time 145938153 ps
CPU time 1.6 seconds
Started Oct 15 12:21:39 PM UTC 24
Finished Oct 15 12:21:42 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6905750
38 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_tx.690575038
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.1070898932
Short name T1577
Test name
Test status
Simulation time 4753297833 ps
CPU time 3.28 seconds
Started Oct 15 12:21:48 PM UTC 24
Finished Oct 15 12:21:52 PM UTC 24
Peak memory 215560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070898
932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_watermar
ks_acq.1070898932
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.3951953623
Short name T1576
Test name
Test status
Simulation time 144874349 ps
CPU time 1.1 seconds
Started Oct 15 12:21:49 PM UTC 24
Finished Oct 15 12:21:51 PM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951953
623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_watermark
s_tx.3951953623
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_hrst.503896631
Short name T1575
Test name
Test status
Simulation time 824688558 ps
CPU time 3.15 seconds
Started Oct 15 12:21:43 PM UTC 24
Finished Oct 15 12:21:48 PM UTC 24
Peak memory 227828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5038966
31 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_hrst.503896631
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_intr_smoke.3685130652
Short name T1565
Test name
Test status
Simulation time 2047510773 ps
CPU time 5.45 seconds
Started Oct 15 12:21:27 PM UTC 24
Finished Oct 15 12:21:33 PM UTC 24
Peak memory 229788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368513
0652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_smoke.3685130652
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.448463853
Short name T1641
Test name
Test status
Simulation time 18907891187 ps
CPU time 186.88 seconds
Started Oct 15 12:21:34 PM UTC 24
Finished Oct 15 12:24:43 PM UTC 24
Peak memory 3247060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=448463853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_stress
_wr.448463853
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.2656616158
Short name T1583
Test name
Test status
Simulation time 2300764461 ps
CPU time 4.44 seconds
Started Oct 15 12:21:52 PM UTC 24
Finished Oct 15 12:21:57 PM UTC 24
Peak memory 225904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656616
158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_acqfull.2656616158
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.1373928897
Short name T1584
Test name
Test status
Simulation time 1098239043 ps
CPU time 4.77 seconds
Started Oct 15 12:21:52 PM UTC 24
Finished Oct 15 12:21:58 PM UTC 24
Peak memory 215412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373928
897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_acqfull_ad
dr.1373928897
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_perf.150970248
Short name T1573
Test name
Test status
Simulation time 866650871 ps
CPU time 6.08 seconds
Started Oct 15 12:21:39 PM UTC 24
Finished Oct 15 12:21:46 PM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509702
48 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_perf.150970248
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.762167159
Short name T1579
Test name
Test status
Simulation time 2215276070 ps
CPU time 4.77 seconds
Started Oct 15 12:21:51 PM UTC 24
Finished Oct 15 12:21:57 PM UTC 24
Peak memory 215228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7621671
59 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smbus_maxlen.762167159
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.2100187080
Short name T1567
Test name
Test status
Simulation time 4127564682 ps
CPU time 44.92 seconds
Started Oct 15 12:20:48 PM UTC 24
Finished Oct 15 12:21:35 PM UTC 24
Peak memory 232440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100187080 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smoke.2100187080
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.2087985019
Short name T1600
Test name
Test status
Simulation time 52899055266 ps
CPU time 108.47 seconds
Started Oct 15 12:21:39 PM UTC 24
Finished Oct 15 12:23:30 PM UTC 24
Peak memory 1533328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208798
5019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_all.2087985019
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.3407453286
Short name T1566
Test name
Test status
Simulation time 1547519541 ps
CPU time 20.39 seconds
Started Oct 15 12:21:12 PM UTC 24
Finished Oct 15 12:21:34 PM UTC 24
Peak memory 232268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407453286 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_rd.3407453286
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.4076643326
Short name T1732
Test name
Test status
Simulation time 56720941973 ps
CPU time 916.43 seconds
Started Oct 15 12:20:56 PM UTC 24
Finished Oct 15 12:36:21 PM UTC 24
Peak memory 9599936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076643326 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_wr.4076643326
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_stretch.3010274813
Short name T1568
Test name
Test status
Simulation time 1593687749 ps
CPU time 28.31 seconds
Started Oct 15 12:21:20 PM UTC 24
Finished Oct 15 12:21:50 PM UTC 24
Peak memory 564032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010274813 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stretch.3010274813
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.3565008166
Short name T1572
Test name
Test status
Simulation time 14870330673 ps
CPU time 10.73 seconds
Started Oct 15 12:21:34 PM UTC 24
Finished Oct 15 12:21:46 PM UTC 24
Peak memory 242668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565008
166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_timeout.3565008166
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.3657346341
Short name T1578
Test name
Test status
Simulation time 86778358 ps
CPU time 3.65 seconds
Started Oct 15 12:21:50 PM UTC 24
Finished Oct 15 12:21:54 PM UTC 24
Peak memory 215720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657346
341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.3657346341
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_alert_test.3379090941
Short name T1614
Test name
Test status
Simulation time 71861958 ps
CPU time 1.05 seconds
Started Oct 15 12:23:44 PM UTC 24
Finished Oct 15 12:23:46 PM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379090941 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.3379090941
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.2907137304
Short name T1592
Test name
Test status
Simulation time 186186388 ps
CPU time 3.13 seconds
Started Oct 15 12:22:16 PM UTC 24
Finished Oct 15 12:22:20 PM UTC 24
Peak memory 225780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907137304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.2907137304
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.3476753325
Short name T1587
Test name
Test status
Simulation time 1277929824 ps
CPU time 6.98 seconds
Started Oct 15 12:21:59 PM UTC 24
Finished Oct 15 12:22:07 PM UTC 24
Peak memory 281408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476753325 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empty.3476753325
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.651037522
Short name T1666
Test name
Test status
Simulation time 3214376271 ps
CPU time 195.6 seconds
Started Oct 15 12:22:02 PM UTC 24
Finished Oct 15 12:25:21 PM UTC 24
Peak memory 801744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651037522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.651037522
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.3714603607
Short name T1616
Test name
Test status
Simulation time 2052899327 ps
CPU time 108.22 seconds
Started Oct 15 12:21:58 PM UTC 24
Finished Oct 15 12:23:49 PM UTC 24
Peak memory 507076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714603607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.3714603607
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.965278395
Short name T1586
Test name
Test status
Simulation time 83931641 ps
CPU time 1.59 seconds
Started Oct 15 12:21:58 PM UTC 24
Finished Oct 15 12:22:01 PM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965278395 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fmt.965278395
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.2402136020
Short name T1590
Test name
Test status
Simulation time 232541064 ps
CPU time 12.9 seconds
Started Oct 15 12:22:01 PM UTC 24
Finished Oct 15 12:22:15 PM UTC 24
Peak memory 215784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402136020 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.2402136020
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.1030841947
Short name T1705
Test name
Test status
Simulation time 18515942626 ps
CPU time 270.87 seconds
Started Oct 15 12:21:58 PM UTC 24
Finished Oct 15 12:26:33 PM UTC 24
Peak memory 1324104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030841947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1030841947
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.565942174
Short name T1617
Test name
Test status
Simulation time 1523802948 ps
CPU time 15.42 seconds
Started Oct 15 12:23:33 PM UTC 24
Finished Oct 15 12:23:49 PM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565942174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.565942174
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_override.2242839489
Short name T150
Test name
Test status
Simulation time 21951469 ps
CPU time 1.04 seconds
Started Oct 15 12:21:58 PM UTC 24
Finished Oct 15 12:22:00 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242839489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.2242839489
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_perf.2426065943
Short name T1662
Test name
Test status
Simulation time 24498114384 ps
CPU time 188.62 seconds
Started Oct 15 12:22:02 PM UTC 24
Finished Oct 15 12:25:14 PM UTC 24
Peak memory 1637692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426065943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.2426065943
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.1044583067
Short name T1591
Test name
Test status
Simulation time 230869664 ps
CPU time 9.98 seconds
Started Oct 15 12:22:08 PM UTC 24
Finished Oct 15 12:22:19 PM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044583067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.1044583067
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.2496288528
Short name T1594
Test name
Test status
Simulation time 1518822511 ps
CPU time 32.13 seconds
Started Oct 15 12:21:57 PM UTC 24
Finished Oct 15 12:22:31 PM UTC 24
Peak memory 357240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496288528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.2496288528
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.1207923555
Short name T1593
Test name
Test status
Simulation time 1968932516 ps
CPU time 8.97 seconds
Started Oct 15 12:22:14 PM UTC 24
Finished Oct 15 12:22:24 PM UTC 24
Peak memory 227764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207923555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.1207923555
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.1719972364
Short name T1603
Test name
Test status
Simulation time 5073649572 ps
CPU time 9.67 seconds
Started Oct 15 12:23:23 PM UTC 24
Finished Oct 15 12:23:34 PM UTC 24
Peak memory 221932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1719972364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_ad
dr.1719972364
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.307281650
Short name T159
Test name
Test status
Simulation time 221035331 ps
CPU time 1.47 seconds
Started Oct 15 12:23:17 PM UTC 24
Finished Oct 15 12:23:20 PM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072816
50 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_acq.307281650
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.2529068158
Short name T1599
Test name
Test status
Simulation time 392498845 ps
CPU time 1.88 seconds
Started Oct 15 12:23:19 PM UTC 24
Finished Oct 15 12:23:22 PM UTC 24
Peak memory 225576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529068
158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_tx.2529068158
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.2819682544
Short name T1607
Test name
Test status
Simulation time 1336864243 ps
CPU time 3.63 seconds
Started Oct 15 12:23:35 PM UTC 24
Finished Oct 15 12:23:39 PM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819682
544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_watermar
ks_acq.2819682544
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.3059420484
Short name T1606
Test name
Test status
Simulation time 136049611 ps
CPU time 2.49 seconds
Started Oct 15 12:23:36 PM UTC 24
Finished Oct 15 12:23:39 PM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059420
484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_watermark
s_tx.3059420484
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.2485553899
Short name T1597
Test name
Test status
Simulation time 5552396135 ps
CPU time 11.68 seconds
Started Oct 15 12:23:04 PM UTC 24
Finished Oct 15 12:23:16 PM UTC 24
Peak memory 232384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248555
3899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_smoke.2485553899
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.985654124
Short name T1624
Test name
Test status
Simulation time 13988358114 ps
CPU time 46.16 seconds
Started Oct 15 12:23:16 PM UTC 24
Finished Oct 15 12:24:03 PM UTC 24
Peak memory 818052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=985654124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_stress
_wr.985654124
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.652395418
Short name T1613
Test name
Test status
Simulation time 1139245653 ps
CPU time 5.17 seconds
Started Oct 15 12:23:40 PM UTC 24
Finished Oct 15 12:23:46 PM UTC 24
Peak memory 225344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6523954
18 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_acqfull.652395418
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.610549185
Short name T1611
Test name
Test status
Simulation time 1907658407 ps
CPU time 4.42 seconds
Started Oct 15 12:23:40 PM UTC 24
Finished Oct 15 12:23:45 PM UTC 24
Peak memory 215408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6105491
85 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_acqfull_addr.610549185
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_nack_txstretch.2127230619
Short name T1612
Test name
Test status
Simulation time 263247861 ps
CPU time 2.56 seconds
Started Oct 15 12:23:42 PM UTC 24
Finished Oct 15 12:23:46 PM UTC 24
Peak memory 232388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127230
619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_txstretch.2127230619
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_perf.1913939468
Short name T1601
Test name
Test status
Simulation time 819653804 ps
CPU time 9.34 seconds
Started Oct 15 12:23:20 PM UTC 24
Finished Oct 15 12:23:31 PM UTC 24
Peak memory 225884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913939
468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_perf.1913939468
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.4244309321
Short name T1609
Test name
Test status
Simulation time 2048531512 ps
CPU time 4.72 seconds
Started Oct 15 12:23:39 PM UTC 24
Finished Oct 15 12:23:45 PM UTC 24
Peak memory 215184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244309
321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smbus_maxlen.4244309321
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.2507648595
Short name T1595
Test name
Test status
Simulation time 5875138397 ps
CPU time 40.37 seconds
Started Oct 15 12:22:20 PM UTC 24
Finished Oct 15 12:23:02 PM UTC 24
Peak memory 232628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507648595 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smoke.2507648595
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.3452984636
Short name T1730
Test name
Test status
Simulation time 92915308345 ps
CPU time 731.79 seconds
Started Oct 15 12:23:22 PM UTC 24
Finished Oct 15 12:35:42 PM UTC 24
Peak memory 6665288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345298
4636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_all.3452984636
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.4034323813
Short name T1604
Test name
Test status
Simulation time 5292482294 ps
CPU time 70.15 seconds
Started Oct 15 12:22:25 PM UTC 24
Finished Oct 15 12:23:37 PM UTC 24
Peak memory 231972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034323813 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_rd.4034323813
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.478792871
Short name T1596
Test name
Test status
Simulation time 37977846946 ps
CPU time 53.12 seconds
Started Oct 15 12:22:21 PM UTC 24
Finished Oct 15 12:23:16 PM UTC 24
Peak memory 1248456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478792871 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_wr.478792871
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.1572225000
Short name T1602
Test name
Test status
Simulation time 1457355253 ps
CPU time 15.01 seconds
Started Oct 15 12:23:16 PM UTC 24
Finished Oct 15 12:23:32 PM UTC 24
Peak memory 232320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572225
000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_timeout.1572225000
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.14455334
Short name T1622
Test name
Test status
Simulation time 1017368996 ps
CPU time 19.95 seconds
Started Oct 15 12:23:39 PM UTC 24
Finished Oct 15 12:24:00 PM UTC 24
Peak memory 225836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445533
4 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.14455334
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_alert_test.2231268143
Short name T1648
Test name
Test status
Simulation time 43382166 ps
CPU time 1.02 seconds
Started Oct 15 12:24:45 PM UTC 24
Finished Oct 15 12:24:47 PM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231268143 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.2231268143
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.3776341071
Short name T1623
Test name
Test status
Simulation time 1178387639 ps
CPU time 3.29 seconds
Started Oct 15 12:23:57 PM UTC 24
Finished Oct 15 12:24:02 PM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776341071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.3776341071
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.3744143103
Short name T1619
Test name
Test status
Simulation time 130748498 ps
CPU time 3.99 seconds
Started Oct 15 12:23:48 PM UTC 24
Finished Oct 15 12:23:53 PM UTC 24
Peak memory 232516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744143103 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empty.3744143103
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.2870675512
Short name T1691
Test name
Test status
Simulation time 12428757241 ps
CPU time 120.46 seconds
Started Oct 15 12:23:50 PM UTC 24
Finished Oct 15 12:25:53 PM UTC 24
Peak memory 678788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870675512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.2870675512
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.1899035244
Short name T1634
Test name
Test status
Simulation time 1641572192 ps
CPU time 45.35 seconds
Started Oct 15 12:23:46 PM UTC 24
Finished Oct 15 12:24:33 PM UTC 24
Peak memory 615312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899035244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1899035244
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.3804286927
Short name T1618
Test name
Test status
Simulation time 491023137 ps
CPU time 1.91 seconds
Started Oct 15 12:23:48 PM UTC 24
Finished Oct 15 12:23:51 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804286927 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fmt.3804286927
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.953045362
Short name T1620
Test name
Test status
Simulation time 729588615 ps
CPU time 6.17 seconds
Started Oct 15 12:23:49 PM UTC 24
Finished Oct 15 12:23:56 PM UTC 24
Peak memory 215656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953045362 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.953045362
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.3872909265
Short name T1672
Test name
Test status
Simulation time 66455187124 ps
CPU time 97.59 seconds
Started Oct 15 12:23:46 PM UTC 24
Finished Oct 15 12:25:26 PM UTC 24
Peak memory 1604868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872909265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.3872909265
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.2654053741
Short name T1646
Test name
Test status
Simulation time 447568194 ps
CPU time 8.06 seconds
Started Oct 15 12:24:38 PM UTC 24
Finished Oct 15 12:24:47 PM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654053741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.2654053741
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_override.1111275930
Short name T1615
Test name
Test status
Simulation time 89361103 ps
CPU time 1 seconds
Started Oct 15 12:23:46 PM UTC 24
Finished Oct 15 12:23:48 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111275930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.1111275930
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_perf.1297055931
Short name T1629
Test name
Test status
Simulation time 3248917849 ps
CPU time 35.24 seconds
Started Oct 15 12:23:50 PM UTC 24
Finished Oct 15 12:24:27 PM UTC 24
Peak memory 249168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297055931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.1297055931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.1125857080
Short name T1621
Test name
Test status
Simulation time 286900994 ps
CPU time 4.14 seconds
Started Oct 15 12:23:51 PM UTC 24
Finished Oct 15 12:23:56 PM UTC 24
Peak memory 215660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125857080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.1125857080
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.1781724891
Short name T1661
Test name
Test status
Simulation time 9556582342 ps
CPU time 82.83 seconds
Started Oct 15 12:23:45 PM UTC 24
Finished Oct 15 12:25:10 PM UTC 24
Peak memory 363528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781724891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.1781724891
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.385423744
Short name T1625
Test name
Test status
Simulation time 3626861296 ps
CPU time 20.18 seconds
Started Oct 15 12:23:54 PM UTC 24
Finished Oct 15 12:24:15 PM UTC 24
Peak memory 242852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385423744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.385423744
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.466522807
Short name T1636
Test name
Test status
Simulation time 655354036 ps
CPU time 3.65 seconds
Started Oct 15 12:24:32 PM UTC 24
Finished Oct 15 12:24:37 PM UTC 24
Peak memory 228020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=466522807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.466522807
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.1001907386
Short name T1632
Test name
Test status
Simulation time 169672283 ps
CPU time 1.42 seconds
Started Oct 15 12:24:28 PM UTC 24
Finished Oct 15 12:24:31 PM UTC 24
Peak memory 225496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001907
386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_acq.1001907386
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.2317432976
Short name T1633
Test name
Test status
Simulation time 198808056 ps
CPU time 1.35 seconds
Started Oct 15 12:24:29 PM UTC 24
Finished Oct 15 12:24:32 PM UTC 24
Peak memory 213572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317432
976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_tx.2317432976
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.1919056696
Short name T1645
Test name
Test status
Simulation time 716291724 ps
CPU time 4.14 seconds
Started Oct 15 12:24:40 PM UTC 24
Finished Oct 15 12:24:45 PM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919056
696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_watermar
ks_acq.1919056696
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.2639818954
Short name T1642
Test name
Test status
Simulation time 93901768 ps
CPU time 1.54 seconds
Started Oct 15 12:24:41 PM UTC 24
Finished Oct 15 12:24:43 PM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639818
954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_watermark
s_tx.2639818954
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_hrst.1480875682
Short name T1639
Test name
Test status
Simulation time 315558509 ps
CPU time 4.34 seconds
Started Oct 15 12:24:34 PM UTC 24
Finished Oct 15 12:24:40 PM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480875
682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_hrst.1480875682
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.3182499581
Short name T1630
Test name
Test status
Simulation time 850005223 ps
CPU time 4.68 seconds
Started Oct 15 12:24:22 PM UTC 24
Finished Oct 15 12:24:28 PM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318249
9581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_smoke.3182499581
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.1696017991
Short name T1654
Test name
Test status
Simulation time 25235992558 ps
CPU time 26.35 seconds
Started Oct 15 12:24:25 PM UTC 24
Finished Oct 15 12:24:53 PM UTC 24
Peak memory 543676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1696017991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_stres
s_wr.1696017991
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.1183156967
Short name T1652
Test name
Test status
Simulation time 2165461399 ps
CPU time 5.46 seconds
Started Oct 15 12:24:44 PM UTC 24
Finished Oct 15 12:24:50 PM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183156
967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_acqfull.1183156967
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.793667844
Short name T1580
Test name
Test status
Simulation time 1104769283 ps
CPU time 5.48 seconds
Started Oct 15 12:24:44 PM UTC 24
Finished Oct 15 12:24:51 PM UTC 24
Peak memory 215480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7936678
44 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_acqfull_addr.793667844
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.2437023536
Short name T1649
Test name
Test status
Simulation time 545341729 ps
CPU time 2.7 seconds
Started Oct 15 12:24:44 PM UTC 24
Finished Oct 15 12:24:48 PM UTC 24
Peak memory 232300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437023
536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_txstretch.2437023536
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_perf.3399052217
Short name T1637
Test name
Test status
Simulation time 3066777657 ps
CPU time 7.74 seconds
Started Oct 15 12:24:30 PM UTC 24
Finished Oct 15 12:24:39 PM UTC 24
Peak memory 232168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399052
217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_perf.3399052217
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.333838310
Short name T1650
Test name
Test status
Simulation time 422201124 ps
CPU time 4.16 seconds
Started Oct 15 12:24:44 PM UTC 24
Finished Oct 15 12:24:49 PM UTC 24
Peak memory 215164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338383
10 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smbus_maxlen.333838310
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.1304954040
Short name T1635
Test name
Test status
Simulation time 981213874 ps
CPU time 31.82 seconds
Started Oct 15 12:24:01 PM UTC 24
Finished Oct 15 12:24:35 PM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304954040 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smoke.1304954040
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.1956327726
Short name T1722
Test name
Test status
Simulation time 29502834049 ps
CPU time 194.15 seconds
Started Oct 15 12:24:31 PM UTC 24
Finished Oct 15 12:27:49 PM UTC 24
Peak memory 2360592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195632
7726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_all.1956327726
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.2684686922
Short name T1627
Test name
Test status
Simulation time 3482764890 ps
CPU time 18.03 seconds
Started Oct 15 12:24:04 PM UTC 24
Finished Oct 15 12:24:24 PM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684686922 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_rd.2684686922
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.3692043908
Short name T1660
Test name
Test status
Simulation time 18700559370 ps
CPU time 64.68 seconds
Started Oct 15 12:24:02 PM UTC 24
Finished Oct 15 12:25:09 PM UTC 24
Peak memory 215844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692043908 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_wr.3692043908
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.2970503538
Short name T1640
Test name
Test status
Simulation time 1517863076 ps
CPU time 14.33 seconds
Started Oct 15 12:24:27 PM UTC 24
Finished Oct 15 12:24:43 PM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970503
538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_timeout.2970503538
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.3777797477
Short name T1644
Test name
Test status
Simulation time 61659663 ps
CPU time 2.35 seconds
Started Oct 15 12:24:41 PM UTC 24
Finished Oct 15 12:24:44 PM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777797
477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.3777797477
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_alert_test.2706457612
Short name T1681
Test name
Test status
Simulation time 28370306 ps
CPU time 1.01 seconds
Started Oct 15 12:25:32 PM UTC 24
Finished Oct 15 12:25:34 PM UTC 24
Peak memory 213388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706457612 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2706457612
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.2718952202
Short name T1657
Test name
Test status
Simulation time 1551275740 ps
CPU time 5.56 seconds
Started Oct 15 12:24:54 PM UTC 24
Finished Oct 15 12:25:01 PM UTC 24
Peak memory 227960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718952202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.2718952202
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.1266884466
Short name T1656
Test name
Test status
Simulation time 750161215 ps
CPU time 10.8 seconds
Started Oct 15 12:24:49 PM UTC 24
Finished Oct 15 12:25:01 PM UTC 24
Peak memory 293744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266884466 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empty.1266884466
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.1108956398
Short name T1720
Test name
Test status
Simulation time 2859821595 ps
CPU time 171.41 seconds
Started Oct 15 12:24:50 PM UTC 24
Finished Oct 15 12:27:44 PM UTC 24
Peak memory 609548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108956398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.1108956398
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.2455048931
Short name T1675
Test name
Test status
Simulation time 7568926862 ps
CPU time 40.05 seconds
Started Oct 15 12:24:48 PM UTC 24
Finished Oct 15 12:25:29 PM UTC 24
Peak memory 644108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455048931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.2455048931
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.3720170293
Short name T1651
Test name
Test status
Simulation time 406674293 ps
CPU time 1.74 seconds
Started Oct 15 12:24:48 PM UTC 24
Finished Oct 15 12:24:50 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720170293 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fmt.3720170293
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.412424283
Short name T1655
Test name
Test status
Simulation time 134401392 ps
CPU time 5.07 seconds
Started Oct 15 12:24:49 PM UTC 24
Finished Oct 15 12:24:55 PM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412424283 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.412424283
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.2034219237
Short name T1693
Test name
Test status
Simulation time 6777041787 ps
CPU time 88.22 seconds
Started Oct 15 12:24:46 PM UTC 24
Finished Oct 15 12:26:17 PM UTC 24
Peak memory 1098696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034219237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.2034219237
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.646946185
Short name T1678
Test name
Test status
Simulation time 5852896762 ps
CPU time 6.69 seconds
Started Oct 15 12:25:23 PM UTC 24
Finished Oct 15 12:25:31 PM UTC 24
Peak memory 215960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646946185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.646946185
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_mode_toggle.1817575303
Short name T1686
Test name
Test status
Simulation time 511040275 ps
CPU time 12.35 seconds
Started Oct 15 12:25:23 PM UTC 24
Finished Oct 15 12:25:37 PM UTC 24
Peak memory 226020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817575303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.1817575303
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_override.2492971147
Short name T1647
Test name
Test status
Simulation time 100647991 ps
CPU time 0.8 seconds
Started Oct 15 12:24:45 PM UTC 24
Finished Oct 15 12:24:47 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492971147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.2492971147
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_perf.435728721
Short name T1733
Test name
Test status
Simulation time 49697900998 ps
CPU time 722.81 seconds
Started Oct 15 12:24:51 PM UTC 24
Finished Oct 15 12:37:01 PM UTC 24
Peak memory 2378624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435728721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.435728721
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.176661916
Short name T1659
Test name
Test status
Simulation time 324308643 ps
CPU time 13.37 seconds
Started Oct 15 12:24:51 PM UTC 24
Finished Oct 15 12:25:05 PM UTC 24
Peak memory 279428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176661916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.176661916
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.972189502
Short name T1669
Test name
Test status
Simulation time 1848841679 ps
CPU time 35.91 seconds
Started Oct 15 12:24:45 PM UTC 24
Finished Oct 15 12:25:22 PM UTC 24
Peak memory 338808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972189502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.972189502
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.2492700920
Short name T1663
Test name
Test status
Simulation time 1744140096 ps
CPU time 23.68 seconds
Started Oct 15 12:24:52 PM UTC 24
Finished Oct 15 12:25:17 PM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492700920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.2492700920
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.2236551423
Short name T1676
Test name
Test status
Simulation time 2813510659 ps
CPU time 6.58 seconds
Started Oct 15 12:25:22 PM UTC 24
Finished Oct 15 12:25:30 PM UTC 24
Peak memory 226028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2236551423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_bad_ad
dr.2236551423
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.3664526005
Short name T1667
Test name
Test status
Simulation time 199663036 ps
CPU time 1.14 seconds
Started Oct 15 12:25:19 PM UTC 24
Finished Oct 15 12:25:21 PM UTC 24
Peak memory 213632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664526
005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_acq.3664526005
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.2941989850
Short name T1668
Test name
Test status
Simulation time 391468277 ps
CPU time 1.77 seconds
Started Oct 15 12:25:19 PM UTC 24
Finished Oct 15 12:25:22 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941989
850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_tx.2941989850
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.2467657727
Short name T1680
Test name
Test status
Simulation time 3525719754 ps
CPU time 5.71 seconds
Started Oct 15 12:25:26 PM UTC 24
Finished Oct 15 12:25:33 PM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467657
727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_watermar
ks_acq.2467657727
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.1614592376
Short name T1677
Test name
Test status
Simulation time 898083469 ps
CPU time 2.54 seconds
Started Oct 15 12:25:27 PM UTC 24
Finished Oct 15 12:25:30 PM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614592
376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_watermark
s_tx.1614592376
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.4184486648
Short name T1664
Test name
Test status
Simulation time 645488934 ps
CPU time 7.29 seconds
Started Oct 15 12:25:10 PM UTC 24
Finished Oct 15 12:25:18 PM UTC 24
Peak memory 229788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418448
6648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_smoke.4184486648
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.3787793500
Short name T1728
Test name
Test status
Simulation time 24282493385 ps
CPU time 366.68 seconds
Started Oct 15 12:25:11 PM UTC 24
Finished Oct 15 12:31:22 PM UTC 24
Peak memory 5931984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3787793500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_stres
s_wr.3787793500
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.4195589112
Short name T1683
Test name
Test status
Simulation time 578688817 ps
CPU time 5.11 seconds
Started Oct 15 12:25:30 PM UTC 24
Finished Oct 15 12:25:36 PM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195589
112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_acqfull.4195589112
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.957756554
Short name T1684
Test name
Test status
Simulation time 2028773187 ps
CPU time 4.35 seconds
Started Oct 15 12:25:31 PM UTC 24
Finished Oct 15 12:25:36 PM UTC 24
Peak memory 215416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9577565
54 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_acqfull_addr.957756554
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_perf.3608026973
Short name T1674
Test name
Test status
Simulation time 1949857809 ps
CPU time 5.38 seconds
Started Oct 15 12:25:21 PM UTC 24
Finished Oct 15 12:25:27 PM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608026
973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_perf.3608026973
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.3881318310
Short name T1682
Test name
Test status
Simulation time 1031748886 ps
CPU time 4.3 seconds
Started Oct 15 12:25:29 PM UTC 24
Finished Oct 15 12:25:34 PM UTC 24
Peak memory 215172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881318
310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smbus_maxlen.3881318310
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.1543045895
Short name T1670
Test name
Test status
Simulation time 2705621220 ps
CPU time 20.36 seconds
Started Oct 15 12:25:01 PM UTC 24
Finished Oct 15 12:25:23 PM UTC 24
Peak memory 225820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543045895 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smoke.1543045895
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.2561601841
Short name T1671
Test name
Test status
Simulation time 1197110425 ps
CPU time 20.25 seconds
Started Oct 15 12:25:04 PM UTC 24
Finished Oct 15 12:25:26 PM UTC 24
Peak memory 232256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561601841 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_rd.2561601841
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.1415888484
Short name T1717
Test name
Test status
Simulation time 39033653993 ps
CPU time 138.48 seconds
Started Oct 15 12:25:01 PM UTC 24
Finished Oct 15 12:27:22 PM UTC 24
Peak memory 2487304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415888484 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_wr.1415888484
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.428062315
Short name T1665
Test name
Test status
Simulation time 1045040664 ps
CPU time 10.37 seconds
Started Oct 15 12:25:06 PM UTC 24
Finished Oct 15 12:25:18 PM UTC 24
Peak memory 299904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428062315 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stretch.428062315
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.3046811702
Short name T1673
Test name
Test status
Simulation time 5319981638 ps
CPU time 10.63 seconds
Started Oct 15 12:25:15 PM UTC 24
Finished Oct 15 12:25:27 PM UTC 24
Peak memory 225836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046811
702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_timeout.3046811702
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.4216252027
Short name T1679
Test name
Test status
Simulation time 245663090 ps
CPU time 4.28 seconds
Started Oct 15 12:25:28 PM UTC 24
Finished Oct 15 12:25:33 PM UTC 24
Peak memory 231976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216252
027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.4216252027
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_alert_test.2158080396
Short name T1713
Test name
Test status
Simulation time 19097952 ps
CPU time 0.92 seconds
Started Oct 15 12:26:40 PM UTC 24
Finished Oct 15 12:26:42 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158080396 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.2158080396
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.2089791682
Short name T1692
Test name
Test status
Simulation time 466007973 ps
CPU time 3.79 seconds
Started Oct 15 12:25:49 PM UTC 24
Finished Oct 15 12:25:54 PM UTC 24
Peak memory 225792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089791682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.2089791682
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.871961691
Short name T1688
Test name
Test status
Simulation time 354528673 ps
CPU time 7.86 seconds
Started Oct 15 12:25:36 PM UTC 24
Finished Oct 15 12:25:45 PM UTC 24
Peak memory 291644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871961691 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empty.871961691
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.601917512
Short name T1724
Test name
Test status
Simulation time 2642645700 ps
CPU time 152.25 seconds
Started Oct 15 12:25:38 PM UTC 24
Finished Oct 15 12:28:12 PM UTC 24
Peak memory 480184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601917512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.601917512
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.1012214944
Short name T1702
Test name
Test status
Simulation time 4055786885 ps
CPU time 53.68 seconds
Started Oct 15 12:25:35 PM UTC 24
Finished Oct 15 12:26:30 PM UTC 24
Peak memory 684996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012214944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1012214944
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.2229133392
Short name T1687
Test name
Test status
Simulation time 76071544 ps
CPU time 1.51 seconds
Started Oct 15 12:25:35 PM UTC 24
Finished Oct 15 12:25:38 PM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229133392 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fmt.2229133392
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.1005553454
Short name T1689
Test name
Test status
Simulation time 565811396 ps
CPU time 9.91 seconds
Started Oct 15 12:25:38 PM UTC 24
Finished Oct 15 12:25:49 PM UTC 24
Peak memory 240508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005553454 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.1005553454
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.1568466932
Short name T1721
Test name
Test status
Simulation time 19694041569 ps
CPU time 130.59 seconds
Started Oct 15 12:25:35 PM UTC 24
Finished Oct 15 12:27:48 PM UTC 24
Peak memory 1430388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568466932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.1568466932
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.499408644
Short name T1708
Test name
Test status
Simulation time 355084104 ps
CPU time 6.46 seconds
Started Oct 15 12:26:31 PM UTC 24
Finished Oct 15 12:26:39 PM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499408644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.499408644
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_override.3805473278
Short name T1685
Test name
Test status
Simulation time 51816550 ps
CPU time 1.12 seconds
Started Oct 15 12:25:34 PM UTC 24
Finished Oct 15 12:25:36 PM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805473278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.3805473278
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_perf.849298607
Short name T1704
Test name
Test status
Simulation time 12312679692 ps
CPU time 742.22 seconds
Started Oct 15 12:25:38 PM UTC 24
Finished Oct 15 12:38:09 PM UTC 24
Peak memory 1450936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849298607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.849298607
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.3636592316
Short name T1690
Test name
Test status
Simulation time 1309617464 ps
CPU time 12.4 seconds
Started Oct 15 12:25:39 PM UTC 24
Finished Oct 15 12:25:52 PM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636592316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.3636592316
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.2862832250
Short name T1718
Test name
Test status
Simulation time 17265201042 ps
CPU time 105.92 seconds
Started Oct 15 12:25:34 PM UTC 24
Finished Oct 15 12:27:22 PM UTC 24
Peak memory 347140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862832250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.2862832250
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_stress_all.745749158
Short name T1726
Test name
Test status
Simulation time 12361950534 ps
CPU time 195.16 seconds
Started Oct 15 12:25:53 PM UTC 24
Finished Oct 15 12:29:12 PM UTC 24
Peak memory 982304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745749158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.745749158
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.3510884632
Short name T1694
Test name
Test status
Simulation time 989357812 ps
CPU time 31.17 seconds
Started Oct 15 12:25:46 PM UTC 24
Finished Oct 15 12:26:18 PM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510884632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.3510884632
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.4052825691
Short name T1709
Test name
Test status
Simulation time 3285131508 ps
CPU time 8.03 seconds
Started Oct 15 12:26:30 PM UTC 24
Finished Oct 15 12:26:39 PM UTC 24
Peak memory 232356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4052825691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_bad_ad
dr.4052825691
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.3621921707
Short name T1698
Test name
Test status
Simulation time 620796607 ps
CPU time 1.96 seconds
Started Oct 15 12:26:26 PM UTC 24
Finished Oct 15 12:26:29 PM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621921
707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_acq.3621921707
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.198139719
Short name T1703
Test name
Test status
Simulation time 302439852 ps
CPU time 1.5 seconds
Started Oct 15 12:26:29 PM UTC 24
Finished Oct 15 12:26:31 PM UTC 24
Peak memory 225616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981397
19 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_tx.198139719
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.2768231630
Short name T1707
Test name
Test status
Simulation time 988518582 ps
CPU time 4.72 seconds
Started Oct 15 12:26:32 PM UTC 24
Finished Oct 15 12:26:38 PM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768231
630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_watermar
ks_acq.2768231630
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.4282731420
Short name T1701
Test name
Test status
Simulation time 2544808240 ps
CPU time 11.02 seconds
Started Oct 15 12:26:18 PM UTC 24
Finished Oct 15 12:26:30 PM UTC 24
Peak memory 232396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428273
1420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_smoke.4282731420
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.3322694210
Short name T1710
Test name
Test status
Simulation time 7378993198 ps
CPU time 18.94 seconds
Started Oct 15 12:26:20 PM UTC 24
Finished Oct 15 12:26:40 PM UTC 24
Peak memory 215860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3322694210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_stres
s_wr.3322694210
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.3172354783
Short name T1715
Test name
Test status
Simulation time 5708871815 ps
CPU time 5.03 seconds
Started Oct 15 12:26:38 PM UTC 24
Finished Oct 15 12:26:44 PM UTC 24
Peak memory 225776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172354
783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_acqfull.3172354783
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.1437382690
Short name T1714
Test name
Test status
Simulation time 3017643271 ps
CPU time 3.72 seconds
Started Oct 15 12:26:38 PM UTC 24
Finished Oct 15 12:26:43 PM UTC 24
Peak memory 215656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437382
690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_acqfull_ad
dr.1437382690
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.334230599
Short name T1712
Test name
Test status
Simulation time 268496590 ps
CPU time 1.99 seconds
Started Oct 15 12:26:39 PM UTC 24
Finished Oct 15 12:26:42 PM UTC 24
Peak memory 231192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342305
99 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_txstretch.334230599
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_perf.957152862
Short name T1706
Test name
Test status
Simulation time 4413489253 ps
CPU time 5.63 seconds
Started Oct 15 12:26:30 PM UTC 24
Finished Oct 15 12:26:37 PM UTC 24
Peak memory 225892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9571528
62 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_perf.957152862
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.1104896832
Short name T1711
Test name
Test status
Simulation time 399615073 ps
CPU time 3.49 seconds
Started Oct 15 12:26:37 PM UTC 24
Finished Oct 15 12:26:41 PM UTC 24
Peak memory 215172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104896
832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smbus_maxlen.1104896832
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.69742905
Short name T1699
Test name
Test status
Simulation time 1778990053 ps
CPU time 34.25 seconds
Started Oct 15 12:25:53 PM UTC 24
Finished Oct 15 12:26:29 PM UTC 24
Peak memory 226016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69742905 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smoke.69742905
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.1831001045
Short name T1628
Test name
Test status
Simulation time 42674403211 ps
CPU time 760.7 seconds
Started Oct 15 12:26:30 PM UTC 24
Finished Oct 15 12:39:18 PM UTC 24
Peak memory 6304968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183100
1045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_all.1831001045
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.3711113245
Short name T1719
Test name
Test status
Simulation time 7301812934 ps
CPU time 81.29 seconds
Started Oct 15 12:26:07 PM UTC 24
Finished Oct 15 12:27:31 PM UTC 24
Peak memory 232292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711113245 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_rd.3711113245
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.1847489397
Short name T1695
Test name
Test status
Simulation time 17819059130 ps
CPU time 22.13 seconds
Started Oct 15 12:25:55 PM UTC 24
Finished Oct 15 12:26:19 PM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847489397 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_wr.1847489397
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.1327358667
Short name T1697
Test name
Test status
Simulation time 406827918 ps
CPU time 13.73 seconds
Started Oct 15 12:26:13 PM UTC 24
Finished Oct 15 12:26:28 PM UTC 24
Peak memory 254760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327358667 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stretch.1327358667
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.4005774055
Short name T1700
Test name
Test status
Simulation time 10837194165 ps
CPU time 8.37 seconds
Started Oct 15 12:26:20 PM UTC 24
Finished Oct 15 12:26:29 PM UTC 24
Peak memory 226084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005774
055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_timeout.4005774055
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/49.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_alert_test.3816733294
Short name T343
Test name
Test status
Simulation time 46779281 ps
CPU time 1 seconds
Started Oct 15 11:43:27 AM UTC 24
Finished Oct 15 11:43:29 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816733294 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3816733294
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_error_intr.2487381662
Short name T30
Test name
Test status
Simulation time 76284517 ps
CPU time 2.62 seconds
Started Oct 15 11:42:52 AM UTC 24
Finished Oct 15 11:42:55 AM UTC 24
Peak memory 225840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487381662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2487381662
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_fmt_empty.3633027386
Short name T342
Test name
Test status
Simulation time 535998746 ps
CPU time 37.23 seconds
Started Oct 15 11:42:49 AM UTC 24
Finished Oct 15 11:43:28 AM UTC 24
Peak memory 343176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633027386 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty.3633027386
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_full.1883732074
Short name T381
Test name
Test status
Simulation time 2237961279 ps
CPU time 95.9 seconds
Started Oct 15 11:42:49 AM UTC 24
Finished Oct 15 11:44:27 AM UTC 24
Peak memory 259196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883732074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.1883732074
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_overflow.2790027049
Short name T191
Test name
Test status
Simulation time 1760028115 ps
CPU time 107.62 seconds
Started Oct 15 11:42:49 AM UTC 24
Finished Oct 15 11:44:39 AM UTC 24
Peak memory 662680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790027049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.2790027049
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_fmt.3580262921
Short name T250
Test name
Test status
Simulation time 229660414 ps
CPU time 1.84 seconds
Started Oct 15 11:42:49 AM UTC 24
Finished Oct 15 11:42:52 AM UTC 24
Peak memory 215708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580262921 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt.3580262921
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_rx.4007358909
Short name T165
Test name
Test status
Simulation time 683451304 ps
CPU time 11.9 seconds
Started Oct 15 11:42:49 AM UTC 24
Finished Oct 15 11:43:02 AM UTC 24
Peak memory 249028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007358909 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.4007358909
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_watermark.1259067024
Short name T464
Test name
Test status
Simulation time 10042464740 ps
CPU time 290.84 seconds
Started Oct 15 11:42:49 AM UTC 24
Finished Oct 15 11:47:44 AM UTC 24
Peak memory 1451216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259067024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.1259067024
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_may_nack.1325733337
Short name T272
Test name
Test status
Simulation time 403085454 ps
CPU time 8.94 seconds
Started Oct 15 11:43:21 AM UTC 24
Finished Oct 15 11:43:31 AM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325733337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.1325733337
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_override.2922069644
Short name T327
Test name
Test status
Simulation time 37557623 ps
CPU time 0.8 seconds
Started Oct 15 11:42:48 AM UTC 24
Finished Oct 15 11:42:50 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922069644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.2922069644
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_perf.2147747660
Short name T751
Test name
Test status
Simulation time 73910425471 ps
CPU time 775.85 seconds
Started Oct 15 11:42:50 AM UTC 24
Finished Oct 15 11:55:55 AM UTC 24
Peak memory 1420216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147747660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.2147747660
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_perf_precise.4278277813
Short name T166
Test name
Test status
Simulation time 6571019816 ps
CPU time 26.35 seconds
Started Oct 15 11:42:50 AM UTC 24
Finished Oct 15 11:43:18 AM UTC 24
Peak memory 521088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278277813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.4278277813
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_smoke.803254186
Short name T291
Test name
Test status
Simulation time 1779970096 ps
CPU time 26.89 seconds
Started Oct 15 11:42:47 AM UTC 24
Finished Oct 15 11:43:15 AM UTC 24
Peak memory 287940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803254186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.803254186
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_stress_all.3943503989
Short name T22
Test name
Test status
Simulation time 14746401870 ps
CPU time 582.31 seconds
Started Oct 15 11:42:53 AM UTC 24
Finished Oct 15 11:52:42 AM UTC 24
Peak memory 2016536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943503989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.3943503989
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_host_stretch_timeout.318425426
Short name T122
Test name
Test status
Simulation time 2042656094 ps
CPU time 26.44 seconds
Started Oct 15 11:42:52 AM UTC 24
Finished Oct 15 11:43:19 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318425426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.318425426
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_bad_addr.2719888883
Short name T339
Test name
Test status
Simulation time 693702492 ps
CPU time 5.46 seconds
Started Oct 15 11:43:19 AM UTC 24
Finished Oct 15 11:43:26 AM UTC 24
Peak memory 229852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2719888883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2719888883
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_acq.225370565
Short name T333
Test name
Test status
Simulation time 643032641 ps
CPU time 1.4 seconds
Started Oct 15 11:43:17 AM UTC 24
Finished Oct 15 11:43:20 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253705
65 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_acq.225370565
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_tx.1572616822
Short name T335
Test name
Test status
Simulation time 404890028 ps
CPU time 1.6 seconds
Started Oct 15 11:43:17 AM UTC 24
Finished Oct 15 11:43:20 AM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572616
822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_tx.1572616822
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_acq.2534467538
Short name T338
Test name
Test status
Simulation time 557963736 ps
CPU time 1.97 seconds
Started Oct 15 11:43:22 AM UTC 24
Finished Oct 15 11:43:25 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534467
538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_watermark
s_acq.2534467538
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_tx.349790780
Short name T340
Test name
Test status
Simulation time 198508752 ps
CPU time 1.47 seconds
Started Oct 15 11:43:24 AM UTC 24
Finished Oct 15 11:43:26 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497907
80 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.349790780
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_hrst.1794897589
Short name T196
Test name
Test status
Simulation time 464159728 ps
CPU time 3.68 seconds
Started Oct 15 11:43:20 AM UTC 24
Finished Oct 15 11:43:25 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794897
589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_hrst.1794897589
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_intr_smoke.3939829726
Short name T332
Test name
Test status
Simulation time 5682319157 ps
CPU time 12.26 seconds
Started Oct 15 11:43:04 AM UTC 24
Finished Oct 15 11:43:17 AM UTC 24
Peak memory 232344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393982
9726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_smoke.3939829726
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_intr_stress_wr.3283916271
Short name T350
Test name
Test status
Simulation time 15499391798 ps
CPU time 34.05 seconds
Started Oct 15 11:43:04 AM UTC 24
Finished Oct 15 11:43:39 AM UTC 24
Peak memory 1002364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3283916271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_stress
_wr.3283916271
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull.4287729259
Short name T344
Test name
Test status
Simulation time 1701027673 ps
CPU time 3.38 seconds
Started Oct 15 11:43:25 AM UTC 24
Finished Oct 15 11:43:30 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287729
259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_acqfull.4287729259
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull_addr.3660410897
Short name T346
Test name
Test status
Simulation time 811020845 ps
CPU time 3.5 seconds
Started Oct 15 11:43:26 AM UTC 24
Finished Oct 15 11:43:31 AM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660410
897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.3660410897
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_nack_txstretch.2265947940
Short name T63
Test name
Test status
Simulation time 126563337 ps
CPU time 2.3 seconds
Started Oct 15 11:43:26 AM UTC 24
Finished Oct 15 11:43:29 AM UTC 24
Peak memory 232328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265947
940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_txstretch.2265947940
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_perf.573507112
Short name T176
Test name
Test status
Simulation time 437550821 ps
CPU time 3.94 seconds
Started Oct 15 11:43:19 AM UTC 24
Finished Oct 15 11:43:24 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5735071
12 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_perf.573507112
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_smbus_maxlen.761129141
Short name T345
Test name
Test status
Simulation time 1641990112 ps
CPU time 4.17 seconds
Started Oct 15 11:43:25 AM UTC 24
Finished Oct 15 11:43:30 AM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7611291
41 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smbus_maxlen.761129141
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_smoke.1195639492
Short name T337
Test name
Test status
Simulation time 1500303742 ps
CPU time 29.25 seconds
Started Oct 15 11:42:53 AM UTC 24
Finished Oct 15 11:43:23 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195639492 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smoke.1195639492
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_stress_all.3780081035
Short name T756
Test name
Test status
Simulation time 51271201471 ps
CPU time 758.36 seconds
Started Oct 15 11:43:19 AM UTC 24
Finished Oct 15 11:56:05 AM UTC 24
Peak memory 7017408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378008
1035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_all.3780081035
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_stress_rd.1566622756
Short name T331
Test name
Test status
Simulation time 520160417 ps
CPU time 3.85 seconds
Started Oct 15 11:42:57 AM UTC 24
Finished Oct 15 11:43:02 AM UTC 24
Peak memory 215584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566622756 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_rd.1566622756
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_stress_wr.3205900594
Short name T569
Test name
Test status
Simulation time 56660648280 ps
CPU time 471.62 seconds
Started Oct 15 11:42:54 AM UTC 24
Finished Oct 15 11:50:50 AM UTC 24
Peak memory 5872840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205900594 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_wr.3205900594
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_stretch.2503559282
Short name T334
Test name
Test status
Simulation time 1414255578 ps
CPU time 20.78 seconds
Started Oct 15 11:42:58 AM UTC 24
Finished Oct 15 11:43:20 AM UTC 24
Peak memory 345028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503559282 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stretch.2503559282
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_timeout.2708140656
Short name T336
Test name
Test status
Simulation time 5517291394 ps
CPU time 13.22 seconds
Started Oct 15 11:43:06 AM UTC 24
Finished Oct 15 11:43:20 AM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708140
656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_timeout.2708140656
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/5.i2c_target_tx_stretch_ctrl.3704883328
Short name T347
Test name
Test status
Simulation time 336405212 ps
CPU time 7.86 seconds
Started Oct 15 11:43:24 AM UTC 24
Finished Oct 15 11:43:33 AM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704883
328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.3704883328
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_alert_test.3138193750
Short name T371
Test name
Test status
Simulation time 196964302 ps
CPU time 0.91 seconds
Started Oct 15 11:44:14 AM UTC 24
Finished Oct 15 11:44:16 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138193750 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.3138193750
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_error_intr.475829936
Short name T352
Test name
Test status
Simulation time 128336202 ps
CPU time 5.67 seconds
Started Oct 15 11:43:35 AM UTC 24
Finished Oct 15 11:43:42 AM UTC 24
Peak memory 225716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475829936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.475829936
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_fmt_empty.1042453316
Short name T351
Test name
Test status
Simulation time 217530935 ps
CPU time 6.94 seconds
Started Oct 15 11:43:32 AM UTC 24
Finished Oct 15 11:43:40 AM UTC 24
Peak memory 260996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042453316 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty.1042453316
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_full.786718970
Short name T28
Test name
Test status
Simulation time 2078297810 ps
CPU time 54.37 seconds
Started Oct 15 11:43:32 AM UTC 24
Finished Oct 15 11:44:28 AM UTC 24
Peak memory 392080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786718970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.786718970
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_overflow.1799702557
Short name T418
Test name
Test status
Simulation time 2172295177 ps
CPU time 131.95 seconds
Started Oct 15 11:43:31 AM UTC 24
Finished Oct 15 11:45:45 AM UTC 24
Peak memory 623616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799702557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1799702557
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_fmt.3332027771
Short name T348
Test name
Test status
Simulation time 380811944 ps
CPU time 1.72 seconds
Started Oct 15 11:43:31 AM UTC 24
Finished Oct 15 11:43:33 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332027771 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt.3332027771
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_rx.2433308010
Short name T168
Test name
Test status
Simulation time 740124123 ps
CPU time 13.49 seconds
Started Oct 15 11:43:32 AM UTC 24
Finished Oct 15 11:43:46 AM UTC 24
Peak memory 250684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433308010 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.2433308010
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_watermark.2319102333
Short name T86
Test name
Test status
Simulation time 3558006652 ps
CPU time 79.96 seconds
Started Oct 15 11:43:30 AM UTC 24
Finished Oct 15 11:44:52 AM UTC 24
Peak memory 1080380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319102333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2319102333
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_mode_toggle.202624411
Short name T80
Test name
Test status
Simulation time 192129246 ps
CPU time 1.72 seconds
Started Oct 15 11:44:04 AM UTC 24
Finished Oct 15 11:44:07 AM UTC 24
Peak memory 232660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202624411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.202624411
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_override.787300718
Short name T83
Test name
Test status
Simulation time 47061695 ps
CPU time 1.03 seconds
Started Oct 15 11:43:28 AM UTC 24
Finished Oct 15 11:43:30 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787300718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.787300718
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_perf.2102040591
Short name T41
Test name
Test status
Simulation time 7746000770 ps
CPU time 468.5 seconds
Started Oct 15 11:43:32 AM UTC 24
Finished Oct 15 11:51:26 AM UTC 24
Peak memory 1768448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102040591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.2102040591
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_perf_precise.1715407277
Short name T349
Test name
Test status
Simulation time 144954098 ps
CPU time 1.54 seconds
Started Oct 15 11:43:34 AM UTC 24
Finished Oct 15 11:43:36 AM UTC 24
Peak memory 225496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715407277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.1715407277
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_smoke.3256305941
Short name T362
Test name
Test status
Simulation time 1988173639 ps
CPU time 36.45 seconds
Started Oct 15 11:43:27 AM UTC 24
Finished Oct 15 11:44:05 AM UTC 24
Peak memory 361612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256305941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.3256305941
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_host_stretch_timeout.503216044
Short name T355
Test name
Test status
Simulation time 3928474594 ps
CPU time 16.07 seconds
Started Oct 15 11:43:34 AM UTC 24
Finished Oct 15 11:43:51 AM UTC 24
Peak memory 242692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503216044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.503216044
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_bad_addr.2824113186
Short name T363
Test name
Test status
Simulation time 3686535951 ps
CPU time 7.89 seconds
Started Oct 15 11:43:59 AM UTC 24
Finished Oct 15 11:44:08 AM UTC 24
Peak memory 226032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2824113186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.2824113186
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_acq.1237570012
Short name T358
Test name
Test status
Simulation time 217971545 ps
CPU time 2.31 seconds
Started Oct 15 11:43:53 AM UTC 24
Finished Oct 15 11:43:56 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237570
012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_acq.1237570012
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_tx.4163567683
Short name T180
Test name
Test status
Simulation time 257477400 ps
CPU time 3.21 seconds
Started Oct 15 11:43:56 AM UTC 24
Finished Oct 15 11:44:00 AM UTC 24
Peak memory 219492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163567
683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_tx.4163567683
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_acq.1497229590
Short name T366
Test name
Test status
Simulation time 1522807253 ps
CPU time 5.68 seconds
Started Oct 15 11:44:06 AM UTC 24
Finished Oct 15 11:44:13 AM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497229
590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_watermark
s_acq.1497229590
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_tx.1809015039
Short name T364
Test name
Test status
Simulation time 143794304 ps
CPU time 2.26 seconds
Started Oct 15 11:44:07 AM UTC 24
Finished Oct 15 11:44:11 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809015
039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_watermarks
_tx.1809015039
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_hrst.3094766132
Short name T197
Test name
Test status
Simulation time 913437032 ps
CPU time 3.8 seconds
Started Oct 15 11:44:00 AM UTC 24
Finished Oct 15 11:44:05 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094766
132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_hrst.3094766132
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_intr_smoke.1886055523
Short name T359
Test name
Test status
Simulation time 4467915905 ps
CPU time 11.55 seconds
Started Oct 15 11:43:45 AM UTC 24
Finished Oct 15 11:43:58 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188605
5523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_smoke.1886055523
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_intr_stress_wr.664079940
Short name T370
Test name
Test status
Simulation time 11484296143 ps
CPU time 25.21 seconds
Started Oct 15 11:43:47 AM UTC 24
Finished Oct 15 11:44:14 AM UTC 24
Peak memory 830664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=664079940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.664079940
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull.854474508
Short name T372
Test name
Test status
Simulation time 702241827 ps
CPU time 3.31 seconds
Started Oct 15 11:44:12 AM UTC 24
Finished Oct 15 11:44:16 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8544745
08 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_acqfull.854474508
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_perf.1450273608
Short name T361
Test name
Test status
Simulation time 431909776 ps
CPU time 5.67 seconds
Started Oct 15 11:43:57 AM UTC 24
Finished Oct 15 11:44:04 AM UTC 24
Peak memory 232648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450273
608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_perf.1450273608
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_smbus_maxlen.394520858
Short name T369
Test name
Test status
Simulation time 498599325 ps
CPU time 3.99 seconds
Started Oct 15 11:44:09 AM UTC 24
Finished Oct 15 11:44:14 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945208
58 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smbus_maxlen.394520858
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_smoke.3871885536
Short name T356
Test name
Test status
Simulation time 3156044220 ps
CPU time 10.8 seconds
Started Oct 15 11:43:40 AM UTC 24
Finished Oct 15 11:43:52 AM UTC 24
Peak memory 226088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871885536 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smoke.3871885536
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_stress_all.1720380239
Short name T137
Test name
Test status
Simulation time 41795545408 ps
CPU time 456.79 seconds
Started Oct 15 11:43:57 AM UTC 24
Finished Oct 15 11:51:39 AM UTC 24
Peak memory 4318056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172038
0239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_all.1720380239
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_stress_rd.3808789906
Short name T360
Test name
Test status
Simulation time 706893204 ps
CPU time 15.27 seconds
Started Oct 15 11:43:42 AM UTC 24
Finished Oct 15 11:43:59 AM UTC 24
Peak memory 227868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808789906 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_rd.3808789906
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_stress_wr.131375979
Short name T378
Test name
Test status
Simulation time 12224888253 ps
CPU time 43.82 seconds
Started Oct 15 11:43:40 AM UTC 24
Finished Oct 15 11:44:25 AM UTC 24
Peak memory 215652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131375979 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_wr.131375979
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_stretch.953594377
Short name T354
Test name
Test status
Simulation time 2245737483 ps
CPU time 6.28 seconds
Started Oct 15 11:43:42 AM UTC 24
Finished Oct 15 11:43:50 AM UTC 24
Peak memory 228072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953594377 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stretch.953594377
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_timeout.3871407982
Short name T274
Test name
Test status
Simulation time 1583946125 ps
CPU time 8.27 seconds
Started Oct 15 11:43:51 AM UTC 24
Finished Oct 15 11:44:00 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871407
982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_timeout.3871407982
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/6.i2c_target_tx_stretch_ctrl.2201547170
Short name T365
Test name
Test status
Simulation time 73240397 ps
CPU time 3.33 seconds
Started Oct 15 11:44:08 AM UTC 24
Finished Oct 15 11:44:12 AM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201547
170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.2201547170
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_alert_test.1058397385
Short name T377
Test name
Test status
Simulation time 18529040 ps
CPU time 0.99 seconds
Started Oct 15 11:44:53 AM UTC 24
Finished Oct 15 11:44:55 AM UTC 24
Peak memory 213392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058397385 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1058397385
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_error_intr.1623356774
Short name T380
Test name
Test status
Simulation time 149363998 ps
CPU time 3.24 seconds
Started Oct 15 11:44:23 AM UTC 24
Finished Oct 15 11:44:27 AM UTC 24
Peak memory 225784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623356774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.1623356774
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_fmt_empty.1182759129
Short name T385
Test name
Test status
Simulation time 354948076 ps
CPU time 21.81 seconds
Started Oct 15 11:44:17 AM UTC 24
Finished Oct 15 11:44:41 AM UTC 24
Peak memory 287624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182759129 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty.1182759129
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_full.4285220648
Short name T407
Test name
Test status
Simulation time 2258337829 ps
CPU time 67.91 seconds
Started Oct 15 11:44:18 AM UTC 24
Finished Oct 15 11:45:28 AM UTC 24
Peak memory 525240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285220648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.4285220648
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_overflow.2269611355
Short name T432
Test name
Test status
Simulation time 8580432595 ps
CPU time 119.17 seconds
Started Oct 15 11:44:16 AM UTC 24
Finished Oct 15 11:46:18 AM UTC 24
Peak memory 629844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269611355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2269611355
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_fmt.2827347866
Short name T374
Test name
Test status
Simulation time 197016816 ps
CPU time 1.63 seconds
Started Oct 15 11:44:17 AM UTC 24
Finished Oct 15 11:44:20 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827347866 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt.2827347866
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_rx.488360184
Short name T169
Test name
Test status
Simulation time 711683959 ps
CPU time 6.6 seconds
Started Oct 15 11:44:18 AM UTC 24
Finished Oct 15 11:44:26 AM UTC 24
Peak memory 250824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488360184 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.488360184
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_watermark.269248977
Short name T414
Test name
Test status
Simulation time 3118080235 ps
CPU time 81.15 seconds
Started Oct 15 11:44:15 AM UTC 24
Finished Oct 15 11:45:38 AM UTC 24
Peak memory 979852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269248977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.269248977
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_may_nack.1667298841
Short name T256
Test name
Test status
Simulation time 598424763 ps
CPU time 14.21 seconds
Started Oct 15 11:44:46 AM UTC 24
Finished Oct 15 11:45:01 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667298841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.1667298841
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_override.4064910929
Short name T373
Test name
Test status
Simulation time 71736237 ps
CPU time 1.11 seconds
Started Oct 15 11:44:15 AM UTC 24
Finished Oct 15 11:44:17 AM UTC 24
Peak memory 213116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064910929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.4064910929
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_perf.2142326743
Short name T246
Test name
Test status
Simulation time 26235814925 ps
CPU time 77.36 seconds
Started Oct 15 11:44:19 AM UTC 24
Finished Oct 15 11:45:39 AM UTC 24
Peak memory 229928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142326743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.2142326743
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_perf_precise.4222202145
Short name T376
Test name
Test status
Simulation time 339671831 ps
CPU time 1.73 seconds
Started Oct 15 11:44:21 AM UTC 24
Finished Oct 15 11:44:23 AM UTC 24
Peak memory 225576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222202145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.4222202145
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_smoke.1947376773
Short name T290
Test name
Test status
Simulation time 3526501574 ps
CPU time 27.95 seconds
Started Oct 15 11:44:14 AM UTC 24
Finished Oct 15 11:44:43 AM UTC 24
Peak memory 373960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947376773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.1947376773
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_host_stretch_timeout.1899402782
Short name T394
Test name
Test status
Simulation time 744246531 ps
CPU time 31.15 seconds
Started Oct 15 11:44:23 AM UTC 24
Finished Oct 15 11:44:55 AM UTC 24
Peak memory 225844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899402782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.1899402782
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_bad_addr.2280699629
Short name T341
Test name
Test status
Simulation time 4094553178 ps
CPU time 6.38 seconds
Started Oct 15 11:44:43 AM UTC 24
Finished Oct 15 11:44:51 AM UTC 24
Peak memory 225892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2280699629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2280699629
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_acq.1484514516
Short name T389
Test name
Test status
Simulation time 157423903 ps
CPU time 1.86 seconds
Started Oct 15 11:44:41 AM UTC 24
Finished Oct 15 11:44:44 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484514
516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_acq.1484514516
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_tx.2203629064
Short name T388
Test name
Test status
Simulation time 399933510 ps
CPU time 1.35 seconds
Started Oct 15 11:44:41 AM UTC 24
Finished Oct 15 11:44:44 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203629
064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_tx.2203629064
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_acq.670032720
Short name T392
Test name
Test status
Simulation time 538650795 ps
CPU time 4.81 seconds
Started Oct 15 11:44:47 AM UTC 24
Finished Oct 15 11:44:53 AM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6700327
20 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_watermarks
_acq.670032720
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_tx.1649772024
Short name T391
Test name
Test status
Simulation time 2631079494 ps
CPU time 2.68 seconds
Started Oct 15 11:44:49 AM UTC 24
Finished Oct 15 11:44:53 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649772
024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_watermarks
_tx.1649772024
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_intr_smoke.3217450085
Short name T383
Test name
Test status
Simulation time 561313676 ps
CPU time 6.36 seconds
Started Oct 15 11:44:30 AM UTC 24
Finished Oct 15 11:44:37 AM UTC 24
Peak memory 229808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321745
0085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_smoke.3217450085
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_intr_stress_wr.1161789226
Short name T473
Test name
Test status
Simulation time 19809064370 ps
CPU time 197.79 seconds
Started Oct 15 11:44:30 AM UTC 24
Finished Oct 15 11:47:50 AM UTC 24
Peak memory 3171200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1161789226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_stress
_wr.1161789226
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull.1589939644
Short name T386
Test name
Test status
Simulation time 584430157 ps
CPU time 4.24 seconds
Started Oct 15 11:44:52 AM UTC 24
Finished Oct 15 11:44:57 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589939
644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_acqfull.1589939644
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull_addr.1871036948
Short name T395
Test name
Test status
Simulation time 2128631483 ps
CPU time 5.08 seconds
Started Oct 15 11:44:53 AM UTC 24
Finished Oct 15 11:44:59 AM UTC 24
Peak memory 215484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871036
948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.1871036948
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_nack_txstretch.3699144824
Short name T181
Test name
Test status
Simulation time 146968019 ps
CPU time 1.85 seconds
Started Oct 15 11:44:53 AM UTC 24
Finished Oct 15 11:44:56 AM UTC 24
Peak memory 232652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699144
824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_txstretch.3699144824
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_perf.1483380310
Short name T379
Test name
Test status
Simulation time 2179544912 ps
CPU time 5.49 seconds
Started Oct 15 11:44:41 AM UTC 24
Finished Oct 15 11:44:48 AM UTC 24
Peak memory 225812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483380
310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_perf.1483380310
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_smbus_maxlen.804061801
Short name T368
Test name
Test status
Simulation time 952193057 ps
CPU time 3.57 seconds
Started Oct 15 11:44:50 AM UTC 24
Finished Oct 15 11:44:55 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8040618
01 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smbus_maxlen.804061801
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_smoke.569203610
Short name T387
Test name
Test status
Simulation time 4031694078 ps
CPU time 15.65 seconds
Started Oct 15 11:44:26 AM UTC 24
Finished Oct 15 11:44:43 AM UTC 24
Peak memory 225748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569203610 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smoke.569203610
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_stress_all.3350004554
Short name T562
Test name
Test status
Simulation time 46882702084 ps
CPU time 359.4 seconds
Started Oct 15 11:44:41 AM UTC 24
Finished Oct 15 11:50:45 AM UTC 24
Peak memory 3687444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335000
4554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_all.3350004554
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_stress_rd.1721399249
Short name T397
Test name
Test status
Simulation time 7857608098 ps
CPU time 34.54 seconds
Started Oct 15 11:44:27 AM UTC 24
Finished Oct 15 11:45:03 AM UTC 24
Peak memory 248840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721399249 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_rd.1721399249
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_stress_wr.2381042277
Short name T423
Test name
Test status
Simulation time 59409230128 ps
CPU time 80.65 seconds
Started Oct 15 11:44:27 AM UTC 24
Finished Oct 15 11:45:49 AM UTC 24
Peak memory 1506504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381042277 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_wr.2381042277
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_stretch.2531433292
Short name T384
Test name
Test status
Simulation time 2610869725 ps
CPU time 8.25 seconds
Started Oct 15 11:44:30 AM UTC 24
Finished Oct 15 11:44:39 AM UTC 24
Peak memory 314316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531433292 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stretch.2531433292
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_timeout.2085337734
Short name T367
Test name
Test status
Simulation time 5557160926 ps
CPU time 13.49 seconds
Started Oct 15 11:44:31 AM UTC 24
Finished Oct 15 11:44:46 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085337
734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_timeout.2085337734
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/7.i2c_target_tx_stretch_ctrl.1334501561
Short name T393
Test name
Test status
Simulation time 202363989 ps
CPU time 4.42 seconds
Started Oct 15 11:44:49 AM UTC 24
Finished Oct 15 11:44:54 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334501
561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.1334501561
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_alert_test.1073780754
Short name T420
Test name
Test status
Simulation time 24899607 ps
CPU time 0.97 seconds
Started Oct 15 11:45:44 AM UTC 24
Finished Oct 15 11:45:46 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073780754 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.1073780754
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_error_intr.2372627297
Short name T400
Test name
Test status
Simulation time 192769061 ps
CPU time 4.57 seconds
Started Oct 15 11:45:02 AM UTC 24
Finished Oct 15 11:45:08 AM UTC 24
Peak memory 242640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372627297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.2372627297
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_fmt_empty.1050019636
Short name T399
Test name
Test status
Simulation time 1053082522 ps
CPU time 5.89 seconds
Started Oct 15 11:44:57 AM UTC 24
Finished Oct 15 11:45:04 AM UTC 24
Peak memory 273540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050019636 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty.1050019636
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_full.1388705679
Short name T439
Test name
Test status
Simulation time 5896911093 ps
CPU time 98.12 seconds
Started Oct 15 11:44:58 AM UTC 24
Finished Oct 15 11:46:38 AM UTC 24
Peak memory 488516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388705679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.1388705679
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_overflow.4107258259
Short name T427
Test name
Test status
Simulation time 5209898600 ps
CPU time 64.69 seconds
Started Oct 15 11:44:56 AM UTC 24
Finished Oct 15 11:46:02 AM UTC 24
Peak memory 867208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107258259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.4107258259
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_fmt.1057144953
Short name T396
Test name
Test status
Simulation time 949952017 ps
CPU time 1.83 seconds
Started Oct 15 11:44:57 AM UTC 24
Finished Oct 15 11:45:00 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057144953 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt.1057144953
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_rx.188568486
Short name T398
Test name
Test status
Simulation time 147228073 ps
CPU time 5.58 seconds
Started Oct 15 11:44:57 AM UTC 24
Finished Oct 15 11:45:03 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188568486 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.188568486
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_watermark.2462136989
Short name T500
Test name
Test status
Simulation time 3932356321 ps
CPU time 217.26 seconds
Started Oct 15 11:44:56 AM UTC 24
Finished Oct 15 11:48:36 AM UTC 24
Peak memory 1221624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462136989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.2462136989
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_may_nack.3278115317
Short name T268
Test name
Test status
Simulation time 517735699 ps
CPU time 11.74 seconds
Started Oct 15 11:45:35 AM UTC 24
Finished Oct 15 11:45:47 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278115317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.3278115317
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_override.1753985503
Short name T357
Test name
Test status
Simulation time 140229475 ps
CPU time 1.1 seconds
Started Oct 15 11:44:55 AM UTC 24
Finished Oct 15 11:44:58 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753985503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.1753985503
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_perf.341051235
Short name T15
Test name
Test status
Simulation time 4848452874 ps
CPU time 128.82 seconds
Started Oct 15 11:44:59 AM UTC 24
Finished Oct 15 11:47:10 AM UTC 24
Peak memory 1280896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341051235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.341051235
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_perf_precise.2512988484
Short name T542
Test name
Test status
Simulation time 23397389395 ps
CPU time 288.06 seconds
Started Oct 15 11:45:00 AM UTC 24
Finished Oct 15 11:49:52 AM UTC 24
Peak memory 226148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512988484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.2512988484
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_smoke.3235235345
Short name T410
Test name
Test status
Simulation time 3439691474 ps
CPU time 38.21 seconds
Started Oct 15 11:44:53 AM UTC 24
Finished Oct 15 11:45:33 AM UTC 24
Peak memory 390132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235235345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.3235235345
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_host_stretch_timeout.1851189289
Short name T401
Test name
Test status
Simulation time 455523489 ps
CPU time 7.32 seconds
Started Oct 15 11:45:00 AM UTC 24
Finished Oct 15 11:45:08 AM UTC 24
Peak memory 225908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851189289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.1851189289
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_bad_addr.1903924407
Short name T415
Test name
Test status
Simulation time 1354781406 ps
CPU time 8.28 seconds
Started Oct 15 11:45:29 AM UTC 24
Finished Oct 15 11:45:39 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1903924407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.1903924407
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_acq.860679494
Short name T406
Test name
Test status
Simulation time 474227436 ps
CPU time 1.79 seconds
Started Oct 15 11:45:25 AM UTC 24
Finished Oct 15 11:45:28 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8606794
94 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_acq.860679494
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_tx.3283659265
Short name T408
Test name
Test status
Simulation time 655582648 ps
CPU time 2.69 seconds
Started Oct 15 11:45:25 AM UTC 24
Finished Oct 15 11:45:29 AM UTC 24
Peak memory 215764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283659
265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_tx.3283659265
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_acq.344000453
Short name T417
Test name
Test status
Simulation time 1115298681 ps
CPU time 5.33 seconds
Started Oct 15 11:45:37 AM UTC 24
Finished Oct 15 11:45:43 AM UTC 24
Peak memory 215444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440004
53 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_watermarks
_acq.344000453
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_tx.4231648452
Short name T416
Test name
Test status
Simulation time 491198359 ps
CPU time 1.94 seconds
Started Oct 15 11:45:40 AM UTC 24
Finished Oct 15 11:45:43 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231648
452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_watermarks
_tx.4231648452
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_hrst.1152205087
Short name T413
Test name
Test status
Simulation time 419541151 ps
CPU time 4.03 seconds
Started Oct 15 11:45:30 AM UTC 24
Finished Oct 15 11:45:36 AM UTC 24
Peak memory 225824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152205
087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_hrst.1152205087
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_intr_smoke.1592563850
Short name T405
Test name
Test status
Simulation time 2764154352 ps
CPU time 15.08 seconds
Started Oct 15 11:45:10 AM UTC 24
Finished Oct 15 11:45:26 AM UTC 24
Peak memory 242644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159256
3850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_smoke.1592563850
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_intr_stress_wr.3799038940
Short name T467
Test name
Test status
Simulation time 16441600747 ps
CPU time 153.21 seconds
Started Oct 15 11:45:12 AM UTC 24
Finished Oct 15 11:47:47 AM UTC 24
Peak memory 2532292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3799038940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_stress
_wr.3799038940
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull.685405835
Short name T56
Test name
Test status
Simulation time 1001070389 ps
CPU time 4.87 seconds
Started Oct 15 11:45:42 AM UTC 24
Finished Oct 15 11:45:48 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6854058
35 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_acqfull.685405835
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull_addr.2992455208
Short name T422
Test name
Test status
Simulation time 2702489905 ps
CPU time 4.89 seconds
Started Oct 15 11:45:43 AM UTC 24
Finished Oct 15 11:45:49 AM UTC 24
Peak memory 215484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992455
208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.2992455208
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_nack_txstretch.2997795845
Short name T182
Test name
Test status
Simulation time 307043521 ps
CPU time 2.31 seconds
Started Oct 15 11:45:44 AM UTC 24
Finished Oct 15 11:45:47 AM UTC 24
Peak memory 232520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997795
845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_txstretch.2997795845
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_perf.360241833
Short name T412
Test name
Test status
Simulation time 453266477 ps
CPU time 5 seconds
Started Oct 15 11:45:27 AM UTC 24
Finished Oct 15 11:45:33 AM UTC 24
Peak memory 232260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602418
33 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_perf.360241833
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_smbus_maxlen.1558774271
Short name T419
Test name
Test status
Simulation time 987968568 ps
CPU time 4.67 seconds
Started Oct 15 11:45:40 AM UTC 24
Finished Oct 15 11:45:46 AM UTC 24
Peak memory 215240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558774
271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smbus_maxlen.1558774271
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_smoke.631924540
Short name T293
Test name
Test status
Simulation time 3461719973 ps
CPU time 13.25 seconds
Started Oct 15 11:45:03 AM UTC 24
Finished Oct 15 11:45:18 AM UTC 24
Peak memory 232448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631924540 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smoke.631924540
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_stress_all.3253792949
Short name T221
Test name
Test status
Simulation time 104698732480 ps
CPU time 376.75 seconds
Started Oct 15 11:45:29 AM UTC 24
Finished Oct 15 11:51:51 AM UTC 24
Peak memory 2966784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325379
2949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_all.3253792949
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_stress_rd.1502637809
Short name T404
Test name
Test status
Simulation time 2117856361 ps
CPU time 18.25 seconds
Started Oct 15 11:45:04 AM UTC 24
Finished Oct 15 11:45:24 AM UTC 24
Peak memory 229844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502637809 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_rd.1502637809
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_stress_wr.2058242384
Short name T1151
Test name
Test status
Simulation time 68162443571 ps
CPU time 1426.93 seconds
Started Oct 15 11:45:04 AM UTC 24
Finished Oct 15 12:09:05 PM UTC 24
Peak memory 12088188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058242384 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_wr.2058242384
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_stretch.2148898802
Short name T402
Test name
Test status
Simulation time 364369593 ps
CPU time 1.69 seconds
Started Oct 15 11:45:08 AM UTC 24
Finished Oct 15 11:45:11 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148898802 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stretch.2148898802
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/8.i2c_target_timeout.4086147177
Short name T409
Test name
Test status
Simulation time 2232559101 ps
CPU time 11.82 seconds
Started Oct 15 11:45:19 AM UTC 24
Finished Oct 15 11:45:32 AM UTC 24
Peak memory 225748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086147
177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_timeout.4086147177
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/8.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_alert_test.2920489176
Short name T450
Test name
Test status
Simulation time 52735142 ps
CPU time 1.03 seconds
Started Oct 15 11:46:51 AM UTC 24
Finished Oct 15 11:46:53 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920489176 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.2920489176
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_error_intr.3412978638
Short name T429
Test name
Test status
Simulation time 130221589 ps
CPU time 2.76 seconds
Started Oct 15 11:46:02 AM UTC 24
Finished Oct 15 11:46:06 AM UTC 24
Peak memory 227760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412978638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3412978638
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_fmt_empty.4212439151
Short name T426
Test name
Test status
Simulation time 165332735 ps
CPU time 11.22 seconds
Started Oct 15 11:45:48 AM UTC 24
Finished Oct 15 11:46:01 AM UTC 24
Peak memory 244984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212439151 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty.4212439151
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_full.535790587
Short name T453
Test name
Test status
Simulation time 11547860053 ps
CPU time 70.91 seconds
Started Oct 15 11:45:50 AM UTC 24
Finished Oct 15 11:47:02 AM UTC 24
Peak memory 531468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535790587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.535790587
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_overflow.1139366773
Short name T442
Test name
Test status
Simulation time 2622198924 ps
CPU time 55.52 seconds
Started Oct 15 11:45:48 AM UTC 24
Finished Oct 15 11:46:45 AM UTC 24
Peak memory 728008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139366773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1139366773
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_fmt.2977690563
Short name T424
Test name
Test status
Simulation time 136258827 ps
CPU time 1.66 seconds
Started Oct 15 11:45:48 AM UTC 24
Finished Oct 15 11:45:51 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977690563 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt.2977690563
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_rx.2263541500
Short name T425
Test name
Test status
Simulation time 387118633 ps
CPU time 5.15 seconds
Started Oct 15 11:45:50 AM UTC 24
Finished Oct 15 11:45:56 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263541500 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.2263541500
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_watermark.797835177
Short name T501
Test name
Test status
Simulation time 12588746188 ps
CPU time 166.52 seconds
Started Oct 15 11:45:47 AM UTC 24
Finished Oct 15 11:48:36 AM UTC 24
Peak memory 988088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797835177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.797835177
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_may_nack.2812377397
Short name T444
Test name
Test status
Simulation time 3879775338 ps
CPU time 7.58 seconds
Started Oct 15 11:46:38 AM UTC 24
Finished Oct 15 11:46:47 AM UTC 24
Peak memory 215580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812377397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.2812377397
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_override.1340618612
Short name T421
Test name
Test status
Simulation time 22102499 ps
CPU time 1.09 seconds
Started Oct 15 11:45:46 AM UTC 24
Finished Oct 15 11:45:48 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340618612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.1340618612
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_perf.3011623555
Short name T428
Test name
Test status
Simulation time 3977058380 ps
CPU time 12.9 seconds
Started Oct 15 11:45:50 AM UTC 24
Finished Oct 15 11:46:04 AM UTC 24
Peak memory 232628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011623555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.3011623555
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_smoke.2179567953
Short name T271
Test name
Test status
Simulation time 1308552412 ps
CPU time 25.01 seconds
Started Oct 15 11:45:46 AM UTC 24
Finished Oct 15 11:46:12 AM UTC 24
Peak memory 314304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179567953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2179567953
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_host_stretch_timeout.1982001857
Short name T433
Test name
Test status
Simulation time 2643461974 ps
CPU time 19.81 seconds
Started Oct 15 11:45:57 AM UTC 24
Finished Oct 15 11:46:18 AM UTC 24
Peak memory 232608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982001857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.1982001857
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_bad_addr.3377569059
Short name T438
Test name
Test status
Simulation time 2136455397 ps
CPU time 8.14 seconds
Started Oct 15 11:46:25 AM UTC 24
Finished Oct 15 11:46:34 AM UTC 24
Peak memory 231908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3377569059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.3377569059
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_acq.3604073623
Short name T183
Test name
Test status
Simulation time 600027904 ps
CPU time 2.52 seconds
Started Oct 15 11:46:19 AM UTC 24
Finished Oct 15 11:46:22 AM UTC 24
Peak memory 215856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604073
623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_acq.3604073623
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_tx.664890100
Short name T435
Test name
Test status
Simulation time 296697906 ps
CPU time 1.53 seconds
Started Oct 15 11:46:22 AM UTC 24
Finished Oct 15 11:46:24 AM UTC 24
Peak memory 225432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6648901
00 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_tx.664890100
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_acq.1141137862
Short name T440
Test name
Test status
Simulation time 2482595697 ps
CPU time 2.61 seconds
Started Oct 15 11:46:39 AM UTC 24
Finished Oct 15 11:46:43 AM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141137
862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_watermark
s_acq.1141137862
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_tx.3367449070
Short name T443
Test name
Test status
Simulation time 289867048 ps
CPU time 1.53 seconds
Started Oct 15 11:46:43 AM UTC 24
Finished Oct 15 11:46:46 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367449
070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_watermarks
_tx.3367449070
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_intr_smoke.3192524431
Short name T434
Test name
Test status
Simulation time 2680477705 ps
CPU time 7.9 seconds
Started Oct 15 11:46:13 AM UTC 24
Finished Oct 15 11:46:22 AM UTC 24
Peak memory 225700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319252
4431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_smoke.3192524431
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_intr_stress_wr.1148899137
Short name T411
Test name
Test status
Simulation time 4565303419 ps
CPU time 54.8 seconds
Started Oct 15 11:46:17 AM UTC 24
Finished Oct 15 11:47:14 AM UTC 24
Peak memory 1213700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1148899137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_stress
_wr.1148899137
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull.113062608
Short name T449
Test name
Test status
Simulation time 2267628977 ps
CPU time 4.86 seconds
Started Oct 15 11:46:47 AM UTC 24
Finished Oct 15 11:46:53 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130626
08 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_acqfull.113062608
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull_addr.3459218092
Short name T448
Test name
Test status
Simulation time 1910844895 ps
CPU time 3.76 seconds
Started Oct 15 11:46:48 AM UTC 24
Finished Oct 15 11:46:53 AM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459218
092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.3459218092
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_nack_txstretch.3757458743
Short name T184
Test name
Test status
Simulation time 317106446 ps
CPU time 1.71 seconds
Started Oct 15 11:46:50 AM UTC 24
Finished Oct 15 11:46:53 AM UTC 24
Peak memory 232652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757458
743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_txstretch.3757458743
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_perf.1718056019
Short name T436
Test name
Test status
Simulation time 2142045508 ps
CPU time 6.75 seconds
Started Oct 15 11:46:23 AM UTC 24
Finished Oct 15 11:46:31 AM UTC 24
Peak memory 227652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718056
019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_perf.1718056019
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_smbus_maxlen.1291002598
Short name T447
Test name
Test status
Simulation time 1823726711 ps
CPU time 3.93 seconds
Started Oct 15 11:46:47 AM UTC 24
Finished Oct 15 11:46:52 AM UTC 24
Peak memory 215496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291002
598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smbus_maxlen.1291002598
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_smoke.1407066462
Short name T430
Test name
Test status
Simulation time 547447519 ps
CPU time 11.92 seconds
Started Oct 15 11:46:04 AM UTC 24
Finished Oct 15 11:46:17 AM UTC 24
Peak memory 225756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407066462 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smoke.1407066462
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_stress_all.1121342066
Short name T552
Test name
Test status
Simulation time 15446084306 ps
CPU time 245.14 seconds
Started Oct 15 11:46:23 AM UTC 24
Finished Oct 15 11:50:32 AM UTC 24
Peak memory 2837504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112134
2066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_all.1121342066
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_stress_rd.1549383197
Short name T441
Test name
Test status
Simulation time 19516552190 ps
CPU time 66.56 seconds
Started Oct 15 11:46:11 AM UTC 24
Finished Oct 15 11:47:20 AM UTC 24
Peak memory 229848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549383197 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_rd.1549383197
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_stress_wr.303794630
Short name T445
Test name
Test status
Simulation time 32190532071 ps
CPU time 41.79 seconds
Started Oct 15 11:46:06 AM UTC 24
Finished Oct 15 11:46:49 AM UTC 24
Peak memory 828364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303794630 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_wr.303794630
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_stretch.3034724626
Short name T431
Test name
Test status
Simulation time 681129660 ps
CPU time 3.86 seconds
Started Oct 15 11:46:12 AM UTC 24
Finished Oct 15 11:46:17 AM UTC 24
Peak memory 228236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034724626 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stretch.3034724626
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_timeout.1518525987
Short name T437
Test name
Test status
Simulation time 4877416326 ps
CPU time 12.11 seconds
Started Oct 15 11:46:19 AM UTC 24
Finished Oct 15 11:46:32 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518525
987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_timeout.1518525987
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/9.i2c_target_tx_stretch_ctrl.657021145
Short name T446
Test name
Test status
Simulation time 109424281 ps
CPU time 2.87 seconds
Started Oct 15 11:46:47 AM UTC 24
Finished Oct 15 11:46:50 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6570211
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.657021145
Directory /workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/9.i2c_target_tx_stretch_ctrl/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%