| T1562 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.615783894 |
|
|
Oct 15 12:19:34 PM UTC 24 |
Oct 15 12:21:19 PM UTC 24 |
3053852707 ps |
| T1563 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_host_stress_all.2811387645 |
|
|
Oct 15 12:15:49 PM UTC 24 |
Oct 15 12:21:25 PM UTC 24 |
46724853106 ps |
| T1564 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.873726555 |
|
|
Oct 15 12:20:39 PM UTC 24 |
Oct 15 12:21:33 PM UTC 24 |
4235915397 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_intr_smoke.3685130652 |
|
|
Oct 15 12:21:27 PM UTC 24 |
Oct 15 12:21:33 PM UTC 24 |
2047510773 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.3407453286 |
|
|
Oct 15 12:21:12 PM UTC 24 |
Oct 15 12:21:34 PM UTC 24 |
1547519541 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.2100187080 |
|
|
Oct 15 12:20:48 PM UTC 24 |
Oct 15 12:21:35 PM UTC 24 |
4127564682 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_stretch.3010274813 |
|
|
Oct 15 12:21:20 PM UTC 24 |
Oct 15 12:21:50 PM UTC 24 |
1593687749 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_acq.971233114 |
|
|
Oct 15 12:21:36 PM UTC 24 |
Oct 15 12:21:39 PM UTC 24 |
537021478 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_tx.690575038 |
|
|
Oct 15 12:21:39 PM UTC 24 |
Oct 15 12:21:42 PM UTC 24 |
145938153 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.2308449113 |
|
|
Oct 15 12:19:31 PM UTC 24 |
Oct 15 12:21:42 PM UTC 24 |
10715598815 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.3565008166 |
|
|
Oct 15 12:21:34 PM UTC 24 |
Oct 15 12:21:46 PM UTC 24 |
14870330673 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_perf.150970248 |
|
|
Oct 15 12:21:39 PM UTC 24 |
Oct 15 12:21:46 PM UTC 24 |
866650871 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/41.i2c_host_perf_precise.2912561985 |
|
|
Oct 15 12:16:23 PM UTC 24 |
Oct 15 12:21:47 PM UTC 24 |
23230757913 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_hrst.503896631 |
|
|
Oct 15 12:21:43 PM UTC 24 |
Oct 15 12:21:48 PM UTC 24 |
824688558 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.3951953623 |
|
|
Oct 15 12:21:49 PM UTC 24 |
Oct 15 12:21:51 PM UTC 24 |
144874349 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.1070898932 |
|
|
Oct 15 12:21:48 PM UTC 24 |
Oct 15 12:21:52 PM UTC 24 |
4753297833 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.3657346341 |
|
|
Oct 15 12:21:50 PM UTC 24 |
Oct 15 12:21:54 PM UTC 24 |
86778358 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.762167159 |
|
|
Oct 15 12:21:51 PM UTC 24 |
Oct 15 12:21:57 PM UTC 24 |
2215276070 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.793667844 |
|
|
Oct 15 12:24:44 PM UTC 24 |
Oct 15 12:24:51 PM UTC 24 |
1104769283 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_alert_test.807539847 |
|
|
Oct 15 12:21:55 PM UTC 24 |
Oct 15 12:21:57 PM UTC 24 |
22665349 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.151914428 |
|
|
Oct 15 12:21:48 PM UTC 24 |
Oct 15 12:21:57 PM UTC 24 |
1031817161 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.2656616158 |
|
|
Oct 15 12:21:52 PM UTC 24 |
Oct 15 12:21:57 PM UTC 24 |
2300764461 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.1373928897 |
|
|
Oct 15 12:21:52 PM UTC 24 |
Oct 15 12:21:58 PM UTC 24 |
1098239043 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.1218223483 |
|
|
Oct 15 12:20:27 PM UTC 24 |
Oct 15 12:22:00 PM UTC 24 |
1990977654 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_override.2242839489 |
|
|
Oct 15 12:21:58 PM UTC 24 |
Oct 15 12:22:00 PM UTC 24 |
21951469 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.965278395 |
|
|
Oct 15 12:21:58 PM UTC 24 |
Oct 15 12:22:01 PM UTC 24 |
83931641 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.3476753325 |
|
|
Oct 15 12:21:59 PM UTC 24 |
Oct 15 12:22:07 PM UTC 24 |
1277929824 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.1609654606 |
|
|
Oct 15 12:18:19 PM UTC 24 |
Oct 15 12:22:14 PM UTC 24 |
3855845228 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_intr_stress_wr.4193561527 |
|
|
Oct 15 12:19:01 PM UTC 24 |
Oct 15 12:22:15 PM UTC 24 |
23668705972 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.2402136020 |
|
|
Oct 15 12:22:01 PM UTC 24 |
Oct 15 12:22:15 PM UTC 24 |
232541064 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.1044583067 |
|
|
Oct 15 12:22:08 PM UTC 24 |
Oct 15 12:22:19 PM UTC 24 |
230869664 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.2907137304 |
|
|
Oct 15 12:22:16 PM UTC 24 |
Oct 15 12:22:20 PM UTC 24 |
186186388 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.1207923555 |
|
|
Oct 15 12:22:14 PM UTC 24 |
Oct 15 12:22:24 PM UTC 24 |
1968932516 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.2496288528 |
|
|
Oct 15 12:21:57 PM UTC 24 |
Oct 15 12:22:31 PM UTC 24 |
1518822511 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.2507648595 |
|
|
Oct 15 12:22:20 PM UTC 24 |
Oct 15 12:23:02 PM UTC 24 |
5875138397 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.478792871 |
|
|
Oct 15 12:22:21 PM UTC 24 |
Oct 15 12:23:16 PM UTC 24 |
37977846946 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.2485553899 |
|
|
Oct 15 12:23:04 PM UTC 24 |
Oct 15 12:23:16 PM UTC 24 |
5552396135 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.307281650 |
|
|
Oct 15 12:23:17 PM UTC 24 |
Oct 15 12:23:20 PM UTC 24 |
221035331 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/39.i2c_target_stress_all.3267769098 |
|
|
Oct 15 12:15:25 PM UTC 24 |
Oct 15 12:39:50 PM UTC 24 |
55692627933 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.2529068158 |
|
|
Oct 15 12:23:19 PM UTC 24 |
Oct 15 12:23:22 PM UTC 24 |
392498845 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.2087985019 |
|
|
Oct 15 12:21:39 PM UTC 24 |
Oct 15 12:23:30 PM UTC 24 |
52899055266 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_perf.1913939468 |
|
|
Oct 15 12:23:20 PM UTC 24 |
Oct 15 12:23:31 PM UTC 24 |
819653804 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.1572225000 |
|
|
Oct 15 12:23:16 PM UTC 24 |
Oct 15 12:23:32 PM UTC 24 |
1457355253 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.1719972364 |
|
|
Oct 15 12:23:23 PM UTC 24 |
Oct 15 12:23:34 PM UTC 24 |
5073649572 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.4034323813 |
|
|
Oct 15 12:22:25 PM UTC 24 |
Oct 15 12:23:37 PM UTC 24 |
5292482294 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.214131993 |
|
|
Oct 15 12:20:28 PM UTC 24 |
Oct 15 12:23:38 PM UTC 24 |
2496889508 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.3059420484 |
|
|
Oct 15 12:23:36 PM UTC 24 |
Oct 15 12:23:39 PM UTC 24 |
136049611 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.2819682544 |
|
|
Oct 15 12:23:35 PM UTC 24 |
Oct 15 12:23:39 PM UTC 24 |
1336864243 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.1803723230 |
|
|
Oct 15 12:18:43 PM UTC 24 |
Oct 15 12:23:43 PM UTC 24 |
49680964730 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.4244309321 |
|
|
Oct 15 12:23:39 PM UTC 24 |
Oct 15 12:23:45 PM UTC 24 |
2048531512 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.424570786 |
|
|
Oct 15 12:20:31 PM UTC 24 |
Oct 15 12:23:45 PM UTC 24 |
25535636886 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.610549185 |
|
|
Oct 15 12:23:40 PM UTC 24 |
Oct 15 12:23:45 PM UTC 24 |
1907658407 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_nack_txstretch.2127230619 |
|
|
Oct 15 12:23:42 PM UTC 24 |
Oct 15 12:23:46 PM UTC 24 |
263247861 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.652395418 |
|
|
Oct 15 12:23:40 PM UTC 24 |
Oct 15 12:23:46 PM UTC 24 |
1139245653 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_alert_test.3379090941 |
|
|
Oct 15 12:23:44 PM UTC 24 |
Oct 15 12:23:46 PM UTC 24 |
71861958 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_override.1111275930 |
|
|
Oct 15 12:23:46 PM UTC 24 |
Oct 15 12:23:48 PM UTC 24 |
89361103 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.3714603607 |
|
|
Oct 15 12:21:58 PM UTC 24 |
Oct 15 12:23:49 PM UTC 24 |
2052899327 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.565942174 |
|
|
Oct 15 12:23:33 PM UTC 24 |
Oct 15 12:23:49 PM UTC 24 |
1523802948 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.3804286927 |
|
|
Oct 15 12:23:48 PM UTC 24 |
Oct 15 12:23:51 PM UTC 24 |
491023137 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.3744143103 |
|
|
Oct 15 12:23:48 PM UTC 24 |
Oct 15 12:23:53 PM UTC 24 |
130748498 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.953045362 |
|
|
Oct 15 12:23:49 PM UTC 24 |
Oct 15 12:23:56 PM UTC 24 |
729588615 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.1125857080 |
|
|
Oct 15 12:23:51 PM UTC 24 |
Oct 15 12:23:56 PM UTC 24 |
286900994 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.14455334 |
|
|
Oct 15 12:23:39 PM UTC 24 |
Oct 15 12:24:00 PM UTC 24 |
1017368996 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.3776341071 |
|
|
Oct 15 12:23:57 PM UTC 24 |
Oct 15 12:24:02 PM UTC 24 |
1178387639 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.985654124 |
|
|
Oct 15 12:23:16 PM UTC 24 |
Oct 15 12:24:03 PM UTC 24 |
13988358114 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.385423744 |
|
|
Oct 15 12:23:54 PM UTC 24 |
Oct 15 12:24:15 PM UTC 24 |
3626861296 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.3263879357 |
|
|
Oct 15 12:17:38 PM UTC 24 |
Oct 15 12:24:21 PM UTC 24 |
39433696913 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.2684686922 |
|
|
Oct 15 12:24:04 PM UTC 24 |
Oct 15 12:24:24 PM UTC 24 |
3482764890 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.1831001045 |
|
|
Oct 15 12:26:30 PM UTC 24 |
Oct 15 12:39:18 PM UTC 24 |
42674403211 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_perf.1297055931 |
|
|
Oct 15 12:23:50 PM UTC 24 |
Oct 15 12:24:27 PM UTC 24 |
3248917849 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.3182499581 |
|
|
Oct 15 12:24:22 PM UTC 24 |
Oct 15 12:24:28 PM UTC 24 |
850005223 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_target_stress_wr.1730189060 |
|
|
Oct 15 12:13:15 PM UTC 24 |
Oct 15 12:24:28 PM UTC 24 |
70445120538 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.1001907386 |
|
|
Oct 15 12:24:28 PM UTC 24 |
Oct 15 12:24:31 PM UTC 24 |
169672283 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.2317432976 |
|
|
Oct 15 12:24:29 PM UTC 24 |
Oct 15 12:24:32 PM UTC 24 |
198808056 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.1899035244 |
|
|
Oct 15 12:23:46 PM UTC 24 |
Oct 15 12:24:33 PM UTC 24 |
1641572192 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.1304954040 |
|
|
Oct 15 12:24:01 PM UTC 24 |
Oct 15 12:24:35 PM UTC 24 |
981213874 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.466522807 |
|
|
Oct 15 12:24:32 PM UTC 24 |
Oct 15 12:24:37 PM UTC 24 |
655354036 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_perf.3399052217 |
|
|
Oct 15 12:24:30 PM UTC 24 |
Oct 15 12:24:39 PM UTC 24 |
3066777657 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/14.i2c_host_perf.2382275928 |
|
|
Oct 15 11:50:56 AM UTC 24 |
Oct 15 12:45:31 PM UTC 24 |
70201675835 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_hrst.1480875682 |
|
|
Oct 15 12:24:34 PM UTC 24 |
Oct 15 12:24:40 PM UTC 24 |
315558509 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.2970503538 |
|
|
Oct 15 12:24:27 PM UTC 24 |
Oct 15 12:24:43 PM UTC 24 |
1517863076 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.448463853 |
|
|
Oct 15 12:21:34 PM UTC 24 |
Oct 15 12:24:43 PM UTC 24 |
18907891187 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.2639818954 |
|
|
Oct 15 12:24:41 PM UTC 24 |
Oct 15 12:24:43 PM UTC 24 |
93901768 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.790512083 |
|
|
Oct 15 12:20:28 PM UTC 24 |
Oct 15 12:24:43 PM UTC 24 |
7683263810 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.3777797477 |
|
|
Oct 15 12:24:41 PM UTC 24 |
Oct 15 12:24:44 PM UTC 24 |
61659663 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.1919056696 |
|
|
Oct 15 12:24:40 PM UTC 24 |
Oct 15 12:24:45 PM UTC 24 |
716291724 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.2654053741 |
|
|
Oct 15 12:24:38 PM UTC 24 |
Oct 15 12:24:47 PM UTC 24 |
447568194 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_override.2492971147 |
|
|
Oct 15 12:24:45 PM UTC 24 |
Oct 15 12:24:47 PM UTC 24 |
100647991 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_alert_test.2231268143 |
|
|
Oct 15 12:24:45 PM UTC 24 |
Oct 15 12:24:47 PM UTC 24 |
43382166 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.2437023536 |
|
|
Oct 15 12:24:44 PM UTC 24 |
Oct 15 12:24:48 PM UTC 24 |
545341729 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.333838310 |
|
|
Oct 15 12:24:44 PM UTC 24 |
Oct 15 12:24:49 PM UTC 24 |
422201124 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.3720170293 |
|
|
Oct 15 12:24:48 PM UTC 24 |
Oct 15 12:24:50 PM UTC 24 |
406674293 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.1183156967 |
|
|
Oct 15 12:24:44 PM UTC 24 |
Oct 15 12:24:50 PM UTC 24 |
2165461399 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.3029928842 |
|
|
Oct 15 12:20:12 PM UTC 24 |
Oct 15 12:54:40 PM UTC 24 |
84155582891 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.1696017991 |
|
|
Oct 15 12:24:25 PM UTC 24 |
Oct 15 12:24:53 PM UTC 24 |
25235992558 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.412424283 |
|
|
Oct 15 12:24:49 PM UTC 24 |
Oct 15 12:24:55 PM UTC 24 |
134401392 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.1266884466 |
|
|
Oct 15 12:24:49 PM UTC 24 |
Oct 15 12:25:01 PM UTC 24 |
750161215 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.2718952202 |
|
|
Oct 15 12:24:54 PM UTC 24 |
Oct 15 12:25:01 PM UTC 24 |
1551275740 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.2402800410 |
|
|
Oct 15 12:20:05 PM UTC 24 |
Oct 15 12:25:03 PM UTC 24 |
21393258980 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.176661916 |
|
|
Oct 15 12:24:51 PM UTC 24 |
Oct 15 12:25:05 PM UTC 24 |
324308643 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.3692043908 |
|
|
Oct 15 12:24:02 PM UTC 24 |
Oct 15 12:25:09 PM UTC 24 |
18700559370 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.1781724891 |
|
|
Oct 15 12:23:45 PM UTC 24 |
Oct 15 12:25:10 PM UTC 24 |
9556582342 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_perf.2426065943 |
|
|
Oct 15 12:22:02 PM UTC 24 |
Oct 15 12:25:14 PM UTC 24 |
24498114384 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.2492700920 |
|
|
Oct 15 12:24:52 PM UTC 24 |
Oct 15 12:25:17 PM UTC 24 |
1744140096 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.4184486648 |
|
|
Oct 15 12:25:10 PM UTC 24 |
Oct 15 12:25:18 PM UTC 24 |
645488934 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.428062315 |
|
|
Oct 15 12:25:06 PM UTC 24 |
Oct 15 12:25:18 PM UTC 24 |
1045040664 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.651037522 |
|
|
Oct 15 12:22:02 PM UTC 24 |
Oct 15 12:25:21 PM UTC 24 |
3214376271 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.3664526005 |
|
|
Oct 15 12:25:19 PM UTC 24 |
Oct 15 12:25:21 PM UTC 24 |
199663036 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.2941989850 |
|
|
Oct 15 12:25:19 PM UTC 24 |
Oct 15 12:25:22 PM UTC 24 |
391468277 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.972189502 |
|
|
Oct 15 12:24:45 PM UTC 24 |
Oct 15 12:25:22 PM UTC 24 |
1848841679 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.1543045895 |
|
|
Oct 15 12:25:01 PM UTC 24 |
Oct 15 12:25:23 PM UTC 24 |
2705621220 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.2561601841 |
|
|
Oct 15 12:25:04 PM UTC 24 |
Oct 15 12:25:26 PM UTC 24 |
1197110425 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.3872909265 |
|
|
Oct 15 12:23:46 PM UTC 24 |
Oct 15 12:25:26 PM UTC 24 |
66455187124 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.3046811702 |
|
|
Oct 15 12:25:15 PM UTC 24 |
Oct 15 12:25:27 PM UTC 24 |
5319981638 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_perf.3608026973 |
|
|
Oct 15 12:25:21 PM UTC 24 |
Oct 15 12:25:27 PM UTC 24 |
1949857809 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.2455048931 |
|
|
Oct 15 12:24:48 PM UTC 24 |
Oct 15 12:25:29 PM UTC 24 |
7568926862 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.2236551423 |
|
|
Oct 15 12:25:22 PM UTC 24 |
Oct 15 12:25:30 PM UTC 24 |
2813510659 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.1614592376 |
|
|
Oct 15 12:25:27 PM UTC 24 |
Oct 15 12:25:30 PM UTC 24 |
898083469 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.646946185 |
|
|
Oct 15 12:25:23 PM UTC 24 |
Oct 15 12:25:31 PM UTC 24 |
5852896762 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.4216252027 |
|
|
Oct 15 12:25:28 PM UTC 24 |
Oct 15 12:25:33 PM UTC 24 |
245663090 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.2467657727 |
|
|
Oct 15 12:25:26 PM UTC 24 |
Oct 15 12:25:33 PM UTC 24 |
3525719754 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_alert_test.2706457612 |
|
|
Oct 15 12:25:32 PM UTC 24 |
Oct 15 12:25:34 PM UTC 24 |
28370306 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.3881318310 |
|
|
Oct 15 12:25:29 PM UTC 24 |
Oct 15 12:25:34 PM UTC 24 |
1031748886 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.4195589112 |
|
|
Oct 15 12:25:30 PM UTC 24 |
Oct 15 12:25:36 PM UTC 24 |
578688817 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.957756554 |
|
|
Oct 15 12:25:31 PM UTC 24 |
Oct 15 12:25:36 PM UTC 24 |
2028773187 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_override.3805473278 |
|
|
Oct 15 12:25:34 PM UTC 24 |
Oct 15 12:25:36 PM UTC 24 |
51816550 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_mode_toggle.1817575303 |
|
|
Oct 15 12:25:23 PM UTC 24 |
Oct 15 12:25:37 PM UTC 24 |
511040275 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.2229133392 |
|
|
Oct 15 12:25:35 PM UTC 24 |
Oct 15 12:25:38 PM UTC 24 |
76071544 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.871961691 |
|
|
Oct 15 12:25:36 PM UTC 24 |
Oct 15 12:25:45 PM UTC 24 |
354528673 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.1005553454 |
|
|
Oct 15 12:25:38 PM UTC 24 |
Oct 15 12:25:49 PM UTC 24 |
565811396 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.3636592316 |
|
|
Oct 15 12:25:39 PM UTC 24 |
Oct 15 12:25:52 PM UTC 24 |
1309617464 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.2870675512 |
|
|
Oct 15 12:23:50 PM UTC 24 |
Oct 15 12:25:53 PM UTC 24 |
12428757241 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.2089791682 |
|
|
Oct 15 12:25:49 PM UTC 24 |
Oct 15 12:25:54 PM UTC 24 |
466007973 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.2034219237 |
|
|
Oct 15 12:24:46 PM UTC 24 |
Oct 15 12:26:17 PM UTC 24 |
6777041787 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.3510884632 |
|
|
Oct 15 12:25:46 PM UTC 24 |
Oct 15 12:26:18 PM UTC 24 |
989357812 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.1847489397 |
|
|
Oct 15 12:25:55 PM UTC 24 |
Oct 15 12:26:19 PM UTC 24 |
17819059130 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.3937093765 |
|
|
Oct 15 12:18:01 PM UTC 24 |
Oct 15 12:26:25 PM UTC 24 |
41605727789 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.1327358667 |
|
|
Oct 15 12:26:13 PM UTC 24 |
Oct 15 12:26:28 PM UTC 24 |
406827918 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.3621921707 |
|
|
Oct 15 12:26:26 PM UTC 24 |
Oct 15 12:26:29 PM UTC 24 |
620796607 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/11.i2c_host_stress_all.1462527000 |
|
|
Oct 15 11:47:59 AM UTC 24 |
Oct 15 12:37:01 PM UTC 24 |
59105011062 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.69742905 |
|
|
Oct 15 12:25:53 PM UTC 24 |
Oct 15 12:26:29 PM UTC 24 |
1778990053 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.4005774055 |
|
|
Oct 15 12:26:20 PM UTC 24 |
Oct 15 12:26:29 PM UTC 24 |
10837194165 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.4282731420 |
|
|
Oct 15 12:26:18 PM UTC 24 |
Oct 15 12:26:30 PM UTC 24 |
2544808240 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.1012214944 |
|
|
Oct 15 12:25:35 PM UTC 24 |
Oct 15 12:26:30 PM UTC 24 |
4055786885 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.198139719 |
|
|
Oct 15 12:26:29 PM UTC 24 |
Oct 15 12:26:31 PM UTC 24 |
302439852 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_perf.849298607 |
|
|
Oct 15 12:25:38 PM UTC 24 |
Oct 15 12:38:09 PM UTC 24 |
12312679692 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.1030841947 |
|
|
Oct 15 12:21:58 PM UTC 24 |
Oct 15 12:26:33 PM UTC 24 |
18515942626 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_perf.957152862 |
|
|
Oct 15 12:26:30 PM UTC 24 |
Oct 15 12:26:37 PM UTC 24 |
4413489253 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.2768231630 |
|
|
Oct 15 12:26:32 PM UTC 24 |
Oct 15 12:26:38 PM UTC 24 |
988518582 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.499408644 |
|
|
Oct 15 12:26:31 PM UTC 24 |
Oct 15 12:26:39 PM UTC 24 |
355084104 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.4052825691 |
|
|
Oct 15 12:26:30 PM UTC 24 |
Oct 15 12:26:39 PM UTC 24 |
3285131508 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.3322694210 |
|
|
Oct 15 12:26:20 PM UTC 24 |
Oct 15 12:26:40 PM UTC 24 |
7378993198 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.1104896832 |
|
|
Oct 15 12:26:37 PM UTC 24 |
Oct 15 12:26:41 PM UTC 24 |
399615073 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.334230599 |
|
|
Oct 15 12:26:39 PM UTC 24 |
Oct 15 12:26:42 PM UTC 24 |
268496590 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_alert_test.2158080396 |
|
|
Oct 15 12:26:40 PM UTC 24 |
Oct 15 12:26:42 PM UTC 24 |
19097952 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.1437382690 |
|
|
Oct 15 12:26:38 PM UTC 24 |
Oct 15 12:26:43 PM UTC 24 |
3017643271 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.3172354783 |
|
|
Oct 15 12:26:38 PM UTC 24 |
Oct 15 12:26:44 PM UTC 24 |
5708871815 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_host_perf_precise.2467069310 |
|
|
Oct 15 12:20:33 PM UTC 24 |
Oct 15 12:26:57 PM UTC 24 |
24252716777 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.1415888484 |
|
|
Oct 15 12:25:01 PM UTC 24 |
Oct 15 12:27:22 PM UTC 24 |
39033653993 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.2862832250 |
|
|
Oct 15 12:25:34 PM UTC 24 |
Oct 15 12:27:22 PM UTC 24 |
17265201042 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.3711113245 |
|
|
Oct 15 12:26:07 PM UTC 24 |
Oct 15 12:27:31 PM UTC 24 |
7301812934 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.1108956398 |
|
|
Oct 15 12:24:50 PM UTC 24 |
Oct 15 12:27:44 PM UTC 24 |
2859821595 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.1568466932 |
|
|
Oct 15 12:25:35 PM UTC 24 |
Oct 15 12:27:48 PM UTC 24 |
19694041569 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.1956327726 |
|
|
Oct 15 12:24:31 PM UTC 24 |
Oct 15 12:27:49 PM UTC 24 |
29502834049 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/27.i2c_target_stress_all.1568793866 |
|
|
Oct 15 12:04:05 PM UTC 24 |
Oct 15 12:27:51 PM UTC 24 |
66696908121 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.601917512 |
|
|
Oct 15 12:25:38 PM UTC 24 |
Oct 15 12:28:12 PM UTC 24 |
2642645700 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.3049307321 |
|
|
Oct 15 12:19:51 PM UTC 24 |
Oct 15 12:28:49 PM UTC 24 |
40877507647 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/49.i2c_host_stress_all.745749158 |
|
|
Oct 15 12:25:53 PM UTC 24 |
Oct 15 12:29:12 PM UTC 24 |
12361950534 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/3.i2c_host_perf.2612028217 |
|
|
Oct 15 11:41:43 AM UTC 24 |
Oct 15 12:30:40 PM UTC 24 |
48958522403 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.3787793500 |
|
|
Oct 15 12:25:11 PM UTC 24 |
Oct 15 12:31:22 PM UTC 24 |
24282493385 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/40.i2c_host_perf.3865565575 |
|
|
Oct 15 12:15:42 PM UTC 24 |
Oct 15 12:32:35 PM UTC 24 |
25760695430 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.3452984636 |
|
|
Oct 15 12:23:22 PM UTC 24 |
Oct 15 12:35:42 PM UTC 24 |
92915308345 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/37.i2c_host_perf.3149684681 |
|
|
Oct 15 12:12:55 PM UTC 24 |
Oct 15 12:36:01 PM UTC 24 |
99042746147 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.4076643326 |
|
|
Oct 15 12:20:56 PM UTC 24 |
Oct 15 12:36:21 PM UTC 24 |
56720941973 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/default/48.i2c_host_perf.435728721 |
|
|
Oct 15 12:24:51 PM UTC 24 |
Oct 15 12:37:01 PM UTC 24 |
49697900998 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.256885338 |
|
|
Oct 15 12:26:40 PM UTC 24 |
Oct 15 12:26:44 PM UTC 24 |
153484745 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.573700737 |
|
|
Oct 15 12:26:41 PM UTC 24 |
Oct 15 12:26:44 PM UTC 24 |
69259625 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.2422481220 |
|
|
Oct 15 12:26:42 PM UTC 24 |
Oct 15 12:26:44 PM UTC 24 |
37615920 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.2971716994 |
|
|
Oct 15 12:26:42 PM UTC 24 |
Oct 15 12:26:45 PM UTC 24 |
28518300 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.3414218122 |
|
|
Oct 15 12:26:43 PM UTC 24 |
Oct 15 12:26:46 PM UTC 24 |
18711263 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1735528927 |
|
|
Oct 15 12:26:45 PM UTC 24 |
Oct 15 12:26:47 PM UTC 24 |
74682713 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1965741192 |
|
|
Oct 15 12:26:45 PM UTC 24 |
Oct 15 12:26:47 PM UTC 24 |
110553790 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.2413817456 |
|
|
Oct 15 12:26:45 PM UTC 24 |
Oct 15 12:26:48 PM UTC 24 |
113710454 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.2060155456 |
|
|
Oct 15 12:26:43 PM UTC 24 |
Oct 15 12:26:48 PM UTC 24 |
65323019 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.1541535698 |
|
|
Oct 15 12:26:46 PM UTC 24 |
Oct 15 12:26:49 PM UTC 24 |
563911712 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.1544717526 |
|
|
Oct 15 12:26:47 PM UTC 24 |
Oct 15 12:26:49 PM UTC 24 |
99643863 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.2569427187 |
|
|
Oct 15 12:26:46 PM UTC 24 |
Oct 15 12:26:50 PM UTC 24 |
149057877 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.1969155057 |
|
|
Oct 15 12:26:48 PM UTC 24 |
Oct 15 12:26:50 PM UTC 24 |
184389212 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.17389158 |
|
|
Oct 15 12:26:48 PM UTC 24 |
Oct 15 12:26:50 PM UTC 24 |
52459281 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1456074352 |
|
|
Oct 15 12:26:49 PM UTC 24 |
Oct 15 12:26:52 PM UTC 24 |
90762012 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.882843018 |
|
|
Oct 15 12:26:49 PM UTC 24 |
Oct 15 12:26:52 PM UTC 24 |
48757230 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.730271134 |
|
|
Oct 15 12:26:50 PM UTC 24 |
Oct 15 12:26:53 PM UTC 24 |
88449173 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.1350176153 |
|
|
Oct 15 12:26:52 PM UTC 24 |
Oct 15 12:26:54 PM UTC 24 |
17938054 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.1999352304 |
|
|
Oct 15 12:26:50 PM UTC 24 |
Oct 15 12:26:54 PM UTC 24 |
332661022 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.3175916859 |
|
|
Oct 15 12:26:50 PM UTC 24 |
Oct 15 12:26:55 PM UTC 24 |
87115026 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.519266616 |
|
|
Oct 15 12:26:49 PM UTC 24 |
Oct 15 12:26:55 PM UTC 24 |
535092674 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.2493199998 |
|
|
Oct 15 12:26:53 PM UTC 24 |
Oct 15 12:26:55 PM UTC 24 |
82450164 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.1532885307 |
|
|
Oct 15 12:26:53 PM UTC 24 |
Oct 15 12:26:55 PM UTC 24 |
54888341 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.2034531862 |
|
|
Oct 15 12:27:25 PM UTC 24 |
Oct 15 12:27:28 PM UTC 24 |
18142243 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2299358982 |
|
|
Oct 15 12:26:55 PM UTC 24 |
Oct 15 12:26:58 PM UTC 24 |
53007986 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.3079838533 |
|
|
Oct 15 12:26:56 PM UTC 24 |
Oct 15 12:26:58 PM UTC 24 |
18479397 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.1350665714 |
|
|
Oct 15 12:26:55 PM UTC 24 |
Oct 15 12:26:59 PM UTC 24 |
96781312 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3512756145 |
|
|
Oct 15 12:26:56 PM UTC 24 |
Oct 15 12:26:59 PM UTC 24 |
276594499 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.2743332648 |
|
|
Oct 15 12:26:56 PM UTC 24 |
Oct 15 12:26:59 PM UTC 24 |
47011905 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.974798880 |
|
|
Oct 15 12:26:56 PM UTC 24 |
Oct 15 12:26:59 PM UTC 24 |
150297178 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.3845650587 |
|
|
Oct 15 12:26:57 PM UTC 24 |
Oct 15 12:27:00 PM UTC 24 |
35293433 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.395641531 |
|
|
Oct 15 12:26:59 PM UTC 24 |
Oct 15 12:27:01 PM UTC 24 |
96666248 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.2829160293 |
|
|
Oct 15 12:26:54 PM UTC 24 |
Oct 15 12:27:02 PM UTC 24 |
525598664 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2245239874 |
|
|
Oct 15 12:27:00 PM UTC 24 |
Oct 15 12:27:02 PM UTC 24 |
88798473 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.107669172 |
|
|
Oct 15 12:27:00 PM UTC 24 |
Oct 15 12:27:02 PM UTC 24 |
40834975 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.3895671526 |
|
|
Oct 15 12:27:00 PM UTC 24 |
Oct 15 12:27:03 PM UTC 24 |
85186894 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.2927681486 |
|
|
Oct 15 12:27:01 PM UTC 24 |
Oct 15 12:27:03 PM UTC 24 |
15255429 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.3467133483 |
|
|
Oct 15 12:27:01 PM UTC 24 |
Oct 15 12:27:04 PM UTC 24 |
81722224 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.3857432271 |
|
|
Oct 15 12:27:02 PM UTC 24 |
Oct 15 12:27:04 PM UTC 24 |
37082465 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.2708230125 |
|
|
Oct 15 12:27:03 PM UTC 24 |
Oct 15 12:27:05 PM UTC 24 |
33736979 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.1977106373 |
|
|
Oct 15 12:27:00 PM UTC 24 |
Oct 15 12:27:06 PM UTC 24 |
125052279 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.332501070 |
|
|
Oct 15 12:27:04 PM UTC 24 |
Oct 15 12:27:06 PM UTC 24 |
34552670 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.3791835152 |
|
|
Oct 15 12:27:04 PM UTC 24 |
Oct 15 12:27:07 PM UTC 24 |
277167897 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.996956636 |
|
|
Oct 15 12:27:05 PM UTC 24 |
Oct 15 12:27:08 PM UTC 24 |
100850686 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.3813385736 |
|
|
Oct 15 12:27:06 PM UTC 24 |
Oct 15 12:27:08 PM UTC 24 |
26052802 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.4294950014 |
|
|
Oct 15 12:27:05 PM UTC 24 |
Oct 15 12:27:08 PM UTC 24 |
76930211 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.2409385049 |
|
|
Oct 15 12:27:00 PM UTC 24 |
Oct 15 12:27:08 PM UTC 24 |
4327213188 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.2595763663 |
|
|
Oct 15 12:27:06 PM UTC 24 |
Oct 15 12:27:09 PM UTC 24 |
55456866 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.3615019560 |
|
|
Oct 15 12:27:07 PM UTC 24 |
Oct 15 12:27:09 PM UTC 24 |
18162708 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.2881465282 |
|
|
Oct 15 12:27:18 PM UTC 24 |
Oct 15 12:27:22 PM UTC 24 |
71366447 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.650464579 |
|
|
Oct 15 12:27:07 PM UTC 24 |
Oct 15 12:27:10 PM UTC 24 |
65955612 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2331663188 |
|
|
Oct 15 12:27:08 PM UTC 24 |
Oct 15 12:27:11 PM UTC 24 |
63657827 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.51645704 |
|
|
Oct 15 12:27:04 PM UTC 24 |
Oct 15 12:27:11 PM UTC 24 |
1463602668 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.319710187 |
|
|
Oct 15 12:27:10 PM UTC 24 |
Oct 15 12:27:12 PM UTC 24 |
63989882 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.950474885 |
|
|
Oct 15 12:27:10 PM UTC 24 |
Oct 15 12:27:12 PM UTC 24 |
16879230 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2537128605 |
|
|
Oct 15 12:27:11 PM UTC 24 |
Oct 15 12:27:13 PM UTC 24 |
24407686 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3719417216 |
|
|
Oct 15 12:27:11 PM UTC 24 |
Oct 15 12:27:13 PM UTC 24 |
31928257 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.852166784 |
|
|
Oct 15 12:27:10 PM UTC 24 |
Oct 15 12:27:14 PM UTC 24 |
226231290 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.2368357038 |
|
|
Oct 15 12:27:10 PM UTC 24 |
Oct 15 12:27:14 PM UTC 24 |
147973660 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.3059171232 |
|
|
Oct 15 12:27:12 PM UTC 24 |
Oct 15 12:27:14 PM UTC 24 |
50143581 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.115049356 |
|
|
Oct 15 12:27:12 PM UTC 24 |
Oct 15 12:27:15 PM UTC 24 |
784820018 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.4127278485 |
|
|
Oct 15 12:27:13 PM UTC 24 |
Oct 15 12:27:15 PM UTC 24 |
19959131 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2958928124 |
|
|
Oct 15 12:27:14 PM UTC 24 |
Oct 15 12:27:17 PM UTC 24 |
23210888 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1921847824 |
|
|
Oct 15 12:27:14 PM UTC 24 |
Oct 15 12:27:17 PM UTC 24 |
40105994 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.2328340522 |
|
|
Oct 15 12:27:12 PM UTC 24 |
Oct 15 12:27:17 PM UTC 24 |
134361865 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.2320572975 |
|
|
Oct 15 12:27:16 PM UTC 24 |
Oct 15 12:27:18 PM UTC 24 |
47671513 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.1733053720 |
|
|
Oct 15 12:27:16 PM UTC 24 |
Oct 15 12:27:18 PM UTC 24 |
68791250 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.145465505 |
|
|
Oct 15 12:27:15 PM UTC 24 |
Oct 15 12:27:18 PM UTC 24 |
194304578 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1589855426 |
|
|
Oct 15 12:27:17 PM UTC 24 |
Oct 15 12:27:19 PM UTC 24 |
200748512 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.300290402 |
|
|
Oct 15 12:27:16 PM UTC 24 |
Oct 15 12:27:20 PM UTC 24 |
553085564 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.4042219586 |
|
|
Oct 15 12:27:18 PM UTC 24 |
Oct 15 12:27:20 PM UTC 24 |
20486202 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.1462789185 |
|
|
Oct 15 12:27:18 PM UTC 24 |
Oct 15 12:27:21 PM UTC 24 |
48421809 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1664204168 |
|
|
Oct 15 12:27:18 PM UTC 24 |
Oct 15 12:27:21 PM UTC 24 |
26796203 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2736234168 |
|
|
Oct 15 12:27:20 PM UTC 24 |
Oct 15 12:27:22 PM UTC 24 |
21513198 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_10_14/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1810523338 |
|
|
Oct 15 12:27:20 PM UTC 24 |
Oct 15 12:27:22 PM UTC 24 |
30174425 ps |