| T1570 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_rx.739154859 |
|
|
Feb 08 01:32:35 PM UTC 25 |
Feb 08 01:32:53 PM UTC 25 |
581112626 ps |
| T1571 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.4244346786 |
|
|
Feb 08 01:32:46 PM UTC 25 |
Feb 08 01:33:03 PM UTC 25 |
1051408089 ps |
| T1572 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.2506828767 |
|
|
Feb 08 01:32:51 PM UTC 25 |
Feb 08 01:33:08 PM UTC 25 |
780777059 ps |
| T1573 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/6.i2c_target_stress_wr.3220195541 |
|
|
Feb 08 12:59:44 PM UTC 25 |
Feb 08 01:33:08 PM UTC 25 |
59458857969 ps |
| T1574 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_intr_smoke.1771355854 |
|
|
Feb 08 01:32:54 PM UTC 25 |
Feb 08 01:33:08 PM UTC 25 |
2037174857 ps |
| T1575 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_perf.1097520322 |
|
|
Feb 08 01:33:12 PM UTC 25 |
Feb 08 01:33:20 PM UTC 25 |
2743992697 ps |
| T1576 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_acq.3372768578 |
|
|
Feb 08 01:33:09 PM UTC 25 |
Feb 08 01:33:12 PM UTC 25 |
194779852 ps |
| T1577 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_tx.1311878056 |
|
|
Feb 08 01:33:10 PM UTC 25 |
Feb 08 01:33:12 PM UTC 25 |
233990919 ps |
| T1578 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.2829401999 |
|
|
Feb 08 01:31:35 PM UTC 25 |
Feb 08 01:33:14 PM UTC 25 |
2660602836 ps |
| T1579 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.2349288212 |
|
|
Feb 08 01:33:03 PM UTC 25 |
Feb 08 01:33:16 PM UTC 25 |
6090178521 ps |
| T1580 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/40.i2c_target_stress_wr.3118833350 |
|
|
Feb 08 01:28:09 PM UTC 25 |
Feb 08 01:33:18 PM UTC 25 |
41691077657 ps |
| T1581 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.69492636 |
|
|
Feb 08 01:33:20 PM UTC 25 |
Feb 08 01:33:23 PM UTC 25 |
238943182 ps |
| T1582 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.3033069605 |
|
|
Feb 08 01:33:21 PM UTC 25 |
Feb 08 01:33:24 PM UTC 25 |
237060516 ps |
| T1583 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.3439348131 |
|
|
Feb 08 01:33:13 PM UTC 25 |
Feb 08 01:33:25 PM UTC 25 |
2208823716 ps |
| T1584 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_perf_precise.241859183 |
|
|
Feb 08 01:32:38 PM UTC 25 |
Feb 08 01:33:26 PM UTC 25 |
899385158 ps |
| T1585 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_perf_precise.125703144 |
|
|
Feb 08 01:29:28 PM UTC 25 |
Feb 08 01:33:27 PM UTC 25 |
5890727122 ps |
| T1586 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.1725892360 |
|
|
Feb 08 01:32:16 PM UTC 25 |
Feb 08 01:33:29 PM UTC 25 |
49683226912 ps |
| T1587 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.3274316932 |
|
|
Feb 08 01:33:24 PM UTC 25 |
Feb 08 01:33:29 PM UTC 25 |
110517060 ps |
| T1588 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.1989552730 |
|
|
Feb 08 01:33:25 PM UTC 25 |
Feb 08 01:33:29 PM UTC 25 |
686371357 ps |
| T1589 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_perf.2004658693 |
|
|
Feb 08 01:31:39 PM UTC 25 |
Feb 08 01:33:31 PM UTC 25 |
2555215198 ps |
| T1590 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_alert_test.2255472443 |
|
|
Feb 08 01:35:30 PM UTC 25 |
Feb 08 01:35:32 PM UTC 25 |
16462803 ps |
| T1591 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.963076847 |
|
|
Feb 08 01:33:25 PM UTC 25 |
Feb 08 01:33:31 PM UTC 25 |
2437935959 ps |
| T1592 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_alert_test.1398047231 |
|
|
Feb 08 01:33:30 PM UTC 25 |
Feb 08 01:33:32 PM UTC 25 |
42437662 ps |
| T1593 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.2780230746 |
|
|
Feb 08 01:33:27 PM UTC 25 |
Feb 08 01:33:32 PM UTC 25 |
540502045 ps |
| T259 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_override.216759540 |
|
|
Feb 08 01:33:30 PM UTC 25 |
Feb 08 01:33:32 PM UTC 25 |
29484716 ps |
| T1594 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.1703035354 |
|
|
Feb 08 01:33:32 PM UTC 25 |
Feb 08 01:33:34 PM UTC 25 |
292901690 ps |
| T1595 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.2304921725 |
|
|
Feb 08 01:33:33 PM UTC 25 |
Feb 08 01:33:40 PM UTC 25 |
151307777 ps |
| T248 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.3080572316 |
|
|
Feb 08 01:33:19 PM UTC 25 |
Feb 08 01:33:41 PM UTC 25 |
737546207 ps |
| T1596 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.3375401050 |
|
|
Feb 08 01:32:32 PM UTC 25 |
Feb 08 01:33:43 PM UTC 25 |
5442515706 ps |
| T1597 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.4131399008 |
|
|
Feb 08 01:33:33 PM UTC 25 |
Feb 08 01:33:43 PM UTC 25 |
1564282109 ps |
| T1598 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.1465746535 |
|
|
Feb 08 01:33:38 PM UTC 25 |
Feb 08 01:33:43 PM UTC 25 |
428791299 ps |
| T1599 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_stretch.291313719 |
|
|
Feb 08 01:32:54 PM UTC 25 |
Feb 08 01:33:46 PM UTC 25 |
3267159272 ps |
| T1600 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.3634131293 |
|
|
Feb 08 01:33:42 PM UTC 25 |
Feb 08 01:33:48 PM UTC 25 |
345225355 ps |
| T1601 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.2774453216 |
|
|
Feb 08 01:33:40 PM UTC 25 |
Feb 08 01:33:58 PM UTC 25 |
2604768854 ps |
| T1602 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.3395157238 |
|
|
Feb 08 01:31:38 PM UTC 25 |
Feb 08 01:34:01 PM UTC 25 |
4080309909 ps |
| T1603 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.3375251189 |
|
|
Feb 08 01:32:35 PM UTC 25 |
Feb 08 01:34:03 PM UTC 25 |
2419834678 ps |
| T1604 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.1017271392 |
|
|
Feb 08 01:32:34 PM UTC 25 |
Feb 08 01:34:05 PM UTC 25 |
3915176007 ps |
| T1605 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.3386634961 |
|
|
Feb 08 01:33:59 PM UTC 25 |
Feb 08 01:34:09 PM UTC 25 |
1040623490 ps |
| T1606 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.3703849785 |
|
|
Feb 08 01:34:10 PM UTC 25 |
Feb 08 01:34:14 PM UTC 25 |
651943710 ps |
| T1607 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.1643540521 |
|
|
Feb 08 01:34:11 PM UTC 25 |
Feb 08 01:34:14 PM UTC 25 |
311385450 ps |
| T1608 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.1112239699 |
|
|
Feb 08 01:34:04 PM UTC 25 |
Feb 08 01:34:18 PM UTC 25 |
6018031272 ps |
| T1609 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_perf.1188460079 |
|
|
Feb 08 01:34:11 PM UTC 25 |
Feb 08 01:34:21 PM UTC 25 |
2968259258 ps |
| T1610 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.4269172957 |
|
|
Feb 08 01:34:02 PM UTC 25 |
Feb 08 01:34:21 PM UTC 25 |
9231069633 ps |
| T1611 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.1498617393 |
|
|
Feb 08 01:34:14 PM UTC 25 |
Feb 08 01:34:22 PM UTC 25 |
796069975 ps |
| T1612 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_mode_toggle.1365560613 |
|
|
Feb 08 01:34:21 PM UTC 25 |
Feb 08 01:34:24 PM UTC 25 |
360575578 ps |
| T1613 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.440639042 |
|
|
Feb 08 01:34:23 PM UTC 25 |
Feb 08 01:34:27 PM UTC 25 |
410260017 ps |
| T1614 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.3115594865 |
|
|
Feb 08 01:33:43 PM UTC 25 |
Feb 08 01:34:27 PM UTC 25 |
1156015650 ps |
| T1615 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.1109257487 |
|
|
Feb 08 01:31:33 PM UTC 25 |
Feb 08 01:34:29 PM UTC 25 |
10544350506 ps |
| T1616 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.2232823635 |
|
|
Feb 08 01:34:26 PM UTC 25 |
Feb 08 01:34:29 PM UTC 25 |
562381599 ps |
| T1617 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.1178366836 |
|
|
Feb 08 01:32:33 PM UTC 25 |
Feb 08 01:34:30 PM UTC 25 |
14824130103 ps |
| T25 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/26.i2c_host_stress_all.661546476 |
|
|
Feb 08 01:17:47 PM UTC 25 |
Feb 08 01:34:32 PM UTC 25 |
51862623366 ps |
| T1618 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.3381340895 |
|
|
Feb 08 01:34:28 PM UTC 25 |
Feb 08 01:34:32 PM UTC 25 |
64644357 ps |
| T1619 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.2472686183 |
|
|
Feb 08 01:34:28 PM UTC 25 |
Feb 08 01:34:32 PM UTC 25 |
1662520800 ps |
| T1620 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_override.4001370721 |
|
|
Feb 08 01:35:31 PM UTC 25 |
Feb 08 01:35:33 PM UTC 25 |
52964536 ps |
| T1621 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.1053978928 |
|
|
Feb 08 01:33:30 PM UTC 25 |
Feb 08 01:34:33 PM UTC 25 |
1301971661 ps |
| T1622 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_alert_test.400665577 |
|
|
Feb 08 01:34:31 PM UTC 25 |
Feb 08 01:34:34 PM UTC 25 |
50272627 ps |
| T1623 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.2137353303 |
|
|
Feb 08 01:34:29 PM UTC 25 |
Feb 08 01:34:34 PM UTC 25 |
2799362014 ps |
| T1624 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.257126913 |
|
|
Feb 08 01:34:29 PM UTC 25 |
Feb 08 01:34:34 PM UTC 25 |
1696471164 ps |
| T1625 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.3130404308 |
|
|
Feb 08 01:33:48 PM UTC 25 |
Feb 08 01:34:35 PM UTC 25 |
4361788144 ps |
| T1626 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_perf.2477389173 |
|
|
Feb 08 01:33:35 PM UTC 25 |
Feb 08 01:34:36 PM UTC 25 |
4999622109 ps |
| T1627 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_override.3289368137 |
|
|
Feb 08 01:34:33 PM UTC 25 |
Feb 08 01:34:36 PM UTC 25 |
30691730 ps |
| T1628 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.4082127712 |
|
|
Feb 08 01:34:34 PM UTC 25 |
Feb 08 01:34:38 PM UTC 25 |
721250896 ps |
| T1629 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.3930697581 |
|
|
Feb 08 01:34:36 PM UTC 25 |
Feb 08 01:34:42 PM UTC 25 |
595214253 ps |
| T1630 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.2676658587 |
|
|
Feb 08 01:34:22 PM UTC 25 |
Feb 08 01:34:44 PM UTC 25 |
457395472 ps |
| T1631 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.2850763548 |
|
|
Feb 08 01:34:39 PM UTC 25 |
Feb 08 01:34:47 PM UTC 25 |
373580716 ps |
| T1632 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.164849803 |
|
|
Feb 08 01:34:48 PM UTC 25 |
Feb 08 01:34:57 PM UTC 25 |
10054151196 ps |
| T1633 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.2765656305 |
|
|
Feb 08 01:34:45 PM UTC 25 |
Feb 08 01:34:58 PM UTC 25 |
669143745 ps |
| T1634 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_perf.3422578516 |
|
|
Feb 08 01:34:37 PM UTC 25 |
Feb 08 01:35:03 PM UTC 25 |
3508769428 ps |
| T1635 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.949752254 |
|
|
Feb 08 01:34:35 PM UTC 25 |
Feb 08 01:35:04 PM UTC 25 |
450031513 ps |
| T1636 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.216716068 |
|
|
Feb 08 01:34:37 PM UTC 25 |
Feb 08 01:35:06 PM UTC 25 |
6174906931 ps |
| T1637 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.548885062 |
|
|
Feb 08 01:35:04 PM UTC 25 |
Feb 08 01:35:10 PM UTC 25 |
8207400303 ps |
| T1638 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.685788341 |
|
|
Feb 08 01:34:37 PM UTC 25 |
Feb 08 01:35:11 PM UTC 25 |
2563481788 ps |
| T1639 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.1954129216 |
|
|
Feb 08 01:35:04 PM UTC 25 |
Feb 08 01:35:11 PM UTC 25 |
5254131972 ps |
| T1640 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.2673592610 |
|
|
Feb 08 01:35:11 PM UTC 25 |
Feb 08 01:35:14 PM UTC 25 |
246896817 ps |
| T1641 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.3391840309 |
|
|
Feb 08 01:35:12 PM UTC 25 |
Feb 08 01:35:14 PM UTC 25 |
224551253 ps |
| T1642 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_perf.4166413575 |
|
|
Feb 08 01:35:12 PM UTC 25 |
Feb 08 01:35:17 PM UTC 25 |
823109845 ps |
| T1643 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.2894140438 |
|
|
Feb 08 01:35:05 PM UTC 25 |
Feb 08 01:35:17 PM UTC 25 |
13535758688 ps |
| T1644 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_hrst.2382348342 |
|
|
Feb 08 01:35:15 PM UTC 25 |
Feb 08 01:35:19 PM UTC 25 |
933430581 ps |
| T1645 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.4218148588 |
|
|
Feb 08 01:35:14 PM UTC 25 |
Feb 08 01:35:23 PM UTC 25 |
3586947459 ps |
| T1646 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.2478397189 |
|
|
Feb 08 01:34:58 PM UTC 25 |
Feb 08 01:35:24 PM UTC 25 |
2678005294 ps |
| T1647 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.3404739367 |
|
|
Feb 08 01:35:21 PM UTC 25 |
Feb 08 01:35:24 PM UTC 25 |
482859000 ps |
| T1648 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.3888784293 |
|
|
Feb 08 01:30:29 PM UTC 25 |
Feb 08 01:35:24 PM UTC 25 |
6941563199 ps |
| T1649 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.1171901330 |
|
|
Feb 08 01:35:20 PM UTC 25 |
Feb 08 01:35:25 PM UTC 25 |
472707309 ps |
| T1650 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.3207247388 |
|
|
Feb 08 01:35:26 PM UTC 25 |
Feb 08 01:35:29 PM UTC 25 |
505190285 ps |
| T1651 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.298692299 |
|
|
Feb 08 01:35:24 PM UTC 25 |
Feb 08 01:35:30 PM UTC 25 |
1744853463 ps |
| T1652 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.3859600441 |
|
|
Feb 08 01:35:26 PM UTC 25 |
Feb 08 01:35:30 PM UTC 25 |
7197557208 ps |
| T1653 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.1692873098 |
|
|
Feb 08 01:35:26 PM UTC 25 |
Feb 08 01:35:31 PM UTC 25 |
1056433913 ps |
| T1654 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.1402167283 |
|
|
Feb 08 01:35:23 PM UTC 25 |
Feb 08 01:35:34 PM UTC 25 |
530015143 ps |
| T1655 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.3003814452 |
|
|
Feb 08 01:35:34 PM UTC 25 |
Feb 08 01:35:37 PM UTC 25 |
501136183 ps |
| T1656 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.4229225102 |
|
|
Feb 08 01:35:18 PM UTC 25 |
Feb 08 01:35:40 PM UTC 25 |
462407549 ps |
| T1657 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.1994804710 |
|
|
Feb 08 01:33:33 PM UTC 25 |
Feb 08 01:35:43 PM UTC 25 |
8258176782 ps |
| T1658 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.2539885309 |
|
|
Feb 08 01:35:35 PM UTC 25 |
Feb 08 01:35:45 PM UTC 25 |
479198842 ps |
| T1659 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.266496065 |
|
|
Feb 08 01:35:46 PM UTC 25 |
Feb 08 01:35:49 PM UTC 25 |
107484827 ps |
| T1660 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.4270077921 |
|
|
Feb 08 01:34:58 PM UTC 25 |
Feb 08 01:35:51 PM UTC 25 |
5677960350 ps |
| T1661 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.255233061 |
|
|
Feb 08 01:35:37 PM UTC 25 |
Feb 08 01:35:52 PM UTC 25 |
471253529 ps |
| T1662 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.3078241237 |
|
|
Feb 08 01:35:51 PM UTC 25 |
Feb 08 01:35:55 PM UTC 25 |
87945471 ps |
| T1663 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.2851580272 |
|
|
Feb 08 01:35:31 PM UTC 25 |
Feb 08 01:35:59 PM UTC 25 |
1757027917 ps |
| T1664 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.3960134425 |
|
|
Feb 08 01:35:49 PM UTC 25 |
Feb 08 01:36:02 PM UTC 25 |
2502191724 ps |
| T1665 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.2845574223 |
|
|
Feb 08 01:35:56 PM UTC 25 |
Feb 08 01:36:11 PM UTC 25 |
1045821152 ps |
| T1666 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_host_perf.592531930 |
|
|
Feb 08 01:15:10 PM UTC 25 |
Feb 08 01:36:13 PM UTC 25 |
26607924503 ps |
| T1667 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.1136465081 |
|
|
Feb 08 01:36:12 PM UTC 25 |
Feb 08 01:36:23 PM UTC 25 |
1142357872 ps |
| T1668 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.1858123491 |
|
|
Feb 08 01:34:33 PM UTC 25 |
Feb 08 01:36:23 PM UTC 25 |
4398893478 ps |
| T1669 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.346186053 |
|
|
Feb 08 01:36:07 PM UTC 25 |
Feb 08 01:36:24 PM UTC 25 |
1914474427 ps |
| T129 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/37.i2c_host_stress_all.1124600307 |
|
|
Feb 08 01:25:47 PM UTC 25 |
Feb 08 01:36:26 PM UTC 25 |
71680312164 ps |
| T1670 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.3731426228 |
|
|
Feb 08 01:36:03 PM UTC 25 |
Feb 08 01:36:26 PM UTC 25 |
3686612311 ps |
| T1671 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.3188639974 |
|
|
Feb 08 01:33:13 PM UTC 25 |
Feb 08 01:36:27 PM UTC 25 |
16422675639 ps |
| T1672 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.555273634 |
|
|
Feb 08 01:36:25 PM UTC 25 |
Feb 08 01:36:28 PM UTC 25 |
101583194 ps |
| T1673 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_host_stress_all.764194383 |
|
|
Feb 08 01:24:05 PM UTC 25 |
Feb 08 01:39:57 PM UTC 25 |
43703699486 ps |
| T1674 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.1196120423 |
|
|
Feb 08 01:36:27 PM UTC 25 |
Feb 08 01:36:30 PM UTC 25 |
180401945 ps |
| T77 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_mode_toggle.4127400646 |
|
|
Feb 08 01:36:31 PM UTC 25 |
Feb 08 01:36:35 PM UTC 25 |
108636488 ps |
| T1675 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.664892759 |
|
|
Feb 08 01:36:23 PM UTC 25 |
Feb 08 01:36:36 PM UTC 25 |
3451694286 ps |
| T1676 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_perf.2364441872 |
|
|
Feb 08 01:36:27 PM UTC 25 |
Feb 08 01:36:37 PM UTC 25 |
2466531766 ps |
| T1677 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.1868050992 |
|
|
Feb 08 01:36:28 PM UTC 25 |
Feb 08 01:36:37 PM UTC 25 |
3623869215 ps |
| T1678 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.3191512362 |
|
|
Feb 08 01:33:32 PM UTC 25 |
Feb 08 01:36:38 PM UTC 25 |
2496404349 ps |
| T1679 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.2139861927 |
|
|
Feb 08 01:35:33 PM UTC 25 |
Feb 08 01:36:39 PM UTC 25 |
11537235162 ps |
| T1680 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.1937853568 |
|
|
Feb 08 01:36:31 PM UTC 25 |
Feb 08 01:36:40 PM UTC 25 |
1057364894 ps |
| T1681 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.1629909803 |
|
|
Feb 08 01:36:37 PM UTC 25 |
Feb 08 01:36:40 PM UTC 25 |
169154658 ps |
| T1682 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.362278499 |
|
|
Feb 08 01:36:36 PM UTC 25 |
Feb 08 01:36:41 PM UTC 25 |
2930721151 ps |
| T1683 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.3865042988 |
|
|
Feb 08 01:36:38 PM UTC 25 |
Feb 08 01:36:43 PM UTC 25 |
506053298 ps |
| T1684 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_alert_test.1270098676 |
|
|
Feb 08 01:36:41 PM UTC 25 |
Feb 08 01:36:43 PM UTC 25 |
17156746 ps |
| T1685 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.1461912056 |
|
|
Feb 08 01:36:38 PM UTC 25 |
Feb 08 01:36:44 PM UTC 25 |
239176749 ps |
| T1686 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.1550385252 |
|
|
Feb 08 01:36:39 PM UTC 25 |
Feb 08 01:36:44 PM UTC 25 |
2794703034 ps |
| T1687 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_nack_txstretch.2089212436 |
|
|
Feb 08 01:36:41 PM UTC 25 |
Feb 08 01:36:45 PM UTC 25 |
614990853 ps |
| T1688 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_override.489541093 |
|
|
Feb 08 01:36:43 PM UTC 25 |
Feb 08 01:36:45 PM UTC 25 |
33670373 ps |
| T1689 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.1121194476 |
|
|
Feb 08 01:36:40 PM UTC 25 |
Feb 08 01:36:45 PM UTC 25 |
7161375116 ps |
| T1690 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.2620186040 |
|
|
Feb 08 01:36:45 PM UTC 25 |
Feb 08 01:36:47 PM UTC 25 |
372130031 ps |
| T1691 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.3076438548 |
|
|
Feb 08 01:36:46 PM UTC 25 |
Feb 08 01:36:52 PM UTC 25 |
134092079 ps |
| T1692 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.1039616729 |
|
|
Feb 08 01:33:32 PM UTC 25 |
Feb 08 01:36:55 PM UTC 25 |
3527583062 ps |
| T1693 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.4179180817 |
|
|
Feb 08 01:36:53 PM UTC 25 |
Feb 08 01:37:02 PM UTC 25 |
606503170 ps |
| T1694 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.2312625393 |
|
|
Feb 08 01:36:49 PM UTC 25 |
Feb 08 01:37:12 PM UTC 25 |
3885368804 ps |
| T1695 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.1030119700 |
|
|
Feb 08 01:36:46 PM UTC 25 |
Feb 08 01:37:16 PM UTC 25 |
469991351 ps |
| T1696 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.2917345994 |
|
|
Feb 08 01:34:36 PM UTC 25 |
Feb 08 01:37:20 PM UTC 25 |
3921463297 ps |
| T1697 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.1563329413 |
|
|
Feb 08 01:37:03 PM UTC 25 |
Feb 08 01:37:23 PM UTC 25 |
5012170167 ps |
| T1698 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.3683954534 |
|
|
Feb 08 01:37:14 PM UTC 25 |
Feb 08 01:37:23 PM UTC 25 |
10041410759 ps |
| T1699 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.1407739691 |
|
|
Feb 08 01:37:17 PM UTC 25 |
Feb 08 01:37:24 PM UTC 25 |
351750642 ps |
| T1700 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.521007035 |
|
|
Feb 08 01:37:24 PM UTC 25 |
Feb 08 01:37:28 PM UTC 25 |
509329507 ps |
| T1701 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.3936087014 |
|
|
Feb 08 01:37:29 PM UTC 25 |
Feb 08 01:37:32 PM UTC 25 |
439585704 ps |
| T233 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.998163623 |
|
|
Feb 08 01:37:29 PM UTC 25 |
Feb 08 01:37:32 PM UTC 25 |
399894626 ps |
| T1702 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.1036724426 |
|
|
Feb 08 01:37:21 PM UTC 25 |
Feb 08 01:37:33 PM UTC 25 |
2442633914 ps |
| T1703 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.3750990141 |
|
|
Feb 08 01:37:24 PM UTC 25 |
Feb 08 01:37:35 PM UTC 25 |
1198088451 ps |
| T1704 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_perf.2104655902 |
|
|
Feb 08 01:36:46 PM UTC 25 |
Feb 08 01:37:40 PM UTC 25 |
5013207929 ps |
| T1705 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.2654357493 |
|
|
Feb 08 01:36:42 PM UTC 25 |
Feb 08 01:37:41 PM UTC 25 |
4242419459 ps |
| T1706 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.425448392 |
|
|
Feb 08 01:37:33 PM UTC 25 |
Feb 08 01:37:42 PM UTC 25 |
3216543123 ps |
| T1707 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_perf.54045869 |
|
|
Feb 08 01:37:32 PM UTC 25 |
Feb 08 01:37:43 PM UTC 25 |
1357448821 ps |
| T1708 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.1806594704 |
|
|
Feb 08 01:37:44 PM UTC 25 |
Feb 08 01:37:47 PM UTC 25 |
122490246 ps |
| T1709 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.3915411260 |
|
|
Feb 08 01:37:44 PM UTC 25 |
Feb 08 01:37:49 PM UTC 25 |
835704835 ps |
| T1710 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.1151157803 |
|
|
Feb 08 01:37:46 PM UTC 25 |
Feb 08 01:37:50 PM UTC 25 |
99264421 ps |
| T1711 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.40229609 |
|
|
Feb 08 01:34:34 PM UTC 25 |
Feb 08 01:37:51 PM UTC 25 |
9018537988 ps |
| T1712 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.2039053396 |
|
|
Feb 08 01:37:48 PM UTC 25 |
Feb 08 01:37:52 PM UTC 25 |
874318470 ps |
| T1713 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.368868732 |
|
|
Feb 08 01:37:52 PM UTC 25 |
Feb 08 01:37:55 PM UTC 25 |
260718140 ps |
| T1714 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_alert_test.1964588920 |
|
|
Feb 08 01:37:53 PM UTC 25 |
Feb 08 01:37:55 PM UTC 25 |
27238085 ps |
| T1715 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.1448501492 |
|
|
Feb 08 01:37:50 PM UTC 25 |
Feb 08 01:37:56 PM UTC 25 |
2003265976 ps |
| T1716 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.3627724747 |
|
|
Feb 08 01:37:51 PM UTC 25 |
Feb 08 01:37:56 PM UTC 25 |
939141975 ps |
| T1717 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/2.i2c_target_stress_wr.2228712984 |
|
|
Feb 08 12:57:02 PM UTC 25 |
Feb 08 01:37:56 PM UTC 25 |
67216082207 ps |
| T1718 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/30.i2c_host_perf.3040481630 |
|
|
Feb 08 01:20:40 PM UTC 25 |
Feb 08 01:37:57 PM UTC 25 |
48136324208 ps |
| T1719 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.681202178 |
|
|
Feb 08 01:37:42 PM UTC 25 |
Feb 08 01:38:02 PM UTC 25 |
526632332 ps |
| T1720 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.3227495281 |
|
|
Feb 08 01:33:45 PM UTC 25 |
Feb 08 01:38:15 PM UTC 25 |
42461751056 ps |
| T1721 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.2006646423 |
|
|
Feb 08 01:37:20 PM UTC 25 |
Feb 08 01:38:16 PM UTC 25 |
4582998417 ps |
| T1722 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_host_perf.3594040656 |
|
|
Feb 08 01:32:37 PM UTC 25 |
Feb 08 01:38:18 PM UTC 25 |
29635804845 ps |
| T278 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/13.i2c_host_stress_all.64761457 |
|
|
Feb 08 01:05:59 PM UTC 25 |
Feb 08 01:38:58 PM UTC 25 |
79222849205 ps |
| T1723 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.589043789 |
|
|
Feb 08 01:35:32 PM UTC 25 |
Feb 08 01:39:20 PM UTC 25 |
9719435270 ps |
| T1724 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.3540851835 |
|
|
Feb 08 01:36:00 PM UTC 25 |
Feb 08 01:39:27 PM UTC 25 |
47791832718 ps |
| T1725 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.3340593935 |
|
|
Feb 08 01:34:33 PM UTC 25 |
Feb 08 01:39:28 PM UTC 25 |
4296153754 ps |
| T1726 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.1693300962 |
|
|
Feb 08 01:35:40 PM UTC 25 |
Feb 08 01:39:32 PM UTC 25 |
47388529409 ps |
| T1727 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.3039735515 |
|
|
Feb 08 01:36:45 PM UTC 25 |
Feb 08 01:39:53 PM UTC 25 |
6035083701 ps |
| T1728 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.2399227915 |
|
|
Feb 08 01:36:46 PM UTC 25 |
Feb 08 01:39:54 PM UTC 25 |
39474838706 ps |
| T1729 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.1586608712 |
|
|
Feb 08 01:36:14 PM UTC 25 |
Feb 08 01:40:04 PM UTC 25 |
12412416845 ps |
| T1730 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.3129037963 |
|
|
Feb 08 01:32:56 PM UTC 25 |
Feb 08 01:40:24 PM UTC 25 |
20041346007 ps |
| T1731 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.274166838 |
|
|
Feb 08 01:29:37 PM UTC 25 |
Feb 08 01:40:37 PM UTC 25 |
55132547547 ps |
| T1732 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.3022883037 |
|
|
Feb 08 01:36:48 PM UTC 25 |
Feb 08 01:40:53 PM UTC 25 |
23275278417 ps |
| T1733 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_target_stress_all.1878198439 |
|
|
Feb 08 01:29:09 PM UTC 25 |
Feb 08 01:41:10 PM UTC 25 |
85752089722 ps |
| T1734 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.253550879 |
|
|
Feb 08 01:31:51 PM UTC 25 |
Feb 08 01:41:40 PM UTC 25 |
38900006651 ps |
| T1735 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.3395764292 |
|
|
Feb 08 01:32:02 PM UTC 25 |
Feb 08 01:41:42 PM UTC 25 |
22809677283 ps |
| T1736 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/42.i2c_host_perf.2512539661 |
|
|
Feb 08 01:29:27 PM UTC 25 |
Feb 08 01:41:46 PM UTC 25 |
27466634150 ps |
| T1737 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.2675454489 |
|
|
Feb 08 01:32:50 PM UTC 25 |
Feb 08 01:42:19 PM UTC 25 |
38538151630 ps |
| T1738 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.3709982549 |
|
|
Feb 08 01:36:44 PM UTC 25 |
Feb 08 01:42:19 PM UTC 25 |
4966991733 ps |
| T1739 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/27.i2c_target_stress_wr.157555332 |
|
|
Feb 08 01:18:32 PM UTC 25 |
Feb 08 01:42:23 PM UTC 25 |
54256571033 ps |
| T1740 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.3891452164 |
|
|
Feb 08 01:34:14 PM UTC 25 |
Feb 08 01:42:51 PM UTC 25 |
67472537687 ps |
| T1741 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.1579040874 |
|
|
Feb 08 01:37:33 PM UTC 25 |
Feb 08 01:43:07 PM UTC 25 |
20434360037 ps |
| T276 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_host_stress_all.3895909089 |
|
|
Feb 08 01:07:41 PM UTC 25 |
Feb 08 01:43:34 PM UTC 25 |
71053108114 ps |
| T1742 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_host_stress_all.2624965260 |
|
|
Feb 08 01:34:43 PM UTC 25 |
Feb 08 01:43:56 PM UTC 25 |
90985063006 ps |
| T1743 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/41.i2c_host_perf.906272036 |
|
|
Feb 08 01:28:38 PM UTC 25 |
Feb 08 01:45:07 PM UTC 25 |
12557235669 ps |
| T1744 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.600065813 |
|
|
Feb 08 01:36:27 PM UTC 25 |
Feb 08 01:45:23 PM UTC 25 |
48532082869 ps |
| T1745 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/31.i2c_target_stress_all.692577397 |
|
|
Feb 08 01:21:32 PM UTC 25 |
Feb 08 01:45:34 PM UTC 25 |
57394632294 ps |
| T1746 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.2761184762 |
|
|
Feb 08 01:35:12 PM UTC 25 |
Feb 08 01:46:18 PM UTC 25 |
24430601083 ps |
| T1747 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/48.i2c_host_perf.576873587 |
|
|
Feb 08 01:35:44 PM UTC 25 |
Feb 08 01:49:31 PM UTC 25 |
18898759616 ps |
| T1748 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/15.i2c_target_stress_wr.2779323958 |
|
|
Feb 08 01:07:45 PM UTC 25 |
Feb 08 01:50:06 PM UTC 25 |
68083949317 ps |
| T1749 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/4.i2c_host_perf.1077115698 |
|
|
Feb 08 12:58:04 PM UTC 25 |
Feb 08 01:55:28 PM UTC 25 |
27678469518 ps |
| T1750 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/24.i2c_target_stress_wr.1180981644 |
|
|
Feb 08 01:15:20 PM UTC 25 |
Feb 08 01:57:02 PM UTC 25 |
68958327788 ps |
| T1751 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/35.i2c_target_stress_all.971983491 |
|
|
Feb 08 01:24:41 PM UTC 25 |
Feb 08 02:00:03 PM UTC 25 |
73323292359 ps |
| T282 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/default/28.i2c_host_stress_all.809358623 |
|
|
Feb 08 01:19:08 PM UTC 25 |
Feb 08 02:01:36 PM UTC 25 |
47638623011 ps |
| T279 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.1791630500 |
|
|
Feb 08 01:37:56 PM UTC 25 |
Feb 08 01:37:58 PM UTC 25 |
41418691 ps |
| T100 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.2464725913 |
|
|
Feb 08 01:37:56 PM UTC 25 |
Feb 08 01:37:59 PM UTC 25 |
80225431 ps |
| T101 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.4291217311 |
|
|
Feb 08 01:37:57 PM UTC 25 |
Feb 08 01:37:59 PM UTC 25 |
73470575 ps |
| T203 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.3214360734 |
|
|
Feb 08 01:37:57 PM UTC 25 |
Feb 08 01:38:00 PM UTC 25 |
45862116 ps |
| T102 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.1377687929 |
|
|
Feb 08 01:37:56 PM UTC 25 |
Feb 08 01:38:00 PM UTC 25 |
98114671 ps |
| T1752 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.1116681454 |
|
|
Feb 08 01:37:59 PM UTC 25 |
Feb 08 01:38:02 PM UTC 25 |
449627087 ps |
| T222 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1098684950 |
|
|
Feb 08 01:38:00 PM UTC 25 |
Feb 08 01:38:02 PM UTC 25 |
139808259 ps |
| T184 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2136674574 |
|
|
Feb 08 01:38:00 PM UTC 25 |
Feb 08 01:38:02 PM UTC 25 |
26515739 ps |
| T130 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.3568448177 |
|
|
Feb 08 01:38:01 PM UTC 25 |
Feb 08 01:38:03 PM UTC 25 |
60333693 ps |
| T103 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.2345542079 |
|
|
Feb 08 01:38:01 PM UTC 25 |
Feb 08 01:38:03 PM UTC 25 |
84477552 ps |
| T220 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.427900593 |
|
|
Feb 08 01:37:58 PM UTC 25 |
Feb 08 01:38:03 PM UTC 25 |
66932757 ps |
| T104 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.660801319 |
|
|
Feb 08 01:38:01 PM UTC 25 |
Feb 08 01:38:05 PM UTC 25 |
140915698 ps |
| T105 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.975209232 |
|
|
Feb 08 01:38:01 PM UTC 25 |
Feb 08 01:38:05 PM UTC 25 |
146694428 ps |
| T1753 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.2061414582 |
|
|
Feb 08 01:38:03 PM UTC 25 |
Feb 08 01:38:05 PM UTC 25 |
216331626 ps |
| T128 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3063267587 |
|
|
Feb 08 01:38:03 PM UTC 25 |
Feb 08 01:38:05 PM UTC 25 |
36019383 ps |
| T106 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.3368837387 |
|
|
Feb 08 01:38:03 PM UTC 25 |
Feb 08 01:38:06 PM UTC 25 |
292763738 ps |
| T204 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3864214016 |
|
|
Feb 08 01:38:04 PM UTC 25 |
Feb 08 01:38:07 PM UTC 25 |
36704923 ps |
| T191 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.3699570113 |
|
|
Feb 08 01:38:04 PM UTC 25 |
Feb 08 01:38:08 PM UTC 25 |
121063713 ps |
| T1754 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.3096464512 |
|
|
Feb 08 01:38:06 PM UTC 25 |
Feb 08 01:38:08 PM UTC 25 |
19232218 ps |
| T214 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.4250063151 |
|
|
Feb 08 01:38:06 PM UTC 25 |
Feb 08 01:38:08 PM UTC 25 |
21323725 ps |
| T107 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.1292019157 |
|
|
Feb 08 01:38:04 PM UTC 25 |
Feb 08 01:38:08 PM UTC 25 |
77632869 ps |
| T1755 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.3497214194 |
|
|
Feb 08 01:38:07 PM UTC 25 |
Feb 08 01:38:09 PM UTC 25 |
175928485 ps |
| T1756 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.2026655193 |
|
|
Feb 08 01:38:07 PM UTC 25 |
Feb 08 01:38:09 PM UTC 25 |
102866868 ps |
| T108 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.3821285511 |
|
|
Feb 08 01:38:03 PM UTC 25 |
Feb 08 01:38:10 PM UTC 25 |
1032599659 ps |
| T223 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2570679689 |
|
|
Feb 08 01:38:08 PM UTC 25 |
Feb 08 01:38:10 PM UTC 25 |
81336447 ps |
| T1757 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.2997420746 |
|
|
Feb 08 01:38:07 PM UTC 25 |
Feb 08 01:38:11 PM UTC 25 |
473901700 ps |
| T1758 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.1222097148 |
|
|
Feb 08 01:38:09 PM UTC 25 |
Feb 08 01:38:11 PM UTC 25 |
45419160 ps |
| T211 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.945916583 |
|
|
Feb 08 01:38:09 PM UTC 25 |
Feb 08 01:38:12 PM UTC 25 |
80368741 ps |
| T1759 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.2881651321 |
|
|
Feb 08 01:38:10 PM UTC 25 |
Feb 08 01:38:12 PM UTC 25 |
33278699 ps |
| T224 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.3054926381 |
|
|
Feb 08 01:38:10 PM UTC 25 |
Feb 08 01:38:13 PM UTC 25 |
16945069 ps |
| T195 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.1554508436 |
|
|
Feb 08 01:38:09 PM UTC 25 |
Feb 08 01:38:13 PM UTC 25 |
46484317 ps |
| T109 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.1528047788 |
|
|
Feb 08 01:38:09 PM UTC 25 |
Feb 08 01:38:14 PM UTC 25 |
158030463 ps |
| T225 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2197834698 |
|
|
Feb 08 01:38:12 PM UTC 25 |
Feb 08 01:38:14 PM UTC 25 |
22373993 ps |
| T153 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.1973262666 |
|
|
Feb 08 01:38:10 PM UTC 25 |
Feb 08 01:38:15 PM UTC 25 |
476207053 ps |
| T215 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.1024192589 |
|
|
Feb 08 01:38:11 PM UTC 25 |
Feb 08 01:38:15 PM UTC 25 |
157465091 ps |
| T212 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3441719515 |
|
|
Feb 08 01:38:13 PM UTC 25 |
Feb 08 01:38:15 PM UTC 25 |
67886198 ps |
| T206 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.2413210417 |
|
|
Feb 08 01:38:13 PM UTC 25 |
Feb 08 01:38:16 PM UTC 25 |
623542015 ps |
| T283 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.540205555 |
|
|
Feb 08 01:38:14 PM UTC 25 |
Feb 08 01:38:16 PM UTC 25 |
158280675 ps |
| T1760 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.3403679551 |
|
|
Feb 08 01:38:14 PM UTC 25 |
Feb 08 01:38:16 PM UTC 25 |
56045983 ps |
| T226 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.2673680651 |
|
|
Feb 08 01:38:15 PM UTC 25 |
Feb 08 01:38:17 PM UTC 25 |
80264040 ps |
| T196 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.2432339050 |
|
|
Feb 08 01:38:14 PM UTC 25 |
Feb 08 01:38:18 PM UTC 25 |
445433786 ps |
| T1761 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.3714163935 |
|
|
Feb 08 01:38:15 PM UTC 25 |
Feb 08 01:38:18 PM UTC 25 |
65421988 ps |
| T227 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.1540774229 |
|
|
Feb 08 01:38:17 PM UTC 25 |
Feb 08 01:38:19 PM UTC 25 |
88129128 ps |
| T1762 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.2046551774 |
|
|
Feb 08 01:38:17 PM UTC 25 |
Feb 08 01:38:19 PM UTC 25 |
62440957 ps |
| T213 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2483110533 |
|
|
Feb 08 01:38:17 PM UTC 25 |
Feb 08 01:38:19 PM UTC 25 |
61121582 ps |
| T228 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3203443292 |
|
|
Feb 08 01:38:17 PM UTC 25 |
Feb 08 01:38:19 PM UTC 25 |
62567512 ps |
| T216 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.2358705169 |
|
|
Feb 08 01:38:15 PM UTC 25 |
Feb 08 01:38:20 PM UTC 25 |
268192889 ps |
| T1763 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.2818211063 |
|
|
Feb 08 01:38:17 PM UTC 25 |
Feb 08 01:38:20 PM UTC 25 |
211057550 ps |
| T194 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.373964735 |
|
|
Feb 08 01:38:17 PM UTC 25 |
Feb 08 01:38:20 PM UTC 25 |
664666428 ps |
| T229 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3827439493 |
|
|
Feb 08 01:38:18 PM UTC 25 |
Feb 08 01:38:20 PM UTC 25 |
104995665 ps |
| T1764 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1669865629 |
|
|
Feb 08 01:38:18 PM UTC 25 |
Feb 08 01:38:21 PM UTC 25 |
74283235 ps |
| T284 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.3445859458 |
|
|
Feb 08 01:38:19 PM UTC 25 |
Feb 08 01:38:21 PM UTC 25 |
15234779 ps |
| T181 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.1186346144 |
|
|
Feb 08 01:38:21 PM UTC 25 |
Feb 08 01:38:23 PM UTC 25 |
142500508 ps |
| T1765 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.3358809730 |
|
|
Feb 08 01:38:19 PM UTC 25 |
Feb 08 01:38:23 PM UTC 25 |
64702358 ps |
| T197 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.854278293 |
|
|
Feb 08 01:38:19 PM UTC 25 |
Feb 08 01:38:23 PM UTC 25 |
92445949 ps |
| T280 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.2584040875 |
|
|
Feb 08 01:38:21 PM UTC 25 |
Feb 08 01:38:23 PM UTC 25 |
27545188 ps |
| T1766 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.3004935763 |
|
|
Feb 08 01:38:21 PM UTC 25 |
Feb 08 01:38:23 PM UTC 25 |
56886630 ps |
| T1767 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2011811982 |
|
|
Feb 08 01:38:21 PM UTC 25 |
Feb 08 01:38:23 PM UTC 25 |
103296382 ps |
| T182 |
/workspaces/repo/scratch/os_regression/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.579005610 |
|
|
Feb 08 01:38:21 PM UTC 25 |
Feb 08 01:38:24 PM UTC 25 |
101757417 ps |