dd5ad5fb77
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 49.510s | 6.447ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 48.870s | 2.282ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.520s | 34.607us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.560s | 57.808us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 32.980s | 21.562ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 10.300s | 1.807ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.500s | 66.750us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.560s | 57.808us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 10.300s | 1.807ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 2.049m | 36.705ms | 50 | 50 | 100.00 |
V2 | sideload | keymgr_sideload | 56.910s | 3.167ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 38.530s | 6.586ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 53.600s | 3.002ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 48.920s | 1.889ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 22.900s | 767.958us | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 8.540s | 316.067us | 49 | 50 | 98.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 6.710s | 187.013us | 49 | 50 | 98.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 28.420s | 9.170ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 1.340m | 19.416ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 20.450s | 4.155ms | 50 | 50 | 100.00 |
V2 | stress_all | keymgr_stress_all | 15.844m | 180.641ms | 50 | 50 | 100.00 |
V2 | intr_test | keymgr_intr_test | 0.990s | 66.938us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.010s | 21.101us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 4.110s | 122.144us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 4.110s | 122.144us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.520s | 34.607us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.560s | 57.808us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.300s | 1.807ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.150s | 450.393us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.520s | 34.607us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.560s | 57.808us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.300s | 1.807ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.150s | 450.393us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 738 | 740 | 99.73 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 22.540s | 5.815ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 22.540s | 5.815ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 10.960s | 1.077ms | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 5.570s | 245.458us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 5.570s | 245.458us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 5.570s | 245.458us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 5.570s | 245.458us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 16.440s | 911.306us | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 22.540s | 5.815ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 22.540s | 5.815ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 10.960s | 1.077ms | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 5.570s | 245.458us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 2.049m | 36.705ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 48.870s | 2.282ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.560s | 57.808us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 48.870s | 2.282ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.560s | 57.808us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 48.870s | 2.282ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.560s | 57.808us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 8.540s | 316.067us | 49 | 50 | 98.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 1.340m | 19.416ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 1.340m | 19.416ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 48.870s | 2.282ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 33.140s | 5.643ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 22.540s | 5.815ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 22.540s | 5.815ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 22.540s | 5.815ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 47.210s | 7.134ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 8.540s | 316.067us | 49 | 50 | 98.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 22.540s | 5.815ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 22.540s | 5.815ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 22.540s | 5.815ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 47.210s | 7.134ms | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 47.210s | 7.134ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 22.540s | 5.815ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 47.210s | 7.134ms | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 22.540s | 5.815ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 47.210s | 7.134ms | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 25.520s | 857.381us | 30 | 50 | 60.00 |
V3 | TOTAL | 30 | 50 | 60.00 | |||
TOTAL | 1088 | 1110 | 98.02 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 14 | 87.50 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.77 | 99.04 | 98.11 | 98.62 | 100.00 | 99.02 | 98.41 | 91.19 |
UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 18 failures:
0.keymgr_stress_all_with_rand_reset.19281855111080909664170032659075310236117588029905763650597420601468410192582
Line 1020, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1443006784 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1443006784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.keymgr_stress_all_with_rand_reset.30228531195168198263541819884097347371419950165692192301554438361232227724940
Line 315, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 474951934 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 474951934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 1 failures:
15.keymgr_kmac_rsp_err.99848920519714053298528427359014447517909729775589541981038828835498617506867
Line 314, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest/run.log
UVM_ERROR @ 8644928 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 8644928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*])
has 1 failures:
34.keymgr_stress_all_with_rand_reset.24674089968515781936996908275867164128905504127607683121208533207556205346819
Line 827, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 852894927 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
UVM_INFO @ 852894927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:1064) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation
has 1 failures:
39.keymgr_stress_all_with_rand_reset.103830662658929941725046258221891589821595539533694131921047510272571264791088
Line 1627, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/39.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1298503066 ps: (keymgr_scoreboard.sv:1064) [uvm_test_top.env.scoreboard] Check failed act == exp (42175999582365568016593364350770232733952373867795406412967162414258996929016651711627336432491232576228681052990694161882067156474522364678049785271300078258074036481500754209283896542333172070228859618176868438208312161423844987143946200274748151618022458147369233460248764352651999685217491417699072859175361049766831223320095781983592214868729 [0xb08096157622996cf0988fb4000000003f22340d00000000a2a5278c3fe50c25d7f0e2c4283efc2c605f67f9e08a6fb56cc8fb9fd9939a1babb630cb878de085c4334c87f05a460d6da0b31fc0ae7c7e8bb13619eeca71d137b4769d19969f610a7e8049493cfafbf6a6145b603133ef3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9] vs 56207059855741478611788783353378622937005369621260556045667054628669754837481821517676925271827955255266690690885233809701944456091217577930106370131609834534193942342028359139574914438441846815494897719647558017849665390066429284516581124260832867372609507501948685518404526772029482003309000409440145342940436201412856211593200200037699921556217 [0xeb388a1c97b6677800000000b4f417e73a54905f000000000b2ee0de00000000d7f0e2c4283efc2c605f67f9e08a6fb56cc8fb9fd9939a1babb630cb878de085c4334c87f05a460d6da0b31fc0ae7c7e8bb13619eeca71d137b4769d19969f610a7e8049493cfafbf6a6145b603133ef3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9]) cdi_type: Attestation
HardwareRevisionSecret act: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9, exp: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9
RomDigest act: 0x8bb13619eeca71d137b4769d19969f610a7e8049493cfafbf6a6145b603133ef, exp: 0x8bb13619eeca71d137b4769d19969f610a7e8049493cfafbf6a6145b603133ef
HealthMeasurement act: 0xc4334c87f05a460d6da0b31fc0ae7c7e, exp: 0xc4334c87f05a460d6da0b31fc0ae7c7e
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Sealing Aes
has 1 failures:
41.keymgr_lc_disable.46715277213867291572805892150439438245555089488611932737351843080724867096329
Line 356, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/41.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 60982982 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (3439533979718246692992407315908934023390428265732309885067790815668797985950048401435138403936319647333079472662206575764507949333887322718329090278983369 [0x41ac1785c6ba5a7736189f74d599138da518ae8ceb2a9686d728e0a56d0bacde064bb2ba138c0c973b1548ac4868a33dc594231fb1281c09b43936a68f1086c9] vs 3439533979718246692992407315908934023390428265732309885067790815668797985950048401435138403936319647333079472662206575764507949333887322718329090278983369 [0x41ac1785c6ba5a7736189f74d599138da518ae8ceb2a9686d728e0a56d0bacde064bb2ba138c0c973b1548ac4868a33dc594231fb1281c09b43936a68f1086c9]) AES key at state StCreatorRootKey for Sealing Aes
UVM_INFO @ 60982982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---