KEYMGR Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	23.210s	2.666ms	49	50	98.00
V1	random	keymgr_random	53.720s	7.874ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.750s	53.920us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.650s	26.671us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.790s	6.086ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.690s	232.542us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.440s	31.893us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.650s	26.671us	20	20	100.00
		keymgr_csr_aliasing	8.690s	232.542us	5	5	100.00
V1		TOTAL			154	155	99.35
V2	cfgen_during_op	keymgr_cfg_regwen	1.794m	3.947ms	50	50	100.00
V2	sideload	keymgr_sideload	1.087m	20.554ms	50	50	100.00
		keymgr_sideload_kmac	58.200s	1.900ms	50	50	100.00
		keymgr_sideload_aes	53.100s	1.675ms	50	50	100.00
		keymgr_sideload_otbn	55.240s	6.060ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	31.480s	2.619ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	10.920s	916.139us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	12.640s	381.851us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	40.590s	6.324ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	25.190s	4.861ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	23.780s	6.415ms	50	50	100.00
V2	stress_all	keymgr_stress_all	3.487m	6.766ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.950s	23.427us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.160s	70.403us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.050s	857.115us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.050s	857.115us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.750s	53.920us	5	5	100.00
		keymgr_csr_rw	1.650s	26.671us	20	20	100.00
		keymgr_csr_aliasing	8.690s	232.542us	5	5	100.00
		keymgr_same_csr_outstanding	4.020s	95.392us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.750s	53.920us	5	5	100.00
		keymgr_csr_rw	1.650s	26.671us	20	20	100.00
		keymgr_csr_aliasing	8.690s	232.542us	5	5	100.00
		keymgr_same_csr_outstanding	4.020s	95.392us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	sec_cm_additional_check	keymgr_sec_cm	20.850s	2.145ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	20.850s	2.145ms	5	5	100.00
		keymgr_tl_intg_err	10.630s	1.025ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.660s	2.092ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.660s	2.092ms	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.660s	2.092ms	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.660s	2.092ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.580s	367.639us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	20.850s	2.145ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	20.850s	2.145ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.630s	1.025ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.660s	2.092ms	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.794m	3.947ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	53.720s	7.874ms	50	50	100.00
		keymgr_csr_rw	1.650s	26.671us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	53.720s	7.874ms	50	50	100.00
		keymgr_csr_rw	1.650s	26.671us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	53.720s	7.874ms	50	50	100.00
		keymgr_csr_rw	1.650s	26.671us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	10.920s	916.139us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	25.190s	4.861ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	25.190s	4.861ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	53.720s	7.874ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	23.350s	2.286ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	20.850s	2.145ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	20.850s	2.145ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	20.850s	2.145ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	25.640s	9.359ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	10.920s	916.139us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	20.850s	2.145ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	20.850s	2.145ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	20.850s	2.145ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	25.640s	9.359ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	25.640s	9.359ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	20.850s	2.145ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	25.640s	9.359ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	20.850s	2.145ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	25.640s	9.359ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	28.780s	4.089ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			1087	1110	97.93

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	16	16	14	87.50
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.70	99.04	98.07	98.25	100.00	99.02	98.41	91.14

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
  • Test keymgr_stress_all_with_rand_reset has 19 failures.

    • 0.keymgr_stress_all_with_rand_reset.99549212714476882348977734739918585199253915108492314592572019260634245658694
      Line 404, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 585414070 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 585414070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.keymgr_stress_all_with_rand_reset.85548346955171771720545396209233489691282565145679396132168461419382865943993
      Line 271, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 223954766 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 223954766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:

  • Test keymgr_stress_all has 1 failures.

    • 2.keymgr_stress_all.62930969279305687271510869827077925282177745223503987654683073163881374821114
      Line 582, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all/latest/run.log

        UVM_ERROR @  51909081 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  51909081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 6.keymgr_stress_all_with_rand_reset.48885033713976860253606611342839763209983369921276642002727682105352336068951
      Line 1009, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 155421709 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 155421709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_lc_disable has 1 failures.

    • 32.keymgr_lc_disable.77614871474958364350741603465861752876923608418128742907605011875193503399256
      Line 505, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/32.keymgr_lc_disable/latest/run.log

        UVM_ERROR @ 117101738 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
        UVM_INFO @ 117101738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_smoke has 1 failures.

    • 47.keymgr_smoke.35874256173635576027890648644135990888430016813368199938182966922816632070280
      Line 268, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/47.keymgr_smoke/latest/run.log

        UVM_ERROR @   2431831 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @   2431831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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