KEYMGR Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	24.750s	1.322ms	50	50	100.00
V1	random	keymgr_random	1.546m	9.098ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.160s	14.530us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.560s	33.072us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	24.180s	3.412ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	16.160s	2.530ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.220s	48.630us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.560s	33.072us	20	20	100.00
		keymgr_csr_aliasing	16.160s	2.530ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.029m	7.824ms	49	50	98.00
V2	sideload	keymgr_sideload	42.200s	4.499ms	50	50	100.00
		keymgr_sideload_kmac	1.190m	36.724ms	49	50	98.00
		keymgr_sideload_aes	1.174m	10.528ms	50	50	100.00
		keymgr_sideload_otbn	48.110s	4.386ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	32.930s	981.055us	49	50	98.00
V2	lc_disable	keymgr_lc_disable	16.570s	380.024us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	13.630s	2.365ms	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.271m	11.410ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	32.320s	2.875ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	18.930s	1.739ms	50	50	100.00
V2	stress_all	keymgr_stress_all	7.831m	89.848ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.950s	18.612us	50	50	100.00
V2	alert_test	keymgr_alert_test	0.950s	23.755us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.920s	137.796us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.920s	137.796us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.160s	14.530us	5	5	100.00
		keymgr_csr_rw	1.560s	33.072us	20	20	100.00
		keymgr_csr_aliasing	16.160s	2.530ms	5	5	100.00
		keymgr_same_csr_outstanding	3.540s	159.073us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.160s	14.530us	5	5	100.00
		keymgr_csr_rw	1.560s	33.072us	20	20	100.00
		keymgr_csr_aliasing	16.160s	2.530ms	5	5	100.00
		keymgr_same_csr_outstanding	3.540s	159.073us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	17.590s	628.017us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	17.590s	628.017us	5	5	100.00
		keymgr_tl_intg_err	10.080s	254.155us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.640s	157.839us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.640s	157.839us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.640s	157.839us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.640s	157.839us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.900s	1.236ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	17.590s	628.017us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	17.590s	628.017us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.080s	254.155us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.640s	157.839us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.029m	7.824ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.546m	9.098ms	50	50	100.00
		keymgr_csr_rw	1.560s	33.072us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.546m	9.098ms	50	50	100.00
		keymgr_csr_rw	1.560s	33.072us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.546m	9.098ms	50	50	100.00
		keymgr_csr_rw	1.560s	33.072us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	16.570s	380.024us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	32.320s	2.875ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	32.320s	2.875ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.546m	9.098ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	18.970s	606.146us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	17.590s	628.017us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	17.590s	628.017us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	17.590s	628.017us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	15.070s	2.711ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	16.570s	380.024us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	17.590s	628.017us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	17.590s	628.017us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	17.590s	628.017us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	15.070s	2.711ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	15.070s	2.711ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	17.590s	628.017us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	15.070s	2.711ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	17.590s	628.017us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	15.070s	2.711ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	36.600s	2.926ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			1087	1110	97.93

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	11	68.75
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.69	99.04	97.83	98.32	100.00	99.02	98.41	91.19

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

  • Test keymgr_stress_all_with_rand_reset has 18 failures.

    • 0.keymgr_stress_all_with_rand_reset.31064333437061721800478081296441900348566232407494463995329777745686465045138
      Line 1241, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 682380760 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 682380760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.keymgr_stress_all_with_rand_reset.57132397104261645979596792016066969463931991236403273786492930609008595034159
      Line 767, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 373585790 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 373585790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:

  • Test keymgr_cfg_regwen has 1 failures.

    • 4.keymgr_cfg_regwen.55735312132454263501725383940607296305366644014057327394983108990379371019493
      Line 263, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_cfg_regwen/latest/run.log

        UVM_ERROR @   2478127 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @   2478127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_direct_to_disabled has 1 failures.

    • 8.keymgr_direct_to_disabled.73247865444721638494787062844563607046757944337126417168645242160045103714803
      Line 396, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/8.keymgr_direct_to_disabled/latest/run.log

        UVM_ERROR @  22885422 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  22885422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 32.keymgr_kmac_rsp_err.105255080833782053320406761449621305389041082262333201103707673404372069060876
      Line 742, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @ 240483533 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 240483533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_sideload_kmac has 1 failures.

    • 40.keymgr_sideload_kmac.58464627066993832974291166164416012691251197841208892385481327610637943994107
      Line 258, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/40.keymgr_sideload_kmac/latest/run.log

        UVM_ERROR @   3419521 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @   3419521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 30.keymgr_stress_all.65865982754559887704543651865890997347303088298333210974922156334431687251658
      Line 2189, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 2218111659 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_7
        UVM_INFO @ 2218111659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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