8fdb25c8d9
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 36.930s | 18.584ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 54.710s | 2.087ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.150s | 44.649us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.540s | 51.621us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 18.040s | 3.477ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 10.360s | 2.290ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.340s | 117.525us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.540s | 51.621us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 10.360s | 2.290ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 2.297m | 5.105ms | 50 | 50 | 100.00 |
V2 | sideload | keymgr_sideload | 25.040s | 3.406ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 48.820s | 3.305ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 53.150s | 7.226ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 36.420s | 3.902ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 37.730s | 4.074ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 7.780s | 291.905us | 49 | 50 | 98.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 18.610s | 1.799ms | 49 | 50 | 98.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 34.570s | 1.027ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 48.220s | 2.783ms | 49 | 50 | 98.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 10.170s | 885.080us | 49 | 50 | 98.00 |
V2 | stress_all | keymgr_stress_all | 9.358m | 59.639ms | 49 | 50 | 98.00 |
V2 | intr_test | keymgr_intr_test | 0.930s | 19.983us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.040s | 28.868us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 4.510s | 128.111us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 4.510s | 128.111us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.150s | 44.649us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.540s | 51.621us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.360s | 2.290ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.610s | 213.033us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.150s | 44.649us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.540s | 51.621us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.360s | 2.290ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.610s | 213.033us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 735 | 740 | 99.32 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 12.410s | 610.230us | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 12.410s | 610.230us | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 11.120s | 3.608ms | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 6.050s | 263.758us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 6.050s | 263.758us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 6.050s | 263.758us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 6.050s | 263.758us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 15.620s | 511.232us | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 12.410s | 610.230us | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 12.410s | 610.230us | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 11.120s | 3.608ms | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 6.050s | 263.758us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 2.297m | 5.105ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 54.710s | 2.087ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.540s | 51.621us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 54.710s | 2.087ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.540s | 51.621us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 54.710s | 2.087ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.540s | 51.621us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 7.780s | 291.905us | 49 | 50 | 98.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 48.220s | 2.783ms | 49 | 50 | 98.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 48.220s | 2.783ms | 49 | 50 | 98.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 54.710s | 2.087ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 22.440s | 4.348ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 12.410s | 610.230us | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 12.410s | 610.230us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 12.410s | 610.230us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 45.490s | 3.154ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 7.780s | 291.905us | 49 | 50 | 98.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 12.410s | 610.230us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 12.410s | 610.230us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 12.410s | 610.230us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 45.490s | 3.154ms | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 45.490s | 3.154ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 12.410s | 610.230us | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 45.490s | 3.154ms | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 12.410s | 610.230us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 45.490s | 3.154ms | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 27.490s | 584.916us | 30 | 50 | 60.00 |
V3 | TOTAL | 30 | 50 | 60.00 | |||
TOTAL | 1085 | 1110 | 97.75 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 11 | 68.75 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.76 | 99.04 | 98.11 | 98.53 | 100.00 | 99.02 | 98.41 | 91.22 |
UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 19 failures:
2.keymgr_stress_all_with_rand_reset.37743420133042925481420684271736340880659161567143875050791941374558210618948
Line 381, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 107822295 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 107822295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.keymgr_stress_all_with_rand_reset.92214202321506500803609943587592116871736862185034170898057189920443236994448
Line 305, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 115487972 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 115487972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 2 failures:
Test keymgr_kmac_rsp_err has 1 failures.
41.keymgr_kmac_rsp_err.112575398316489250596376542769204743787022729139908121829861948693442016184101
Line 1005, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest/run.log
UVM_ERROR @ 150807186 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 150807186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_lc_disable has 1 failures.
44.keymgr_lc_disable.10474436964175819494711351189555197689391701604358762236795843792613441349314
Line 277, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/44.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 13465302 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 13465302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
9.keymgr_stress_all.60815739732870644193236251354638613391544342325003407041540080510894181270268
Line 694, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_stress_all/latest/run.log
UVM_ERROR @ 552074894 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_7
UVM_INFO @ 552074894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [*] vs * [*])
has 1 failures:
18.keymgr_sync_async_fault_cross.56539452221700286989301281165967613034154473827637715767375430363403639730268
Line 326, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest/run.log
UVM_ERROR @ 155013068 ps: (keymgr_sync_async_fault_cross_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 155013068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:752) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
has 1 failures:
21.keymgr_stress_all_with_rand_reset.33361679819216462601401531976733479201056238355961339843634850750049182254658
Line 366, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/21.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 109495445 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 109495445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly
has 1 failures:
25.keymgr_hwsw_invalid_input.16634853152827536675984901907009298005965002080837928657351278288008376248331
Line 723, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest/run.log
UVM_ERROR @ 38400642 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
UVM_INFO @ 38400642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---