KEYMGR Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: `25e609d6bb`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	45.980s	3.307ms	50	50	100.00
V1	random	keymgr_random	48.760s	7.193ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.240s	33.614us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.410s	22.840us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.010s	1.288ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	15.470s	1.004ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.470s	31.826us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.410s	22.840us	20	20	100.00
		keymgr_csr_aliasing	15.470s	1.004ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.049m	1.323ms	49	50	98.00
V2	sideload	keymgr_sideload	49.030s	2.572ms	50	50	100.00
		keymgr_sideload_kmac	50.760s	2.703ms	50	50	100.00
		keymgr_sideload_aes	34.520s	1.207ms	50	50	100.00
		keymgr_sideload_otbn	44.700s	6.914ms	49	50	98.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	7.500s	441.073us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	24.320s	1.672ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	8.330s	1.770ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	54.510s	6.912ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	37.730s	9.178ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	20.220s	11.442ms	50	50	100.00
V2	stress_all	keymgr_stress_all	11.500m	73.250ms	46	50	92.00
V2	intr_test	keymgr_intr_test	0.900s	14.637us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.030s	20.942us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	6.230s	617.255us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	6.230s	617.255us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.240s	33.614us	5	5	100.00
		keymgr_csr_rw	1.410s	22.840us	20	20	100.00
		keymgr_csr_aliasing	15.470s	1.004ms	5	5	100.00
		keymgr_same_csr_outstanding	3.280s	448.816us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.240s	33.614us	5	5	100.00
		keymgr_csr_rw	1.410s	22.840us	20	20	100.00
		keymgr_csr_aliasing	15.470s	1.004ms	5	5	100.00
		keymgr_same_csr_outstanding	3.280s	448.816us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	sec_cm_additional_check	keymgr_sec_cm	15.780s	545.510us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	15.780s	545.510us	5	5	100.00
		keymgr_tl_intg_err	10.490s	315.095us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.720s	306.675us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.720s	306.675us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.720s	306.675us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.720s	306.675us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.730s	402.714us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	15.780s	545.510us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	15.780s	545.510us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.490s	315.095us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.720s	306.675us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.049m	1.323ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	48.760s	7.193ms	50	50	100.00
		keymgr_csr_rw	1.410s	22.840us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	48.760s	7.193ms	50	50	100.00
		keymgr_csr_rw	1.410s	22.840us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	48.760s	7.193ms	50	50	100.00
		keymgr_csr_rw	1.410s	22.840us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	24.320s	1.672ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	37.730s	9.178ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	37.730s	9.178ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	48.760s	7.193ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	13.510s	526.896us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	15.780s	545.510us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	15.780s	545.510us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	15.780s	545.510us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	19.780s	1.505ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	24.320s	1.672ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	15.780s	545.510us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	15.780s	545.510us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	15.780s	545.510us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	19.780s	1.505ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	19.780s	1.505ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	15.780s	545.510us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	19.780s	1.505ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	15.780s	545.510us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	19.780s	1.505ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	29.980s	2.283ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			1087	1110	97.93

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.34	99.00	97.99	98.26	97.67	98.93	98.41	91.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test keymgr_stress_all_with_rand_reset has 17 failures.
  - 0.keymgr_stress_all_with_rand_reset.2586208013884771458106620322403127098317258121877507264098258216847752169845
    Line 417, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 469700826 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 469700826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.keymgr_stress_all_with_rand_reset.87199933998544309754988924031322101592919076533061657079637558636165656210665
    Line 511, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 141475194 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 141475194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.

UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:

Test keymgr_stress_all has 2 failures.

10.keymgr_stress_all.13602968754910208630880280880549890685902293468988900595067326536455952466498
Line 746, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_stress_all/latest/run.log

  UVM_ERROR @  60929541 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  60929541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.keymgr_stress_all.63185941258509494188976787818904394023517158988044779442678017794258336835557
Line 1890, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/40.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 715689149 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @ 715689149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_cfg_regwen has 1 failures.

23.keymgr_cfg_regwen.103955697552774769140664475427748080289853420534748716052657501863030308752795
Line 323, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/23.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @  13008826 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  13008826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sideload_otbn has 1 failures.

49.keymgr_sideload_otbn.86353604142678747266869598164360423498683579964900018321800139337008963603424
Line 277, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/49.keymgr_sideload_otbn/latest/run.log

  UVM_ERROR @   4183394 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   4183394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StCreatorRootKey for Sealing Kmac has 1 failures:

Test keymgr_stress_all has 1 failures.

1.keymgr_stress_all.48341282641250893120979200078707678227467826282122211775999547719391256532908
Line 570, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 498701144 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (5951157419155525047130746366681790038869025882861708827254019236316472956690934451155050687741740090360957467989991093500726703105755020954548038903733858 [0x71a0a6ca81a10036017b60a5b1f2dba3e9843ad1cd2cef4816cc2f08d4f09d507bcd23a0579e2395cc2c1ddb352a37bdf1d613a0dc55373b16ab11dc92971e62] vs 5951157419155525047130746366681790038869025882861708827254019236316472956690934451155050687741740090360957467989991093500726703105755020954548038903733858 [0x71a0a6ca81a10036017b60a5b1f2dba3e9843ad1cd2cef4816cc2f08d4f09d507bcd23a0579e2395cc2c1ddb352a37bdf1d613a0dc55373b16ab11dc92971e62]) KMAC key at state StCreatorRootKey for Sealing Kmac
  UVM_INFO @ 498701144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 11.keymgr_stress_all.66731780217370985870885398916265621805493124023427968463942038832425958748209
    Line 4967, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 3801422159 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (1053464631 [0x3eca9837] vs 1053464631 [0x3eca9837]) reg name: keymgr_reg_block.sw_share0_output_7
  UVM_INFO @ 3801422159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```