KEYMGR Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: 6e698b4dfe

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	48.920s	3.033ms	49	50	98.00
V1	random	keymgr_random	1.191m	6.919ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.270s	22.539us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.490s	27.361us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	23.850s	3.415ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.510s	374.648us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.430s	33.333us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.490s	27.361us	20	20	100.00
		keymgr_csr_aliasing	8.510s	374.648us	5	5	100.00
V1		TOTAL			154	155	99.35
V2	cfgen_during_op	keymgr_cfg_regwen	1.276m	9.306ms	49	50	98.00
V2	sideload	keymgr_sideload	1.078m	3.378ms	50	50	100.00
		keymgr_sideload_kmac	1.096m	6.663ms	50	50	100.00
		keymgr_sideload_aes	47.590s	2.597ms	50	50	100.00
		keymgr_sideload_otbn	43.170s	1.925ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	30.440s	1.921ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	8.210s	283.676us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	11.700s	841.688us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.022m	2.481ms	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.445m	4.186ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	28.190s	1.557ms	49	50	98.00
V2	stress_all	keymgr_stress_all	13.288m	84.645ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.060s	29.807us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.040s	37.939us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.750s	456.316us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.750s	456.316us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.270s	22.539us	5	5	100.00
		keymgr_csr_rw	1.490s	27.361us	20	20	100.00
		keymgr_csr_aliasing	8.510s	374.648us	5	5	100.00
		keymgr_same_csr_outstanding	4.050s	440.071us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.270s	22.539us	5	5	100.00
		keymgr_csr_rw	1.490s	27.361us	20	20	100.00
		keymgr_csr_aliasing	8.510s	374.648us	5	5	100.00
		keymgr_same_csr_outstanding	4.050s	440.071us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	sec_cm_additional_check	keymgr_sec_cm	19.410s	5.842ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	19.410s	5.842ms	5	5	100.00
		keymgr_tl_intg_err	11.210s	328.934us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.030s	132.713us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.030s	132.713us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.030s	132.713us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.030s	132.713us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	16.640s	7.912ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	19.410s	5.842ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	19.410s	5.842ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	11.210s	328.934us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.030s	132.713us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.276m	9.306ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.191m	6.919ms	50	50	100.00
		keymgr_csr_rw	1.490s	27.361us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.191m	6.919ms	50	50	100.00
		keymgr_csr_rw	1.490s	27.361us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.191m	6.919ms	50	50	100.00
		keymgr_csr_rw	1.490s	27.361us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	8.210s	283.676us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.445m	4.186ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.445m	4.186ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.191m	6.919ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	26.580s	3.842ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	19.410s	5.842ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	19.410s	5.842ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	19.410s	5.842ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	10.080s	2.659ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	8.210s	283.676us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	19.410s	5.842ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	19.410s	5.842ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	19.410s	5.842ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	10.080s	2.659ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	10.080s	2.659ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	19.410s	5.842ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	10.080s	2.659ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	19.410s	5.842ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	10.080s	2.659ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	25.650s	1.240ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			1086	1110	97.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	16	16	11	68.75
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.76	99.04	97.95	98.58	100.00	99.02	98.41	91.34

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

  • Test keymgr_stress_all_with_rand_reset has 16 failures.

    • 1.keymgr_stress_all_with_rand_reset.93165611675198283752032440796088171510051718418667189589580119693686759136562
      Line 786, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 368882804 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 368882804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.keymgr_stress_all_with_rand_reset.113027329894806067316716791493554328610989168736823726815245865045250732567417
      Line 766, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 671017477 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 671017477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:

  • Test keymgr_sw_invalid_input has 1 failures.

    • 16.keymgr_sw_invalid_input.84345737708587876042303024486075777927527945368428729870006638233685566909742
      Line 505, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest/run.log

        UVM_ERROR @  62884220 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  62884220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_smoke has 1 failures.

    • 17.keymgr_smoke.104399515771579904512645733480876648366847370316490362013940670657423498945560
      Line 339, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/17.keymgr_smoke/latest/run.log

        UVM_ERROR @  30837663 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  30837663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_stress_all has 1 failures.

    • 24.keymgr_stress_all.29351020074732160997579117331989046618200912565951688761741854846660791340712
      Line 4088, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/24.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 7663409629 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 7663409629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 33.keymgr_kmac_rsp_err.22878518722633221204453253706665588119140373704903438340591034109958779850525
      Line 432, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @  12450957 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  12450957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:

  • Test keymgr_cfg_regwen has 1 failures.

    • 2.keymgr_cfg_regwen.13407028194531357985453325303440361488921304608540135763584976269796314177973
      Line 261, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest/run.log

        UVM_ERROR @   2192865 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
        UVM_INFO @   2192865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 23.keymgr_stress_all.84293143339350921767692617174020456674595875530483687055830729659370893946289
      Line 1122, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/23.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 338805978 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_0
        UVM_INFO @ 338805978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:752) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 45.keymgr_stress_all_with_rand_reset.11605846676426842269224394454508361241431067826408845069999152509733191141212
      Line 341, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 987040961 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 987040961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:261) scoreboard [scoreboard] alert recov_operation_err is not received! has 1 failures:

  • Test keymgr_sync_async_fault_cross has 1 failures.

    • 46.keymgr_sync_async_fault_cross.25202840547399161761362560418076743633820477087615453879956879893560752930247
      Line 365, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest/run.log

        UVM_ERROR @  80454479 ps: (cip_base_scoreboard.sv:261) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
        UVM_INFO @  80454479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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