3fd3528c8c
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 48.910s | 5.937ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 46.490s | 1.985ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.390s | 111.584us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.480s | 82.055us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 17.810s | 5.117ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 14.590s | 804.782us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.600s | 32.598us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.480s | 82.055us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 14.590s | 804.782us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 2.118m | 9.481ms | 50 | 50 | 100.00 |
V2 | sideload | keymgr_sideload | 59.480s | 6.048ms | 49 | 50 | 98.00 |
keymgr_sideload_kmac | 45.390s | 2.514ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 1.036m | 1.836ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 39.640s | 1.467ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 45.800s | 1.537ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 26.500s | 1.869ms | 50 | 50 | 100.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 6.510s | 157.859us | 50 | 50 | 100.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 38.330s | 5.346ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 54.580s | 9.739ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 11.000s | 800.895us | 49 | 50 | 98.00 |
V2 | stress_all | keymgr_stress_all | 8.851m | 16.754ms | 48 | 50 | 96.00 |
V2 | intr_test | keymgr_intr_test | 0.940s | 56.608us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.200s | 29.145us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 6.310s | 722.254us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 6.310s | 722.254us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.390s | 111.584us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.480s | 82.055us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 14.590s | 804.782us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.970s | 120.318us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.390s | 111.584us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.480s | 82.055us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 14.590s | 804.782us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.970s | 120.318us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 736 | 740 | 99.46 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 34.540s | 1.780ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 34.540s | 1.780ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 10.150s | 264.837us | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 4.690s | 317.195us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 4.690s | 317.195us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 4.690s | 317.195us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 4.690s | 317.195us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 15.960s | 6.331ms | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 34.540s | 1.780ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 34.540s | 1.780ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 10.150s | 264.837us | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 4.690s | 317.195us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 2.118m | 9.481ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 46.490s | 1.985ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.480s | 82.055us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 46.490s | 1.985ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.480s | 82.055us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 46.490s | 1.985ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.480s | 82.055us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 26.500s | 1.869ms | 50 | 50 | 100.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 54.580s | 9.739ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 54.580s | 9.739ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 46.490s | 1.985ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 27.410s | 6.575ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 34.540s | 1.780ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 34.540s | 1.780ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 34.540s | 1.780ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 21.300s | 3.318ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 26.500s | 1.869ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 34.540s | 1.780ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 34.540s | 1.780ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 34.540s | 1.780ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 21.300s | 3.318ms | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 21.300s | 3.318ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 34.540s | 1.780ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 21.300s | 3.318ms | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 34.540s | 1.780ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 21.300s | 3.318ms | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 23.840s | 2.130ms | 29 | 50 | 58.00 |
V3 | TOTAL | 29 | 50 | 58.00 | |||
TOTAL | 1085 | 1110 | 97.75 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 13 | 81.25 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.77 | 99.04 | 98.11 | 98.65 | 100.00 | 99.02 | 98.41 | 91.17 |
UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 20 failures:
0.keymgr_stress_all_with_rand_reset.67149162890838149561309724061296887848616471347452808789051377629334432227106
Line 342, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 127992961 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 127992961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.keymgr_stress_all_with_rand_reset.110702480920782235154641040461025914861838008117560103830304594955558239050335
Line 421, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1364574243 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1364574243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 3 failures:
Test keymgr_stress_all has 1 failures.
18.keymgr_stress_all.89188925396169165385131215668423958682651293276304190993508545356738734680680
Line 2046, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/18.keymgr_stress_all/latest/run.log
UVM_ERROR @ 827662102 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 827662102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all_with_rand_reset has 1 failures.
20.keymgr_stress_all_with_rand_reset.14591015956899459069740371820185623788512969311959702671093570122614722354399
Line 270, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13106212 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 13106212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_sideload has 1 failures.
42.keymgr_sideload.107471712706707433310751875934106238174657308389953979001981523017909313804240
Line 273, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_sideload/latest/run.log
UVM_ERROR @ 5188293 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 5188293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [*] vs * [*])
has 1 failures:
3.keymgr_sync_async_fault_cross.35321958144950564935942809270677461716541768887231889070759318243020497431414
Line 323, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest/run.log
UVM_ERROR @ 112503037 ps: (keymgr_sync_async_fault_cross_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 112503037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
41.keymgr_stress_all.52999167157867419650283512038977686600901390386735804811994713492103418093179
Line 3065, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/41.keymgr_stress_all/latest/run.log
UVM_ERROR @ 3223954998 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3502729042 [0xd0c76752] vs 3502729042 [0xd0c76752]) reg name: keymgr_reg_block.sw_share0_output_3
UVM_INFO @ 3223954998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---