be1c4a4f52
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 50.450s | 14.092ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 1.231m | 3.676ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.360s | 37.186us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.530s | 24.502us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 31.800s | 5.587ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 17.320s | 1.022ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.390s | 286.680us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.530s | 24.502us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 17.320s | 1.022ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 1.920m | 7.489ms | 49 | 50 | 98.00 |
V2 | sideload | keymgr_sideload | 50.230s | 4.547ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 47.750s | 2.095ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 30.670s | 5.298ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 1.066m | 6.685ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 27.410s | 1.174ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 7.680s | 732.883us | 50 | 50 | 100.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 19.290s | 2.277ms | 50 | 50 | 100.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 59.590s | 3.340ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 1.157m | 2.502ms | 49 | 50 | 98.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 27.420s | 2.974ms | 50 | 50 | 100.00 |
V2 | stress_all | keymgr_stress_all | 5.554m | 49.225ms | 49 | 50 | 98.00 |
V2 | intr_test | keymgr_intr_test | 0.960s | 14.275us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.040s | 30.354us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 4.660s | 396.076us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 4.660s | 396.076us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.360s | 37.186us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.530s | 24.502us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 17.320s | 1.022ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.800s | 187.787us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.360s | 37.186us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.530s | 24.502us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 17.320s | 1.022ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.800s | 187.787us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 737 | 740 | 99.59 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 17.170s | 837.396us | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 17.170s | 837.396us | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 9.830s | 505.340us | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 5.660s | 196.228us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 5.660s | 196.228us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 5.660s | 196.228us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 5.660s | 196.228us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 15.080s | 415.061us | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 17.170s | 837.396us | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 17.170s | 837.396us | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 9.830s | 505.340us | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 5.660s | 196.228us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 1.920m | 7.489ms | 49 | 50 | 98.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 1.231m | 3.676ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.530s | 24.502us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 1.231m | 3.676ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.530s | 24.502us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 1.231m | 3.676ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.530s | 24.502us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 7.680s | 732.883us | 50 | 50 | 100.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 1.157m | 2.502ms | 49 | 50 | 98.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 1.157m | 2.502ms | 49 | 50 | 98.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 1.231m | 3.676ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 24.860s | 1.026ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 17.170s | 837.396us | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 17.170s | 837.396us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 17.170s | 837.396us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 19.880s | 447.868us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 7.680s | 732.883us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 17.170s | 837.396us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 17.170s | 837.396us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 17.170s | 837.396us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 19.880s | 447.868us | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 19.880s | 447.868us | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 17.170s | 837.396us | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 19.880s | 447.868us | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 17.170s | 837.396us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 19.880s | 447.868us | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 34.400s | 4.402ms | 32 | 50 | 64.00 |
V3 | TOTAL | 32 | 50 | 64.00 | |||
TOTAL | 1089 | 1110 | 98.11 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 13 | 81.25 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.73 | 99.04 | 98.11 | 98.37 | 100.00 | 99.02 | 98.41 | 91.17 |
UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 18 failures:
1.keymgr_stress_all_with_rand_reset.11281949396715734669624159876395654973742669896203615373815553646277623263125
Line 2316, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4402223554 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4402223554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.keymgr_stress_all_with_rand_reset.12145105736717531280089671162300729227728141362325307752712593063310474386721
Line 1462, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1087718400 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1087718400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 2 failures:
Test keymgr_stress_all has 1 failures.
3.keymgr_stress_all.72384144091934158897035103831510795984874164920248563363116311424646830365982
Line 1781, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all/latest/run.log
UVM_ERROR @ 1098115628 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 1098115628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_cfg_regwen has 1 failures.
47.keymgr_cfg_regwen.60110514259485472306941682257027373464578714887354960581732462014498121084287
Line 558, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest/run.log
UVM_ERROR @ 32277174 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 32277174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly
has 1 failures:
32.keymgr_hwsw_invalid_input.77632109479098494522744681119135173926225877619374619049844587543188260285052
Line 620, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/32.keymgr_hwsw_invalid_input/latest/run.log
UVM_ERROR @ 79777450 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
UVM_INFO @ 79777450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---