KEYMGR Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: 8db2a18db1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	29.810s	4.982ms	50	50	100.00
V1	random	keymgr_random	1.022m	2.042ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.560s	41.549us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.600s	116.415us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	26.520s	6.587ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	4.980s	931.595us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.210s	258.331us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.600s	116.415us	20	20	100.00
		keymgr_csr_aliasing	4.980s	931.595us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	55.210s	4.436ms	50	50	100.00
V2	sideload	keymgr_sideload	53.820s	1.689ms	50	50	100.00
		keymgr_sideload_kmac	53.610s	2.135ms	50	50	100.00
		keymgr_sideload_aes	36.430s	5.359ms	50	50	100.00
		keymgr_sideload_otbn	33.770s	3.629ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	48.580s	10.966ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	23.580s	434.408us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.850s	841.817us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.054m	5.707ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	49.390s	7.945ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	18.040s	742.572us	49	50	98.00
V2	stress_all	keymgr_stress_all	3.614m	36.259ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.960s	18.585us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.020s	17.712us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.350s	899.998us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.350s	899.998us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.560s	41.549us	5	5	100.00
		keymgr_csr_rw	1.600s	116.415us	20	20	100.00
		keymgr_csr_aliasing	4.980s	931.595us	5	5	100.00
		keymgr_same_csr_outstanding	3.710s	347.487us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.560s	41.549us	5	5	100.00
		keymgr_csr_rw	1.600s	116.415us	20	20	100.00
		keymgr_csr_aliasing	4.980s	931.595us	5	5	100.00
		keymgr_same_csr_outstanding	3.710s	347.487us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	sec_cm_additional_check	keymgr_sec_cm	12.940s	1.557ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	12.940s	1.557ms	5	5	100.00
		keymgr_tl_intg_err	10.340s	2.109ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.860s	172.573us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.860s	172.573us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.860s	172.573us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.860s	172.573us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.480s	1.488ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	12.940s	1.557ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	12.940s	1.557ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.340s	2.109ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.860s	172.573us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	55.210s	4.436ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.022m	2.042ms	50	50	100.00
		keymgr_csr_rw	1.600s	116.415us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.022m	2.042ms	50	50	100.00
		keymgr_csr_rw	1.600s	116.415us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.022m	2.042ms	50	50	100.00
		keymgr_csr_rw	1.600s	116.415us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	23.580s	434.408us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	49.390s	7.945ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	49.390s	7.945ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.022m	2.042ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	31.400s	1.967ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	12.940s	1.557ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	12.940s	1.557ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	12.940s	1.557ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	56.760s	2.146ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	23.580s	434.408us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	12.940s	1.557ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	12.940s	1.557ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	12.940s	1.557ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	56.760s	2.146ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	56.760s	2.146ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	12.940s	1.557ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	56.760s	2.146ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	12.940s	1.557ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	56.760s	2.146ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	22.300s	2.136ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1085	1110	97.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	14	87.50
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.71	99.04	98.11	98.24	100.00	99.02	98.41	91.14

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test keymgr_stress_all_with_rand_reset has 22 failures.

    • 2.keymgr_stress_all_with_rand_reset.62045448638227340781002119611290745245704081558593405157799830607127037185269
      Line 511, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1000968186 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1000968186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.keymgr_stress_all_with_rand_reset.80703735683544472069881044456280703385382824346124297829018090816529781352275
      Line 337, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 496291641 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 496291641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:

  • Test keymgr_sync_async_fault_cross has 1 failures.

    • 10.keymgr_sync_async_fault_cross.106898060813407825621706116591832048543584528786222745189783267011543768644768
      Line 273, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest/run.log

        UVM_ERROR @  36831687 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  36831687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_stress_all has 1 failures.

    • 28.keymgr_stress_all.70060915191643219635600039315562455661861647218645293347484988614062712509423
      Line 1124, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/28.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 391311387 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
        UVM_INFO @ 391311387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 3.keymgr_stress_all.95629307113656122819341262538985049765447608666684980771692429799933846672801
      Line 2070, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 679193978 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2540836531 [0x977216b3] vs 2540836531 [0x977216b3]) reg name: keymgr_reg_block.sw_share1_output_7
        UVM_INFO @ 679193978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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