KEYMGR Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: 3d5220a43f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	49.870s	6.714ms	50	50	100.00
V1	random	keymgr_random	1.036m	8.677ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.290s	122.662us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.770s	183.999us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	24.730s	7.123ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.910s	1.905ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.130s	119.151us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.770s	183.999us	20	20	100.00
		keymgr_csr_aliasing	10.910s	1.905ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.589m	7.042ms	50	50	100.00
V2	sideload	keymgr_sideload	48.930s	6.834ms	50	50	100.00
		keymgr_sideload_kmac	1.091m	6.692ms	50	50	100.00
		keymgr_sideload_aes	51.440s	2.942ms	50	50	100.00
		keymgr_sideload_otbn	49.960s	21.411ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	26.680s	3.953ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	15.950s	1.114ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	20.710s	2.177ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.196m	2.166ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	31.730s	1.752ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	29.350s	3.802ms	50	50	100.00
V2	stress_all	keymgr_stress_all	8.074m	44.789ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.980s	21.827us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.060s	310.031us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.240s	302.647us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.240s	302.647us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.290s	122.662us	5	5	100.00
		keymgr_csr_rw	1.770s	183.999us	20	20	100.00
		keymgr_csr_aliasing	10.910s	1.905ms	5	5	100.00
		keymgr_same_csr_outstanding	4.200s	439.065us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.290s	122.662us	5	5	100.00
		keymgr_csr_rw	1.770s	183.999us	20	20	100.00
		keymgr_csr_aliasing	10.910s	1.905ms	5	5	100.00
		keymgr_same_csr_outstanding	4.200s	439.065us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	sec_cm_additional_check	keymgr_sec_cm	17.480s	559.161us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	17.480s	559.161us	5	5	100.00
		keymgr_tl_intg_err	9.700s	302.657us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.440s	202.966us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.440s	202.966us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.440s	202.966us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.440s	202.966us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.930s	381.156us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	17.480s	559.161us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	17.480s	559.161us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	9.700s	302.657us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.440s	202.966us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.589m	7.042ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.036m	8.677ms	50	50	100.00
		keymgr_csr_rw	1.770s	183.999us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.036m	8.677ms	50	50	100.00
		keymgr_csr_rw	1.770s	183.999us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.036m	8.677ms	50	50	100.00
		keymgr_csr_rw	1.770s	183.999us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	15.950s	1.114ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	31.730s	1.752ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	31.730s	1.752ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.036m	8.677ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	32.800s	3.869ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	17.480s	559.161us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	17.480s	559.161us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	17.480s	559.161us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	31.260s	5.134ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	15.950s	1.114ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	17.480s	559.161us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	17.480s	559.161us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	17.480s	559.161us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	31.260s	5.134ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	31.260s	5.134ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	17.480s	559.161us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	31.260s	5.134ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	17.480s	559.161us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	31.260s	5.134ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	27.490s	2.881ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			1090	1110	98.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	15	93.75
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.04	98.15	98.30	100.00	99.02	98.41	91.24

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
  • Test keymgr_stress_all_with_rand_reset has 18 failures.

    • 3.keymgr_stress_all_with_rand_reset.16811835277982833470378515713561557805814704404214678725558180210894400601840
      Line 680, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 225076478 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 225076478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.keymgr_stress_all_with_rand_reset.37855140043155965104262379411844641609354471584397992674432405842333823067249
      Line 564, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 155151142 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 155151142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
  • Test keymgr_stress_all has 2 failures.

    • 20.keymgr_stress_all.35577600577362738851167429180740174803538036193165816866902057296049850959990
      Line 1610, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/20.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 214801468 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 214801468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 38.keymgr_stress_all.1878868089023659913281522144081175409334379664701378635292944409068678798249
      Line 1817, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/38.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 366827144 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 366827144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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