b33f0bcb4a
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 29.500s | 6.829ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 1.000m | 8.819ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.410s | 118.784us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.550s | 27.941us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 25.050s | 3.554ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 14.330s | 1.565ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.890s | 36.621us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.550s | 27.941us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 14.330s | 1.565ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 1.558m | 3.613ms | 50 | 50 | 100.00 |
V2 | sideload | keymgr_sideload | 47.640s | 6.472ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 48.380s | 2.487ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 53.640s | 3.476ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 42.630s | 1.774ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 22.060s | 3.708ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 9.760s | 1.341ms | 50 | 50 | 100.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 7.630s | 263.533us | 50 | 50 | 100.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 37.740s | 6.210ms | 49 | 50 | 98.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 1.114m | 6.862ms | 49 | 50 | 98.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 31.680s | 1.350ms | 50 | 50 | 100.00 |
V2 | stress_all | keymgr_stress_all | 3.675m | 7.306ms | 49 | 50 | 98.00 |
V2 | intr_test | keymgr_intr_test | 0.930s | 15.989us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.000s | 17.792us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 5.570s | 174.965us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 5.570s | 174.965us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.410s | 118.784us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.550s | 27.941us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 14.330s | 1.565ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.830s | 207.707us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.410s | 118.784us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.550s | 27.941us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 14.330s | 1.565ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.830s | 207.707us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 737 | 740 | 99.59 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 15.670s | 1.960ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 15.670s | 1.960ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 11.510s | 1.125ms | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 4.300s | 271.031us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 4.300s | 271.031us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 4.300s | 271.031us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 4.300s | 271.031us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 10.770s | 3.658ms | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 15.670s | 1.960ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 15.670s | 1.960ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 11.510s | 1.125ms | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 4.300s | 271.031us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 1.558m | 3.613ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 1.000m | 8.819ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.550s | 27.941us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 1.000m | 8.819ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.550s | 27.941us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 1.000m | 8.819ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.550s | 27.941us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 9.760s | 1.341ms | 50 | 50 | 100.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 1.114m | 6.862ms | 49 | 50 | 98.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 1.114m | 6.862ms | 49 | 50 | 98.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 1.000m | 8.819ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 21.000s | 1.338ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 15.670s | 1.960ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 15.670s | 1.960ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 15.670s | 1.960ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 19.310s | 996.051us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 9.760s | 1.341ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 15.670s | 1.960ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 15.670s | 1.960ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 15.670s | 1.960ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 19.310s | 996.051us | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 19.310s | 996.051us | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 15.670s | 1.960ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 19.310s | 996.051us | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 15.670s | 1.960ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 19.310s | 996.051us | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 30.400s | 1.389ms | 26 | 50 | 52.00 |
V3 | TOTAL | 26 | 50 | 52.00 | |||
TOTAL | 1083 | 1110 | 97.57 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 13 | 81.25 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.79 | 99.04 | 98.11 | 98.66 | 100.00 | 99.02 | 98.41 | 91.32 |
UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 24 failures:
4.keymgr_stress_all_with_rand_reset.78344465697258115531910469937028644386762669250795728449358038686524843414493
Line 1168, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 670785793 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 670785793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.keymgr_stress_all_with_rand_reset.5275814642165910159907775961031326374906590149141823715579488805796100611586
Line 336, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 444227481 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 444227481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 2 failures:
Test keymgr_stress_all has 1 failures.
5.keymgr_stress_all.59568590839065072106953721131690856926616326272151274189931222007213821405698
Line 268, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all/latest/run.log
UVM_ERROR @ 20262140 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 20262140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_sw_invalid_input has 1 failures.
25.keymgr_sw_invalid_input.37857064189490524833460120809142557738278888098620173707199267057572675267815
Line 388, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest/run.log
UVM_ERROR @ 5870246 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 5870246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly
has 1 failures:
25.keymgr_hwsw_invalid_input.3564361121964905449873137641202120488070044920331247699932885091826765082370
Line 452, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest/run.log
UVM_ERROR @ 12143919 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
UVM_INFO @ 12143919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---