b33f0bcb4a
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 23.030s | 1.000ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 50.600s | 1.738ms | 49 | 50 | 98.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.150s | 55.774us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.580s | 37.663us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 25.330s | 3.567ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 10.760s | 449.287us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.370s | 64.260us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.580s | 37.663us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 10.760s | 449.287us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 154 | 155 | 99.35 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 1.378m | 1.580ms | 50 | 50 | 100.00 |
V2 | sideload | keymgr_sideload | 22.490s | 1.591ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 1.117m | 6.531ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 24.710s | 3.114ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 35.860s | 1.411ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 40.900s | 1.480ms | 49 | 50 | 98.00 |
V2 | lc_disable | keymgr_lc_disable | 24.040s | 825.935us | 49 | 50 | 98.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 10.700s | 1.294ms | 50 | 50 | 100.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 58.160s | 4.050ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 43.490s | 4.427ms | 49 | 50 | 98.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 20.140s | 2.621ms | 49 | 50 | 98.00 |
V2 | stress_all | keymgr_stress_all | 6.475m | 34.320ms | 46 | 50 | 92.00 |
V2 | intr_test | keymgr_intr_test | 1.070s | 26.693us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.030s | 21.965us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 5.790s | 200.148us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 5.790s | 200.148us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.150s | 55.774us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.580s | 37.663us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.760s | 449.287us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.320s | 527.446us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.150s | 55.774us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.580s | 37.663us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.760s | 449.287us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.320s | 527.446us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 732 | 740 | 98.92 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 12.160s | 2.164ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 12.160s | 2.164ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 12.300s | 1.298ms | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 4.460s | 564.335us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 4.460s | 564.335us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 4.460s | 564.335us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 4.460s | 564.335us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 16.860s | 508.607us | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 12.160s | 2.164ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 12.160s | 2.164ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 12.300s | 1.298ms | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 4.460s | 564.335us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 1.378m | 1.580ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 50.600s | 1.738ms | 49 | 50 | 98.00 |
keymgr_csr_rw | 1.580s | 37.663us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 50.600s | 1.738ms | 49 | 50 | 98.00 |
keymgr_csr_rw | 1.580s | 37.663us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 50.600s | 1.738ms | 49 | 50 | 98.00 |
keymgr_csr_rw | 1.580s | 37.663us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 24.040s | 825.935us | 49 | 50 | 98.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 43.490s | 4.427ms | 49 | 50 | 98.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 43.490s | 4.427ms | 49 | 50 | 98.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 50.600s | 1.738ms | 49 | 50 | 98.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 24.340s | 3.590ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 12.160s | 2.164ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 12.160s | 2.164ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 12.160s | 2.164ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 29.820s | 9.005ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 24.040s | 825.935us | 49 | 50 | 98.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 12.160s | 2.164ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 12.160s | 2.164ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 12.160s | 2.164ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 29.820s | 9.005ms | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 29.820s | 9.005ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 12.160s | 2.164ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 29.820s | 9.005ms | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 12.160s | 2.164ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 29.820s | 9.005ms | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 27.210s | 1.361ms | 28 | 50 | 56.00 |
V3 | TOTAL | 28 | 50 | 56.00 | |||
TOTAL | 1079 | 1110 | 97.21 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 6 | 85.71 |
V2 | 16 | 16 | 11 | 68.75 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.67 | 99.04 | 97.91 | 98.11 | 100.00 | 99.02 | 98.41 | 91.22 |
UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 22 failures:
2.keymgr_stress_all_with_rand_reset.115147495243184174214450734918766998499776512160695204149322737102821821676777
Line 1527, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2702054984 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2702054984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.keymgr_stress_all_with_rand_reset.81525848977000653997532819748197371732591880947997329371936135951807084706261
Line 1612, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 497202008 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 497202008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 3 failures:
Test keymgr_direct_to_disabled has 1 failures.
24.keymgr_direct_to_disabled.18489677686241427600386344421842553538052738311790029955412271566789581326521
Line 263, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/24.keymgr_direct_to_disabled/latest/run.log
UVM_ERROR @ 4210342 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 4210342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_sync_async_fault_cross has 1 failures.
45.keymgr_sync_async_fault_cross.7508673238808387274468460311168885965179059688452221004805449616686762509812
Line 269, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest/run.log
UVM_ERROR @ 20181073 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 20181073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_random has 1 failures.
46.keymgr_random.32665095702729791345671086589236858222766894508030898436578656078843509008298
Line 364, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/46.keymgr_random/latest/run.log
UVM_ERROR @ 88892211 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 88892211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Sealing Aes
has 1 failures:
17.keymgr_stress_all.67984314286464493718951858126286706838385933695246112311084654725445403387217
Line 1672, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/17.keymgr_stress_all/latest/run.log
UVM_ERROR @ 308382726 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (6944077568762972869739779902113592254218749649885367780523204858751488779408733468127987794471639502431952330154910729468765175799552369335208226416981285 [0x8495f1b1edffaa9d6f4089fe6a3c7fdb3407450b3c28489304f3ba9a97486cad08e8562402a5fc4978b4fec5f98d567c5b5e237a248f5aa4fa626fdcc4837525] vs 6944077568762972869739779902113592254218749649885367780523204858751488779408733468127987794471639502431952330154910729468765175799552369335208226416981285 [0x8495f1b1edffaa9d6f4089fe6a3c7fdb3407450b3c28489304f3ba9a97486cad08e8562402a5fc4978b4fec5f98d567c5b5e237a248f5aa4fa626fdcc4837525]) AES key at state StCreatorRootKey for Sealing Aes
UVM_INFO @ 308382726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
24.keymgr_stress_all.41218512264527997825165067794944345087620298848993424343698866733869646332446
Line 2935, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/24.keymgr_stress_all/latest/run.log
UVM_ERROR @ 1701886410 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_6
UVM_INFO @ 1701886410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly
has 1 failures:
34.keymgr_hwsw_invalid_input.104226766051196601645496874199354716500669845565502560941673541353371882225076
Line 488, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest/run.log
UVM_ERROR @ 39401851 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
UVM_INFO @ 39401851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StOwnerIntKey for Sealing Kmac
has 1 failures:
37.keymgr_stress_all.51443686836435348397356012713360545409953684003057973007314476101578053984700
Line 2362, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/37.keymgr_stress_all/latest/run.log
UVM_ERROR @ 207161883 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (13350589053066787407009062795827963042339025492876261180829949600489389170436127062752000139804290113739156284393318484798660674259613874110542191121136010 [0xfee851e89efd4c101775739c52ec1ae3128f7fc84455ad8bb9094391c7470b1e817a9f2c71afa9972781618e0cf51c1ca8ae0f2e3d6c766fed5664cec5fff98a] vs 13350589053066787407009062795827963042339025492876261180829949600489389170436127062752000139804290113739156284393318484798660674259613874110542191121136010 [0xfee851e89efd4c101775739c52ec1ae3128f7fc84455ad8bb9094391c7470b1e817a9f2c71afa9972781618e0cf51c1ca8ae0f2e3d6c766fed5664cec5fff98a]) KMAC key at state StOwnerIntKey for Sealing Kmac
UVM_INFO @ 207161883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
40.keymgr_stress_all.53438364829513454899174228760901361760382161413846010352512385865363874759418
Line 1403, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/40.keymgr_stress_all/latest/run.log
UVM_ERROR @ 428733903 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_3
UVM_INFO @ 428733903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StOwnerKey for Sealing Kmac
has 1 failures:
44.keymgr_lc_disable.32633282562827710030233242590174485392799939742176780823070340256100364168958
Line 631, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/44.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 225856483 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (13306728041043079855062395789935447178232111099460744662757655274859860239806380754834132883634560844564012073375031419952459520304640804653163152451730235 [0xfe11ee8a1b7efdd95734f8e0d6daa6fae2e36182e9d28d244895f5536db01a6c33269414f7f777ee75296e7b18308e5f4308f908d3e77497b70d1e1aa8527b3b] vs 13306728041043079855062395789935447178232111099460744662757655274859860239806380754834132883634560844564012073375031419952459520304640804653163152451730235 [0xfe11ee8a1b7efdd95734f8e0d6daa6fae2e36182e9d28d244895f5536db01a6c33269414f7f777ee75296e7b18308e5f4308f908d3e77497b70d1e1aa8527b3b]) KMAC key at state StOwnerKey for Sealing Kmac
UVM_INFO @ 225856483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---