KEYMGR Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: `eb56ef55d0`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	30.710s	1.631ms	50	50	100.00
V1	random	keymgr_random	28.680s	954.498us	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.570s	58.015us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.520s	25.749us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	14.910s	580.072us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	16.640s	922.412us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.020s	96.908us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.520s	25.749us	20	20	100.00
		keymgr_csr_aliasing	16.640s	922.412us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.392m	3.136ms	50	50	100.00
V2	sideload	keymgr_sideload	24.870s	2.133ms	50	50	100.00
		keymgr_sideload_kmac	34.450s	1.785ms	50	50	100.00
		keymgr_sideload_aes	46.870s	4.977ms	50	50	100.00
		keymgr_sideload_otbn	1.027m	1.866ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	24.680s	1.030ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	12.200s	1.967ms	47	50	94.00
V2	kmac_error_response	keymgr_kmac_rsp_err	9.870s	327.413us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	49.310s	11.098ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.673m	16.807ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	11.760s	433.835us	50	50	100.00
V2	stress_all	keymgr_stress_all	13.563m	98.715ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.980s	20.721us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.010s	25.573us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.100s	160.760us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.100s	160.760us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.570s	58.015us	5	5	100.00
		keymgr_csr_rw	1.520s	25.749us	20	20	100.00
		keymgr_csr_aliasing	16.640s	922.412us	5	5	100.00
		keymgr_same_csr_outstanding	3.250s	90.098us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.570s	58.015us	5	5	100.00
		keymgr_csr_rw	1.520s	25.749us	20	20	100.00
		keymgr_csr_aliasing	16.640s	922.412us	5	5	100.00
		keymgr_same_csr_outstanding	3.250s	90.098us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	sec_cm_additional_check	keymgr_sec_cm	18.850s	835.348us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	18.850s	835.348us	5	5	100.00
		keymgr_tl_intg_err	5.880s	458.882us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.590s	803.437us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.590s	803.437us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.590s	803.437us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.590s	803.437us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.980s	4.170ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	18.850s	835.348us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	18.850s	835.348us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	5.880s	458.882us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.590s	803.437us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.392m	3.136ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	28.680s	954.498us	50	50	100.00
		keymgr_csr_rw	1.520s	25.749us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	28.680s	954.498us	50	50	100.00
		keymgr_csr_rw	1.520s	25.749us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	28.680s	954.498us	50	50	100.00
		keymgr_csr_rw	1.520s	25.749us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	12.200s	1.967ms	47	50	94.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.673m	16.807ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.673m	16.807ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	28.680s	954.498us	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	27.530s	1.588ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	18.850s	835.348us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	18.850s	835.348us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	18.850s	835.348us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	33.710s	1.435ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	12.200s	1.967ms	47	50	94.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	18.850s	835.348us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	18.850s	835.348us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	18.850s	835.348us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	33.710s	1.435ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	33.710s	1.435ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	18.850s	835.348us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	33.710s	1.435ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	18.850s	835.348us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	33.710s	1.435ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	27.840s	666.572us	36	50	72.00
V3		TOTAL			36	50	72.00
		TOTAL			1090	1110	98.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.70	99.04	97.87	98.46	100.00	99.02	98.41	91.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
- Test keymgr_stress_all_with_rand_reset has 14 failures.
  - 0.keymgr_stress_all_with_rand_reset.92416154219858291682777779143916873165542956265735435787043634616273849553154
    Line 1010, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3243557039 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3243557039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.keymgr_stress_all_with_rand_reset.46551056675709627357262075710033489938519226295530230979236831785848175741880
    Line 541, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 165606040 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 165606040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_stress_all has 1 failures.
  - 24.keymgr_stress_all.65588745648114878926523298900492142539287419992046572969458032179883742575987
    Line 3112, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/24.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 3250774128 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 3250774128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_lc_disable has 1 failures.
  - 30.keymgr_lc_disable.33517544529520114740911092721061209912782708987491033501853428844461806437809
    Line 292, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  28478075 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  28478075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerKey for Sealing Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

5.keymgr_lc_disable.108330390509983023123608235812599301408068720055887063978723241851810929780300
Line 581, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  84892115 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (2642416602794505753532467866582666533487566792189435559043258130020650876707380001801252876406889719577219865123168405506112574077008673006135876391647564 [0x3273dd01bde4637e0efd0a14d61bdf43719fabc90611bd382e011f580c5589421abf8f4f54c31e3fba3a87341f4bda66d4a121a2952bd35ed142519fac99b94c] vs 2642416602794505753532467866582666533487566792189435559043258130020650876707380001801252876406889719577219865123168405506112574077008673006135876391647564 [0x3273dd01bde4637e0efd0a14d61bdf43719fabc90611bd382e011f580c5589421abf8f4f54c31e3fba3a87341f4bda66d4a121a2952bd35ed142519fac99b94c]) AES key at state StOwnerKey for Sealing Aes
  UVM_INFO @  84892115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 31.keymgr_hwsw_invalid_input.105328302810885815459548991688898643539092148083007005657453333437339189799139
    Line 572, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/31.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @  28410120 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  28410120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 41.keymgr_stress_all.111678961993471462650671518503108666117957467457652857457427542884293968881985
    Line 1132, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/41.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 643157613 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (3 [0x3] vs 6 [0x6])
  UVM_INFO @ 643157613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:689) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*]) has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 45.keymgr_lc_disable.29377184388008846082140026128814290804638983129378750789311695898033521282497
    Line 400, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/45.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @   6584281 ps: (keymgr_scoreboard.sv:689) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (0 [0x0] vs 2 [0x2])
  UVM_INFO @   6584281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```