KEYMGR Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: e9ae10fb42

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	21.770s	853.758us	50	50	100.00
V1	random	keymgr_random	55.020s	4.369ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.310s	24.525us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.460s	25.050us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	27.390s	1.166ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.100s	479.957us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.550s	36.740us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.460s	25.050us	20	20	100.00
		keymgr_csr_aliasing	10.100s	479.957us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.309m	2.639ms	50	50	100.00
V2	sideload	keymgr_sideload	42.920s	6.109ms	49	50	98.00
		keymgr_sideload_kmac	34.760s	5.882ms	50	50	100.00
		keymgr_sideload_aes	46.360s	1.516ms	50	50	100.00
		keymgr_sideload_otbn	40.030s	3.612ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	20.630s	4.096ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	26.720s	1.896ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	11.800s	1.106ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	37.640s	1.744ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.204m	2.312ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	17.080s	720.780us	50	50	100.00
V2	stress_all	keymgr_stress_all	4.605m	111.615ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.900s	17.336us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.030s	17.796us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.390s	120.697us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.390s	120.697us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.310s	24.525us	5	5	100.00
		keymgr_csr_rw	1.460s	25.050us	20	20	100.00
		keymgr_csr_aliasing	10.100s	479.957us	5	5	100.00
		keymgr_same_csr_outstanding	3.630s	174.306us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.310s	24.525us	5	5	100.00
		keymgr_csr_rw	1.460s	25.050us	20	20	100.00
		keymgr_csr_aliasing	10.100s	479.957us	5	5	100.00
		keymgr_same_csr_outstanding	3.630s	174.306us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	sec_cm_additional_check	keymgr_sec_cm	9.630s	1.280ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	9.630s	1.280ms	5	5	100.00
		keymgr_tl_intg_err	12.160s	431.134us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.140s	140.957us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.140s	140.957us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.140s	140.957us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.140s	140.957us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	17.350s	1.862ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	9.630s	1.280ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	9.630s	1.280ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	12.160s	431.134us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.140s	140.957us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.309m	2.639ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	55.020s	4.369ms	50	50	100.00
		keymgr_csr_rw	1.460s	25.050us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	55.020s	4.369ms	50	50	100.00
		keymgr_csr_rw	1.460s	25.050us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	55.020s	4.369ms	50	50	100.00
		keymgr_csr_rw	1.460s	25.050us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	26.720s	1.896ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.204m	2.312ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.204m	2.312ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	55.020s	4.369ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	24.800s	1.100ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	9.630s	1.280ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	9.630s	1.280ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	9.630s	1.280ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	8.940s	260.245us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	26.720s	1.896ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	9.630s	1.280ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	9.630s	1.280ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	9.630s	1.280ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	8.940s	260.245us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	8.940s	260.245us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	9.630s	1.280ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	8.940s	260.245us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	9.630s	1.280ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	8.940s	260.245us	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	29.640s	3.181ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			1089	1110	98.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	14	87.50
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.76	99.04	98.03	98.66	100.00	99.02	98.41	91.14

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

  • Test keymgr_stress_all_with_rand_reset has 17 failures.

    • 3.keymgr_stress_all_with_rand_reset.3211433880658951434774239114111714771643135113667546743915464277430076232432
      Line 999, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1934367602 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1934367602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.keymgr_stress_all_with_rand_reset.55722205591315784219470155281862088446127176121007229239740582507044856548501
      Line 400, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2194821238 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2194821238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:

  • Test keymgr_stress_all has 1 failures.

    • 13.keymgr_stress_all.1161702609722341808982062160952999880647734479449180649106812140651588141791
      Line 662, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/13.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 9827785777 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 9827785777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_sideload has 1 failures.

    • 48.keymgr_sideload.109211316774265581397596887029798435150666627971432246579843996325460933676136
      Line 309, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/48.keymgr_sideload/latest/run.log

        UVM_ERROR @  34077670 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  34077670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 11.keymgr_stress_all.78750779998459556177197492925760337613008728924673787828274201433917510549276
      Line 486, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 262049286 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3938397480 [0xeabf2d28] vs 3938397480 [0xeabf2d28]) reg name: keymgr_reg_block.sw_share1_output_2
        UVM_INFO @ 262049286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 36.keymgr_stress_all_with_rand_reset.45664109550418551250838759204744611132575795366579502663044129667133317746396
      Line 466, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/36.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 979341806 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
        UVM_INFO @ 979341806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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