KEYMGR Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	38.740s	1.654ms	50	50	100.00
V1	random	keymgr_random	1.011m	2.831ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.450s	72.635us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.610s	29.288us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	32.480s	1.310ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.170s	424.674us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.490s	198.400us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.610s	29.288us	20	20	100.00
		keymgr_csr_aliasing	10.170s	424.674us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.062m	12.496ms	49	50	98.00
V2	sideload	keymgr_sideload	42.910s	7.050ms	50	50	100.00
		keymgr_sideload_kmac	51.550s	6.536ms	50	50	100.00
		keymgr_sideload_aes	1.165m	7.507ms	50	50	100.00
		keymgr_sideload_otbn	1.067m	4.963ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	20.240s	3.003ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	21.060s	1.555ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	14.770s	1.999ms	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	49.010s	1.596ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	38.030s	1.311ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	13.340s	1.720ms	50	50	100.00
V2	stress_all	keymgr_stress_all	8.464m	44.278ms	50	50	100.00
V2	intr_test	keymgr_intr_test	0.910s	28.100us	50	50	100.00
V2	alert_test	keymgr_alert_test	0.980s	181.501us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.310s	115.737us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.310s	115.737us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.450s	72.635us	5	5	100.00
		keymgr_csr_rw	1.610s	29.288us	20	20	100.00
		keymgr_csr_aliasing	10.170s	424.674us	5	5	100.00
		keymgr_same_csr_outstanding	2.750s	86.450us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.450s	72.635us	5	5	100.00
		keymgr_csr_rw	1.610s	29.288us	20	20	100.00
		keymgr_csr_aliasing	10.170s	424.674us	5	5	100.00
		keymgr_same_csr_outstanding	2.750s	86.450us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	sec_cm_additional_check	keymgr_sec_cm	14.130s	1.548ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	14.130s	1.548ms	5	5	100.00
		keymgr_tl_intg_err	8.340s	796.908us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	11.490s	555.734us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	11.490s	555.734us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	11.490s	555.734us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	11.490s	555.734us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.050s	460.989us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	14.130s	1.548ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	14.130s	1.548ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.340s	796.908us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	11.490s	555.734us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.062m	12.496ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.011m	2.831ms	50	50	100.00
		keymgr_csr_rw	1.610s	29.288us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.011m	2.831ms	50	50	100.00
		keymgr_csr_rw	1.610s	29.288us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.011m	2.831ms	50	50	100.00
		keymgr_csr_rw	1.610s	29.288us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	21.060s	1.555ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	38.030s	1.311ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	38.030s	1.311ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.011m	2.831ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	33.120s	5.197ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	14.130s	1.548ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	14.130s	1.548ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	14.130s	1.548ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	43.070s	1.540ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	21.060s	1.555ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	14.130s	1.548ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	14.130s	1.548ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	14.130s	1.548ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	43.070s	1.540ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	43.070s	1.540ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	14.130s	1.548ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	43.070s	1.540ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	14.130s	1.548ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	43.070s	1.540ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	22.960s	4.082ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1085	1110	97.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	14	87.50
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.42	99.00	98.07	98.65	97.67	98.93	98.41	91.22

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
  • Test keymgr_stress_all_with_rand_reset has 23 failures.

    • 2.keymgr_stress_all_with_rand_reset.79676581118911941669609617537623550049113968147206413725496126397746830060952
      Line 1255, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 436724332 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 436724332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.keymgr_stress_all_with_rand_reset.7716664365389013249314675945330192639072204739106175334135514029062454462524
      Line 316, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 219438540 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 219438540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:

  • Test keymgr_cfg_regwen has 1 failures.

    • 1.keymgr_cfg_regwen.12399960483693581971101305133129535473325730673535347018443398277618313779145
      Line 336, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest/run.log

        UVM_ERROR @  11853414 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  11853414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 7.keymgr_kmac_rsp_err.4721781936526515615326917146847964962781254366957312677699378311894848459059
      Line 788, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @  48837623 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  48837623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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