e6706fcc7b
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 14.250s | 503.927us | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 39.510s | 14.700ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.230s | 38.912us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.700s | 447.622us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 16.910s | 2.675ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 10.860s | 1.696ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.320s | 108.371us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.700s | 447.622us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 10.860s | 1.696ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 1.952m | 9.121ms | 49 | 50 | 98.00 |
V2 | sideload | keymgr_sideload | 1.003m | 2.979ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 1.218m | 7.174ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 30.500s | 2.754ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 44.340s | 8.665ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 30.160s | 3.097ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 34.940s | 1.269ms | 48 | 50 | 96.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 8.050s | 1.612ms | 50 | 50 | 100.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 1.794m | 9.459ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 34.530s | 1.396ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 27.890s | 1.174ms | 48 | 50 | 96.00 |
V2 | stress_all | keymgr_stress_all | 7.207m | 37.183ms | 48 | 50 | 96.00 |
V2 | intr_test | keymgr_intr_test | 0.930s | 256.460us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 0.990s | 70.350us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 5.260s | 162.395us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 5.260s | 162.395us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.230s | 38.912us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.700s | 447.622us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.860s | 1.696ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.100s | 222.999us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.230s | 38.912us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.700s | 447.622us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.860s | 1.696ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.100s | 222.999us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 733 | 740 | 99.05 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 12.750s | 2.327ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 12.750s | 2.327ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 10.060s | 568.444us | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 3.950s | 134.245us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 3.950s | 134.245us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 3.950s | 134.245us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 3.950s | 134.245us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 14.070s | 727.015us | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 12.750s | 2.327ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 12.750s | 2.327ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 10.060s | 568.444us | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 3.950s | 134.245us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 1.952m | 9.121ms | 49 | 50 | 98.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 39.510s | 14.700ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.700s | 447.622us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 39.510s | 14.700ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.700s | 447.622us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 39.510s | 14.700ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.700s | 447.622us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 34.940s | 1.269ms | 48 | 50 | 96.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 34.530s | 1.396ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 34.530s | 1.396ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 39.510s | 14.700ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 17.540s | 777.270us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 12.750s | 2.327ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 12.750s | 2.327ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 12.750s | 2.327ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 35.600s | 2.756ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 34.940s | 1.269ms | 48 | 50 | 96.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 12.750s | 2.327ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 12.750s | 2.327ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 12.750s | 2.327ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 35.600s | 2.756ms | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 35.600s | 2.756ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 12.750s | 2.327ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 35.600s | 2.756ms | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 12.750s | 2.327ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 35.600s | 2.756ms | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 29.550s | 5.920ms | 31 | 50 | 62.00 |
V3 | TOTAL | 31 | 50 | 62.00 | |||
TOTAL | 1084 | 1110 | 97.66 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 12 | 75.00 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.70 | 99.04 | 98.03 | 98.26 | 100.00 | 99.02 | 98.41 | 91.17 |
UVM_ERROR (cip_base_vseq.sv:825) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 19 failures:
4.keymgr_stress_all_with_rand_reset.109346168201900261205352230393522151696892052456909670417830574371246029675077
Line 1359, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1200767502 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1200767502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.keymgr_stress_all_with_rand_reset.76696726541287070358997489628605776154934808648942037000546728325139968120927
Line 537, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 240911293 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 240911293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 2 failures:
Test keymgr_sync_async_fault_cross has 1 failures.
42.keymgr_sync_async_fault_cross.82095442596317679360743507410890041938876105924996271654078029585613926957902
Line 293, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_sync_async_fault_cross/latest/run.log
UVM_ERROR @ 3459251 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 3459251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_cfg_regwen has 1 failures.
47.keymgr_cfg_regwen.22068547496549317188161168610785220851400831633893703895477964979475085116890
Line 337, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest/run.log
UVM_ERROR @ 5512900 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 5512900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:261) scoreboard [scoreboard] alert recov_operation_err is not received!
has 1 failures:
9.keymgr_sync_async_fault_cross.69987334950935227286362538897404589433585406322811456084914054617233323599141
Line 331, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_sync_async_fault_cross/latest/run.log
UVM_ERROR @ 98688939 ps: (cip_base_scoreboard.sv:261) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
UVM_INFO @ 98688939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
34.keymgr_lc_disable.87744068905239533145831530631391709235339231107690688917136604185694394920866
Line 488, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/34.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 86756623 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_1
UVM_INFO @ 86756623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Attestation Kmac
has 1 failures:
34.keymgr_stress_all.72349207024233051804188445550582046183911445344376525051386420477038805379467
Line 1475, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/34.keymgr_stress_all/latest/run.log
UVM_ERROR @ 1826323311 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (4447359227262907402829923767466219737704801913026807055118265505288301025532247741457264589228192295919807158248895926464784040879612840956204578997189169 [0x54ea3d3456693cd55b3ab77046736979d32b0a83dda1b25d5a212eaf42a6b08ef1aae0b1b5a9356dc29597cb7464de72146993061e8c24a67fb8bbd91d5aba31] vs 4447359227262907402829923767466219737704801913026807055118265505288301025532247741457264589228192295919807158248895926464784040879612840956204578997189169 [0x54ea3d3456693cd55b3ab77046736979d32b0a83dda1b25d5a212eaf42a6b08ef1aae0b1b5a9356dc29597cb7464de72146993061e8c24a67fb8bbd91d5aba31]) KMAC key at state StDisabled for Attestation Kmac
UVM_INFO @ 1826323311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StOwnerKey for Attestation Kmac
has 1 failures:
42.keymgr_stress_all.35407720022347306567920305070792131510794961948976465812732712900789307624060
Line 664, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_stress_all/latest/run.log
UVM_ERROR @ 119924753 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (4573929263324472434335229212630048417180404401808407745296680362928760331704812858829809296303153555982173440597139969226320826658747483279035083469429992 [0x5754e6891101e6df958c8c3c9d2bbf8d044e3389a71f20744d6d707d48cf4a624e02259cc2aabb2511334427180517af931ecfcf4bd987dd68fe1c43e69d1ce8] vs 4573929263324472434335229212630048417180404401808407745296680362928760331704812858829809296303153555982173440597139969226320826658747483279035083469429992 [0x5754e6891101e6df958c8c3c9d2bbf8d044e3389a71f20744d6d707d48cf4a624e02259cc2aabb2511334427180517af931ecfcf4bd987dd68fe1c43e69d1ce8]) KMAC key at state StOwnerKey for Attestation Kmac
UVM_INFO @ 119924753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
46.keymgr_lc_disable.78435922522141483002257643947768164642492496546447132695759374359750461991106
Line 431, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/46.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 176762102 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3201818528 [0xbed7dfa0] vs 3201818528 [0xbed7dfa0]) reg name: keymgr_reg_block.sw_share0_output_2
UVM_INFO @ 176762102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---